LLVM 17.0.0git
AArch64PBQPRegAlloc.h
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1//==- AArch64PBQPRegAlloc.h - AArch64 specific PBQP constraints --*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64PBQPREGALOC_H
10#define LLVM_LIB_TARGET_AARCH64_AARCH64PBQPREGALOC_H
11
12#include "llvm/ADT/SetVector.h"
14
15namespace llvm {
16
17class TargetRegisterInfo;
18
19/// Add the accumulator chaining constraint to a PBQP graph
21public:
22 // Add A57 specific constraints to the PBQP graph.
23 void apply(PBQPRAGraph &G) override;
24
25private:
27 const TargetRegisterInfo *TRI;
28
29 // Add the accumulator chaining constraint, inside the chain, i.e. so that
30 // parity(Rd) == parity(Ra).
31 // \return true if a constraint was added
32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
33
34 // Add constraints between existing chains
35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
36};
37
38} // end namespace llvm
39
40#endif // LLVM_LIB_TARGET_AARCH64_AARCH64PBQPREGALOC_H
#define G(x, y, z)
Definition: MD5.cpp:56
This file implements a set that has insertion order iteration characteristics.
Add the accumulator chaining constraint to a PBQP graph.
void apply(PBQPRAGraph &G) override
Abstract base for classes implementing PBQP register allocation constraints (e.g.
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:301
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18