9#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64PBQPREGALOC_H
10#define LLVM_LIB_TARGET_AARCH64_AARCH64PBQPREGALOC_H
17class TargetRegisterInfo;
32 bool addIntraChainConstraint(
PBQPRAGraph &
G,
unsigned Rd,
unsigned Ra);
35 void addInterChainConstraint(
PBQPRAGraph &
G,
unsigned Rd,
unsigned Ra);
This file implements a set that has insertion order iteration characteristics.
Add the accumulator chaining constraint to a PBQP graph.
void apply(PBQPRAGraph &G) override
Abstract base for classes implementing PBQP register allocation constraints (e.g.
A SetVector that performs no allocations if smaller than a certain size.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.