LLVM  15.0.0git
Public Member Functions | List of all members
AMDGPUCombinerHelper Class Reference

#include "Target/AMDGPU/AMDGPUCombinerHelper.h"

Inheritance diagram for AMDGPUCombinerHelper:
Inheritance graph
[legend]
Collaboration diagram for AMDGPUCombinerHelper:
Collaboration graph
[legend]

Public Member Functions

bool matchFoldableFneg (MachineInstr &MI, MachineInstr *&MatchInfo)
 
void applyFoldableFneg (MachineInstr &MI, MachineInstr *&MatchInfo)
 
- Public Member Functions inherited from llvm::CombinerHelper
 CombinerHelper (GISelChangeObserver &Observer, MachineIRBuilder &B, GISelKnownBits *KB=nullptr, MachineDominatorTree *MDT=nullptr, const LegalizerInfo *LI=nullptr)
 
GISelKnownBitsgetKnownBits () const
 
const TargetLoweringgetTargetLowering () const
 
bool isPreLegalize () const
 
bool isLegal (const LegalityQuery &Query) const
 
bool isLegalOrBeforeLegalizer (const LegalityQuery &Query) const
 
bool isConstantLegalOrBeforeLegalizer (const LLT Ty) const
 
void replaceRegWith (MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const
 MachineRegisterInfo::replaceRegWith() and inform the observer of the changes. More...
 
void replaceRegOpWith (MachineRegisterInfo &MRI, MachineOperand &FromRegOp, Register ToReg) const
 Replace a single register operand with a new register and inform the observer of the changes. More...
 
void replaceOpcodeWith (MachineInstr &FromMI, unsigned ToOpcode) const
 Replace the opcode in instruction with a new opcode and inform the observer of the changes. More...
 
const RegisterBankgetRegBank (Register Reg) const
 Get the register bank of Reg. More...
 
void setRegBank (Register Reg, const RegisterBank *RegBank)
 Set the register bank of Reg. More...
 
bool tryCombineCopy (MachineInstr &MI)
 If MI is COPY, try to combine it. More...
 
bool matchCombineCopy (MachineInstr &MI)
 
void applyCombineCopy (MachineInstr &MI)
 
bool isPredecessor (const MachineInstr &DefMI, const MachineInstr &UseMI)
 Returns true if DefMI precedes UseMI or they are the same instruction. More...
 
bool dominates (const MachineInstr &DefMI, const MachineInstr &UseMI)
 Returns true if DefMI dominates UseMI. More...
 
bool tryCombineExtendingLoads (MachineInstr &MI)
 If MI is extend that consumes the result of a load, try to combine it. More...
 
bool matchCombineExtendingLoads (MachineInstr &MI, PreferredTuple &MatchInfo)
 
void applyCombineExtendingLoads (MachineInstr &MI, PreferredTuple &MatchInfo)
 
bool matchCombineLoadWithAndMask (MachineInstr &MI, BuildFnTy &MatchInfo)
 Match (and (load x), mask) -> zextload x. More...
 
bool tryCombineIndexedLoadStore (MachineInstr &MI)
 Combine MI into a pre-indexed or post-indexed load/store operation if legal and the surrounding code makes it useful. More...
 
bool matchCombineIndexedLoadStore (MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
 
void applyCombineIndexedLoadStore (MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo)
 
bool matchSextTruncSextLoad (MachineInstr &MI)
 
void applySextTruncSextLoad (MachineInstr &MI)
 
bool matchSextInRegOfLoad (MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
 Match sext_inreg(load p), imm -> sextload p. More...
 
void applySextInRegOfLoad (MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
 
bool matchCombineDivRem (MachineInstr &MI, MachineInstr *&OtherMI)
 Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM when their source operands are identical. More...
 
void applyCombineDivRem (MachineInstr &MI, MachineInstr *&OtherMI)
 
bool matchOptBrCondByInvertingCond (MachineInstr &MI, MachineInstr *&BrCond)
 If a brcond's true block is not the fallthrough, make it so by inverting the condition and swapping operands. More...
 
void applyOptBrCondByInvertingCond (MachineInstr &MI, MachineInstr *&BrCond)
 
bool tryCombineConcatVectors (MachineInstr &MI)
 If MI is G_CONCAT_VECTORS, try to combine it. More...
 
bool matchCombineConcatVectors (MachineInstr &MI, bool &IsUndef, SmallVectorImpl< Register > &Ops)
 Check if the G_CONCAT_VECTORS MI is undef or if it can be flattened into a build_vector. More...
 
void applyCombineConcatVectors (MachineInstr &MI, bool IsUndef, const ArrayRef< Register > Ops)
 Replace MI with a flattened build_vector with Ops or an implicit_def if IsUndef is true. More...
 
bool tryCombineShuffleVector (MachineInstr &MI)
 Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS. More...
 
bool matchCombineShuffleVector (MachineInstr &MI, SmallVectorImpl< Register > &Ops)
 Check if the G_SHUFFLE_VECTOR MI can be replaced by a concat_vectors. More...
 
void applyCombineShuffleVector (MachineInstr &MI, const ArrayRef< Register > Ops)
 Replace MI with a concat_vectors with Ops. More...
 
bool tryCombineMemCpyFamily (MachineInstr &MI, unsigned MaxLen=0)
 Optimize memcpy intrinsics et al, e.g. More...
 
bool matchPtrAddImmedChain (MachineInstr &MI, PtrAddChain &MatchInfo)
 
void applyPtrAddImmedChain (MachineInstr &MI, PtrAddChain &MatchInfo)
 
bool matchShiftImmedChain (MachineInstr &MI, RegisterImmPair &MatchInfo)
 Fold (shift (shift base, x), y) -> (shift base (x+y)) More...
 
void applyShiftImmedChain (MachineInstr &MI, RegisterImmPair &MatchInfo)
 
bool matchShiftOfShiftedLogic (MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
 If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with identical opcode, we may be able to convert that into 2 independent shifts followed by the logic op. More...
 
void applyShiftOfShiftedLogic (MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo)
 
bool matchCombineMulToShl (MachineInstr &MI, unsigned &ShiftVal)
 Transform a multiply by a power-of-2 value to a left shift. More...
 
void applyCombineMulToShl (MachineInstr &MI, unsigned &ShiftVal)
 
bool matchCombineShlOfExtend (MachineInstr &MI, RegisterImmPair &MatchData)
 
void applyCombineShlOfExtend (MachineInstr &MI, const RegisterImmPair &MatchData)
 
bool matchCombineMergeUnmerge (MachineInstr &MI, Register &MatchInfo)
 Fold away a merge of an unmerge of the corresponding values. More...
 
bool matchCombineShiftToUnmerge (MachineInstr &MI, unsigned TargetShiftSize, unsigned &ShiftVal)
 Reduce a shift by a constant to an unmerge and a shift on a half sized type. More...
 
void applyCombineShiftToUnmerge (MachineInstr &MI, const unsigned &ShiftVal)
 
bool tryCombineShiftToUnmerge (MachineInstr &MI, unsigned TargetShiftAmount)
 
bool matchCombineUnmergeMergeToPlainValues (MachineInstr &MI, SmallVectorImpl< Register > &Operands)
 Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z. More...
 
void applyCombineUnmergeMergeToPlainValues (MachineInstr &MI, SmallVectorImpl< Register > &Operands)
 
bool matchCombineUnmergeConstant (MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
 Transform G_UNMERGE Constant -> Constant1, Constant2, ... More...
 
void applyCombineUnmergeConstant (MachineInstr &MI, SmallVectorImpl< APInt > &Csts)
 
bool matchCombineUnmergeUndef (MachineInstr &MI, std::function< void(MachineIRBuilder &)> &MatchInfo)
 Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ... More...
 
bool matchCombineUnmergeWithDeadLanesToTrunc (MachineInstr &MI)
 Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z. More...
 
void applyCombineUnmergeWithDeadLanesToTrunc (MachineInstr &MI)
 
bool matchCombineUnmergeZExtToZExt (MachineInstr &MI)
 Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0. More...
 
void applyCombineUnmergeZExtToZExt (MachineInstr &MI)
 
bool matchCombineConstantFoldFpUnary (MachineInstr &MI, Optional< APFloat > &Cst)
 Transform fp_instr(cst) to constant result of the fp operation. More...
 
void applyCombineConstantFoldFpUnary (MachineInstr &MI, Optional< APFloat > &Cst)
 
bool matchCombineI2PToP2I (MachineInstr &MI, Register &Reg)
 Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space. More...
 
void applyCombineI2PToP2I (MachineInstr &MI, Register &Reg)
 
bool matchCombineP2IToI2P (MachineInstr &MI, Register &Reg)
 Transform PtrToInt(IntToPtr(x)) to x. More...
 
void applyCombineP2IToI2P (MachineInstr &MI, Register &Reg)
 
bool matchCombineAddP2IToPtrAdd (MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute)
 Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y) Transform G_ADD y, (G_PTRTOINT x) -> G_PTRTOINT (G_PTR_ADD x, y) More...
 
void applyCombineAddP2IToPtrAdd (MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute)
 
bool matchCombineConstPtrAddToI2P (MachineInstr &MI, APInt &NewCst)
 
void applyCombineConstPtrAddToI2P (MachineInstr &MI, APInt &NewCst)
 
bool matchCombineAnyExtTrunc (MachineInstr &MI, Register &Reg)
 Transform anyext(trunc(x)) to x. More...
 
void applyCombineAnyExtTrunc (MachineInstr &MI, Register &Reg)
 
bool matchCombineZextTrunc (MachineInstr &MI, Register &Reg)
 Transform zext(trunc(x)) to x. More...
 
bool matchCombineExtOfExt (MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
 Transform [asz]ext([asz]ext(x)) to [asz]ext x. More...
 
void applyCombineExtOfExt (MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo)
 
bool matchCombineFNegOfFNeg (MachineInstr &MI, Register &Reg)
 Transform fneg(fneg(x)) to x. More...
 
bool matchCombineFAbsOfFAbs (MachineInstr &MI, Register &Src)
 Match fabs(fabs(x)) to fabs(x). More...
 
void applyCombineFAbsOfFAbs (MachineInstr &MI, Register &Src)
 
bool matchCombineFAbsOfFNeg (MachineInstr &MI, BuildFnTy &MatchInfo)
 Transform fabs(fneg(x)) to fabs(x). More...
 
bool matchCombineTruncOfExt (MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
 Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x). More...
 
void applyCombineTruncOfExt (MachineInstr &MI, std::pair< Register, unsigned > &MatchInfo)
 
bool matchCombineTruncOfShl (MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
 Transform trunc (shl x, K) to shl (trunc x), K => K < VT.getScalarSizeInBits(). More...
 
void applyCombineTruncOfShl (MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
 
void applyCombineMulByNegativeOne (MachineInstr &MI)
 Transform G_MUL(x, -1) to G_SUB(0, x) More...
 
bool matchAnyExplicitUseIsUndef (MachineInstr &MI)
 Return true if any explicit use operand on MI is defined by a G_IMPLICIT_DEF. More...
 
bool matchAllExplicitUsesAreUndef (MachineInstr &MI)
 Return true if all register explicit use operands on MI are defined by a G_IMPLICIT_DEF. More...
 
bool matchUndefShuffleVectorMask (MachineInstr &MI)
 Return true if a G_SHUFFLE_VECTOR instruction MI has an undef mask. More...
 
bool matchUndefStore (MachineInstr &MI)
 Return true if a G_STORE instruction MI is storing an undef value. More...
 
bool matchUndefSelectCmp (MachineInstr &MI)
 Return true if a G_SELECT instruction MI has an undef comparison. More...
 
bool matchConstantSelectCmp (MachineInstr &MI, unsigned &OpIdx)
 Return true if a G_SELECT instruction MI has a constant comparison. More...
 
bool replaceInstWithFConstant (MachineInstr &MI, double C)
 Replace an instruction with a G_FCONSTANT with value C. More...
 
bool replaceInstWithConstant (MachineInstr &MI, int64_t C)
 Replace an instruction with a G_CONSTANT with value C. More...
 
bool replaceInstWithConstant (MachineInstr &MI, APInt C)
 Replace an instruction with a G_CONSTANT with value C. More...
 
bool replaceInstWithUndef (MachineInstr &MI)
 Replace an instruction with a G_IMPLICIT_DEF. More...
 
bool replaceSingleDefInstWithOperand (MachineInstr &MI, unsigned OpIdx)
 Delete MI and replace all of its uses with its OpIdx-th operand. More...
 
bool replaceSingleDefInstWithReg (MachineInstr &MI, Register Replacement)
 Delete MI and replace all of its uses with Replacement. More...
 
bool matchEqualDefs (const MachineOperand &MOP1, const MachineOperand &MOP2)
 Return true if MOP1 and MOP2 are register operands are defined by equivalent instructions. More...
 
bool matchConstantOp (const MachineOperand &MOP, int64_t C)
 Return true if MOP is defined by a G_CONSTANT with a value equal to C. More...
 
bool matchSelectSameVal (MachineInstr &MI)
 Optimize (cond ? x : x) -> x. More...
 
bool matchBinOpSameVal (MachineInstr &MI)
 Optimize (x op x) -> x. More...
 
bool matchOperandIsZero (MachineInstr &MI, unsigned OpIdx)
 Check if operand OpIdx is zero. More...
 
bool matchOperandIsUndef (MachineInstr &MI, unsigned OpIdx)
 Check if operand OpIdx is undef. More...
 
bool matchOperandIsKnownToBeAPowerOfTwo (MachineInstr &MI, unsigned OpIdx)
 Check if operand OpIdx is known to be a power of 2. More...
 
bool eraseInst (MachineInstr &MI)
 Erase MI. More...
 
bool matchSimplifyAddToSub (MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
 Return true if MI is a G_ADD which can be simplified to a G_SUB. More...
 
void applySimplifyAddToSub (MachineInstr &MI, std::tuple< Register, Register > &MatchInfo)
 
bool matchHoistLogicOpWithSameOpcodeHands (MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
 Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y)) More...
 
void applyBuildInstructionSteps (MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo)
 Replace MI with a series of instructions described in MatchInfo. More...
 
bool matchAshrShlToSextInreg (MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
 Match ashr (shl x, C), C -> sext_inreg (C) More...
 
void applyAshShlToSextInreg (MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo)
 
bool matchOverlappingAnd (MachineInstr &MI, BuildFnTy &MatchInfo)
 Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0. More...
 
bool matchRedundantAnd (MachineInstr &MI, Register &Replacement)
 
bool matchRedundantOr (MachineInstr &MI, Register &Replacement)
 
bool matchRedundantSExtInReg (MachineInstr &MI)
 
bool matchNotCmp (MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate)
 Combine inverting a result of a compare into the opposite cond code. More...
 
void applyNotCmp (MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate)
 
bool matchXorOfAndWithSameReg (MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
 Fold (xor (and x, y), y) -> (and (not x), y) {. More...
 
void applyXorOfAndWithSameReg (MachineInstr &MI, std::pair< Register, Register > &MatchInfo)
 
bool matchPtrAddZero (MachineInstr &MI)
 } More...
 
void applyPtrAddZero (MachineInstr &MI)
 
void applySimplifyURemByPow2 (MachineInstr &MI)
 Combine G_UREM x, (known power of 2) to an add and bitmasking. More...
 
bool matchFoldBinOpIntoSelect (MachineInstr &MI, unsigned &SelectOpNo)
 Push a binary operator through a select on constants. More...
 
bool applyFoldBinOpIntoSelect (MachineInstr &MI, const unsigned &SelectOpNo)
 SelectOperand is the operand in binary operator MI that is the select to fold. More...
 
bool matchCombineInsertVecElts (MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
 
void applyCombineInsertVecElts (MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo)
 
bool matchLoadOrCombine (MachineInstr &MI, BuildFnTy &MatchInfo)
 Match expression trees of the form. More...
 
bool matchTruncStoreMerge (MachineInstr &MI, MergeTruncStoresInfo &MatchInfo)
 Match a pattern where a wide type scalar value is stored by several narrow stores. More...
 
void applyTruncStoreMerge (MachineInstr &MI, MergeTruncStoresInfo &MatchInfo)
 
bool matchExtendThroughPhis (MachineInstr &MI, MachineInstr *&ExtMI)
 
void applyExtendThroughPhis (MachineInstr &MI, MachineInstr *&ExtMI)
 
bool matchExtractVecEltBuildVec (MachineInstr &MI, Register &Reg)
 
void applyExtractVecEltBuildVec (MachineInstr &MI, Register &Reg)
 
bool matchExtractAllEltsFromBuildVector (MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
 
void applyExtractAllEltsFromBuildVector (MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * >> &MatchInfo)
 
void applyBuildFn (MachineInstr &MI, BuildFnTy &MatchInfo)
 Use a function which takes in a MachineIRBuilder to perform a combine. More...
 
void applyBuildFnNoErase (MachineInstr &MI, BuildFnTy &MatchInfo)
 Use a function which takes in a MachineIRBuilder to perform a combine. More...
 
bool matchOrShiftToFunnelShift (MachineInstr &MI, BuildFnTy &MatchInfo)
 
bool matchFunnelShiftToRotate (MachineInstr &MI)
 Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate. More...
 
void applyFunnelShiftToRotate (MachineInstr &MI)
 
bool matchRotateOutOfRange (MachineInstr &MI)
 
void applyRotateOutOfRange (MachineInstr &MI)
 
bool matchICmpToTrueFalseKnownBits (MachineInstr &MI, int64_t &MatchInfo)
 
bool matchICmpToLHSKnownBits (MachineInstr &MI, BuildFnTy &MatchInfo)
 
bool matchAndOrDisjointMask (MachineInstr &MI, BuildFnTy &MatchInfo)
 
bool matchBitfieldExtractFromSExtInReg (MachineInstr &MI, BuildFnTy &MatchInfo)
 Form a G_SBFX from a G_SEXT_INREG fed by a right shift. More...
 
bool matchBitfieldExtractFromAnd (MachineInstr &MI, BuildFnTy &MatchInfo)
 Match: and (lshr x, cst), mask -> ubfx x, cst, width. More...
 
bool matchBitfieldExtractFromShr (MachineInstr &MI, BuildFnTy &MatchInfo)
 Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width. More...
 
bool matchBitfieldExtractFromShrAnd (MachineInstr &MI, BuildFnTy &MatchInfo)
 Match: shr (and x, n), k -> ubfx x, pos, width. More...
 
bool matchReassocConstantInnerRHS (GPtrAdd &MI, MachineInstr *RHS, BuildFnTy &MatchInfo)
 
bool matchReassocFoldConstantsInSubTree (GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo)
 
bool matchReassocConstantInnerLHS (GPtrAdd &MI, MachineInstr *LHS, MachineInstr *RHS, BuildFnTy &MatchInfo)
 
bool matchReassocPtrAdd (MachineInstr &MI, BuildFnTy &MatchInfo)
 Reassociate pointer calculations with G_ADD involved, to allow better addressing mode usage. More...
 
bool matchConstantFold (MachineInstr &MI, APInt &MatchInfo)
 Do constant folding when opportunities are exposed after MIR building. More...
 
bool matchNarrowBinopFeedingAnd (MachineInstr &MI, BuildFnTy &MatchInfo)
 
MachineInstrbuildUDivUsingMul (MachineInstr &MI)
 Given an G_UDIV MI expressing a divide by constant, return an expression that implements it by multiplying by a magic number. More...
 
bool matchUDivByConst (MachineInstr &MI)
 Combine G_UDIV by constant into a multiply by magic constant. More...
 
void applyUDivByConst (MachineInstr &MI)
 
bool matchUMulHToLShr (MachineInstr &MI)
 
void applyUMulHToLShr (MachineInstr &MI)
 
bool tryCombine (MachineInstr &MI)
 Try to transform MI by using all of the above combine functions. More...
 
bool tryEmitMemcpyInline (MachineInstr &MI)
 Emit loads and stores that perform the given memcpy. More...
 
bool matchMulOBy2 (MachineInstr &MI, BuildFnTy &MatchInfo)
 Match: (G_UMULO x, 2) -> (G_UADDO x, x) (G_SMULO x, 2) -> (G_SADDO x, x) More...
 
bool matchMulOBy0 (MachineInstr &MI, BuildFnTy &MatchInfo)
 Match: (G_*MULO x, 0) -> 0 + no carry out. More...
 
bool matchAddOBy0 (MachineInstr &MI, BuildFnTy &MatchInfo)
 Match: (G_*ADDO x, 0) -> x + no carry out. More...
 
bool matchRedundantNegOperands (MachineInstr &MI, BuildFnTy &MatchInfo)
 Transform (fadd x, fneg(y)) -> (fsub x, y) (fadd fneg(x), y) -> (fsub y, x) (fsub x, fneg(y)) -> (fadd x, y) (fmul fneg(x), fneg(y)) -> (fmul x, y) (fdiv fneg(x), fneg(y)) -> (fdiv x, y) (fmad fneg(x), fneg(y), z) -> (fmad x, y, z) (fma fneg(x), fneg(y), z) -> (fma x, y, z) More...
 
bool canCombineFMadOrFMA (MachineInstr &MI, bool &AllowFusionGlobally, bool &HasFMAD, bool &Aggressive, bool CanReassociate=false)
 
bool matchCombineFAddFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo)
 Transform (fadd (fmul x, y), z) -> (fma x, y, z) (fadd (fmul x, y), z) -> (fmad x, y, z) More...
 
bool matchCombineFAddFpExtFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo)
 Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) (fadd (fpext (fmul x, y)), z) -> (fmad (fpext x), (fpext y), z) More...
 
bool matchCombineFAddFMAFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo)
 Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z)) (fadd (fmad x, y, (fmul u, v)), z) -> (fmad x, y, (fmad u, v, z)) More...
 
bool matchCombineFAddFpExtFMulToFMadOrFMAAggressive (MachineInstr &MI, BuildFnTy &MatchInfo)
 
bool matchCombineFSubFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo)
 Transform (fsub (fmul x, y), z) -> (fma x, y, -z) (fsub (fmul x, y), z) -> (fmad x, y, -z) More...
 
bool matchCombineFSubFNegFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo)
 Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) (fsub (fneg (fmul, x, y)), z) -> (fmad (fneg x), y, (fneg z)) More...
 
bool matchCombineFSubFpExtFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo)
 Transform (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z)) (fsub (fpext (fmul x, y)), z) -> (fmad (fpext x), (fpext y), (fneg z)) More...
 
bool matchCombineFSubFpExtFNegFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo)
 Transform (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fma (fpext x), (fpext y), z)) (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fmad (fpext x), (fpext y), z)) More...
 
bool matchSelectToLogical (MachineInstr &MI, BuildFnTy &MatchInfo)
 Fold boolean selects to logical operations. More...
 
bool matchCombineFMinMaxNaN (MachineInstr &MI, unsigned &Info)
 
bool matchAddSubSameReg (MachineInstr &MI, Register &Src)
 Transform G_ADD(x, G_SUB(y, x)) to y. More...
 

Additional Inherited Members

- Protected Attributes inherited from llvm::CombinerHelper
MachineIRBuilderBuilder
 
MachineRegisterInfoMRI
 
GISelChangeObserverObserver
 
GISelKnownBitsKB
 
MachineDominatorTreeMDT
 
const LegalizerInfoLI
 
const RegisterBankInfoRBI
 
const TargetRegisterInfoTRI
 

Detailed Description

Definition at line 20 of file AMDGPUCombinerHelper.h.

Member Function Documentation

◆ applyFoldableFneg()

void AMDGPUCombinerHelper::applyFoldableFneg ( MachineInstr MI,
MachineInstr *&  MatchInfo 
)

◆ matchFoldableFneg()

bool AMDGPUCombinerHelper::matchFoldableFneg ( MachineInstr MI,
MachineInstr *&  MatchInfo 
)

The documentation for this class was generated from the following files: