LLVM  6.0.0svn
LegalizeFloatTypes.cpp
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1 //===-------- LegalizeFloatTypes.cpp - Legalization of float types --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements float type expansion and softening for LegalizeTypes.
11 // Softening is the act of turning a computation in an illegal floating point
12 // type into a computation in an integer type of the same size; also known as
13 // "soft float". For example, turning f32 arithmetic into operations using i32.
14 // The resulting integer value is the same as what you would get by performing
15 // the floating point operation and bitcasting the result to the integer type.
16 // Expansion is the act of changing a computation in an illegal type to be a
17 // computation in two identical registers of a smaller type. For example,
18 // implementing ppcf128 arithmetic in two f64 registers.
19 //
20 //===----------------------------------------------------------------------===//
21 
22 #include "LegalizeTypes.h"
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "legalize-types"
28 
29 /// GetFPLibCall - Return the right libcall for the given floating point type.
31  RTLIB::Libcall Call_F32,
32  RTLIB::Libcall Call_F64,
33  RTLIB::Libcall Call_F80,
34  RTLIB::Libcall Call_F128,
35  RTLIB::Libcall Call_PPCF128) {
36  return
37  VT == MVT::f32 ? Call_F32 :
38  VT == MVT::f64 ? Call_F64 :
39  VT == MVT::f80 ? Call_F80 :
40  VT == MVT::f128 ? Call_F128 :
41  VT == MVT::ppcf128 ? Call_PPCF128 :
42  RTLIB::UNKNOWN_LIBCALL;
43 }
44 
45 //===----------------------------------------------------------------------===//
46 // Convert Float Results to Integer for Non-HW-supported Operations.
47 //===----------------------------------------------------------------------===//
48 
49 bool DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
50  DEBUG(dbgs() << "Soften float result " << ResNo << ": "; N->dump(&DAG);
51  dbgs() << "\n");
52  SDValue R = SDValue();
53 
54  switch (N->getOpcode()) {
55  default:
56 #ifndef NDEBUG
57  dbgs() << "SoftenFloatResult #" << ResNo << ": ";
58  N->dump(&DAG); dbgs() << "\n";
59 #endif
60  llvm_unreachable("Do not know how to soften the result of this operator!");
61 
62  case ISD::Register:
63  case ISD::CopyFromReg:
64  case ISD::CopyToReg:
65  assert(isLegalInHWReg(N->getValueType(ResNo)) &&
66  "Unsupported SoftenFloatRes opcode!");
67  // Only when isLegalInHWReg, we can skip check of the operands.
68  R = SDValue(N, ResNo);
69  break;
70  case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
71  case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N, ResNo); break;
72  case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break;
73  case ISD::ConstantFP: R = SoftenFloatRes_ConstantFP(N, ResNo); break;
75  R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break;
76  case ISD::FABS: R = SoftenFloatRes_FABS(N, ResNo); break;
77  case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break;
78  case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break;
79  case ISD::FADD: R = SoftenFloatRes_FADD(N); break;
80  case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break;
81  case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N, ResNo); break;
82  case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break;
83  case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break;
84  case ISD::FEXP: R = SoftenFloatRes_FEXP(N); break;
85  case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break;
86  case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break;
87  case ISD::FLOG: R = SoftenFloatRes_FLOG(N); break;
88  case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break;
89  case ISD::FLOG10: R = SoftenFloatRes_FLOG10(N); break;
90  case ISD::FMA: R = SoftenFloatRes_FMA(N); break;
91  case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break;
92  case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break;
93  case ISD::FNEG: R = SoftenFloatRes_FNEG(N, ResNo); break;
94  case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break;
95  case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break;
96  case ISD::FP16_TO_FP: R = SoftenFloatRes_FP16_TO_FP(N); break;
97  case ISD::FPOW: R = SoftenFloatRes_FPOW(N); break;
98  case ISD::FPOWI: R = SoftenFloatRes_FPOWI(N); break;
99  case ISD::FREM: R = SoftenFloatRes_FREM(N); break;
100  case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break;
101  case ISD::FROUND: R = SoftenFloatRes_FROUND(N); break;
102  case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break;
103  case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break;
104  case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
105  case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break;
106  case ISD::LOAD: R = SoftenFloatRes_LOAD(N, ResNo); break;
107  case ISD::SELECT: R = SoftenFloatRes_SELECT(N, ResNo); break;
108  case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N, ResNo); break;
109  case ISD::SINT_TO_FP:
110  case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break;
111  case ISD::UNDEF: R = SoftenFloatRes_UNDEF(N); break;
112  case ISD::VAARG: R = SoftenFloatRes_VAARG(N); break;
113  }
114 
115  if (R.getNode() && R.getNode() != N) {
116  SetSoftenedFloat(SDValue(N, ResNo), R);
117  // Return true only if the node is changed, assuming that the operands
118  // are also converted when necessary.
119  return true;
120  }
121 
122  // Otherwise, return false to tell caller to scan operands.
123  return false;
124 }
125 
126 SDValue DAGTypeLegalizer::SoftenFloatRes_BITCAST(SDNode *N, unsigned ResNo) {
127  if (isLegalInHWReg(N->getValueType(ResNo)))
128  return SDValue(N, ResNo);
129  return BitConvertToInteger(N->getOperand(0));
130 }
131 
132 SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(SDNode *N,
133  unsigned ResNo) {
134  SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
135  return BitConvertToInteger(Op);
136 }
137 
138 SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
139  // Convert the inputs to integers, and build a new pair out of them.
140  return DAG.getNode(ISD::BUILD_PAIR, SDLoc(N),
141  TLI.getTypeToTransformTo(*DAG.getContext(),
142  N->getValueType(0)),
143  BitConvertToInteger(N->getOperand(0)),
144  BitConvertToInteger(N->getOperand(1)));
145 }
146 
147 SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode *N, unsigned ResNo) {
148  // When LegalInHWReg, we can load better from the constant pool.
149  if (isLegalInHWReg(N->getValueType(ResNo)))
150  return SDValue(N, ResNo);
151  ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
152  // In ppcf128, the high 64 bits are always first in memory regardless
153  // of Endianness. LLVM's APFloat representation is not Endian sensitive,
154  // and so always converts into a 128-bit APInt in a non-Endian-sensitive
155  // way. However, APInt's are serialized in an Endian-sensitive fashion,
156  // so on big-Endian targets, the two doubles are output in the wrong
157  // order. Fix this by manually flipping the order of the high 64 bits
158  // and the low 64 bits here.
159  if (DAG.getDataLayout().isBigEndian() &&
161  uint64_t words[2] = { CN->getValueAPF().bitcastToAPInt().getRawData()[1],
162  CN->getValueAPF().bitcastToAPInt().getRawData()[0] };
163  APInt Val(128, words);
164  return DAG.getConstant(Val, SDLoc(CN),
165  TLI.getTypeToTransformTo(*DAG.getContext(),
166  CN->getValueType(0)));
167  } else {
168  return DAG.getConstant(CN->getValueAPF().bitcastToAPInt(), SDLoc(CN),
169  TLI.getTypeToTransformTo(*DAG.getContext(),
170  CN->getValueType(0)));
171  }
172 }
173 
174 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo) {
175  // When LegalInHWReg, keep the extracted value in register.
176  if (isLegalInHWReg(N->getValueType(ResNo)))
177  return SDValue(N, ResNo);
178  SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
179  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
181  NewOp, N->getOperand(1));
182 }
183 
184 SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N, unsigned ResNo) {
185  // When LegalInHWReg, FABS can be implemented as native bitwise operations.
186  if (isLegalInHWReg(N->getValueType(ResNo)))
187  return SDValue(N, ResNo);
188  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
189  unsigned Size = NVT.getSizeInBits();
190 
191  // Mask = ~(1 << (Size-1))
192  APInt API = APInt::getAllOnesValue(Size);
193  API.clearBit(Size - 1);
194  SDValue Mask = DAG.getConstant(API, SDLoc(N), NVT);
195  SDValue Op = GetSoftenedFloat(N->getOperand(0));
196  return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
197 }
198 
199 SDValue DAGTypeLegalizer::SoftenFloatRes_FMINNUM(SDNode *N) {
200  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
201  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
202  GetSoftenedFloat(N->getOperand(1)) };
203  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
204  RTLIB::FMIN_F32,
205  RTLIB::FMIN_F64,
206  RTLIB::FMIN_F80,
207  RTLIB::FMIN_F128,
208  RTLIB::FMIN_PPCF128),
209  NVT, Ops, false, SDLoc(N)).first;
210 }
211 
212 SDValue DAGTypeLegalizer::SoftenFloatRes_FMAXNUM(SDNode *N) {
213  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
214  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
215  GetSoftenedFloat(N->getOperand(1)) };
216  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
217  RTLIB::FMAX_F32,
218  RTLIB::FMAX_F64,
219  RTLIB::FMAX_F80,
220  RTLIB::FMAX_F128,
221  RTLIB::FMAX_PPCF128),
222  NVT, Ops, false, SDLoc(N)).first;
223 }
224 
225 SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
226  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
227  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
228  GetSoftenedFloat(N->getOperand(1)) };
229  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
230  RTLIB::ADD_F32,
231  RTLIB::ADD_F64,
232  RTLIB::ADD_F80,
233  RTLIB::ADD_F128,
234  RTLIB::ADD_PPCF128),
235  NVT, Ops, false, SDLoc(N)).first;
236 }
237 
238 SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) {
239  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
240  SDValue Op = GetSoftenedFloat(N->getOperand(0));
241  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
242  RTLIB::CEIL_F32,
243  RTLIB::CEIL_F64,
244  RTLIB::CEIL_F80,
245  RTLIB::CEIL_F128,
246  RTLIB::CEIL_PPCF128),
247  NVT, Op, false, SDLoc(N)).first;
248 }
249 
250 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N, unsigned ResNo) {
251  // When LegalInHWReg, FCOPYSIGN can be implemented as native bitwise operations.
252  if (isLegalInHWReg(N->getValueType(ResNo)))
253  return SDValue(N, ResNo);
254  SDValue LHS = GetSoftenedFloat(N->getOperand(0));
255  SDValue RHS = BitConvertToInteger(N->getOperand(1));
256  SDLoc dl(N);
257 
258  EVT LVT = LHS.getValueType();
259  EVT RVT = RHS.getValueType();
260 
261  unsigned LSize = LVT.getSizeInBits();
262  unsigned RSize = RVT.getSizeInBits();
263 
264  // First get the sign bit of second operand.
265  SDValue SignBit = DAG.getNode(
266  ISD::SHL, dl, RVT, DAG.getConstant(1, dl, RVT),
267  DAG.getConstant(RSize - 1, dl,
268  TLI.getShiftAmountTy(RVT, DAG.getDataLayout())));
269  SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit);
270 
271  // Shift right or sign-extend it if the two operands have different types.
272  int SizeDiff = RVT.getSizeInBits() - LVT.getSizeInBits();
273  if (SizeDiff > 0) {
274  SignBit =
275  DAG.getNode(ISD::SRL, dl, RVT, SignBit,
276  DAG.getConstant(SizeDiff, dl,
277  TLI.getShiftAmountTy(SignBit.getValueType(),
278  DAG.getDataLayout())));
279  SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit);
280  } else if (SizeDiff < 0) {
281  SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit);
282  SignBit =
283  DAG.getNode(ISD::SHL, dl, LVT, SignBit,
284  DAG.getConstant(-SizeDiff, dl,
285  TLI.getShiftAmountTy(SignBit.getValueType(),
286  DAG.getDataLayout())));
287  }
288 
289  // Clear the sign bit of the first operand.
290  SDValue Mask = DAG.getNode(
291  ISD::SHL, dl, LVT, DAG.getConstant(1, dl, LVT),
292  DAG.getConstant(LSize - 1, dl,
293  TLI.getShiftAmountTy(LVT, DAG.getDataLayout())));
294  Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, dl, LVT));
295  LHS = DAG.getNode(ISD::AND, dl, LVT, LHS, Mask);
296 
297  // Or the value with the sign bit.
298  return DAG.getNode(ISD::OR, dl, LVT, LHS, SignBit);
299 }
300 
301 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N) {
302  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
303  SDValue Op = GetSoftenedFloat(N->getOperand(0));
304  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
305  RTLIB::COS_F32,
306  RTLIB::COS_F64,
307  RTLIB::COS_F80,
308  RTLIB::COS_F128,
309  RTLIB::COS_PPCF128),
310  NVT, Op, false, SDLoc(N)).first;
311 }
312 
313 SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
314  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
315  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
316  GetSoftenedFloat(N->getOperand(1)) };
317  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
318  RTLIB::DIV_F32,
319  RTLIB::DIV_F64,
320  RTLIB::DIV_F80,
321  RTLIB::DIV_F128,
322  RTLIB::DIV_PPCF128),
323  NVT, Ops, false, SDLoc(N)).first;
324 }
325 
326 SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP(SDNode *N) {
327  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
328  SDValue Op = GetSoftenedFloat(N->getOperand(0));
329  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
330  RTLIB::EXP_F32,
331  RTLIB::EXP_F64,
332  RTLIB::EXP_F80,
333  RTLIB::EXP_F128,
334  RTLIB::EXP_PPCF128),
335  NVT, Op, false, SDLoc(N)).first;
336 }
337 
338 SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP2(SDNode *N) {
339  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
340  SDValue Op = GetSoftenedFloat(N->getOperand(0));
341  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
342  RTLIB::EXP2_F32,
343  RTLIB::EXP2_F64,
344  RTLIB::EXP2_F80,
345  RTLIB::EXP2_F128,
346  RTLIB::EXP2_PPCF128),
347  NVT, Op, false, SDLoc(N)).first;
348 }
349 
350 SDValue DAGTypeLegalizer::SoftenFloatRes_FFLOOR(SDNode *N) {
351  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
352  SDValue Op = GetSoftenedFloat(N->getOperand(0));
353  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
354  RTLIB::FLOOR_F32,
355  RTLIB::FLOOR_F64,
356  RTLIB::FLOOR_F80,
357  RTLIB::FLOOR_F128,
358  RTLIB::FLOOR_PPCF128),
359  NVT, Op, false, SDLoc(N)).first;
360 }
361 
362 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG(SDNode *N) {
363  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
364  SDValue Op = GetSoftenedFloat(N->getOperand(0));
365  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
366  RTLIB::LOG_F32,
367  RTLIB::LOG_F64,
368  RTLIB::LOG_F80,
369  RTLIB::LOG_F128,
370  RTLIB::LOG_PPCF128),
371  NVT, Op, false, SDLoc(N)).first;
372 }
373 
374 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG2(SDNode *N) {
375  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
376  SDValue Op = GetSoftenedFloat(N->getOperand(0));
377  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
378  RTLIB::LOG2_F32,
379  RTLIB::LOG2_F64,
380  RTLIB::LOG2_F80,
381  RTLIB::LOG2_F128,
382  RTLIB::LOG2_PPCF128),
383  NVT, Op, false, SDLoc(N)).first;
384 }
385 
386 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG10(SDNode *N) {
387  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
388  SDValue Op = GetSoftenedFloat(N->getOperand(0));
389  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
390  RTLIB::LOG10_F32,
391  RTLIB::LOG10_F64,
392  RTLIB::LOG10_F80,
393  RTLIB::LOG10_F128,
394  RTLIB::LOG10_PPCF128),
395  NVT, Op, false, SDLoc(N)).first;
396 }
397 
398 SDValue DAGTypeLegalizer::SoftenFloatRes_FMA(SDNode *N) {
399  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
400  SDValue Ops[3] = { GetSoftenedFloat(N->getOperand(0)),
401  GetSoftenedFloat(N->getOperand(1)),
402  GetSoftenedFloat(N->getOperand(2)) };
403  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
404  RTLIB::FMA_F32,
405  RTLIB::FMA_F64,
406  RTLIB::FMA_F80,
407  RTLIB::FMA_F128,
408  RTLIB::FMA_PPCF128),
409  NVT, Ops, false, SDLoc(N)).first;
410 }
411 
412 SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
413  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
414  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
415  GetSoftenedFloat(N->getOperand(1)) };
416  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
417  RTLIB::MUL_F32,
418  RTLIB::MUL_F64,
419  RTLIB::MUL_F80,
420  RTLIB::MUL_F128,
421  RTLIB::MUL_PPCF128),
422  NVT, Ops, false, SDLoc(N)).first;
423 }
424 
425 SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(SDNode *N) {
426  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
427  SDValue Op = GetSoftenedFloat(N->getOperand(0));
428  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
429  RTLIB::NEARBYINT_F32,
430  RTLIB::NEARBYINT_F64,
431  RTLIB::NEARBYINT_F80,
432  RTLIB::NEARBYINT_F128,
433  RTLIB::NEARBYINT_PPCF128),
434  NVT, Op, false, SDLoc(N)).first;
435 }
436 
437 SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N, unsigned ResNo) {
438  // When LegalInHWReg, FNEG can be implemented as native bitwise operations.
439  if (isLegalInHWReg(N->getValueType(ResNo)))
440  return SDValue(N, ResNo);
441  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
442  SDLoc dl(N);
443  // Expand Y = FNEG(X) -> Y = SUB -0.0, X
444  SDValue Ops[2] = { DAG.getConstantFP(-0.0, dl, N->getValueType(0)),
445  GetSoftenedFloat(N->getOperand(0)) };
446  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
447  RTLIB::SUB_F32,
448  RTLIB::SUB_F64,
449  RTLIB::SUB_F80,
450  RTLIB::SUB_F128,
451  RTLIB::SUB_PPCF128),
452  NVT, Ops, false, dl).first;
453 }
454 
455 SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
456  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
457  SDValue Op = N->getOperand(0);
458 
459  // There's only a libcall for f16 -> f32, so proceed in two stages. Also, it's
460  // entirely possible for both f16 and f32 to be legal, so use the fully
461  // hard-float FP_EXTEND rather than FP16_TO_FP.
462  if (Op.getValueType() == MVT::f16 && N->getValueType(0) != MVT::f32) {
463  Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op);
464  if (getTypeAction(MVT::f32) == TargetLowering::TypeSoftenFloat)
465  AddToWorklist(Op.getNode());
466  }
467 
468  if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat) {
469  Op = GetPromotedFloat(Op);
470  // If the promotion did the FP_EXTEND to the destination type for us,
471  // there's nothing left to do here.
472  if (Op.getValueType() == N->getValueType(0)) {
473  return BitConvertToInteger(Op);
474  }
475  }
476 
478  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
479  return TLI.makeLibCall(DAG, LC, NVT, Op, false, SDLoc(N)).first;
480 }
481 
482 // FIXME: Should we just use 'normal' FP_EXTEND / FP_TRUNC instead of special
483 // nodes?
484 SDValue DAGTypeLegalizer::SoftenFloatRes_FP16_TO_FP(SDNode *N) {
485  EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32);
486  SDValue Op = N->getOperand(0);
487  SDValue Res32 = TLI.makeLibCall(DAG, RTLIB::FPEXT_F16_F32, MidVT, Op,
488  false, SDLoc(N)).first;
489  if (N->getValueType(0) == MVT::f32)
490  return Res32;
491 
492  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
494  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
495  return TLI.makeLibCall(DAG, LC, NVT, Res32, false, SDLoc(N)).first;
496 }
497 
498 SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
499  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
500  SDValue Op = N->getOperand(0);
501  if (N->getValueType(0) == MVT::f16) {
502  // Semi-soften first, to FP_TO_FP16, so that targets which support f16 as a
503  // storage-only type get a chance to select things.
504  return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, Op);
505  }
506 
508  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
509  return TLI.makeLibCall(DAG, LC, NVT, Op, false, SDLoc(N)).first;
510 }
511 
512 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOW(SDNode *N) {
513  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
514  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
515  GetSoftenedFloat(N->getOperand(1)) };
516  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
517  RTLIB::POW_F32,
518  RTLIB::POW_F64,
519  RTLIB::POW_F80,
520  RTLIB::POW_F128,
521  RTLIB::POW_PPCF128),
522  NVT, Ops, false, SDLoc(N)).first;
523 }
524 
525 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
526  assert(N->getOperand(1).getValueType() == MVT::i32 &&
527  "Unsupported power type!");
528  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
529  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
530  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
531  RTLIB::POWI_F32,
532  RTLIB::POWI_F64,
533  RTLIB::POWI_F80,
534  RTLIB::POWI_F128,
535  RTLIB::POWI_PPCF128),
536  NVT, Ops, false, SDLoc(N)).first;
537 }
538 
539 SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) {
540  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
541  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
542  GetSoftenedFloat(N->getOperand(1)) };
543  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
544  RTLIB::REM_F32,
545  RTLIB::REM_F64,
546  RTLIB::REM_F80,
547  RTLIB::REM_F128,
548  RTLIB::REM_PPCF128),
549  NVT, Ops, false, SDLoc(N)).first;
550 }
551 
552 SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) {
553  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
554  SDValue Op = GetSoftenedFloat(N->getOperand(0));
555  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
556  RTLIB::RINT_F32,
557  RTLIB::RINT_F64,
558  RTLIB::RINT_F80,
559  RTLIB::RINT_F128,
560  RTLIB::RINT_PPCF128),
561  NVT, Op, false, SDLoc(N)).first;
562 }
563 
564 SDValue DAGTypeLegalizer::SoftenFloatRes_FROUND(SDNode *N) {
565  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
566  SDValue Op = GetSoftenedFloat(N->getOperand(0));
567  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
568  RTLIB::ROUND_F32,
569  RTLIB::ROUND_F64,
570  RTLIB::ROUND_F80,
571  RTLIB::ROUND_F128,
572  RTLIB::ROUND_PPCF128),
573  NVT, Op, false, SDLoc(N)).first;
574 }
575 
576 SDValue DAGTypeLegalizer::SoftenFloatRes_FSIN(SDNode *N) {
577  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
578  SDValue Op = GetSoftenedFloat(N->getOperand(0));
579  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
580  RTLIB::SIN_F32,
581  RTLIB::SIN_F64,
582  RTLIB::SIN_F80,
583  RTLIB::SIN_F128,
584  RTLIB::SIN_PPCF128),
585  NVT, Op, false, SDLoc(N)).first;
586 }
587 
588 SDValue DAGTypeLegalizer::SoftenFloatRes_FSQRT(SDNode *N) {
589  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
590  SDValue Op = GetSoftenedFloat(N->getOperand(0));
591  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
592  RTLIB::SQRT_F32,
593  RTLIB::SQRT_F64,
594  RTLIB::SQRT_F80,
595  RTLIB::SQRT_F128,
596  RTLIB::SQRT_PPCF128),
597  NVT, Op, false, SDLoc(N)).first;
598 }
599 
600 SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
601  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
602  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
603  GetSoftenedFloat(N->getOperand(1)) };
604  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
605  RTLIB::SUB_F32,
606  RTLIB::SUB_F64,
607  RTLIB::SUB_F80,
608  RTLIB::SUB_F128,
609  RTLIB::SUB_PPCF128),
610  NVT, Ops, false, SDLoc(N)).first;
611 }
612 
613 SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) {
614  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
615  if (N->getValueType(0) == MVT::f16)
616  return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, N->getOperand(0));
617 
618  SDValue Op = GetSoftenedFloat(N->getOperand(0));
619  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
620  RTLIB::TRUNC_F32,
621  RTLIB::TRUNC_F64,
622  RTLIB::TRUNC_F80,
623  RTLIB::TRUNC_F128,
624  RTLIB::TRUNC_PPCF128),
625  NVT, Op, false, SDLoc(N)).first;
626 }
627 
628 SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N, unsigned ResNo) {
629  bool LegalInHWReg = isLegalInHWReg(N->getValueType(ResNo));
630  LoadSDNode *L = cast<LoadSDNode>(N);
631  EVT VT = N->getValueType(0);
632  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
633  SDLoc dl(N);
634 
635  auto MMOFlags =
636  L->getMemOperand()->getFlags() &
638  SDValue NewL;
639  if (L->getExtensionType() == ISD::NON_EXTLOAD) {
640  NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), NVT, dl,
641  L->getChain(), L->getBasePtr(), L->getOffset(),
642  L->getPointerInfo(), NVT, L->getAlignment(), MMOFlags,
643  L->getAAInfo());
644  // Legalized the chain result - switch anything that used the old chain to
645  // use the new one.
646  if (N != NewL.getValue(1).getNode())
647  ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
648  return NewL;
649  }
650 
651  // Do a non-extending load followed by FP_EXTEND.
652  NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD, L->getMemoryVT(),
653  dl, L->getChain(), L->getBasePtr(), L->getOffset(),
654  L->getPointerInfo(), L->getMemoryVT(), L->getAlignment(),
655  MMOFlags, L->getAAInfo());
656  // Legalized the chain result - switch anything that used the old chain to
657  // use the new one.
658  ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
659  auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL);
660  if (LegalInHWReg)
661  return ExtendNode;
662  return BitConvertToInteger(ExtendNode);
663 }
664 
665 SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT(SDNode *N, unsigned ResNo) {
666  if (isLegalInHWReg(N->getValueType(ResNo)))
667  return SDValue(N, ResNo);
668  SDValue LHS = GetSoftenedFloat(N->getOperand(1));
669  SDValue RHS = GetSoftenedFloat(N->getOperand(2));
670  return DAG.getSelect(SDLoc(N),
671  LHS.getValueType(), N->getOperand(0), LHS, RHS);
672 }
673 
674 SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT_CC(SDNode *N, unsigned ResNo) {
675  if (isLegalInHWReg(N->getValueType(ResNo)))
676  return SDValue(N, ResNo);
677  SDValue LHS = GetSoftenedFloat(N->getOperand(2));
678  SDValue RHS = GetSoftenedFloat(N->getOperand(3));
679  return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
680  LHS.getValueType(), N->getOperand(0),
681  N->getOperand(1), LHS, RHS, N->getOperand(4));
682 }
683 
684 SDValue DAGTypeLegalizer::SoftenFloatRes_UNDEF(SDNode *N) {
685  return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
686  N->getValueType(0)));
687 }
688 
689 SDValue DAGTypeLegalizer::SoftenFloatRes_VAARG(SDNode *N) {
690  SDValue Chain = N->getOperand(0); // Get the chain.
691  SDValue Ptr = N->getOperand(1); // Get the pointer.
692  EVT VT = N->getValueType(0);
693  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
694  SDLoc dl(N);
695 
696  SDValue NewVAARG;
697  NewVAARG = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2),
698  N->getConstantOperandVal(3));
699 
700  // Legalized the chain result - switch anything that used the old chain to
701  // use the new one.
702  if (N != NewVAARG.getValue(1).getNode())
703  ReplaceValueWith(SDValue(N, 1), NewVAARG.getValue(1));
704  return NewVAARG;
705 }
706 
707 SDValue DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP(SDNode *N) {
708  bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
709  EVT SVT = N->getOperand(0).getValueType();
710  EVT RVT = N->getValueType(0);
711  EVT NVT = EVT();
712  SDLoc dl(N);
713 
714  // If the input is not legal, eg: i1 -> fp, then it needs to be promoted to
715  // a larger type, eg: i8 -> fp. Even if it is legal, no libcall may exactly
716  // match. Look for an appropriate libcall.
717  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
718  for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
719  t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
720  NVT = (MVT::SimpleValueType)t;
721  // The source needs to big enough to hold the operand.
722  if (NVT.bitsGE(SVT))
723  LC = Signed ? RTLIB::getSINTTOFP(NVT, RVT):RTLIB::getUINTTOFP (NVT, RVT);
724  }
725  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
726 
727  // Sign/zero extend the argument if the libcall takes a larger type.
728  SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
729  NVT, N->getOperand(0));
730  return TLI.makeLibCall(DAG, LC,
731  TLI.getTypeToTransformTo(*DAG.getContext(), RVT),
732  Op, Signed, dl).first;
733 }
734 
735 
736 //===----------------------------------------------------------------------===//
737 // Convert Float Operand to Integer for Non-HW-supported Operations.
738 //===----------------------------------------------------------------------===//
739 
740 bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
741  DEBUG(dbgs() << "Soften float operand " << OpNo << ": "; N->dump(&DAG);
742  dbgs() << "\n");
743  SDValue Res = SDValue();
744 
745  switch (N->getOpcode()) {
746  default:
747  if (CanSkipSoftenFloatOperand(N, OpNo))
748  return false;
749 #ifndef NDEBUG
750  dbgs() << "SoftenFloatOperand Op #" << OpNo << ": ";
751  N->dump(&DAG); dbgs() << "\n";
752 #endif
753  llvm_unreachable("Do not know how to soften this operator's operand!");
754 
755  case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break;
756  case ISD::CopyToReg: Res = SoftenFloatOp_COPY_TO_REG(N); break;
757  case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break;
758  case ISD::FABS: Res = SoftenFloatOp_FABS(N); break;
759  case ISD::FCOPYSIGN: Res = SoftenFloatOp_FCOPYSIGN(N); break;
760  case ISD::FNEG: Res = SoftenFloatOp_FNEG(N); break;
761  case ISD::FP_EXTEND: Res = SoftenFloatOp_FP_EXTEND(N); break;
762  case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes
763  case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break;
764  case ISD::FP_TO_SINT:
765  case ISD::FP_TO_UINT: Res = SoftenFloatOp_FP_TO_XINT(N); break;
766  case ISD::SELECT: Res = SoftenFloatOp_SELECT(N); break;
767  case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break;
768  case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
769  case ISD::STORE:
770  Res = SoftenFloatOp_STORE(N, OpNo);
771  // Do not try to analyze or soften this node again if the value is
772  // or can be held in a register. In that case, Res.getNode() should
773  // be equal to N.
774  if (Res.getNode() == N &&
775  isLegalInHWReg(N->getOperand(OpNo).getValueType()))
776  return false;
777  // Otherwise, we need to reanalyze and lower the new Res nodes.
778  break;
779  }
780 
781  // If the result is null, the sub-method took care of registering results etc.
782  if (!Res.getNode()) return false;
783 
784  // If the result is N, the sub-method updated N in place. Tell the legalizer
785  // core about this to re-analyze.
786  if (Res.getNode() == N)
787  return true;
788 
789  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
790  "Invalid operand expansion");
791 
792  ReplaceValueWith(SDValue(N, 0), Res);
793  return false;
794 }
795 
796 bool DAGTypeLegalizer::CanSkipSoftenFloatOperand(SDNode *N, unsigned OpNo) {
797  if (!isLegalInHWReg(N->getOperand(OpNo).getValueType()))
798  return false;
799 
800  // When the operand type can be kept in registers there is nothing to do for
801  // the following opcodes.
802  switch (N->getOperand(OpNo).getOpcode()) {
803  case ISD::BITCAST:
804  case ISD::ConstantFP:
805  case ISD::CopyFromReg:
806  case ISD::CopyToReg:
807  case ISD::FABS:
808  case ISD::FCOPYSIGN:
809  case ISD::FNEG:
810  case ISD::Register:
811  case ISD::SELECT:
812  case ISD::SELECT_CC:
813  return true;
814  }
815 
816  switch (N->getOpcode()) {
817  case ISD::ConstantFP: // Leaf node.
818  case ISD::CopyFromReg: // Operand is a register that we know to be left
819  // unchanged by SoftenFloatResult().
820  case ISD::Register: // Leaf node.
821  return true;
822  }
823  return false;
824 }
825 
826 SDValue DAGTypeLegalizer::SoftenFloatOp_BITCAST(SDNode *N) {
827  return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
828  GetSoftenedFloat(N->getOperand(0)));
829 }
830 
831 SDValue DAGTypeLegalizer::SoftenFloatOp_COPY_TO_REG(SDNode *N) {
832  SDValue Op1 = GetSoftenedFloat(N->getOperand(1));
833  SDValue Op2 = GetSoftenedFloat(N->getOperand(2));
834 
835  if (Op1 == N->getOperand(1) && Op2 == N->getOperand(2))
836  return SDValue();
837 
838  if (N->getNumOperands() == 3)
839  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op1, Op2), 0);
840 
841  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op1, Op2,
842  N->getOperand(3)),
843  0);
844 }
845 
846 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_EXTEND(SDNode *N) {
847  // If we get here, the result must be legal but the source illegal.
848  EVT SVT = N->getOperand(0).getValueType();
849  EVT RVT = N->getValueType(0);
850  SDValue Op = GetSoftenedFloat(N->getOperand(0));
851 
852  if (SVT == MVT::f16)
853  return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), RVT, Op);
854 
855  RTLIB::Libcall LC = RTLIB::getFPEXT(SVT, RVT);
856  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND libcall");
857 
858  return TLI.makeLibCall(DAG, LC, RVT, Op, false, SDLoc(N)).first;
859 }
860 
861 
862 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_ROUND(SDNode *N) {
863  // We actually deal with the partially-softened FP_TO_FP16 node too, which
864  // returns an i16 so doesn't meet the constraints necessary for FP_ROUND.
866 
867  EVT SVT = N->getOperand(0).getValueType();
868  EVT RVT = N->getValueType(0);
869  EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT;
870 
871  RTLIB::Libcall LC = RTLIB::getFPROUND(SVT, FloatRVT);
872  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND libcall");
873 
874  SDValue Op = GetSoftenedFloat(N->getOperand(0));
875  return TLI.makeLibCall(DAG, LC, RVT, Op, false, SDLoc(N)).first;
876 }
877 
878 SDValue DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) {
879  SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
880  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
881 
882  EVT VT = NewLHS.getValueType();
883  NewLHS = GetSoftenedFloat(NewLHS);
884  NewRHS = GetSoftenedFloat(NewRHS);
885  TLI.softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, SDLoc(N));
886 
887  // If softenSetCCOperands returned a scalar, we need to compare the result
888  // against zero to select between true and false values.
889  if (!NewRHS.getNode()) {
890  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
891  CCCode = ISD::SETNE;
892  }
893 
894  // Update N to have the operands specified.
895  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
896  DAG.getCondCode(CCCode), NewLHS, NewRHS,
897  N->getOperand(4)),
898  0);
899 }
900 
901 SDValue DAGTypeLegalizer::SoftenFloatOp_FABS(SDNode *N) {
902  SDValue Op = GetSoftenedFloat(N->getOperand(0));
903 
904  if (Op == N->getOperand(0))
905  return SDValue();
906 
907  return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
908 }
909 
910 SDValue DAGTypeLegalizer::SoftenFloatOp_FCOPYSIGN(SDNode *N) {
911  SDValue Op0 = GetSoftenedFloat(N->getOperand(0));
912  SDValue Op1 = GetSoftenedFloat(N->getOperand(1));
913 
914  if (Op0 == N->getOperand(0) && Op1 == N->getOperand(1))
915  return SDValue();
916 
917  return SDValue(DAG.UpdateNodeOperands(N, Op0, Op1), 0);
918 }
919 
920 SDValue DAGTypeLegalizer::SoftenFloatOp_FNEG(SDNode *N) {
921  SDValue Op = GetSoftenedFloat(N->getOperand(0));
922 
923  if (Op == N->getOperand(0))
924  return SDValue();
925 
926  return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
927 }
928 
929 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_XINT(SDNode *N) {
930  bool Signed = N->getOpcode() == ISD::FP_TO_SINT;
931  EVT SVT = N->getOperand(0).getValueType();
932  EVT RVT = N->getValueType(0);
933  EVT NVT = EVT();
934  SDLoc dl(N);
935 
936  // If the result is not legal, eg: fp -> i1, then it needs to be promoted to
937  // a larger type, eg: fp -> i32. Even if it is legal, no libcall may exactly
938  // match, eg. we don't have fp -> i8 conversions.
939  // Look for an appropriate libcall.
940  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
941  for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE;
942  IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL;
943  ++IntVT) {
944  NVT = (MVT::SimpleValueType)IntVT;
945  // The type needs to big enough to hold the result.
946  if (NVT.bitsGE(RVT))
947  LC = Signed ? RTLIB::getFPTOSINT(SVT, NVT):RTLIB::getFPTOUINT(SVT, NVT);
948  }
949  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_XINT!");
950 
951  SDValue Op = GetSoftenedFloat(N->getOperand(0));
952  SDValue Res = TLI.makeLibCall(DAG, LC, NVT, Op, false, dl).first;
953 
954  // Truncate the result if the libcall returns a larger type.
955  return DAG.getNode(ISD::TRUNCATE, dl, RVT, Res);
956 }
957 
958 SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT(SDNode *N) {
959  SDValue Op1 = GetSoftenedFloat(N->getOperand(1));
960  SDValue Op2 = GetSoftenedFloat(N->getOperand(2));
961 
962  if (Op1 == N->getOperand(1) && Op2 == N->getOperand(2))
963  return SDValue();
964 
965  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op1, Op2),
966  0);
967 }
968 
969 SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(SDNode *N) {
970  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
971  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
972 
973  EVT VT = NewLHS.getValueType();
974  NewLHS = GetSoftenedFloat(NewLHS);
975  NewRHS = GetSoftenedFloat(NewRHS);
976  TLI.softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, SDLoc(N));
977 
978  // If softenSetCCOperands returned a scalar, we need to compare the result
979  // against zero to select between true and false values.
980  if (!NewRHS.getNode()) {
981  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
982  CCCode = ISD::SETNE;
983  }
984 
985  // Update N to have the operands specified.
986  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
987  N->getOperand(2), N->getOperand(3),
988  DAG.getCondCode(CCCode)),
989  0);
990 }
991 
992 SDValue DAGTypeLegalizer::SoftenFloatOp_SETCC(SDNode *N) {
993  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
994  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
995 
996  EVT VT = NewLHS.getValueType();
997  NewLHS = GetSoftenedFloat(NewLHS);
998  NewRHS = GetSoftenedFloat(NewRHS);
999  TLI.softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, SDLoc(N));
1000 
1001  // If softenSetCCOperands returned a scalar, use it.
1002  if (!NewRHS.getNode()) {
1003  assert(NewLHS.getValueType() == N->getValueType(0) &&
1004  "Unexpected setcc expansion!");
1005  return NewLHS;
1006  }
1007 
1008  // Otherwise, update N to have the operands specified.
1009  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
1010  DAG.getCondCode(CCCode)),
1011  0);
1012 }
1013 
1014 SDValue DAGTypeLegalizer::SoftenFloatOp_STORE(SDNode *N, unsigned OpNo) {
1015  assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1016  assert(OpNo == 1 && "Can only soften the stored value!");
1017  StoreSDNode *ST = cast<StoreSDNode>(N);
1018  SDValue Val = ST->getValue();
1019  SDLoc dl(N);
1020 
1021  if (ST->isTruncatingStore())
1022  // Do an FP_ROUND followed by a non-truncating store.
1023  Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(),
1024  Val, DAG.getIntPtrConstant(0, dl)));
1025  else
1026  Val = GetSoftenedFloat(Val);
1027 
1028  return DAG.getStore(ST->getChain(), dl, Val, ST->getBasePtr(),
1029  ST->getMemOperand());
1030 }
1031 
1032 
1033 //===----------------------------------------------------------------------===//
1034 // Float Result Expansion
1035 //===----------------------------------------------------------------------===//
1036 
1037 /// ExpandFloatResult - This method is called when the specified result of the
1038 /// specified node is found to need expansion. At this point, the node may also
1039 /// have invalid operands or may have other results that need promotion, we just
1040 /// know that (at least) one result needs expansion.
1041 void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
1042  DEBUG(dbgs() << "Expand float result: "; N->dump(&DAG); dbgs() << "\n");
1043  SDValue Lo, Hi;
1044  Lo = Hi = SDValue();
1045 
1046  // See if the target wants to custom expand this node.
1047  if (CustomLowerNode(N, N->getValueType(ResNo), true))
1048  return;
1049 
1050  switch (N->getOpcode()) {
1051  default:
1052 #ifndef NDEBUG
1053  dbgs() << "ExpandFloatResult #" << ResNo << ": ";
1054  N->dump(&DAG); dbgs() << "\n";
1055 #endif
1056  llvm_unreachable("Do not know how to expand the result of this operator!");
1057 
1058  case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1059  case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1060  case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1061 
1062  case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1063  case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1064  case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1065  case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1066  case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1067  case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1068 
1069  case ISD::ConstantFP: ExpandFloatRes_ConstantFP(N, Lo, Hi); break;
1070  case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break;
1071  case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break;
1072  case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break;
1073  case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break;
1074  case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break;
1075  case ISD::FCOPYSIGN: ExpandFloatRes_FCOPYSIGN(N, Lo, Hi); break;
1076  case ISD::FCOS: ExpandFloatRes_FCOS(N, Lo, Hi); break;
1077  case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break;
1078  case ISD::FEXP: ExpandFloatRes_FEXP(N, Lo, Hi); break;
1079  case ISD::FEXP2: ExpandFloatRes_FEXP2(N, Lo, Hi); break;
1080  case ISD::FFLOOR: ExpandFloatRes_FFLOOR(N, Lo, Hi); break;
1081  case ISD::FLOG: ExpandFloatRes_FLOG(N, Lo, Hi); break;
1082  case ISD::FLOG2: ExpandFloatRes_FLOG2(N, Lo, Hi); break;
1083  case ISD::FLOG10: ExpandFloatRes_FLOG10(N, Lo, Hi); break;
1084  case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi); break;
1085  case ISD::FMUL: ExpandFloatRes_FMUL(N, Lo, Hi); break;
1086  case ISD::FNEARBYINT: ExpandFloatRes_FNEARBYINT(N, Lo, Hi); break;
1087  case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break;
1088  case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break;
1089  case ISD::FPOW: ExpandFloatRes_FPOW(N, Lo, Hi); break;
1090  case ISD::FPOWI: ExpandFloatRes_FPOWI(N, Lo, Hi); break;
1091  case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break;
1092  case ISD::FROUND: ExpandFloatRes_FROUND(N, Lo, Hi); break;
1093  case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break;
1094  case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break;
1095  case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
1096  case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break;
1097  case ISD::LOAD: ExpandFloatRes_LOAD(N, Lo, Hi); break;
1098  case ISD::SINT_TO_FP:
1099  case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break;
1100  case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break;
1101  }
1102 
1103  // If Lo/Hi is null, the sub-method took care of registering results etc.
1104  if (Lo.getNode())
1105  SetExpandedFloat(SDValue(N, ResNo), Lo, Hi);
1106 }
1107 
1108 void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo,
1109  SDValue &Hi) {
1110  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1111  assert(NVT.getSizeInBits() == 64 &&
1112  "Do not know how to expand this float constant!");
1113  APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().bitcastToAPInt();
1114  SDLoc dl(N);
1115  Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1116  APInt(64, C.getRawData()[1])),
1117  dl, NVT);
1118  Hi = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1119  APInt(64, C.getRawData()[0])),
1120  dl, NVT);
1121 }
1122 
1123 void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
1124  SDValue &Hi) {
1125  assert(N->getValueType(0) == MVT::ppcf128 &&
1126  "Logic only correct for ppcf128!");
1127  SDLoc dl(N);
1128  SDValue Tmp;
1129  GetExpandedFloat(N->getOperand(0), Lo, Tmp);
1130  Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp);
1131  // Lo = Hi==fabs(Hi) ? Lo : -Lo;
1132  Lo = DAG.getSelectCC(dl, Tmp, Hi, Lo,
1133  DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo),
1134  ISD::SETEQ);
1135 }
1136 
1137 void DAGTypeLegalizer::ExpandFloatRes_FMINNUM(SDNode *N, SDValue &Lo,
1138  SDValue &Hi) {
1139  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1140  RTLIB::FMIN_F32, RTLIB::FMIN_F64,
1141  RTLIB::FMIN_F80, RTLIB::FMIN_F128,
1142  RTLIB::FMIN_PPCF128),
1143  N, false);
1144  GetPairElements(Call, Lo, Hi);
1145 }
1146 
1147 void DAGTypeLegalizer::ExpandFloatRes_FMAXNUM(SDNode *N, SDValue &Lo,
1148  SDValue &Hi) {
1149  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1150  RTLIB::FMAX_F32, RTLIB::FMAX_F64,
1151  RTLIB::FMAX_F80, RTLIB::FMAX_F128,
1152  RTLIB::FMAX_PPCF128),
1153  N, false);
1154  GetPairElements(Call, Lo, Hi);
1155 }
1156 
1157 void DAGTypeLegalizer::ExpandFloatRes_FADD(SDNode *N, SDValue &Lo,
1158  SDValue &Hi) {
1159  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1160  RTLIB::ADD_F32, RTLIB::ADD_F64,
1161  RTLIB::ADD_F80, RTLIB::ADD_F128,
1162  RTLIB::ADD_PPCF128),
1163  N, false);
1164  GetPairElements(Call, Lo, Hi);
1165 }
1166 
1167 void DAGTypeLegalizer::ExpandFloatRes_FCEIL(SDNode *N,
1168  SDValue &Lo, SDValue &Hi) {
1169  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1170  RTLIB::CEIL_F32, RTLIB::CEIL_F64,
1171  RTLIB::CEIL_F80, RTLIB::CEIL_F128,
1172  RTLIB::CEIL_PPCF128),
1173  N, false);
1174  GetPairElements(Call, Lo, Hi);
1175 }
1176 
1177 void DAGTypeLegalizer::ExpandFloatRes_FCOPYSIGN(SDNode *N,
1178  SDValue &Lo, SDValue &Hi) {
1179  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1180  RTLIB::COPYSIGN_F32,
1181  RTLIB::COPYSIGN_F64,
1182  RTLIB::COPYSIGN_F80,
1183  RTLIB::COPYSIGN_F128,
1184  RTLIB::COPYSIGN_PPCF128),
1185  N, false);
1186  GetPairElements(Call, Lo, Hi);
1187 }
1188 
1189 void DAGTypeLegalizer::ExpandFloatRes_FCOS(SDNode *N,
1190  SDValue &Lo, SDValue &Hi) {
1191  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1192  RTLIB::COS_F32, RTLIB::COS_F64,
1193  RTLIB::COS_F80, RTLIB::COS_F128,
1194  RTLIB::COS_PPCF128),
1195  N, false);
1196  GetPairElements(Call, Lo, Hi);
1197 }
1198 
1199 void DAGTypeLegalizer::ExpandFloatRes_FDIV(SDNode *N, SDValue &Lo,
1200  SDValue &Hi) {
1201  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1202  SDValue Call = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
1203  RTLIB::DIV_F32,
1204  RTLIB::DIV_F64,
1205  RTLIB::DIV_F80,
1206  RTLIB::DIV_F128,
1207  RTLIB::DIV_PPCF128),
1208  N->getValueType(0), Ops, false,
1209  SDLoc(N)).first;
1210  GetPairElements(Call, Lo, Hi);
1211 }
1212 
1213 void DAGTypeLegalizer::ExpandFloatRes_FEXP(SDNode *N,
1214  SDValue &Lo, SDValue &Hi) {
1215  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1216  RTLIB::EXP_F32, RTLIB::EXP_F64,
1217  RTLIB::EXP_F80, RTLIB::EXP_F128,
1218  RTLIB::EXP_PPCF128),
1219  N, false);
1220  GetPairElements(Call, Lo, Hi);
1221 }
1222 
1223 void DAGTypeLegalizer::ExpandFloatRes_FEXP2(SDNode *N,
1224  SDValue &Lo, SDValue &Hi) {
1225  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1226  RTLIB::EXP2_F32, RTLIB::EXP2_F64,
1227  RTLIB::EXP2_F80, RTLIB::EXP2_F128,
1228  RTLIB::EXP2_PPCF128),
1229  N, false);
1230  GetPairElements(Call, Lo, Hi);
1231 }
1232 
1233 void DAGTypeLegalizer::ExpandFloatRes_FFLOOR(SDNode *N,
1234  SDValue &Lo, SDValue &Hi) {
1235  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1236  RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
1237  RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
1238  RTLIB::FLOOR_PPCF128),
1239  N, false);
1240  GetPairElements(Call, Lo, Hi);
1241 }
1242 
1243 void DAGTypeLegalizer::ExpandFloatRes_FLOG(SDNode *N,
1244  SDValue &Lo, SDValue &Hi) {
1245  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1246  RTLIB::LOG_F32, RTLIB::LOG_F64,
1247  RTLIB::LOG_F80, RTLIB::LOG_F128,
1248  RTLIB::LOG_PPCF128),
1249  N, false);
1250  GetPairElements(Call, Lo, Hi);
1251 }
1252 
1253 void DAGTypeLegalizer::ExpandFloatRes_FLOG2(SDNode *N,
1254  SDValue &Lo, SDValue &Hi) {
1255  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1256  RTLIB::LOG2_F32, RTLIB::LOG2_F64,
1257  RTLIB::LOG2_F80, RTLIB::LOG2_F128,
1258  RTLIB::LOG2_PPCF128),
1259  N, false);
1260  GetPairElements(Call, Lo, Hi);
1261 }
1262 
1263 void DAGTypeLegalizer::ExpandFloatRes_FLOG10(SDNode *N,
1264  SDValue &Lo, SDValue &Hi) {
1265  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1266  RTLIB::LOG10_F32, RTLIB::LOG10_F64,
1267  RTLIB::LOG10_F80, RTLIB::LOG10_F128,
1268  RTLIB::LOG10_PPCF128),
1269  N, false);
1270  GetPairElements(Call, Lo, Hi);
1271 }
1272 
1273 void DAGTypeLegalizer::ExpandFloatRes_FMA(SDNode *N, SDValue &Lo,
1274  SDValue &Hi) {
1275  SDValue Ops[3] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
1276  SDValue Call = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
1277  RTLIB::FMA_F32,
1278  RTLIB::FMA_F64,
1279  RTLIB::FMA_F80,
1280  RTLIB::FMA_F128,
1281  RTLIB::FMA_PPCF128),
1282  N->getValueType(0), Ops, false,
1283  SDLoc(N)).first;
1284  GetPairElements(Call, Lo, Hi);
1285 }
1286 
1287 void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo,
1288  SDValue &Hi) {
1289  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1290  SDValue Call = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
1291  RTLIB::MUL_F32,
1292  RTLIB::MUL_F64,
1293  RTLIB::MUL_F80,
1294  RTLIB::MUL_F128,
1295  RTLIB::MUL_PPCF128),
1296  N->getValueType(0), Ops, false,
1297  SDLoc(N)).first;
1298  GetPairElements(Call, Lo, Hi);
1299 }
1300 
1301 void DAGTypeLegalizer::ExpandFloatRes_FNEARBYINT(SDNode *N,
1302  SDValue &Lo, SDValue &Hi) {
1303  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1304  RTLIB::NEARBYINT_F32,
1305  RTLIB::NEARBYINT_F64,
1306  RTLIB::NEARBYINT_F80,
1307  RTLIB::NEARBYINT_F128,
1308  RTLIB::NEARBYINT_PPCF128),
1309  N, false);
1310  GetPairElements(Call, Lo, Hi);
1311 }
1312 
1313 void DAGTypeLegalizer::ExpandFloatRes_FNEG(SDNode *N, SDValue &Lo,
1314  SDValue &Hi) {
1315  SDLoc dl(N);
1316  GetExpandedFloat(N->getOperand(0), Lo, Hi);
1317  Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo);
1318  Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi);
1319 }
1320 
1321 void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo,
1322  SDValue &Hi) {
1323  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1324  SDLoc dl(N);
1325  Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0));
1326  Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1327  APInt(NVT.getSizeInBits(), 0)), dl, NVT);
1328 }
1329 
1330 void DAGTypeLegalizer::ExpandFloatRes_FPOW(SDNode *N,
1331  SDValue &Lo, SDValue &Hi) {
1332  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1333  RTLIB::POW_F32, RTLIB::POW_F64,
1334  RTLIB::POW_F80, RTLIB::POW_F128,
1335  RTLIB::POW_PPCF128),
1336  N, false);
1337  GetPairElements(Call, Lo, Hi);
1338 }
1339 
1340 void DAGTypeLegalizer::ExpandFloatRes_FPOWI(SDNode *N,
1341  SDValue &Lo, SDValue &Hi) {
1342  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1343  RTLIB::POWI_F32, RTLIB::POWI_F64,
1344  RTLIB::POWI_F80, RTLIB::POWI_F128,
1345  RTLIB::POWI_PPCF128),
1346  N, false);
1347  GetPairElements(Call, Lo, Hi);
1348 }
1349 
1350 void DAGTypeLegalizer::ExpandFloatRes_FREM(SDNode *N,
1351  SDValue &Lo, SDValue &Hi) {
1352  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1353  RTLIB::REM_F32, RTLIB::REM_F64,
1354  RTLIB::REM_F80, RTLIB::REM_F128,
1355  RTLIB::REM_PPCF128),
1356  N, false);
1357  GetPairElements(Call, Lo, Hi);
1358 }
1359 
1360 void DAGTypeLegalizer::ExpandFloatRes_FRINT(SDNode *N,
1361  SDValue &Lo, SDValue &Hi) {
1362  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1363  RTLIB::RINT_F32, RTLIB::RINT_F64,
1364  RTLIB::RINT_F80, RTLIB::RINT_F128,
1365  RTLIB::RINT_PPCF128),
1366  N, false);
1367  GetPairElements(Call, Lo, Hi);
1368 }
1369 
1370 void DAGTypeLegalizer::ExpandFloatRes_FROUND(SDNode *N,
1371  SDValue &Lo, SDValue &Hi) {
1372  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1373  RTLIB::ROUND_F32,
1374  RTLIB::ROUND_F64,
1375  RTLIB::ROUND_F80,
1376  RTLIB::ROUND_F128,
1377  RTLIB::ROUND_PPCF128),
1378  N, false);
1379  GetPairElements(Call, Lo, Hi);
1380 }
1381 
1382 void DAGTypeLegalizer::ExpandFloatRes_FSIN(SDNode *N,
1383  SDValue &Lo, SDValue &Hi) {
1384  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1385  RTLIB::SIN_F32, RTLIB::SIN_F64,
1386  RTLIB::SIN_F80, RTLIB::SIN_F128,
1387  RTLIB::SIN_PPCF128),
1388  N, false);
1389  GetPairElements(Call, Lo, Hi);
1390 }
1391 
1392 void DAGTypeLegalizer::ExpandFloatRes_FSQRT(SDNode *N,
1393  SDValue &Lo, SDValue &Hi) {
1394  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1395  RTLIB::SQRT_F32, RTLIB::SQRT_F64,
1396  RTLIB::SQRT_F80, RTLIB::SQRT_F128,
1397  RTLIB::SQRT_PPCF128),
1398  N, false);
1399  GetPairElements(Call, Lo, Hi);
1400 }
1401 
1402 void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo,
1403  SDValue &Hi) {
1404  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1405  SDValue Call = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
1406  RTLIB::SUB_F32,
1407  RTLIB::SUB_F64,
1408  RTLIB::SUB_F80,
1409  RTLIB::SUB_F128,
1410  RTLIB::SUB_PPCF128),
1411  N->getValueType(0), Ops, false,
1412  SDLoc(N)).first;
1413  GetPairElements(Call, Lo, Hi);
1414 }
1415 
1416 void DAGTypeLegalizer::ExpandFloatRes_FTRUNC(SDNode *N,
1417  SDValue &Lo, SDValue &Hi) {
1418  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1419  RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
1420  RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
1421  RTLIB::TRUNC_PPCF128),
1422  N, false);
1423  GetPairElements(Call, Lo, Hi);
1424 }
1425 
1426 void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo,
1427  SDValue &Hi) {
1428  if (ISD::isNormalLoad(N)) {
1429  ExpandRes_NormalLoad(N, Lo, Hi);
1430  return;
1431  }
1432 
1433  assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1434  LoadSDNode *LD = cast<LoadSDNode>(N);
1435  SDValue Chain = LD->getChain();
1436  SDValue Ptr = LD->getBasePtr();
1437  SDLoc dl(N);
1438 
1439  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), LD->getValueType(0));
1440  assert(NVT.isByteSized() && "Expanded type not byte sized!");
1441  assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?");
1442 
1443  Hi = DAG.getExtLoad(LD->getExtensionType(), dl, NVT, Chain, Ptr,
1444  LD->getMemoryVT(), LD->getMemOperand());
1445 
1446  // Remember the chain.
1447  Chain = Hi.getValue(1);
1448 
1449  // The low part is zero.
1450  Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1451  APInt(NVT.getSizeInBits(), 0)), dl, NVT);
1452 
1453  // Modified the chain - switch anything that used the old chain to use the
1454  // new one.
1455  ReplaceValueWith(SDValue(LD, 1), Chain);
1456 }
1457 
1458 void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
1459  SDValue &Hi) {
1460  assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
1461  EVT VT = N->getValueType(0);
1462  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1463  SDValue Src = N->getOperand(0);
1464  EVT SrcVT = Src.getValueType();
1465  bool isSigned = N->getOpcode() == ISD::SINT_TO_FP;
1466  SDLoc dl(N);
1467 
1468  // First do an SINT_TO_FP, whether the original was signed or unsigned.
1469  // When promoting partial word types to i32 we must honor the signedness,
1470  // though.
1471  if (SrcVT.bitsLE(MVT::i32)) {
1472  // The integer can be represented exactly in an f64.
1473  Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1474  MVT::i32, Src);
1475  Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1476  APInt(NVT.getSizeInBits(), 0)), dl, NVT);
1477  Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src);
1478  } else {
1479  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1480  if (SrcVT.bitsLE(MVT::i64)) {
1481  Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1482  MVT::i64, Src);
1483  LC = RTLIB::SINTTOFP_I64_PPCF128;
1484  } else if (SrcVT.bitsLE(MVT::i128)) {
1485  Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
1486  LC = RTLIB::SINTTOFP_I128_PPCF128;
1487  }
1488  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
1489 
1490  Hi = TLI.makeLibCall(DAG, LC, VT, Src, true, dl).first;
1491  GetPairElements(Hi, Lo, Hi);
1492  }
1493 
1494  if (isSigned)
1495  return;
1496 
1497  // Unsigned - fix up the SINT_TO_FP value just calculated.
1498  Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
1499  SrcVT = Src.getValueType();
1500 
1501  // x>=0 ? (ppcf128)(iN)x : (ppcf128)(iN)x + 2^N; N=32,64,128.
1502  static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
1503  static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
1504  static const uint64_t TwoE128[] = { 0x47f0000000000000LL, 0 };
1505  ArrayRef<uint64_t> Parts;
1506 
1507  switch (SrcVT.getSimpleVT().SimpleTy) {
1508  default:
1509  llvm_unreachable("Unsupported UINT_TO_FP!");
1510  case MVT::i32:
1511  Parts = TwoE32;
1512  break;
1513  case MVT::i64:
1514  Parts = TwoE64;
1515  break;
1516  case MVT::i128:
1517  Parts = TwoE128;
1518  break;
1519  }
1520 
1521  // TODO: Are there fast-math-flags to propagate to this FADD?
1522  Lo = DAG.getNode(ISD::FADD, dl, VT, Hi,
1524  APInt(128, Parts)),
1525  dl, MVT::ppcf128));
1526  Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, dl, SrcVT),
1527  Lo, Hi, ISD::SETLT);
1528  GetPairElements(Lo, Lo, Hi);
1529 }
1530 
1531 
1532 //===----------------------------------------------------------------------===//
1533 // Float Operand Expansion
1534 //===----------------------------------------------------------------------===//
1535 
1536 /// ExpandFloatOperand - This method is called when the specified operand of the
1537 /// specified node is found to need expansion. At this point, all of the result
1538 /// types of the node are known to be legal, but other operands of the node may
1539 /// need promotion or expansion as well as the specified one.
1540 bool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) {
1541  DEBUG(dbgs() << "Expand float operand: "; N->dump(&DAG); dbgs() << "\n");
1542  SDValue Res = SDValue();
1543 
1544  // See if the target wants to custom expand this node.
1545  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1546  return false;
1547 
1548  switch (N->getOpcode()) {
1549  default:
1550 #ifndef NDEBUG
1551  dbgs() << "ExpandFloatOperand Op #" << OpNo << ": ";
1552  N->dump(&DAG); dbgs() << "\n";
1553 #endif
1554  llvm_unreachable("Do not know how to expand this operator's operand!");
1555 
1556  case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
1557  case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1558  case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1559 
1560  case ISD::BR_CC: Res = ExpandFloatOp_BR_CC(N); break;
1561  case ISD::FCOPYSIGN: Res = ExpandFloatOp_FCOPYSIGN(N); break;
1562  case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break;
1563  case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break;
1564  case ISD::FP_TO_UINT: Res = ExpandFloatOp_FP_TO_UINT(N); break;
1565  case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break;
1566  case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break;
1567  case ISD::STORE: Res = ExpandFloatOp_STORE(cast<StoreSDNode>(N),
1568  OpNo); break;
1569  }
1570 
1571  // If the result is null, the sub-method took care of registering results etc.
1572  if (!Res.getNode()) return false;
1573 
1574  // If the result is N, the sub-method updated N in place. Tell the legalizer
1575  // core about this.
1576  if (Res.getNode() == N)
1577  return true;
1578 
1579  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1580  "Invalid operand expansion");
1581 
1582  ReplaceValueWith(SDValue(N, 0), Res);
1583  return false;
1584 }
1585 
1586 /// FloatExpandSetCCOperands - Expand the operands of a comparison. This code
1587 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1588 void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS,
1589  SDValue &NewRHS,
1590  ISD::CondCode &CCCode,
1591  const SDLoc &dl) {
1592  SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1593  GetExpandedFloat(NewLHS, LHSLo, LHSHi);
1594  GetExpandedFloat(NewRHS, RHSLo, RHSHi);
1595 
1596  assert(NewLHS.getValueType() == MVT::ppcf128 && "Unsupported setcc type!");
1597 
1598  // FIXME: This generated code sucks. We want to generate
1599  // FCMPU crN, hi1, hi2
1600  // BNE crN, L:
1601  // FCMPU crN, lo1, lo2
1602  // The following can be improved, but not that much.
1603  SDValue Tmp1, Tmp2, Tmp3;
1604  Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
1605  LHSHi, RHSHi, ISD::SETOEQ);
1606  Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
1607  LHSLo, RHSLo, CCCode);
1608  Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1609  Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
1610  LHSHi, RHSHi, ISD::SETUNE);
1611  Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
1612  LHSHi, RHSHi, CCCode);
1613  Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1614  NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
1615  NewRHS = SDValue(); // LHS is the result, not a compare.
1616 }
1617 
1618 SDValue DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) {
1619  SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1620  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1621  FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
1622 
1623  // If ExpandSetCCOperands returned a scalar, we need to compare the result
1624  // against zero to select between true and false values.
1625  if (!NewRHS.getNode()) {
1626  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
1627  CCCode = ISD::SETNE;
1628  }
1629 
1630  // Update N to have the operands specified.
1631  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1632  DAG.getCondCode(CCCode), NewLHS, NewRHS,
1633  N->getOperand(4)), 0);
1634 }
1635 
1636 SDValue DAGTypeLegalizer::ExpandFloatOp_FCOPYSIGN(SDNode *N) {
1638  "Logic only correct for ppcf128!");
1639  SDValue Lo, Hi;
1640  GetExpandedFloat(N->getOperand(1), Lo, Hi);
1641  // The ppcf128 value is providing only the sign; take it from the
1642  // higher-order double (which must have the larger magnitude).
1643  return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N),
1644  N->getValueType(0), N->getOperand(0), Hi);
1645 }
1646 
1647 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
1649  "Logic only correct for ppcf128!");
1650  SDValue Lo, Hi;
1651  GetExpandedFloat(N->getOperand(0), Lo, Hi);
1652  // Round it the rest of the way (e.g. to f32) if needed.
1653  return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
1654  N->getValueType(0), Hi, N->getOperand(1));
1655 }
1656 
1657 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
1658  EVT RVT = N->getValueType(0);
1659  SDLoc dl(N);
1660 
1661  // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
1662  // PPC (the libcall is not available). FIXME: Do this in a less hacky way.
1663  if (RVT == MVT::i32) {
1665  "Logic only correct for ppcf128!");
1667  N->getOperand(0), DAG.getValueType(MVT::f64));
1668  Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res,
1669  DAG.getIntPtrConstant(1, dl));
1670  return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
1671  }
1672 
1674  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
1675  return TLI.makeLibCall(DAG, LC, RVT, N->getOperand(0), false, dl).first;
1676 }
1677 
1678 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
1679  EVT RVT = N->getValueType(0);
1680  SDLoc dl(N);
1681 
1682  // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
1683  // PPC (the libcall is not available). FIXME: Do this in a less hacky way.
1684  if (RVT == MVT::i32) {
1686  "Logic only correct for ppcf128!");
1687  const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
1688  APFloat APF = APFloat(APFloat::PPCDoubleDouble(), APInt(128, TwoE31));
1689  SDValue Tmp = DAG.getConstantFP(APF, dl, MVT::ppcf128);
1690  // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
1691  // FIXME: generated code sucks.
1692  // TODO: Are there fast-math-flags to propagate to this FSUB?
1693  return DAG.getSelectCC(dl, N->getOperand(0), Tmp,
1694  DAG.getNode(ISD::ADD, dl, MVT::i32,
1695  DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32,
1696  DAG.getNode(ISD::FSUB, dl,
1697  MVT::ppcf128,
1698  N->getOperand(0),
1699  Tmp)),
1700  DAG.getConstant(0x80000000, dl,
1701  MVT::i32)),
1702  DAG.getNode(ISD::FP_TO_SINT, dl,
1703  MVT::i32, N->getOperand(0)),
1704  ISD::SETGE);
1705  }
1706 
1708  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!");
1709  return TLI.makeLibCall(DAG, LC, N->getValueType(0), N->getOperand(0),
1710  false, dl).first;
1711 }
1712 
1713 SDValue DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(SDNode *N) {
1714  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1715  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
1716  FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
1717 
1718  // If ExpandSetCCOperands returned a scalar, we need to compare the result
1719  // against zero to select between true and false values.
1720  if (!NewRHS.getNode()) {
1721  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
1722  CCCode = ISD::SETNE;
1723  }
1724 
1725  // Update N to have the operands specified.
1726  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
1727  N->getOperand(2), N->getOperand(3),
1728  DAG.getCondCode(CCCode)), 0);
1729 }
1730 
1731 SDValue DAGTypeLegalizer::ExpandFloatOp_SETCC(SDNode *N) {
1732  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1733  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1734  FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
1735 
1736  // If ExpandSetCCOperands returned a scalar, use it.
1737  if (!NewRHS.getNode()) {
1738  assert(NewLHS.getValueType() == N->getValueType(0) &&
1739  "Unexpected setcc expansion!");
1740  return NewLHS;
1741  }
1742 
1743  // Otherwise, update N to have the operands specified.
1744  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
1745  DAG.getCondCode(CCCode)), 0);
1746 }
1747 
1748 SDValue DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) {
1749  if (ISD::isNormalStore(N))
1750  return ExpandOp_NormalStore(N, OpNo);
1751 
1752  assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1753  assert(OpNo == 1 && "Can only expand the stored value so far");
1754  StoreSDNode *ST = cast<StoreSDNode>(N);
1755 
1756  SDValue Chain = ST->getChain();
1757  SDValue Ptr = ST->getBasePtr();
1758 
1759  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(),
1760  ST->getValue().getValueType());
1761  assert(NVT.isByteSized() && "Expanded type not byte sized!");
1762  assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?");
1763  (void)NVT;
1764 
1765  SDValue Lo, Hi;
1766  GetExpandedOp(ST->getValue(), Lo, Hi);
1767 
1768  return DAG.getTruncStore(Chain, SDLoc(N), Hi, Ptr,
1769  ST->getMemoryVT(), ST->getMemOperand());
1770 }
1771 
1772 //===----------------------------------------------------------------------===//
1773 // Float Operand Promotion
1774 //===----------------------------------------------------------------------===//
1775 //
1776 
1778  if (OpVT == MVT::f16) {
1779  return ISD::FP16_TO_FP;
1780  } else if (RetVT == MVT::f16) {
1781  return ISD::FP_TO_FP16;
1782  }
1783 
1784  report_fatal_error("Attempt at an invalid promotion-related conversion");
1785 }
1786 
1787 bool DAGTypeLegalizer::PromoteFloatOperand(SDNode *N, unsigned OpNo) {
1788  SDValue R = SDValue();
1789 
1790  // Nodes that use a promotion-requiring floating point operand, but doesn't
1791  // produce a promotion-requiring floating point result, need to be legalized
1792  // to use the promoted float operand. Nodes that produce at least one
1793  // promotion-requiring floating point result have their operands legalized as
1794  // a part of PromoteFloatResult.
1795  switch (N->getOpcode()) {
1796  default:
1797  llvm_unreachable("Do not know how to promote this operator's operand!");
1798 
1799  case ISD::BITCAST: R = PromoteFloatOp_BITCAST(N, OpNo); break;
1800  case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break;
1801  case ISD::FP_TO_SINT:
1802  case ISD::FP_TO_UINT: R = PromoteFloatOp_FP_TO_XINT(N, OpNo); break;
1803  case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break;
1804  case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break;
1805  case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break;
1806  case ISD::STORE: R = PromoteFloatOp_STORE(N, OpNo); break;
1807  }
1808 
1809  if (R.getNode())
1810  ReplaceValueWith(SDValue(N, 0), R);
1811  return false;
1812 }
1813 
1814 SDValue DAGTypeLegalizer::PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo) {
1815  SDValue Op = N->getOperand(0);
1816  EVT OpVT = Op->getValueType(0);
1817 
1818  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits());
1819  assert (IVT == N->getValueType(0) && "Bitcast to type of different size");
1820 
1821  SDValue Promoted = GetPromotedFloat(N->getOperand(0));
1822  EVT PromotedVT = Promoted->getValueType(0);
1823 
1824  // Convert the promoted float value to the desired IVT.
1825  return DAG.getNode(GetPromotionOpcode(PromotedVT, OpVT), SDLoc(N), IVT,
1826  Promoted);
1827 }
1828 
1829 // Promote Operand 1 of FCOPYSIGN. Operand 0 ought to be handled by
1830 // PromoteFloatRes_FCOPYSIGN.
1831 SDValue DAGTypeLegalizer::PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo) {
1832  assert (OpNo == 1 && "Only Operand 1 must need promotion here");
1833  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
1834 
1835  return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
1836  N->getOperand(0), Op1);
1837 }
1838 
1839 // Convert the promoted float value to the desired integer type
1840 SDValue DAGTypeLegalizer::PromoteFloatOp_FP_TO_XINT(SDNode *N, unsigned OpNo) {
1841  SDValue Op = GetPromotedFloat(N->getOperand(0));
1842  return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), Op);
1843 }
1844 
1845 SDValue DAGTypeLegalizer::PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo) {
1846  SDValue Op = GetPromotedFloat(N->getOperand(0));
1847  EVT VT = N->getValueType(0);
1848 
1849  // Desired VT is same as promoted type. Use promoted float directly.
1850  if (VT == Op->getValueType(0))
1851  return Op;
1852 
1853  // Else, extend the promoted float value to the desired VT.
1854  return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op);
1855 }
1856 
1857 // Promote the float operands used for comparison. The true- and false-
1858 // operands have the same type as the result and are promoted, if needed, by
1859 // PromoteFloatRes_SELECT_CC
1860 SDValue DAGTypeLegalizer::PromoteFloatOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1861  SDValue LHS = GetPromotedFloat(N->getOperand(0));
1862  SDValue RHS = GetPromotedFloat(N->getOperand(1));
1863 
1864  return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1865  LHS, RHS, N->getOperand(2), N->getOperand(3),
1866  N->getOperand(4));
1867 }
1868 
1869 // Construct a SETCC that compares the promoted values and sets the conditional
1870 // code.
1871 SDValue DAGTypeLegalizer::PromoteFloatOp_SETCC(SDNode *N, unsigned OpNo) {
1872  EVT VT = N->getValueType(0);
1873  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1874  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
1875  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
1876  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1877 
1878  return DAG.getSetCC(SDLoc(N), NVT, Op0, Op1, CCCode);
1879 
1880 }
1881 
1882 // Lower the promoted Float down to the integer value of same size and construct
1883 // a STORE of the integer value.
1884 SDValue DAGTypeLegalizer::PromoteFloatOp_STORE(SDNode *N, unsigned OpNo) {
1885  StoreSDNode *ST = cast<StoreSDNode>(N);
1886  SDValue Val = ST->getValue();
1887  SDLoc DL(N);
1888 
1889  SDValue Promoted = GetPromotedFloat(Val);
1890  EVT VT = ST->getOperand(1)->getValueType(0);
1891  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
1892 
1893  SDValue NewVal;
1894  NewVal = DAG.getNode(GetPromotionOpcode(Promoted.getValueType(), VT), DL,
1895  IVT, Promoted);
1896 
1897  return DAG.getStore(ST->getChain(), DL, NewVal, ST->getBasePtr(),
1898  ST->getMemOperand());
1899 }
1900 
1901 //===----------------------------------------------------------------------===//
1902 // Float Result Promotion
1903 //===----------------------------------------------------------------------===//
1904 
1905 void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
1906  SDValue R = SDValue();
1907 
1908  switch (N->getOpcode()) {
1909  // These opcodes cannot appear if promotion of FP16 is done in the backend
1910  // instead of Clang
1911  case ISD::FP16_TO_FP:
1912  case ISD::FP_TO_FP16:
1913  default:
1914  llvm_unreachable("Do not know how to promote this operator's result!");
1915 
1916  case ISD::BITCAST: R = PromoteFloatRes_BITCAST(N); break;
1917  case ISD::ConstantFP: R = PromoteFloatRes_ConstantFP(N); break;
1919  R = PromoteFloatRes_EXTRACT_VECTOR_ELT(N); break;
1920  case ISD::FCOPYSIGN: R = PromoteFloatRes_FCOPYSIGN(N); break;
1921 
1922  // Unary FP Operations
1923  case ISD::FABS:
1924  case ISD::FCEIL:
1925  case ISD::FCOS:
1926  case ISD::FEXP:
1927  case ISD::FEXP2:
1928  case ISD::FFLOOR:
1929  case ISD::FLOG:
1930  case ISD::FLOG2:
1931  case ISD::FLOG10:
1932  case ISD::FNEARBYINT:
1933  case ISD::FNEG:
1934  case ISD::FRINT:
1935  case ISD::FROUND:
1936  case ISD::FSIN:
1937  case ISD::FSQRT:
1938  case ISD::FTRUNC: R = PromoteFloatRes_UnaryOp(N); break;
1939 
1940  // Binary FP Operations
1941  case ISD::FADD:
1942  case ISD::FDIV:
1943  case ISD::FMAXNAN:
1944  case ISD::FMINNAN:
1945  case ISD::FMAXNUM:
1946  case ISD::FMINNUM:
1947  case ISD::FMUL:
1948  case ISD::FPOW:
1949  case ISD::FREM:
1950  case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break;
1951 
1952  case ISD::FMA: // FMA is same as FMAD
1953  case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break;
1954 
1955  case ISD::FPOWI: R = PromoteFloatRes_FPOWI(N); break;
1956 
1957  case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break;
1958  case ISD::LOAD: R = PromoteFloatRes_LOAD(N); break;
1959  case ISD::SELECT: R = PromoteFloatRes_SELECT(N); break;
1960  case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break;
1961 
1962  case ISD::SINT_TO_FP:
1963  case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break;
1964  case ISD::UNDEF: R = PromoteFloatRes_UNDEF(N); break;
1965 
1966  }
1967 
1968  if (R.getNode())
1969  SetPromotedFloat(SDValue(N, ResNo), R);
1970 }
1971 
1972 // Bitcast from i16 to f16: convert the i16 to a f32 value instead.
1973 // At this point, it is not possible to determine if the bitcast value is
1974 // eventually stored to memory or promoted to f32 or promoted to a floating
1975 // point at a higher precision. Some of these cases are handled by FP_EXTEND,
1976 // STORE promotion handlers.
1977 SDValue DAGTypeLegalizer::PromoteFloatRes_BITCAST(SDNode *N) {
1978  EVT VT = N->getValueType(0);
1979  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1980  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT,
1981  N->getOperand(0));
1982 }
1983 
1984 SDValue DAGTypeLegalizer::PromoteFloatRes_ConstantFP(SDNode *N) {
1985  ConstantFPSDNode *CFPNode = cast<ConstantFPSDNode>(N);
1986  EVT VT = N->getValueType(0);
1987  SDLoc DL(N);
1988 
1989  // Get the (bit-cast) APInt of the APFloat and build an integer constant
1990  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
1991  SDValue C = DAG.getConstant(CFPNode->getValueAPF().bitcastToAPInt(), DL,
1992  IVT);
1993 
1994  // Convert the Constant to the desired FP type
1995  // FIXME We might be able to do the conversion during compilation and get rid
1996  // of it from the object code
1997  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1998  return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, C);
1999 }
2000 
2001 // If the Index operand is a constant, try to redirect the extract operation to
2002 // the correct legalized vector. If not, bit-convert the input vector to
2003 // equivalent integer vector. Extract the element as an (bit-cast) integer
2004 // value and convert it to the promoted type.
2005 SDValue DAGTypeLegalizer::PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
2006  SDLoc DL(N);
2007 
2008  // If the index is constant, try to extract the value from the legalized
2009  // vector type.
2010  if (isa<ConstantSDNode>(N->getOperand(1))) {
2011  SDValue Vec = N->getOperand(0);
2012  SDValue Idx = N->getOperand(1);
2013  EVT VecVT = Vec->getValueType(0);
2014  EVT EltVT = VecVT.getVectorElementType();
2015 
2016  uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2017 
2018  switch (getTypeAction(VecVT)) {
2019  default: break;
2021  SDValue Res = GetScalarizedVector(N->getOperand(0));
2022  ReplaceValueWith(SDValue(N, 0), Res);
2023  return SDValue();
2024  }
2026  Vec = GetWidenedVector(Vec);
2027  SDValue Res = DAG.getNode(N->getOpcode(), DL, EltVT, Vec, Idx);
2028  ReplaceValueWith(SDValue(N, 0), Res);
2029  return SDValue();
2030  }
2032  SDValue Lo, Hi;
2033  GetSplitVector(Vec, Lo, Hi);
2034 
2035  uint64_t LoElts = Lo.getValueType().getVectorNumElements();
2036  SDValue Res;
2037  if (IdxVal < LoElts)
2038  Res = DAG.getNode(N->getOpcode(), DL, EltVT, Lo, Idx);
2039  else
2040  Res = DAG.getNode(N->getOpcode(), DL, EltVT, Hi,
2041  DAG.getConstant(IdxVal - LoElts, DL,
2042  Idx.getValueType()));
2043  ReplaceValueWith(SDValue(N, 0), Res);
2044  return SDValue();
2045  }
2046 
2047  }
2048  }
2049 
2050  // Bit-convert the input vector to the equivalent integer vector
2051  SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
2052  EVT IVT = NewOp.getValueType().getVectorElementType();
2053 
2054  // Extract the element as an (bit-cast) integer value
2055  SDValue NewVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IVT,
2056  NewOp, N->getOperand(1));
2057 
2058  // Convert the element to the desired FP type
2059  EVT VT = N->getValueType(0);
2060  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2061  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, NewVal);
2062 }
2063 
2064 // FCOPYSIGN(X, Y) returns the value of X with the sign of Y. If the result
2065 // needs promotion, so does the argument X. Note that Y, if needed, will be
2066 // handled during operand promotion.
2067 SDValue DAGTypeLegalizer::PromoteFloatRes_FCOPYSIGN(SDNode *N) {
2068  EVT VT = N->getValueType(0);
2069  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2070  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2071 
2072  SDValue Op1 = N->getOperand(1);
2073 
2074  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1);
2075 }
2076 
2077 // Unary operation where the result and the operand have PromoteFloat type
2078 // action. Construct a new SDNode with the promoted float value of the old
2079 // operand.
2080 SDValue DAGTypeLegalizer::PromoteFloatRes_UnaryOp(SDNode *N) {
2081  EVT VT = N->getValueType(0);
2082  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2083  SDValue Op = GetPromotedFloat(N->getOperand(0));
2084 
2085  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op);
2086 }
2087 
2088 // Binary operations where the result and both operands have PromoteFloat type
2089 // action. Construct a new SDNode with the promoted float values of the old
2090 // operands.
2091 SDValue DAGTypeLegalizer::PromoteFloatRes_BinOp(SDNode *N) {
2092  EVT VT = N->getValueType(0);
2093  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2094  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2095  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
2096  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, N->getFlags());
2097 }
2098 
2099 SDValue DAGTypeLegalizer::PromoteFloatRes_FMAD(SDNode *N) {
2100  EVT VT = N->getValueType(0);
2101  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2102  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2103  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
2104  SDValue Op2 = GetPromotedFloat(N->getOperand(2));
2105 
2106  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, Op2);
2107 }
2108 
2109 // Promote the Float (first) operand and retain the Integer (second) operand
2110 SDValue DAGTypeLegalizer::PromoteFloatRes_FPOWI(SDNode *N) {
2111  EVT VT = N->getValueType(0);
2112  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2113  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2114  SDValue Op1 = N->getOperand(1);
2115 
2116  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1);
2117 }
2118 
2119 // Explicit operation to reduce precision. Reduce the value to half precision
2120 // and promote it back to the legal type.
2121 SDValue DAGTypeLegalizer::PromoteFloatRes_FP_ROUND(SDNode *N) {
2122  SDLoc DL(N);
2123 
2124  SDValue Op = N->getOperand(0);
2125  EVT VT = N->getValueType(0);
2126  EVT OpVT = Op->getValueType(0);
2127  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2128  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
2129 
2130  // Round promoted float to desired precision
2131  SDValue Round = DAG.getNode(GetPromotionOpcode(OpVT, VT), DL, IVT, Op);
2132  // Promote it back to the legal output type
2133  return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, Round);
2134 }
2135 
2136 SDValue DAGTypeLegalizer::PromoteFloatRes_LOAD(SDNode *N) {
2137  LoadSDNode *L = cast<LoadSDNode>(N);
2138  EVT VT = N->getValueType(0);
2139 
2140  // Load the value as an integer value with the same number of bits.
2141  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
2142  auto MMOFlags =
2143  L->getMemOperand()->getFlags() &
2145  SDValue newL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), IVT,
2146  SDLoc(N), L->getChain(), L->getBasePtr(),
2147  L->getOffset(), L->getPointerInfo(), IVT,
2148  L->getAlignment(), MMOFlags, L->getAAInfo());
2149  // Legalize the chain result by replacing uses of the old value chain with the
2150  // new one
2151  ReplaceValueWith(SDValue(N, 1), newL.getValue(1));
2152 
2153  // Convert the integer value to the desired FP type
2154  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2155  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, newL);
2156 }
2157 
2158 // Construct a new SELECT node with the promoted true- and false- values.
2159 SDValue DAGTypeLegalizer::PromoteFloatRes_SELECT(SDNode *N) {
2160  SDValue TrueVal = GetPromotedFloat(N->getOperand(1));
2161  SDValue FalseVal = GetPromotedFloat(N->getOperand(2));
2162 
2163  return DAG.getNode(ISD::SELECT, SDLoc(N), TrueVal->getValueType(0),
2164  N->getOperand(0), TrueVal, FalseVal);
2165 }
2166 
2167 // Construct a new SELECT_CC node with the promoted true- and false- values.
2168 // The operands used for comparison are promoted by PromoteFloatOp_SELECT_CC.
2169 SDValue DAGTypeLegalizer::PromoteFloatRes_SELECT_CC(SDNode *N) {
2170  SDValue TrueVal = GetPromotedFloat(N->getOperand(2));
2171  SDValue FalseVal = GetPromotedFloat(N->getOperand(3));
2172 
2173  return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
2174  N->getOperand(0), N->getOperand(1), TrueVal, FalseVal,
2175  N->getOperand(4));
2176 }
2177 
2178 // Construct a SDNode that transforms the SINT or UINT operand to the promoted
2179 // float type.
2180 SDValue DAGTypeLegalizer::PromoteFloatRes_XINT_TO_FP(SDNode *N) {
2181  SDLoc DL(N);
2182  EVT VT = N->getValueType(0);
2183  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2184  SDValue NV = DAG.getNode(N->getOpcode(), DL, NVT, N->getOperand(0));
2185  // Round the value to the desired precision (that of the source type).
2186  return DAG.getNode(
2187  ISD::FP_EXTEND, DL, NVT,
2188  DAG.getNode(ISD::FP_ROUND, DL, VT, NV, DAG.getIntPtrConstant(0, DL)));
2189 }
2190 
2191 SDValue DAGTypeLegalizer::PromoteFloatRes_UNDEF(SDNode *N) {
2192  return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
2193  N->getValueType(0)));
2194 }
2195 
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:545
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:512
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:569
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOffset() const
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:184
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:555
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
DiagnosticInfoOptimizationBase::Argument NV
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:898
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:617
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
const SDValue & getBasePtr() const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const SDValue & getValue() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:253
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
const SDValue & getChain() const
ISD::MemIndexedMode getAddressingMode() const
Return the addressing mode for this load or store: unindexed, pre-inc, pre-dec, post-inc, or post-dec.
static const fltSemantics & EVTToAPFloatSemantics(EVT VT)
Returns an APFloat semantics tag appropriate for the given type.
unsigned getAlignment() const
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select&#39;s if you just have operands and don&#39;t want to check...
Definition: SelectionDAG.h:911
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) const
Soften the operands of a comparison.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:212
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:404
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
bool isTruncatingStore() const
Return true if the op does a truncation before store.
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Shift and rotation operations.
Definition: ISDOpcodes.h:379
bool isNormalStore(const SDNode *N)
Returns true if the specified node is a non-truncating and unindexed store.
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
CopyToReg - This node has three operands: a chain, a register number to set to this value...
Definition: ISDOpcodes.h:170
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
SimpleValueType SimpleTy
The memory access is dereferenceable (i.e., doesn&#39;t trap).
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:388
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:455
bool isUNINDEXEDStore(const SDNode *N)
Returns true if the specified node is an unindexed store.
void clearBit(unsigned BitPosition)
Set a given bit to 0.
Definition: APInt.h:1441
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:830
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:916
static RTLIB::Libcall GetFPLibCall(EVT VT, RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128, RTLIB::Libcall Call_PPCF128)
GetFPLibCall - Return the right libcall for the given floating point type.
UNDEF - An undefined node.
Definition: ISDOpcodes.h:178
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:498
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:302
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
const SDValue & getBasePtr() const
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
Definition: ValueTypes.h:235
bool isNormalLoad(const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
Simple binary floating point operators.
Definition: ISDOpcodes.h:259
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:273
const SDValue & getOperand(unsigned Num) const
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
Definition: ValueTypes.h:247
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:686
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:530
Extended Value Type.
Definition: ValueTypes.h:34
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned first
bool isUNINDEXEDLoad(const SDNode *N)
Returns true if the specified node is an unindexed load.
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
void dump() const
Dump this node, for debugging.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:314
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:265
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and rounds it to a floating point val...
Definition: ISDOpcodes.h:527
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:555
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
EVT getMemoryVT() const
Return the type of the in-memory value.
Class for arbitrary precision integers.
Definition: APInt.h:69
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:389
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:445
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:448
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:287
FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that when a single input is NaN...
Definition: ISDOpcodes.h:572
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:668
static const fltSemantics & PPCDoubleDouble() LLVM_READNONE
Definition: APFloat.cpp:134
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:362
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:581
#define N
Flags getFlags() const
Return the raw flags of the source value,.
The memory access always returns the same value (or traps).
unsigned getOpcode() const
SDValue getValue(unsigned R) const
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:175
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getCondCode(ISD::CondCode Cond)
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input...
const MachinePointerInfo & getPointerInfo() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:277
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC&#39;s if you just have an ISD::CondCode instead of an...
Definition: SelectionDAG.h:924
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
#define DEBUG(X)
Definition: Debug.h:118
const APFloat & getValueAPF() const
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
Definition: ISDOpcodes.h:281
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:412
APInt bitcastToAPInt() const
Definition: APFloat.h:1094
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
Conversion operators.
Definition: ISDOpcodes.h:442
bool isBigEndian() const
Definition: DataLayout.h:217
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:451
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
Definition: ISDOpcodes.h:561
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:64
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
static ISD::NodeType GetPromotionOpcode(EVT OpVT, EVT RetVT)
LLVMContext * getContext() const
Definition: SelectionDAG.h:393
This class is used to represent ISD::LOAD nodes.