LLVM  9.0.0svn
LegalizeFloatTypes.cpp
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1 //===-------- LegalizeFloatTypes.cpp - Legalization of float types --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements float type expansion and softening for LegalizeTypes.
10 // Softening is the act of turning a computation in an illegal floating point
11 // type into a computation in an integer type of the same size; also known as
12 // "soft float". For example, turning f32 arithmetic into operations using i32.
13 // The resulting integer value is the same as what you would get by performing
14 // the floating point operation and bitcasting the result to the integer type.
15 // Expansion is the act of changing a computation in an illegal type to be a
16 // computation in two identical registers of a smaller type. For example,
17 // implementing ppcf128 arithmetic in two f64 registers.
18 //
19 //===----------------------------------------------------------------------===//
20 
21 #include "LegalizeTypes.h"
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "legalize-types"
27 
28 /// GetFPLibCall - Return the right libcall for the given floating point type.
30  RTLIB::Libcall Call_F32,
31  RTLIB::Libcall Call_F64,
32  RTLIB::Libcall Call_F80,
33  RTLIB::Libcall Call_F128,
34  RTLIB::Libcall Call_PPCF128) {
35  return
36  VT == MVT::f32 ? Call_F32 :
37  VT == MVT::f64 ? Call_F64 :
38  VT == MVT::f80 ? Call_F80 :
39  VT == MVT::f128 ? Call_F128 :
40  VT == MVT::ppcf128 ? Call_PPCF128 :
41  RTLIB::UNKNOWN_LIBCALL;
42 }
43 
44 //===----------------------------------------------------------------------===//
45 // Convert Float Results to Integer for Non-HW-supported Operations.
46 //===----------------------------------------------------------------------===//
47 
48 bool DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
49  LLVM_DEBUG(dbgs() << "Soften float result " << ResNo << ": "; N->dump(&DAG);
50  dbgs() << "\n");
51  SDValue R = SDValue();
52 
53  switch (N->getOpcode()) {
54  default:
55 #ifndef NDEBUG
56  dbgs() << "SoftenFloatResult #" << ResNo << ": ";
57  N->dump(&DAG); dbgs() << "\n";
58 #endif
59  llvm_unreachable("Do not know how to soften the result of this operator!");
60 
61  case ISD::Register:
62  case ISD::CopyFromReg:
63  case ISD::CopyToReg:
64  assert(isLegalInHWReg(N->getValueType(ResNo)) &&
65  "Unsupported SoftenFloatRes opcode!");
66  // Only when isLegalInHWReg, we can skip check of the operands.
67  R = SDValue(N, ResNo);
68  break;
69  case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
70  case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N, ResNo); break;
71  case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break;
72  case ISD::ConstantFP: R = SoftenFloatRes_ConstantFP(N, ResNo); break;
74  R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break;
75  case ISD::FABS: R = SoftenFloatRes_FABS(N, ResNo); break;
76  case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break;
77  case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break;
78  case ISD::FADD: R = SoftenFloatRes_FADD(N); break;
79  case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break;
80  case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N, ResNo); break;
81  case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break;
82  case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break;
83  case ISD::FEXP: R = SoftenFloatRes_FEXP(N); break;
84  case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break;
85  case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break;
86  case ISD::FLOG: R = SoftenFloatRes_FLOG(N); break;
87  case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break;
88  case ISD::FLOG10: R = SoftenFloatRes_FLOG10(N); break;
89  case ISD::FMA: R = SoftenFloatRes_FMA(N); break;
90  case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break;
91  case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break;
92  case ISD::FNEG: R = SoftenFloatRes_FNEG(N, ResNo); break;
93  case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break;
94  case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break;
95  case ISD::FP16_TO_FP: R = SoftenFloatRes_FP16_TO_FP(N); break;
96  case ISD::FPOW: R = SoftenFloatRes_FPOW(N); break;
97  case ISD::FPOWI: R = SoftenFloatRes_FPOWI(N); break;
98  case ISD::FREM: R = SoftenFloatRes_FREM(N); break;
99  case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break;
100  case ISD::FROUND: R = SoftenFloatRes_FROUND(N); break;
101  case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break;
102  case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break;
103  case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
104  case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break;
105  case ISD::LOAD: R = SoftenFloatRes_LOAD(N, ResNo); break;
106  case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break;
107  case ISD::SELECT: R = SoftenFloatRes_SELECT(N, ResNo); break;
108  case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N, ResNo); break;
109  case ISD::SINT_TO_FP:
110  case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break;
111  case ISD::UNDEF: R = SoftenFloatRes_UNDEF(N); break;
112  case ISD::VAARG: R = SoftenFloatRes_VAARG(N); break;
113  }
114 
115  if (R.getNode() && R.getNode() != N) {
116  SetSoftenedFloat(SDValue(N, ResNo), R);
117  // Return true only if the node is changed, assuming that the operands
118  // are also converted when necessary.
119  return true;
120  }
121 
122  // Otherwise, return false to tell caller to scan operands.
123  return false;
124 }
125 
126 SDValue DAGTypeLegalizer::SoftenFloatRes_BITCAST(SDNode *N, unsigned ResNo) {
127  if (isLegalInHWReg(N->getValueType(ResNo)))
128  return SDValue(N, ResNo);
129  return BitConvertToInteger(N->getOperand(0));
130 }
131 
132 SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(SDNode *N,
133  unsigned ResNo) {
134  SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
135  return BitConvertToInteger(Op);
136 }
137 
138 SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
139  // Convert the inputs to integers, and build a new pair out of them.
140  return DAG.getNode(ISD::BUILD_PAIR, SDLoc(N),
141  TLI.getTypeToTransformTo(*DAG.getContext(),
142  N->getValueType(0)),
143  BitConvertToInteger(N->getOperand(0)),
144  BitConvertToInteger(N->getOperand(1)));
145 }
146 
147 SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode *N, unsigned ResNo) {
148  // When LegalInHWReg, we can load better from the constant pool.
149  if (isLegalInHWReg(N->getValueType(ResNo)))
150  return SDValue(N, ResNo);
151  ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
152  // In ppcf128, the high 64 bits are always first in memory regardless
153  // of Endianness. LLVM's APFloat representation is not Endian sensitive,
154  // and so always converts into a 128-bit APInt in a non-Endian-sensitive
155  // way. However, APInt's are serialized in an Endian-sensitive fashion,
156  // so on big-Endian targets, the two doubles are output in the wrong
157  // order. Fix this by manually flipping the order of the high 64 bits
158  // and the low 64 bits here.
159  if (DAG.getDataLayout().isBigEndian() &&
161  uint64_t words[2] = { CN->getValueAPF().bitcastToAPInt().getRawData()[1],
162  CN->getValueAPF().bitcastToAPInt().getRawData()[0] };
163  APInt Val(128, words);
164  return DAG.getConstant(Val, SDLoc(CN),
165  TLI.getTypeToTransformTo(*DAG.getContext(),
166  CN->getValueType(0)));
167  } else {
168  return DAG.getConstant(CN->getValueAPF().bitcastToAPInt(), SDLoc(CN),
169  TLI.getTypeToTransformTo(*DAG.getContext(),
170  CN->getValueType(0)));
171  }
172 }
173 
174 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo) {
175  // When LegalInHWReg, keep the extracted value in register.
176  if (isLegalInHWReg(N->getValueType(ResNo)))
177  return SDValue(N, ResNo);
178  SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
179  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
181  NewOp, N->getOperand(1));
182 }
183 
184 SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N, unsigned ResNo) {
185  // When LegalInHWReg, FABS can be implemented as native bitwise operations.
186  if (isLegalInHWReg(N->getValueType(ResNo)))
187  return SDValue(N, ResNo);
188  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
189  unsigned Size = NVT.getSizeInBits();
190 
191  // Mask = ~(1 << (Size-1))
192  APInt API = APInt::getAllOnesValue(Size);
193  API.clearBit(Size - 1);
194  SDValue Mask = DAG.getConstant(API, SDLoc(N), NVT);
195  SDValue Op = GetSoftenedFloat(N->getOperand(0));
196  return DAG.getNode(ISD::AND, SDLoc(N), NVT, Op, Mask);
197 }
198 
199 SDValue DAGTypeLegalizer::SoftenFloatRes_FMINNUM(SDNode *N) {
200  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
201  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
202  GetSoftenedFloat(N->getOperand(1)) };
203  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
204  RTLIB::FMIN_F32,
205  RTLIB::FMIN_F64,
206  RTLIB::FMIN_F80,
207  RTLIB::FMIN_F128,
208  RTLIB::FMIN_PPCF128),
209  NVT, Ops, false, SDLoc(N)).first;
210 }
211 
212 SDValue DAGTypeLegalizer::SoftenFloatRes_FMAXNUM(SDNode *N) {
213  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
214  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
215  GetSoftenedFloat(N->getOperand(1)) };
216  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
217  RTLIB::FMAX_F32,
218  RTLIB::FMAX_F64,
219  RTLIB::FMAX_F80,
220  RTLIB::FMAX_F128,
221  RTLIB::FMAX_PPCF128),
222  NVT, Ops, false, SDLoc(N)).first;
223 }
224 
225 SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
226  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
227  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
228  GetSoftenedFloat(N->getOperand(1)) };
229  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
230  RTLIB::ADD_F32,
231  RTLIB::ADD_F64,
232  RTLIB::ADD_F80,
233  RTLIB::ADD_F128,
234  RTLIB::ADD_PPCF128),
235  NVT, Ops, false, SDLoc(N)).first;
236 }
237 
238 SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) {
239  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
240  SDValue Op = GetSoftenedFloat(N->getOperand(0));
241  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
242  RTLIB::CEIL_F32,
243  RTLIB::CEIL_F64,
244  RTLIB::CEIL_F80,
245  RTLIB::CEIL_F128,
246  RTLIB::CEIL_PPCF128),
247  NVT, Op, false, SDLoc(N)).first;
248 }
249 
250 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N, unsigned ResNo) {
251  // When LegalInHWReg, FCOPYSIGN can be implemented as native bitwise operations.
252  if (isLegalInHWReg(N->getValueType(ResNo)))
253  return SDValue(N, ResNo);
254  SDValue LHS = GetSoftenedFloat(N->getOperand(0));
255  SDValue RHS = BitConvertToInteger(N->getOperand(1));
256  SDLoc dl(N);
257 
258  EVT LVT = LHS.getValueType();
259  EVT RVT = RHS.getValueType();
260 
261  unsigned LSize = LVT.getSizeInBits();
262  unsigned RSize = RVT.getSizeInBits();
263 
264  // First get the sign bit of second operand.
265  SDValue SignBit = DAG.getNode(
266  ISD::SHL, dl, RVT, DAG.getConstant(1, dl, RVT),
267  DAG.getConstant(RSize - 1, dl,
268  TLI.getShiftAmountTy(RVT, DAG.getDataLayout())));
269  SignBit = DAG.getNode(ISD::AND, dl, RVT, RHS, SignBit);
270 
271  // Shift right or sign-extend it if the two operands have different types.
272  int SizeDiff = RVT.getSizeInBits() - LVT.getSizeInBits();
273  if (SizeDiff > 0) {
274  SignBit =
275  DAG.getNode(ISD::SRL, dl, RVT, SignBit,
276  DAG.getConstant(SizeDiff, dl,
277  TLI.getShiftAmountTy(SignBit.getValueType(),
278  DAG.getDataLayout())));
279  SignBit = DAG.getNode(ISD::TRUNCATE, dl, LVT, SignBit);
280  } else if (SizeDiff < 0) {
281  SignBit = DAG.getNode(ISD::ANY_EXTEND, dl, LVT, SignBit);
282  SignBit =
283  DAG.getNode(ISD::SHL, dl, LVT, SignBit,
284  DAG.getConstant(-SizeDiff, dl,
285  TLI.getShiftAmountTy(SignBit.getValueType(),
286  DAG.getDataLayout())));
287  }
288 
289  // Clear the sign bit of the first operand.
290  SDValue Mask = DAG.getNode(
291  ISD::SHL, dl, LVT, DAG.getConstant(1, dl, LVT),
292  DAG.getConstant(LSize - 1, dl,
293  TLI.getShiftAmountTy(LVT, DAG.getDataLayout())));
294  Mask = DAG.getNode(ISD::SUB, dl, LVT, Mask, DAG.getConstant(1, dl, LVT));
295  LHS = DAG.getNode(ISD::AND, dl, LVT, LHS, Mask);
296 
297  // Or the value with the sign bit.
298  return DAG.getNode(ISD::OR, dl, LVT, LHS, SignBit);
299 }
300 
301 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N) {
302  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
303  SDValue Op = GetSoftenedFloat(N->getOperand(0));
304  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
305  RTLIB::COS_F32,
306  RTLIB::COS_F64,
307  RTLIB::COS_F80,
308  RTLIB::COS_F128,
309  RTLIB::COS_PPCF128),
310  NVT, Op, false, SDLoc(N)).first;
311 }
312 
313 SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
314  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
315  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
316  GetSoftenedFloat(N->getOperand(1)) };
317  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
318  RTLIB::DIV_F32,
319  RTLIB::DIV_F64,
320  RTLIB::DIV_F80,
321  RTLIB::DIV_F128,
322  RTLIB::DIV_PPCF128),
323  NVT, Ops, false, SDLoc(N)).first;
324 }
325 
326 SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP(SDNode *N) {
327  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
328  SDValue Op = GetSoftenedFloat(N->getOperand(0));
329  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
330  RTLIB::EXP_F32,
331  RTLIB::EXP_F64,
332  RTLIB::EXP_F80,
333  RTLIB::EXP_F128,
334  RTLIB::EXP_PPCF128),
335  NVT, Op, false, SDLoc(N)).first;
336 }
337 
338 SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP2(SDNode *N) {
339  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
340  SDValue Op = GetSoftenedFloat(N->getOperand(0));
341  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
342  RTLIB::EXP2_F32,
343  RTLIB::EXP2_F64,
344  RTLIB::EXP2_F80,
345  RTLIB::EXP2_F128,
346  RTLIB::EXP2_PPCF128),
347  NVT, Op, false, SDLoc(N)).first;
348 }
349 
350 SDValue DAGTypeLegalizer::SoftenFloatRes_FFLOOR(SDNode *N) {
351  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
352  SDValue Op = GetSoftenedFloat(N->getOperand(0));
353  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
354  RTLIB::FLOOR_F32,
355  RTLIB::FLOOR_F64,
356  RTLIB::FLOOR_F80,
357  RTLIB::FLOOR_F128,
358  RTLIB::FLOOR_PPCF128),
359  NVT, Op, false, SDLoc(N)).first;
360 }
361 
362 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG(SDNode *N) {
363  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
364  SDValue Op = GetSoftenedFloat(N->getOperand(0));
365  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
366  RTLIB::LOG_F32,
367  RTLIB::LOG_F64,
368  RTLIB::LOG_F80,
369  RTLIB::LOG_F128,
370  RTLIB::LOG_PPCF128),
371  NVT, Op, false, SDLoc(N)).first;
372 }
373 
374 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG2(SDNode *N) {
375  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
376  SDValue Op = GetSoftenedFloat(N->getOperand(0));
377  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
378  RTLIB::LOG2_F32,
379  RTLIB::LOG2_F64,
380  RTLIB::LOG2_F80,
381  RTLIB::LOG2_F128,
382  RTLIB::LOG2_PPCF128),
383  NVT, Op, false, SDLoc(N)).first;
384 }
385 
386 SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG10(SDNode *N) {
387  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
388  SDValue Op = GetSoftenedFloat(N->getOperand(0));
389  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
390  RTLIB::LOG10_F32,
391  RTLIB::LOG10_F64,
392  RTLIB::LOG10_F80,
393  RTLIB::LOG10_F128,
394  RTLIB::LOG10_PPCF128),
395  NVT, Op, false, SDLoc(N)).first;
396 }
397 
398 SDValue DAGTypeLegalizer::SoftenFloatRes_FMA(SDNode *N) {
399  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
400  SDValue Ops[3] = { GetSoftenedFloat(N->getOperand(0)),
401  GetSoftenedFloat(N->getOperand(1)),
402  GetSoftenedFloat(N->getOperand(2)) };
403  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
404  RTLIB::FMA_F32,
405  RTLIB::FMA_F64,
406  RTLIB::FMA_F80,
407  RTLIB::FMA_F128,
408  RTLIB::FMA_PPCF128),
409  NVT, Ops, false, SDLoc(N)).first;
410 }
411 
412 SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
413  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
414  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
415  GetSoftenedFloat(N->getOperand(1)) };
416  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
417  RTLIB::MUL_F32,
418  RTLIB::MUL_F64,
419  RTLIB::MUL_F80,
420  RTLIB::MUL_F128,
421  RTLIB::MUL_PPCF128),
422  NVT, Ops, false, SDLoc(N)).first;
423 }
424 
425 SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(SDNode *N) {
426  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
427  SDValue Op = GetSoftenedFloat(N->getOperand(0));
428  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
429  RTLIB::NEARBYINT_F32,
430  RTLIB::NEARBYINT_F64,
431  RTLIB::NEARBYINT_F80,
432  RTLIB::NEARBYINT_F128,
433  RTLIB::NEARBYINT_PPCF128),
434  NVT, Op, false, SDLoc(N)).first;
435 }
436 
437 SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N, unsigned ResNo) {
438  // When LegalInHWReg, FNEG can be implemented as native bitwise operations.
439  if (isLegalInHWReg(N->getValueType(ResNo)))
440  return SDValue(N, ResNo);
441  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
442  SDLoc dl(N);
443 
444  EVT FloatVT = N->getValueType(ResNo);
445  if (FloatVT == MVT::f32 || FloatVT == MVT::f64 || FloatVT == MVT::f128) {
446  // Expand Y = FNEG(X) -> Y = X ^ sign mask
447  APInt SignMask = APInt::getSignMask(NVT.getSizeInBits());
448  return DAG.getNode(ISD::XOR, dl, NVT, GetSoftenedFloat(N->getOperand(0)),
449  DAG.getConstant(SignMask, dl, NVT));
450  }
451 
452  // Expand Y = FNEG(X) -> Y = SUB -0.0, X
453  SDValue Ops[2] = { DAG.getConstantFP(-0.0, dl, N->getValueType(0)),
454  GetSoftenedFloat(N->getOperand(0)) };
455  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
456  RTLIB::SUB_F32,
457  RTLIB::SUB_F64,
458  RTLIB::SUB_F80,
459  RTLIB::SUB_F128,
460  RTLIB::SUB_PPCF128),
461  NVT, Ops, false, dl).first;
462 }
463 
464 SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
465  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
466  SDValue Op = N->getOperand(0);
467 
468  // There's only a libcall for f16 -> f32, so proceed in two stages. Also, it's
469  // entirely possible for both f16 and f32 to be legal, so use the fully
470  // hard-float FP_EXTEND rather than FP16_TO_FP.
471  if (Op.getValueType() == MVT::f16 && N->getValueType(0) != MVT::f32) {
472  Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op);
473  if (getTypeAction(MVT::f32) == TargetLowering::TypeSoftenFloat)
474  AddToWorklist(Op.getNode());
475  }
476 
477  if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat) {
478  Op = GetPromotedFloat(Op);
479  // If the promotion did the FP_EXTEND to the destination type for us,
480  // there's nothing left to do here.
481  if (Op.getValueType() == N->getValueType(0)) {
482  return BitConvertToInteger(Op);
483  }
484  }
485 
487  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
488  return TLI.makeLibCall(DAG, LC, NVT, Op, false, SDLoc(N)).first;
489 }
490 
491 // FIXME: Should we just use 'normal' FP_EXTEND / FP_TRUNC instead of special
492 // nodes?
493 SDValue DAGTypeLegalizer::SoftenFloatRes_FP16_TO_FP(SDNode *N) {
494  EVT MidVT = TLI.getTypeToTransformTo(*DAG.getContext(), MVT::f32);
495  SDValue Op = N->getOperand(0);
496  SDValue Res32 = TLI.makeLibCall(DAG, RTLIB::FPEXT_F16_F32, MidVT, Op,
497  false, SDLoc(N)).first;
498  if (N->getValueType(0) == MVT::f32)
499  return Res32;
500 
501  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
503  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
504  return TLI.makeLibCall(DAG, LC, NVT, Res32, false, SDLoc(N)).first;
505 }
506 
507 SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
508  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
509  SDValue Op = N->getOperand(0);
510  if (N->getValueType(0) == MVT::f16) {
511  // Semi-soften first, to FP_TO_FP16, so that targets which support f16 as a
512  // storage-only type get a chance to select things.
513  return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, Op);
514  }
515 
517  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
518  return TLI.makeLibCall(DAG, LC, NVT, Op, false, SDLoc(N)).first;
519 }
520 
521 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOW(SDNode *N) {
522  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
523  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
524  GetSoftenedFloat(N->getOperand(1)) };
525  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
526  RTLIB::POW_F32,
527  RTLIB::POW_F64,
528  RTLIB::POW_F80,
529  RTLIB::POW_F128,
530  RTLIB::POW_PPCF128),
531  NVT, Ops, false, SDLoc(N)).first;
532 }
533 
534 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
535  assert(N->getOperand(1).getValueType() == MVT::i32 &&
536  "Unsupported power type!");
537  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
538  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
539  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
540  RTLIB::POWI_F32,
541  RTLIB::POWI_F64,
542  RTLIB::POWI_F80,
543  RTLIB::POWI_F128,
544  RTLIB::POWI_PPCF128),
545  NVT, Ops, false, SDLoc(N)).first;
546 }
547 
548 SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) {
549  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
550  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
551  GetSoftenedFloat(N->getOperand(1)) };
552  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
553  RTLIB::REM_F32,
554  RTLIB::REM_F64,
555  RTLIB::REM_F80,
556  RTLIB::REM_F128,
557  RTLIB::REM_PPCF128),
558  NVT, Ops, false, SDLoc(N)).first;
559 }
560 
561 SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) {
562  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
563  SDValue Op = GetSoftenedFloat(N->getOperand(0));
564  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
565  RTLIB::RINT_F32,
566  RTLIB::RINT_F64,
567  RTLIB::RINT_F80,
568  RTLIB::RINT_F128,
569  RTLIB::RINT_PPCF128),
570  NVT, Op, false, SDLoc(N)).first;
571 }
572 
573 SDValue DAGTypeLegalizer::SoftenFloatRes_FROUND(SDNode *N) {
574  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
575  SDValue Op = GetSoftenedFloat(N->getOperand(0));
576  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
577  RTLIB::ROUND_F32,
578  RTLIB::ROUND_F64,
579  RTLIB::ROUND_F80,
580  RTLIB::ROUND_F128,
581  RTLIB::ROUND_PPCF128),
582  NVT, Op, false, SDLoc(N)).first;
583 }
584 
585 SDValue DAGTypeLegalizer::SoftenFloatRes_FSIN(SDNode *N) {
586  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
587  SDValue Op = GetSoftenedFloat(N->getOperand(0));
588  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
589  RTLIB::SIN_F32,
590  RTLIB::SIN_F64,
591  RTLIB::SIN_F80,
592  RTLIB::SIN_F128,
593  RTLIB::SIN_PPCF128),
594  NVT, Op, false, SDLoc(N)).first;
595 }
596 
597 SDValue DAGTypeLegalizer::SoftenFloatRes_FSQRT(SDNode *N) {
598  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
599  SDValue Op = GetSoftenedFloat(N->getOperand(0));
600  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
601  RTLIB::SQRT_F32,
602  RTLIB::SQRT_F64,
603  RTLIB::SQRT_F80,
604  RTLIB::SQRT_F128,
605  RTLIB::SQRT_PPCF128),
606  NVT, Op, false, SDLoc(N)).first;
607 }
608 
609 SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
610  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
611  SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
612  GetSoftenedFloat(N->getOperand(1)) };
613  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
614  RTLIB::SUB_F32,
615  RTLIB::SUB_F64,
616  RTLIB::SUB_F80,
617  RTLIB::SUB_F128,
618  RTLIB::SUB_PPCF128),
619  NVT, Ops, false, SDLoc(N)).first;
620 }
621 
622 SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) {
623  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
624  if (N->getValueType(0) == MVT::f16)
625  return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), NVT, N->getOperand(0));
626 
627  SDValue Op = GetSoftenedFloat(N->getOperand(0));
628  return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
629  RTLIB::TRUNC_F32,
630  RTLIB::TRUNC_F64,
631  RTLIB::TRUNC_F80,
632  RTLIB::TRUNC_F128,
633  RTLIB::TRUNC_PPCF128),
634  NVT, Op, false, SDLoc(N)).first;
635 }
636 
637 SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N, unsigned ResNo) {
638  bool LegalInHWReg = isLegalInHWReg(N->getValueType(ResNo));
639  LoadSDNode *L = cast<LoadSDNode>(N);
640  EVT VT = N->getValueType(0);
641  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
642  SDLoc dl(N);
643 
644  auto MMOFlags =
645  L->getMemOperand()->getFlags() &
647  SDValue NewL;
648  if (L->getExtensionType() == ISD::NON_EXTLOAD) {
649  NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), NVT, dl,
650  L->getChain(), L->getBasePtr(), L->getOffset(),
651  L->getPointerInfo(), NVT, L->getAlignment(), MMOFlags,
652  L->getAAInfo());
653  // Legalized the chain result - switch anything that used the old chain to
654  // use the new one.
655  if (N != NewL.getValue(1).getNode())
656  ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
657  return NewL;
658  }
659 
660  // Do a non-extending load followed by FP_EXTEND.
661  NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD, L->getMemoryVT(),
662  dl, L->getChain(), L->getBasePtr(), L->getOffset(),
663  L->getPointerInfo(), L->getMemoryVT(), L->getAlignment(),
664  MMOFlags, L->getAAInfo());
665  // Legalized the chain result - switch anything that used the old chain to
666  // use the new one.
667  ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
668  auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL);
669  if (LegalInHWReg)
670  return ExtendNode;
671  return BitConvertToInteger(ExtendNode);
672 }
673 
674 SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT(SDNode *N, unsigned ResNo) {
675  if (isLegalInHWReg(N->getValueType(ResNo)))
676  return SDValue(N, ResNo);
677  SDValue LHS = GetSoftenedFloat(N->getOperand(1));
678  SDValue RHS = GetSoftenedFloat(N->getOperand(2));
679  return DAG.getSelect(SDLoc(N),
680  LHS.getValueType(), N->getOperand(0), LHS, RHS);
681 }
682 
683 SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT_CC(SDNode *N, unsigned ResNo) {
684  if (isLegalInHWReg(N->getValueType(ResNo)))
685  return SDValue(N, ResNo);
686  SDValue LHS = GetSoftenedFloat(N->getOperand(2));
687  SDValue RHS = GetSoftenedFloat(N->getOperand(3));
688  return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
689  LHS.getValueType(), N->getOperand(0),
690  N->getOperand(1), LHS, RHS, N->getOperand(4));
691 }
692 
693 SDValue DAGTypeLegalizer::SoftenFloatRes_UNDEF(SDNode *N) {
694  return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
695  N->getValueType(0)));
696 }
697 
698 SDValue DAGTypeLegalizer::SoftenFloatRes_VAARG(SDNode *N) {
699  SDValue Chain = N->getOperand(0); // Get the chain.
700  SDValue Ptr = N->getOperand(1); // Get the pointer.
701  EVT VT = N->getValueType(0);
702  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
703  SDLoc dl(N);
704 
705  SDValue NewVAARG;
706  NewVAARG = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2),
707  N->getConstantOperandVal(3));
708 
709  // Legalized the chain result - switch anything that used the old chain to
710  // use the new one.
711  if (N != NewVAARG.getValue(1).getNode())
712  ReplaceValueWith(SDValue(N, 1), NewVAARG.getValue(1));
713  return NewVAARG;
714 }
715 
716 SDValue DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP(SDNode *N) {
717  bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
718  EVT SVT = N->getOperand(0).getValueType();
719  EVT RVT = N->getValueType(0);
720  EVT NVT = EVT();
721  SDLoc dl(N);
722 
723  // If the input is not legal, eg: i1 -> fp, then it needs to be promoted to
724  // a larger type, eg: i8 -> fp. Even if it is legal, no libcall may exactly
725  // match. Look for an appropriate libcall.
726  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
727  for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
728  t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
729  NVT = (MVT::SimpleValueType)t;
730  // The source needs to big enough to hold the operand.
731  if (NVT.bitsGE(SVT))
732  LC = Signed ? RTLIB::getSINTTOFP(NVT, RVT):RTLIB::getUINTTOFP (NVT, RVT);
733  }
734  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
735 
736  // Sign/zero extend the argument if the libcall takes a larger type.
737  SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
738  NVT, N->getOperand(0));
739  return TLI.makeLibCall(DAG, LC,
740  TLI.getTypeToTransformTo(*DAG.getContext(), RVT),
741  Op, Signed, dl).first;
742 }
743 
744 
745 //===----------------------------------------------------------------------===//
746 // Convert Float Operand to Integer for Non-HW-supported Operations.
747 //===----------------------------------------------------------------------===//
748 
749 bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
750  LLVM_DEBUG(dbgs() << "Soften float operand " << OpNo << ": "; N->dump(&DAG);
751  dbgs() << "\n");
752  SDValue Res = SDValue();
753 
754  switch (N->getOpcode()) {
755  default:
756  if (CanSkipSoftenFloatOperand(N, OpNo))
757  return false;
758 #ifndef NDEBUG
759  dbgs() << "SoftenFloatOperand Op #" << OpNo << ": ";
760  N->dump(&DAG); dbgs() << "\n";
761 #endif
762  llvm_unreachable("Do not know how to soften this operator's operand!");
763 
764  case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N); break;
765  case ISD::CopyToReg: Res = SoftenFloatOp_COPY_TO_REG(N); break;
766  case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break;
767  case ISD::FABS: Res = SoftenFloatOp_FABS(N); break;
768  case ISD::FCOPYSIGN: Res = SoftenFloatOp_FCOPYSIGN(N); break;
769  case ISD::FNEG: Res = SoftenFloatOp_FNEG(N); break;
770  case ISD::FP_EXTEND: Res = SoftenFloatOp_FP_EXTEND(N); break;
771  case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes
772  case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break;
773  case ISD::FP_TO_SINT:
774  case ISD::FP_TO_UINT: Res = SoftenFloatOp_FP_TO_XINT(N); break;
775  case ISD::SELECT: Res = SoftenFloatOp_SELECT(N); break;
776  case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break;
777  case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break;
778  case ISD::STORE:
779  Res = SoftenFloatOp_STORE(N, OpNo);
780  // Do not try to analyze or soften this node again if the value is
781  // or can be held in a register. In that case, Res.getNode() should
782  // be equal to N.
783  if (Res.getNode() == N &&
784  isLegalInHWReg(N->getOperand(OpNo).getValueType()))
785  return false;
786  // Otherwise, we need to reanalyze and lower the new Res nodes.
787  break;
788  }
789 
790  // If the result is null, the sub-method took care of registering results etc.
791  if (!Res.getNode()) return false;
792 
793  // If the result is N, the sub-method updated N in place. Tell the legalizer
794  // core about this to re-analyze.
795  if (Res.getNode() == N)
796  return true;
797 
798  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
799  "Invalid operand expansion");
800 
801  ReplaceValueWith(SDValue(N, 0), Res);
802  return false;
803 }
804 
805 bool DAGTypeLegalizer::CanSkipSoftenFloatOperand(SDNode *N, unsigned OpNo) {
806  if (!isLegalInHWReg(N->getOperand(OpNo).getValueType()))
807  return false;
808 
809  // When the operand type can be kept in registers there is nothing to do for
810  // the following opcodes.
811  switch (N->getOperand(OpNo).getOpcode()) {
812  case ISD::BITCAST:
813  case ISD::ConstantFP:
814  case ISD::CopyFromReg:
815  case ISD::CopyToReg:
816  case ISD::FABS:
817  case ISD::FCOPYSIGN:
818  case ISD::FNEG:
819  case ISD::Register:
820  case ISD::SELECT:
821  case ISD::SELECT_CC:
822  return true;
823  }
824 
825  switch (N->getOpcode()) {
826  case ISD::ConstantFP: // Leaf node.
827  case ISD::CopyFromReg: // Operand is a register that we know to be left
828  // unchanged by SoftenFloatResult().
829  case ISD::Register: // Leaf node.
830  return true;
831  }
832  return false;
833 }
834 
835 SDValue DAGTypeLegalizer::SoftenFloatOp_BITCAST(SDNode *N) {
836  return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
837  GetSoftenedFloat(N->getOperand(0)));
838 }
839 
840 SDValue DAGTypeLegalizer::SoftenFloatOp_COPY_TO_REG(SDNode *N) {
841  SDValue Op1 = GetSoftenedFloat(N->getOperand(1));
842  SDValue Op2 = GetSoftenedFloat(N->getOperand(2));
843 
844  if (Op1 == N->getOperand(1) && Op2 == N->getOperand(2))
845  return SDValue();
846 
847  if (N->getNumOperands() == 3)
848  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op1, Op2), 0);
849 
850  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op1, Op2,
851  N->getOperand(3)),
852  0);
853 }
854 
855 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_EXTEND(SDNode *N) {
856  // If we get here, the result must be legal but the source illegal.
857  EVT SVT = N->getOperand(0).getValueType();
858  EVT RVT = N->getValueType(0);
859  SDValue Op = GetSoftenedFloat(N->getOperand(0));
860 
861  if (SVT == MVT::f16)
862  return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), RVT, Op);
863 
864  RTLIB::Libcall LC = RTLIB::getFPEXT(SVT, RVT);
865  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND libcall");
866 
867  return TLI.makeLibCall(DAG, LC, RVT, Op, false, SDLoc(N)).first;
868 }
869 
870 
871 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_ROUND(SDNode *N) {
872  // We actually deal with the partially-softened FP_TO_FP16 node too, which
873  // returns an i16 so doesn't meet the constraints necessary for FP_ROUND.
875 
876  EVT SVT = N->getOperand(0).getValueType();
877  EVT RVT = N->getValueType(0);
878  EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT;
879 
880  RTLIB::Libcall LC = RTLIB::getFPROUND(SVT, FloatRVT);
881  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND libcall");
882 
883  SDValue Op = GetSoftenedFloat(N->getOperand(0));
884  return TLI.makeLibCall(DAG, LC, RVT, Op, false, SDLoc(N)).first;
885 }
886 
887 SDValue DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) {
888  SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
889  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
890 
891  EVT VT = NewLHS.getValueType();
892  NewLHS = GetSoftenedFloat(NewLHS);
893  NewRHS = GetSoftenedFloat(NewRHS);
894  TLI.softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, SDLoc(N));
895 
896  // If softenSetCCOperands returned a scalar, we need to compare the result
897  // against zero to select between true and false values.
898  if (!NewRHS.getNode()) {
899  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
900  CCCode = ISD::SETNE;
901  }
902 
903  // Update N to have the operands specified.
904  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
905  DAG.getCondCode(CCCode), NewLHS, NewRHS,
906  N->getOperand(4)),
907  0);
908 }
909 
910 SDValue DAGTypeLegalizer::SoftenFloatOp_FABS(SDNode *N) {
911  SDValue Op = GetSoftenedFloat(N->getOperand(0));
912 
913  if (Op == N->getOperand(0))
914  return SDValue();
915 
916  return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
917 }
918 
919 SDValue DAGTypeLegalizer::SoftenFloatOp_FCOPYSIGN(SDNode *N) {
920  SDValue Op0 = GetSoftenedFloat(N->getOperand(0));
921  SDValue Op1 = GetSoftenedFloat(N->getOperand(1));
922 
923  if (Op0 == N->getOperand(0) && Op1 == N->getOperand(1))
924  return SDValue();
925 
926  return SDValue(DAG.UpdateNodeOperands(N, Op0, Op1), 0);
927 }
928 
929 SDValue DAGTypeLegalizer::SoftenFloatOp_FNEG(SDNode *N) {
930  SDValue Op = GetSoftenedFloat(N->getOperand(0));
931 
932  if (Op == N->getOperand(0))
933  return SDValue();
934 
935  return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
936 }
937 
938 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_XINT(SDNode *N) {
939  bool Signed = N->getOpcode() == ISD::FP_TO_SINT;
940  EVT SVT = N->getOperand(0).getValueType();
941  EVT RVT = N->getValueType(0);
942  EVT NVT = EVT();
943  SDLoc dl(N);
944 
945  // If the result is not legal, eg: fp -> i1, then it needs to be promoted to
946  // a larger type, eg: fp -> i32. Even if it is legal, no libcall may exactly
947  // match, eg. we don't have fp -> i8 conversions.
948  // Look for an appropriate libcall.
949  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
950  for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE;
951  IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL;
952  ++IntVT) {
953  NVT = (MVT::SimpleValueType)IntVT;
954  // The type needs to big enough to hold the result.
955  if (NVT.bitsGE(RVT))
956  LC = Signed ? RTLIB::getFPTOSINT(SVT, NVT):RTLIB::getFPTOUINT(SVT, NVT);
957  }
958  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_XINT!");
959 
960  SDValue Op = GetSoftenedFloat(N->getOperand(0));
961  SDValue Res = TLI.makeLibCall(DAG, LC, NVT, Op, false, dl).first;
962 
963  // Truncate the result if the libcall returns a larger type.
964  return DAG.getNode(ISD::TRUNCATE, dl, RVT, Res);
965 }
966 
967 SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT(SDNode *N) {
968  SDValue Op1 = GetSoftenedFloat(N->getOperand(1));
969  SDValue Op2 = GetSoftenedFloat(N->getOperand(2));
970 
971  if (Op1 == N->getOperand(1) && Op2 == N->getOperand(2))
972  return SDValue();
973 
974  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op1, Op2),
975  0);
976 }
977 
978 SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(SDNode *N) {
979  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
980  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
981 
982  EVT VT = NewLHS.getValueType();
983  NewLHS = GetSoftenedFloat(NewLHS);
984  NewRHS = GetSoftenedFloat(NewRHS);
985  TLI.softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, SDLoc(N));
986 
987  // If softenSetCCOperands returned a scalar, we need to compare the result
988  // against zero to select between true and false values.
989  if (!NewRHS.getNode()) {
990  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
991  CCCode = ISD::SETNE;
992  }
993 
994  // Update N to have the operands specified.
995  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
996  N->getOperand(2), N->getOperand(3),
997  DAG.getCondCode(CCCode)),
998  0);
999 }
1000 
1001 SDValue DAGTypeLegalizer::SoftenFloatOp_SETCC(SDNode *N) {
1002  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1003  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1004 
1005  EVT VT = NewLHS.getValueType();
1006  NewLHS = GetSoftenedFloat(NewLHS);
1007  NewRHS = GetSoftenedFloat(NewRHS);
1008  TLI.softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, SDLoc(N));
1009 
1010  // If softenSetCCOperands returned a scalar, use it.
1011  if (!NewRHS.getNode()) {
1012  assert(NewLHS.getValueType() == N->getValueType(0) &&
1013  "Unexpected setcc expansion!");
1014  return NewLHS;
1015  }
1016 
1017  // Otherwise, update N to have the operands specified.
1018  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
1019  DAG.getCondCode(CCCode)),
1020  0);
1021 }
1022 
1023 SDValue DAGTypeLegalizer::SoftenFloatOp_STORE(SDNode *N, unsigned OpNo) {
1024  assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1025  assert(OpNo == 1 && "Can only soften the stored value!");
1026  StoreSDNode *ST = cast<StoreSDNode>(N);
1027  SDValue Val = ST->getValue();
1028  SDLoc dl(N);
1029 
1030  if (ST->isTruncatingStore())
1031  // Do an FP_ROUND followed by a non-truncating store.
1032  Val = BitConvertToInteger(DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(),
1033  Val, DAG.getIntPtrConstant(0, dl)));
1034  else
1035  Val = GetSoftenedFloat(Val);
1036 
1037  return DAG.getStore(ST->getChain(), dl, Val, ST->getBasePtr(),
1038  ST->getMemOperand());
1039 }
1040 
1041 
1042 //===----------------------------------------------------------------------===//
1043 // Float Result Expansion
1044 //===----------------------------------------------------------------------===//
1045 
1046 /// ExpandFloatResult - This method is called when the specified result of the
1047 /// specified node is found to need expansion. At this point, the node may also
1048 /// have invalid operands or may have other results that need promotion, we just
1049 /// know that (at least) one result needs expansion.
1050 void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
1051  LLVM_DEBUG(dbgs() << "Expand float result: "; N->dump(&DAG); dbgs() << "\n");
1052  SDValue Lo, Hi;
1053  Lo = Hi = SDValue();
1054 
1055  // See if the target wants to custom expand this node.
1056  if (CustomLowerNode(N, N->getValueType(ResNo), true))
1057  return;
1058 
1059  switch (N->getOpcode()) {
1060  default:
1061 #ifndef NDEBUG
1062  dbgs() << "ExpandFloatResult #" << ResNo << ": ";
1063  N->dump(&DAG); dbgs() << "\n";
1064 #endif
1065  llvm_unreachable("Do not know how to expand the result of this operator!");
1066 
1067  case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1068  case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1069  case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1070 
1071  case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1072  case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1073  case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1074  case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1075  case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1076  case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1077 
1078  case ISD::ConstantFP: ExpandFloatRes_ConstantFP(N, Lo, Hi); break;
1079  case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break;
1080  case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break;
1081  case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break;
1082  case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break;
1083  case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break;
1084  case ISD::FCOPYSIGN: ExpandFloatRes_FCOPYSIGN(N, Lo, Hi); break;
1085  case ISD::FCOS: ExpandFloatRes_FCOS(N, Lo, Hi); break;
1086  case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break;
1087  case ISD::FEXP: ExpandFloatRes_FEXP(N, Lo, Hi); break;
1088  case ISD::FEXP2: ExpandFloatRes_FEXP2(N, Lo, Hi); break;
1089  case ISD::FFLOOR: ExpandFloatRes_FFLOOR(N, Lo, Hi); break;
1090  case ISD::FLOG: ExpandFloatRes_FLOG(N, Lo, Hi); break;
1091  case ISD::FLOG2: ExpandFloatRes_FLOG2(N, Lo, Hi); break;
1092  case ISD::FLOG10: ExpandFloatRes_FLOG10(N, Lo, Hi); break;
1093  case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi); break;
1094  case ISD::FMUL: ExpandFloatRes_FMUL(N, Lo, Hi); break;
1095  case ISD::FNEARBYINT: ExpandFloatRes_FNEARBYINT(N, Lo, Hi); break;
1096  case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break;
1097  case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break;
1098  case ISD::FPOW: ExpandFloatRes_FPOW(N, Lo, Hi); break;
1099  case ISD::FPOWI: ExpandFloatRes_FPOWI(N, Lo, Hi); break;
1100  case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break;
1101  case ISD::FROUND: ExpandFloatRes_FROUND(N, Lo, Hi); break;
1102  case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break;
1103  case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break;
1104  case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
1105  case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break;
1106  case ISD::LOAD: ExpandFloatRes_LOAD(N, Lo, Hi); break;
1107  case ISD::SINT_TO_FP:
1108  case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break;
1109  case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break;
1110  }
1111 
1112  // If Lo/Hi is null, the sub-method took care of registering results etc.
1113  if (Lo.getNode())
1114  SetExpandedFloat(SDValue(N, ResNo), Lo, Hi);
1115 }
1116 
1117 void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo,
1118  SDValue &Hi) {
1119  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1120  assert(NVT.getSizeInBits() == 64 &&
1121  "Do not know how to expand this float constant!");
1122  APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().bitcastToAPInt();
1123  SDLoc dl(N);
1124  Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1125  APInt(64, C.getRawData()[1])),
1126  dl, NVT);
1127  Hi = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1128  APInt(64, C.getRawData()[0])),
1129  dl, NVT);
1130 }
1131 
1132 void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
1133  SDValue &Hi) {
1134  assert(N->getValueType(0) == MVT::ppcf128 &&
1135  "Logic only correct for ppcf128!");
1136  SDLoc dl(N);
1137  SDValue Tmp;
1138  GetExpandedFloat(N->getOperand(0), Lo, Tmp);
1139  Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp);
1140  // Lo = Hi==fabs(Hi) ? Lo : -Lo;
1141  Lo = DAG.getSelectCC(dl, Tmp, Hi, Lo,
1142  DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo),
1143  ISD::SETEQ);
1144 }
1145 
1146 void DAGTypeLegalizer::ExpandFloatRes_FMINNUM(SDNode *N, SDValue &Lo,
1147  SDValue &Hi) {
1148  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1149  RTLIB::FMIN_F32, RTLIB::FMIN_F64,
1150  RTLIB::FMIN_F80, RTLIB::FMIN_F128,
1151  RTLIB::FMIN_PPCF128),
1152  N, false);
1153  GetPairElements(Call, Lo, Hi);
1154 }
1155 
1156 void DAGTypeLegalizer::ExpandFloatRes_FMAXNUM(SDNode *N, SDValue &Lo,
1157  SDValue &Hi) {
1158  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1159  RTLIB::FMAX_F32, RTLIB::FMAX_F64,
1160  RTLIB::FMAX_F80, RTLIB::FMAX_F128,
1161  RTLIB::FMAX_PPCF128),
1162  N, false);
1163  GetPairElements(Call, Lo, Hi);
1164 }
1165 
1166 void DAGTypeLegalizer::ExpandFloatRes_FADD(SDNode *N, SDValue &Lo,
1167  SDValue &Hi) {
1168  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1169  RTLIB::ADD_F32, RTLIB::ADD_F64,
1170  RTLIB::ADD_F80, RTLIB::ADD_F128,
1171  RTLIB::ADD_PPCF128),
1172  N, false);
1173  GetPairElements(Call, Lo, Hi);
1174 }
1175 
1176 void DAGTypeLegalizer::ExpandFloatRes_FCEIL(SDNode *N,
1177  SDValue &Lo, SDValue &Hi) {
1178  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1179  RTLIB::CEIL_F32, RTLIB::CEIL_F64,
1180  RTLIB::CEIL_F80, RTLIB::CEIL_F128,
1181  RTLIB::CEIL_PPCF128),
1182  N, false);
1183  GetPairElements(Call, Lo, Hi);
1184 }
1185 
1186 void DAGTypeLegalizer::ExpandFloatRes_FCOPYSIGN(SDNode *N,
1187  SDValue &Lo, SDValue &Hi) {
1188  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1189  RTLIB::COPYSIGN_F32,
1190  RTLIB::COPYSIGN_F64,
1191  RTLIB::COPYSIGN_F80,
1192  RTLIB::COPYSIGN_F128,
1193  RTLIB::COPYSIGN_PPCF128),
1194  N, false);
1195  GetPairElements(Call, Lo, Hi);
1196 }
1197 
1198 void DAGTypeLegalizer::ExpandFloatRes_FCOS(SDNode *N,
1199  SDValue &Lo, SDValue &Hi) {
1200  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1201  RTLIB::COS_F32, RTLIB::COS_F64,
1202  RTLIB::COS_F80, RTLIB::COS_F128,
1203  RTLIB::COS_PPCF128),
1204  N, false);
1205  GetPairElements(Call, Lo, Hi);
1206 }
1207 
1208 void DAGTypeLegalizer::ExpandFloatRes_FDIV(SDNode *N, SDValue &Lo,
1209  SDValue &Hi) {
1210  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1211  SDValue Call = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
1212  RTLIB::DIV_F32,
1213  RTLIB::DIV_F64,
1214  RTLIB::DIV_F80,
1215  RTLIB::DIV_F128,
1216  RTLIB::DIV_PPCF128),
1217  N->getValueType(0), Ops, false,
1218  SDLoc(N)).first;
1219  GetPairElements(Call, Lo, Hi);
1220 }
1221 
1222 void DAGTypeLegalizer::ExpandFloatRes_FEXP(SDNode *N,
1223  SDValue &Lo, SDValue &Hi) {
1224  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1225  RTLIB::EXP_F32, RTLIB::EXP_F64,
1226  RTLIB::EXP_F80, RTLIB::EXP_F128,
1227  RTLIB::EXP_PPCF128),
1228  N, false);
1229  GetPairElements(Call, Lo, Hi);
1230 }
1231 
1232 void DAGTypeLegalizer::ExpandFloatRes_FEXP2(SDNode *N,
1233  SDValue &Lo, SDValue &Hi) {
1234  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1235  RTLIB::EXP2_F32, RTLIB::EXP2_F64,
1236  RTLIB::EXP2_F80, RTLIB::EXP2_F128,
1237  RTLIB::EXP2_PPCF128),
1238  N, false);
1239  GetPairElements(Call, Lo, Hi);
1240 }
1241 
1242 void DAGTypeLegalizer::ExpandFloatRes_FFLOOR(SDNode *N,
1243  SDValue &Lo, SDValue &Hi) {
1244  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1245  RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
1246  RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
1247  RTLIB::FLOOR_PPCF128),
1248  N, false);
1249  GetPairElements(Call, Lo, Hi);
1250 }
1251 
1252 void DAGTypeLegalizer::ExpandFloatRes_FLOG(SDNode *N,
1253  SDValue &Lo, SDValue &Hi) {
1254  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1255  RTLIB::LOG_F32, RTLIB::LOG_F64,
1256  RTLIB::LOG_F80, RTLIB::LOG_F128,
1257  RTLIB::LOG_PPCF128),
1258  N, false);
1259  GetPairElements(Call, Lo, Hi);
1260 }
1261 
1262 void DAGTypeLegalizer::ExpandFloatRes_FLOG2(SDNode *N,
1263  SDValue &Lo, SDValue &Hi) {
1264  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1265  RTLIB::LOG2_F32, RTLIB::LOG2_F64,
1266  RTLIB::LOG2_F80, RTLIB::LOG2_F128,
1267  RTLIB::LOG2_PPCF128),
1268  N, false);
1269  GetPairElements(Call, Lo, Hi);
1270 }
1271 
1272 void DAGTypeLegalizer::ExpandFloatRes_FLOG10(SDNode *N,
1273  SDValue &Lo, SDValue &Hi) {
1274  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1275  RTLIB::LOG10_F32, RTLIB::LOG10_F64,
1276  RTLIB::LOG10_F80, RTLIB::LOG10_F128,
1277  RTLIB::LOG10_PPCF128),
1278  N, false);
1279  GetPairElements(Call, Lo, Hi);
1280 }
1281 
1282 void DAGTypeLegalizer::ExpandFloatRes_FMA(SDNode *N, SDValue &Lo,
1283  SDValue &Hi) {
1284  SDValue Ops[3] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
1285  SDValue Call = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
1286  RTLIB::FMA_F32,
1287  RTLIB::FMA_F64,
1288  RTLIB::FMA_F80,
1289  RTLIB::FMA_F128,
1290  RTLIB::FMA_PPCF128),
1291  N->getValueType(0), Ops, false,
1292  SDLoc(N)).first;
1293  GetPairElements(Call, Lo, Hi);
1294 }
1295 
1296 void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo,
1297  SDValue &Hi) {
1298  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1299  SDValue Call = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
1300  RTLIB::MUL_F32,
1301  RTLIB::MUL_F64,
1302  RTLIB::MUL_F80,
1303  RTLIB::MUL_F128,
1304  RTLIB::MUL_PPCF128),
1305  N->getValueType(0), Ops, false,
1306  SDLoc(N)).first;
1307  GetPairElements(Call, Lo, Hi);
1308 }
1309 
1310 void DAGTypeLegalizer::ExpandFloatRes_FNEARBYINT(SDNode *N,
1311  SDValue &Lo, SDValue &Hi) {
1312  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1313  RTLIB::NEARBYINT_F32,
1314  RTLIB::NEARBYINT_F64,
1315  RTLIB::NEARBYINT_F80,
1316  RTLIB::NEARBYINT_F128,
1317  RTLIB::NEARBYINT_PPCF128),
1318  N, false);
1319  GetPairElements(Call, Lo, Hi);
1320 }
1321 
1322 void DAGTypeLegalizer::ExpandFloatRes_FNEG(SDNode *N, SDValue &Lo,
1323  SDValue &Hi) {
1324  SDLoc dl(N);
1325  GetExpandedFloat(N->getOperand(0), Lo, Hi);
1326  Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo);
1327  Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi);
1328 }
1329 
1330 void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo,
1331  SDValue &Hi) {
1332  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1333  SDLoc dl(N);
1334  Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0));
1335  Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1336  APInt(NVT.getSizeInBits(), 0)), dl, NVT);
1337 }
1338 
1339 void DAGTypeLegalizer::ExpandFloatRes_FPOW(SDNode *N,
1340  SDValue &Lo, SDValue &Hi) {
1341  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1342  RTLIB::POW_F32, RTLIB::POW_F64,
1343  RTLIB::POW_F80, RTLIB::POW_F128,
1344  RTLIB::POW_PPCF128),
1345  N, false);
1346  GetPairElements(Call, Lo, Hi);
1347 }
1348 
1349 void DAGTypeLegalizer::ExpandFloatRes_FPOWI(SDNode *N,
1350  SDValue &Lo, SDValue &Hi) {
1351  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1352  RTLIB::POWI_F32, RTLIB::POWI_F64,
1353  RTLIB::POWI_F80, RTLIB::POWI_F128,
1354  RTLIB::POWI_PPCF128),
1355  N, false);
1356  GetPairElements(Call, Lo, Hi);
1357 }
1358 
1359 void DAGTypeLegalizer::ExpandFloatRes_FREM(SDNode *N,
1360  SDValue &Lo, SDValue &Hi) {
1361  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1362  RTLIB::REM_F32, RTLIB::REM_F64,
1363  RTLIB::REM_F80, RTLIB::REM_F128,
1364  RTLIB::REM_PPCF128),
1365  N, false);
1366  GetPairElements(Call, Lo, Hi);
1367 }
1368 
1369 void DAGTypeLegalizer::ExpandFloatRes_FRINT(SDNode *N,
1370  SDValue &Lo, SDValue &Hi) {
1371  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1372  RTLIB::RINT_F32, RTLIB::RINT_F64,
1373  RTLIB::RINT_F80, RTLIB::RINT_F128,
1374  RTLIB::RINT_PPCF128),
1375  N, false);
1376  GetPairElements(Call, Lo, Hi);
1377 }
1378 
1379 void DAGTypeLegalizer::ExpandFloatRes_FROUND(SDNode *N,
1380  SDValue &Lo, SDValue &Hi) {
1381  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1382  RTLIB::ROUND_F32,
1383  RTLIB::ROUND_F64,
1384  RTLIB::ROUND_F80,
1385  RTLIB::ROUND_F128,
1386  RTLIB::ROUND_PPCF128),
1387  N, false);
1388  GetPairElements(Call, Lo, Hi);
1389 }
1390 
1391 void DAGTypeLegalizer::ExpandFloatRes_FSIN(SDNode *N,
1392  SDValue &Lo, SDValue &Hi) {
1393  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1394  RTLIB::SIN_F32, RTLIB::SIN_F64,
1395  RTLIB::SIN_F80, RTLIB::SIN_F128,
1396  RTLIB::SIN_PPCF128),
1397  N, false);
1398  GetPairElements(Call, Lo, Hi);
1399 }
1400 
1401 void DAGTypeLegalizer::ExpandFloatRes_FSQRT(SDNode *N,
1402  SDValue &Lo, SDValue &Hi) {
1403  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1404  RTLIB::SQRT_F32, RTLIB::SQRT_F64,
1405  RTLIB::SQRT_F80, RTLIB::SQRT_F128,
1406  RTLIB::SQRT_PPCF128),
1407  N, false);
1408  GetPairElements(Call, Lo, Hi);
1409 }
1410 
1411 void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo,
1412  SDValue &Hi) {
1413  SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1414  SDValue Call = TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
1415  RTLIB::SUB_F32,
1416  RTLIB::SUB_F64,
1417  RTLIB::SUB_F80,
1418  RTLIB::SUB_F128,
1419  RTLIB::SUB_PPCF128),
1420  N->getValueType(0), Ops, false,
1421  SDLoc(N)).first;
1422  GetPairElements(Call, Lo, Hi);
1423 }
1424 
1425 void DAGTypeLegalizer::ExpandFloatRes_FTRUNC(SDNode *N,
1426  SDValue &Lo, SDValue &Hi) {
1427  SDValue Call = LibCallify(GetFPLibCall(N->getValueType(0),
1428  RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
1429  RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
1430  RTLIB::TRUNC_PPCF128),
1431  N, false);
1432  GetPairElements(Call, Lo, Hi);
1433 }
1434 
1435 void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo,
1436  SDValue &Hi) {
1437  if (ISD::isNormalLoad(N)) {
1438  ExpandRes_NormalLoad(N, Lo, Hi);
1439  return;
1440  }
1441 
1442  assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1443  LoadSDNode *LD = cast<LoadSDNode>(N);
1444  SDValue Chain = LD->getChain();
1445  SDValue Ptr = LD->getBasePtr();
1446  SDLoc dl(N);
1447 
1448  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), LD->getValueType(0));
1449  assert(NVT.isByteSized() && "Expanded type not byte sized!");
1450  assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?");
1451 
1452  Hi = DAG.getExtLoad(LD->getExtensionType(), dl, NVT, Chain, Ptr,
1453  LD->getMemoryVT(), LD->getMemOperand());
1454 
1455  // Remember the chain.
1456  Chain = Hi.getValue(1);
1457 
1458  // The low part is zero.
1459  Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1460  APInt(NVT.getSizeInBits(), 0)), dl, NVT);
1461 
1462  // Modified the chain - switch anything that used the old chain to use the
1463  // new one.
1464  ReplaceValueWith(SDValue(LD, 1), Chain);
1465 }
1466 
1467 void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
1468  SDValue &Hi) {
1469  assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
1470  EVT VT = N->getValueType(0);
1471  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1472  SDValue Src = N->getOperand(0);
1473  EVT SrcVT = Src.getValueType();
1474  bool isSigned = N->getOpcode() == ISD::SINT_TO_FP;
1475  SDLoc dl(N);
1476 
1477  // First do an SINT_TO_FP, whether the original was signed or unsigned.
1478  // When promoting partial word types to i32 we must honor the signedness,
1479  // though.
1480  if (SrcVT.bitsLE(MVT::i32)) {
1481  // The integer can be represented exactly in an f64.
1482  Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1483  MVT::i32, Src);
1484  Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1485  APInt(NVT.getSizeInBits(), 0)), dl, NVT);
1486  Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src);
1487  } else {
1488  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1489  if (SrcVT.bitsLE(MVT::i64)) {
1490  Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1491  MVT::i64, Src);
1492  LC = RTLIB::SINTTOFP_I64_PPCF128;
1493  } else if (SrcVT.bitsLE(MVT::i128)) {
1494  Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
1495  LC = RTLIB::SINTTOFP_I128_PPCF128;
1496  }
1497  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
1498 
1499  Hi = TLI.makeLibCall(DAG, LC, VT, Src, true, dl).first;
1500  GetPairElements(Hi, Lo, Hi);
1501  }
1502 
1503  if (isSigned)
1504  return;
1505 
1506  // Unsigned - fix up the SINT_TO_FP value just calculated.
1507  Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
1508  SrcVT = Src.getValueType();
1509 
1510  // x>=0 ? (ppcf128)(iN)x : (ppcf128)(iN)x + 2^N; N=32,64,128.
1511  static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
1512  static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
1513  static const uint64_t TwoE128[] = { 0x47f0000000000000LL, 0 };
1514  ArrayRef<uint64_t> Parts;
1515 
1516  switch (SrcVT.getSimpleVT().SimpleTy) {
1517  default:
1518  llvm_unreachable("Unsupported UINT_TO_FP!");
1519  case MVT::i32:
1520  Parts = TwoE32;
1521  break;
1522  case MVT::i64:
1523  Parts = TwoE64;
1524  break;
1525  case MVT::i128:
1526  Parts = TwoE128;
1527  break;
1528  }
1529 
1530  // TODO: Are there fast-math-flags to propagate to this FADD?
1531  Lo = DAG.getNode(ISD::FADD, dl, VT, Hi,
1533  APInt(128, Parts)),
1534  dl, MVT::ppcf128));
1535  Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, dl, SrcVT),
1536  Lo, Hi, ISD::SETLT);
1537  GetPairElements(Lo, Lo, Hi);
1538 }
1539 
1540 
1541 //===----------------------------------------------------------------------===//
1542 // Float Operand Expansion
1543 //===----------------------------------------------------------------------===//
1544 
1545 /// ExpandFloatOperand - This method is called when the specified operand of the
1546 /// specified node is found to need expansion. At this point, all of the result
1547 /// types of the node are known to be legal, but other operands of the node may
1548 /// need promotion or expansion as well as the specified one.
1549 bool DAGTypeLegalizer::ExpandFloatOperand(SDNode *N, unsigned OpNo) {
1550  LLVM_DEBUG(dbgs() << "Expand float operand: "; N->dump(&DAG); dbgs() << "\n");
1551  SDValue Res = SDValue();
1552 
1553  // See if the target wants to custom expand this node.
1554  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1555  return false;
1556 
1557  switch (N->getOpcode()) {
1558  default:
1559 #ifndef NDEBUG
1560  dbgs() << "ExpandFloatOperand Op #" << OpNo << ": ";
1561  N->dump(&DAG); dbgs() << "\n";
1562 #endif
1563  llvm_unreachable("Do not know how to expand this operator's operand!");
1564 
1565  case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
1566  case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1567  case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1568 
1569  case ISD::BR_CC: Res = ExpandFloatOp_BR_CC(N); break;
1570  case ISD::FCOPYSIGN: Res = ExpandFloatOp_FCOPYSIGN(N); break;
1571  case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break;
1572  case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break;
1573  case ISD::FP_TO_UINT: Res = ExpandFloatOp_FP_TO_UINT(N); break;
1574  case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break;
1575  case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break;
1576  case ISD::STORE: Res = ExpandFloatOp_STORE(cast<StoreSDNode>(N),
1577  OpNo); break;
1578  }
1579 
1580  // If the result is null, the sub-method took care of registering results etc.
1581  if (!Res.getNode()) return false;
1582 
1583  // If the result is N, the sub-method updated N in place. Tell the legalizer
1584  // core about this.
1585  if (Res.getNode() == N)
1586  return true;
1587 
1588  assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1589  "Invalid operand expansion");
1590 
1591  ReplaceValueWith(SDValue(N, 0), Res);
1592  return false;
1593 }
1594 
1595 /// FloatExpandSetCCOperands - Expand the operands of a comparison. This code
1596 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1597 void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS,
1598  SDValue &NewRHS,
1599  ISD::CondCode &CCCode,
1600  const SDLoc &dl) {
1601  SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1602  GetExpandedFloat(NewLHS, LHSLo, LHSHi);
1603  GetExpandedFloat(NewRHS, RHSLo, RHSHi);
1604 
1605  assert(NewLHS.getValueType() == MVT::ppcf128 && "Unsupported setcc type!");
1606 
1607  // FIXME: This generated code sucks. We want to generate
1608  // FCMPU crN, hi1, hi2
1609  // BNE crN, L:
1610  // FCMPU crN, lo1, lo2
1611  // The following can be improved, but not that much.
1612  SDValue Tmp1, Tmp2, Tmp3;
1613  Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
1614  LHSHi, RHSHi, ISD::SETOEQ);
1615  Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
1616  LHSLo, RHSLo, CCCode);
1617  Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1618  Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
1619  LHSHi, RHSHi, ISD::SETUNE);
1620  Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
1621  LHSHi, RHSHi, CCCode);
1622  Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1623  NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
1624  NewRHS = SDValue(); // LHS is the result, not a compare.
1625 }
1626 
1627 SDValue DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) {
1628  SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1629  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1630  FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
1631 
1632  // If ExpandSetCCOperands returned a scalar, we need to compare the result
1633  // against zero to select between true and false values.
1634  if (!NewRHS.getNode()) {
1635  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
1636  CCCode = ISD::SETNE;
1637  }
1638 
1639  // Update N to have the operands specified.
1640  return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1641  DAG.getCondCode(CCCode), NewLHS, NewRHS,
1642  N->getOperand(4)), 0);
1643 }
1644 
1645 SDValue DAGTypeLegalizer::ExpandFloatOp_FCOPYSIGN(SDNode *N) {
1647  "Logic only correct for ppcf128!");
1648  SDValue Lo, Hi;
1649  GetExpandedFloat(N->getOperand(1), Lo, Hi);
1650  // The ppcf128 value is providing only the sign; take it from the
1651  // higher-order double (which must have the larger magnitude).
1652  return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N),
1653  N->getValueType(0), N->getOperand(0), Hi);
1654 }
1655 
1656 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
1658  "Logic only correct for ppcf128!");
1659  SDValue Lo, Hi;
1660  GetExpandedFloat(N->getOperand(0), Lo, Hi);
1661  // Round it the rest of the way (e.g. to f32) if needed.
1662  return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
1663  N->getValueType(0), Hi, N->getOperand(1));
1664 }
1665 
1666 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
1667  EVT RVT = N->getValueType(0);
1668  SDLoc dl(N);
1669 
1671  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
1672  return TLI.makeLibCall(DAG, LC, RVT, N->getOperand(0), false, dl).first;
1673 }
1674 
1675 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
1676  EVT RVT = N->getValueType(0);
1677  SDLoc dl(N);
1678 
1680  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!");
1681  return TLI.makeLibCall(DAG, LC, N->getValueType(0), N->getOperand(0),
1682  false, dl).first;
1683 }
1684 
1685 SDValue DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(SDNode *N) {
1686  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1687  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
1688  FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
1689 
1690  // If ExpandSetCCOperands returned a scalar, we need to compare the result
1691  // against zero to select between true and false values.
1692  if (!NewRHS.getNode()) {
1693  NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
1694  CCCode = ISD::SETNE;
1695  }
1696 
1697  // Update N to have the operands specified.
1698  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
1699  N->getOperand(2), N->getOperand(3),
1700  DAG.getCondCode(CCCode)), 0);
1701 }
1702 
1703 SDValue DAGTypeLegalizer::ExpandFloatOp_SETCC(SDNode *N) {
1704  SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1705  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1706  FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
1707 
1708  // If ExpandSetCCOperands returned a scalar, use it.
1709  if (!NewRHS.getNode()) {
1710  assert(NewLHS.getValueType() == N->getValueType(0) &&
1711  "Unexpected setcc expansion!");
1712  return NewLHS;
1713  }
1714 
1715  // Otherwise, update N to have the operands specified.
1716  return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
1717  DAG.getCondCode(CCCode)), 0);
1718 }
1719 
1720 SDValue DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) {
1721  if (ISD::isNormalStore(N))
1722  return ExpandOp_NormalStore(N, OpNo);
1723 
1724  assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1725  assert(OpNo == 1 && "Can only expand the stored value so far");
1726  StoreSDNode *ST = cast<StoreSDNode>(N);
1727 
1728  SDValue Chain = ST->getChain();
1729  SDValue Ptr = ST->getBasePtr();
1730 
1731  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(),
1732  ST->getValue().getValueType());
1733  assert(NVT.isByteSized() && "Expanded type not byte sized!");
1734  assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?");
1735  (void)NVT;
1736 
1737  SDValue Lo, Hi;
1738  GetExpandedOp(ST->getValue(), Lo, Hi);
1739 
1740  return DAG.getTruncStore(Chain, SDLoc(N), Hi, Ptr,
1741  ST->getMemoryVT(), ST->getMemOperand());
1742 }
1743 
1744 //===----------------------------------------------------------------------===//
1745 // Float Operand Promotion
1746 //===----------------------------------------------------------------------===//
1747 //
1748 
1750  if (OpVT == MVT::f16) {
1751  return ISD::FP16_TO_FP;
1752  } else if (RetVT == MVT::f16) {
1753  return ISD::FP_TO_FP16;
1754  }
1755 
1756  report_fatal_error("Attempt at an invalid promotion-related conversion");
1757 }
1758 
1759 bool DAGTypeLegalizer::PromoteFloatOperand(SDNode *N, unsigned OpNo) {
1760  LLVM_DEBUG(dbgs() << "Promote float operand " << OpNo << ": "; N->dump(&DAG);
1761  dbgs() << "\n");
1762  SDValue R = SDValue();
1763 
1764  if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
1765  LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
1766  return false;
1767  }
1768 
1769  // Nodes that use a promotion-requiring floating point operand, but doesn't
1770  // produce a promotion-requiring floating point result, need to be legalized
1771  // to use the promoted float operand. Nodes that produce at least one
1772  // promotion-requiring floating point result have their operands legalized as
1773  // a part of PromoteFloatResult.
1774  switch (N->getOpcode()) {
1775  default:
1776  #ifndef NDEBUG
1777  dbgs() << "PromoteFloatOperand Op #" << OpNo << ": ";
1778  N->dump(&DAG); dbgs() << "\n";
1779  #endif
1780  llvm_unreachable("Do not know how to promote this operator's operand!");
1781 
1782  case ISD::BITCAST: R = PromoteFloatOp_BITCAST(N, OpNo); break;
1783  case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break;
1784  case ISD::FP_TO_SINT:
1785  case ISD::FP_TO_UINT: R = PromoteFloatOp_FP_TO_XINT(N, OpNo); break;
1786  case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break;
1787  case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break;
1788  case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break;
1789  case ISD::STORE: R = PromoteFloatOp_STORE(N, OpNo); break;
1790  }
1791 
1792  if (R.getNode())
1793  ReplaceValueWith(SDValue(N, 0), R);
1794  return false;
1795 }
1796 
1797 SDValue DAGTypeLegalizer::PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo) {
1798  SDValue Op = N->getOperand(0);
1799  EVT OpVT = Op->getValueType(0);
1800 
1801  SDValue Promoted = GetPromotedFloat(N->getOperand(0));
1802  EVT PromotedVT = Promoted->getValueType(0);
1803 
1804  // Convert the promoted float value to the desired IVT.
1805  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits());
1806  SDValue Convert = DAG.getNode(GetPromotionOpcode(PromotedVT, OpVT), SDLoc(N),
1807  IVT, Promoted);
1808  // The final result type might not be an scalar so we need a bitcast. The
1809  // bitcast will be further legalized if needed.
1810  return DAG.getBitcast(N->getValueType(0), Convert);
1811 }
1812 
1813 // Promote Operand 1 of FCOPYSIGN. Operand 0 ought to be handled by
1814 // PromoteFloatRes_FCOPYSIGN.
1815 SDValue DAGTypeLegalizer::PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo) {
1816  assert (OpNo == 1 && "Only Operand 1 must need promotion here");
1817  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
1818 
1819  return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
1820  N->getOperand(0), Op1);
1821 }
1822 
1823 // Convert the promoted float value to the desired integer type
1824 SDValue DAGTypeLegalizer::PromoteFloatOp_FP_TO_XINT(SDNode *N, unsigned OpNo) {
1825  SDValue Op = GetPromotedFloat(N->getOperand(0));
1826  return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), Op);
1827 }
1828 
1829 SDValue DAGTypeLegalizer::PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo) {
1830  SDValue Op = GetPromotedFloat(N->getOperand(0));
1831  EVT VT = N->getValueType(0);
1832 
1833  // Desired VT is same as promoted type. Use promoted float directly.
1834  if (VT == Op->getValueType(0))
1835  return Op;
1836 
1837  // Else, extend the promoted float value to the desired VT.
1838  return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op);
1839 }
1840 
1841 // Promote the float operands used for comparison. The true- and false-
1842 // operands have the same type as the result and are promoted, if needed, by
1843 // PromoteFloatRes_SELECT_CC
1844 SDValue DAGTypeLegalizer::PromoteFloatOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1845  SDValue LHS = GetPromotedFloat(N->getOperand(0));
1846  SDValue RHS = GetPromotedFloat(N->getOperand(1));
1847 
1848  return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1849  LHS, RHS, N->getOperand(2), N->getOperand(3),
1850  N->getOperand(4));
1851 }
1852 
1853 // Construct a SETCC that compares the promoted values and sets the conditional
1854 // code.
1855 SDValue DAGTypeLegalizer::PromoteFloatOp_SETCC(SDNode *N, unsigned OpNo) {
1856  EVT VT = N->getValueType(0);
1857  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1858  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
1859  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
1860  ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1861 
1862  return DAG.getSetCC(SDLoc(N), NVT, Op0, Op1, CCCode);
1863 
1864 }
1865 
1866 // Lower the promoted Float down to the integer value of same size and construct
1867 // a STORE of the integer value.
1868 SDValue DAGTypeLegalizer::PromoteFloatOp_STORE(SDNode *N, unsigned OpNo) {
1869  StoreSDNode *ST = cast<StoreSDNode>(N);
1870  SDValue Val = ST->getValue();
1871  SDLoc DL(N);
1872 
1873  SDValue Promoted = GetPromotedFloat(Val);
1874  EVT VT = ST->getOperand(1).getValueType();
1875  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
1876 
1877  SDValue NewVal;
1878  NewVal = DAG.getNode(GetPromotionOpcode(Promoted.getValueType(), VT), DL,
1879  IVT, Promoted);
1880 
1881  return DAG.getStore(ST->getChain(), DL, NewVal, ST->getBasePtr(),
1882  ST->getMemOperand());
1883 }
1884 
1885 //===----------------------------------------------------------------------===//
1886 // Float Result Promotion
1887 //===----------------------------------------------------------------------===//
1888 
1889 void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
1890  LLVM_DEBUG(dbgs() << "Promote float result " << ResNo << ": "; N->dump(&DAG);
1891  dbgs() << "\n");
1892  SDValue R = SDValue();
1893 
1894  switch (N->getOpcode()) {
1895  // These opcodes cannot appear if promotion of FP16 is done in the backend
1896  // instead of Clang
1897  case ISD::FP16_TO_FP:
1898  case ISD::FP_TO_FP16:
1899  default:
1900 #ifndef NDEBUG
1901  dbgs() << "PromoteFloatResult #" << ResNo << ": ";
1902  N->dump(&DAG); dbgs() << "\n";
1903 #endif
1904  llvm_unreachable("Do not know how to promote this operator's result!");
1905 
1906  case ISD::BITCAST: R = PromoteFloatRes_BITCAST(N); break;
1907  case ISD::ConstantFP: R = PromoteFloatRes_ConstantFP(N); break;
1909  R = PromoteFloatRes_EXTRACT_VECTOR_ELT(N); break;
1910  case ISD::FCOPYSIGN: R = PromoteFloatRes_FCOPYSIGN(N); break;
1911 
1912  // Unary FP Operations
1913  case ISD::FABS:
1914  case ISD::FCEIL:
1915  case ISD::FCOS:
1916  case ISD::FEXP:
1917  case ISD::FEXP2:
1918  case ISD::FFLOOR:
1919  case ISD::FLOG:
1920  case ISD::FLOG2:
1921  case ISD::FLOG10:
1922  case ISD::FNEARBYINT:
1923  case ISD::FNEG:
1924  case ISD::FRINT:
1925  case ISD::FROUND:
1926  case ISD::FSIN:
1927  case ISD::FSQRT:
1928  case ISD::FTRUNC:
1929  case ISD::FCANONICALIZE: R = PromoteFloatRes_UnaryOp(N); break;
1930 
1931  // Binary FP Operations
1932  case ISD::FADD:
1933  case ISD::FDIV:
1934  case ISD::FMAXIMUM:
1935  case ISD::FMINIMUM:
1936  case ISD::FMAXNUM:
1937  case ISD::FMINNUM:
1938  case ISD::FMUL:
1939  case ISD::FPOW:
1940  case ISD::FREM:
1941  case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break;
1942 
1943  case ISD::FMA: // FMA is same as FMAD
1944  case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break;
1945 
1946  case ISD::FPOWI: R = PromoteFloatRes_FPOWI(N); break;
1947 
1948  case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break;
1949  case ISD::LOAD: R = PromoteFloatRes_LOAD(N); break;
1950  case ISD::SELECT: R = PromoteFloatRes_SELECT(N); break;
1951  case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break;
1952 
1953  case ISD::SINT_TO_FP:
1954  case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break;
1955  case ISD::UNDEF: R = PromoteFloatRes_UNDEF(N); break;
1956  case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break;
1957  }
1958 
1959  if (R.getNode())
1960  SetPromotedFloat(SDValue(N, ResNo), R);
1961 }
1962 
1963 // Bitcast from i16 to f16: convert the i16 to a f32 value instead.
1964 // At this point, it is not possible to determine if the bitcast value is
1965 // eventually stored to memory or promoted to f32 or promoted to a floating
1966 // point at a higher precision. Some of these cases are handled by FP_EXTEND,
1967 // STORE promotion handlers.
1968 SDValue DAGTypeLegalizer::PromoteFloatRes_BITCAST(SDNode *N) {
1969  EVT VT = N->getValueType(0);
1970  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1971  // Input type isn't guaranteed to be a scalar int so bitcast if not. The
1972  // bitcast will be legalized further if necessary.
1973  EVT IVT = EVT::getIntegerVT(*DAG.getContext(),
1975  SDValue Cast = DAG.getBitcast(IVT, N->getOperand(0));
1976  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, Cast);
1977 }
1978 
1979 SDValue DAGTypeLegalizer::PromoteFloatRes_ConstantFP(SDNode *N) {
1980  ConstantFPSDNode *CFPNode = cast<ConstantFPSDNode>(N);
1981  EVT VT = N->getValueType(0);
1982  SDLoc DL(N);
1983 
1984  // Get the (bit-cast) APInt of the APFloat and build an integer constant
1985  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
1986  SDValue C = DAG.getConstant(CFPNode->getValueAPF().bitcastToAPInt(), DL,
1987  IVT);
1988 
1989  // Convert the Constant to the desired FP type
1990  // FIXME We might be able to do the conversion during compilation and get rid
1991  // of it from the object code
1992  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1993  return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, C);
1994 }
1995 
1996 // If the Index operand is a constant, try to redirect the extract operation to
1997 // the correct legalized vector. If not, bit-convert the input vector to
1998 // equivalent integer vector. Extract the element as an (bit-cast) integer
1999 // value and convert it to the promoted type.
2000 SDValue DAGTypeLegalizer::PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
2001  SDLoc DL(N);
2002 
2003  // If the index is constant, try to extract the value from the legalized
2004  // vector type.
2005  if (isa<ConstantSDNode>(N->getOperand(1))) {
2006  SDValue Vec = N->getOperand(0);
2007  SDValue Idx = N->getOperand(1);
2008  EVT VecVT = Vec->getValueType(0);
2009  EVT EltVT = VecVT.getVectorElementType();
2010 
2011  uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2012 
2013  switch (getTypeAction(VecVT)) {
2014  default: break;
2016  SDValue Res = GetScalarizedVector(N->getOperand(0));
2017  ReplaceValueWith(SDValue(N, 0), Res);
2018  return SDValue();
2019  }
2021  Vec = GetWidenedVector(Vec);
2022  SDValue Res = DAG.getNode(N->getOpcode(), DL, EltVT, Vec, Idx);
2023  ReplaceValueWith(SDValue(N, 0), Res);
2024  return SDValue();
2025  }
2027  SDValue Lo, Hi;
2028  GetSplitVector(Vec, Lo, Hi);
2029 
2030  uint64_t LoElts = Lo.getValueType().getVectorNumElements();
2031  SDValue Res;
2032  if (IdxVal < LoElts)
2033  Res = DAG.getNode(N->getOpcode(), DL, EltVT, Lo, Idx);
2034  else
2035  Res = DAG.getNode(N->getOpcode(), DL, EltVT, Hi,
2036  DAG.getConstant(IdxVal - LoElts, DL,
2037  Idx.getValueType()));
2038  ReplaceValueWith(SDValue(N, 0), Res);
2039  return SDValue();
2040  }
2041 
2042  }
2043  }
2044 
2045  // Bit-convert the input vector to the equivalent integer vector
2046  SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
2047  EVT IVT = NewOp.getValueType().getVectorElementType();
2048 
2049  // Extract the element as an (bit-cast) integer value
2050  SDValue NewVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IVT,
2051  NewOp, N->getOperand(1));
2052 
2053  // Convert the element to the desired FP type
2054  EVT VT = N->getValueType(0);
2055  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2056  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, NewVal);
2057 }
2058 
2059 // FCOPYSIGN(X, Y) returns the value of X with the sign of Y. If the result
2060 // needs promotion, so does the argument X. Note that Y, if needed, will be
2061 // handled during operand promotion.
2062 SDValue DAGTypeLegalizer::PromoteFloatRes_FCOPYSIGN(SDNode *N) {
2063  EVT VT = N->getValueType(0);
2064  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2065  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2066 
2067  SDValue Op1 = N->getOperand(1);
2068 
2069  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1);
2070 }
2071 
2072 // Unary operation where the result and the operand have PromoteFloat type
2073 // action. Construct a new SDNode with the promoted float value of the old
2074 // operand.
2075 SDValue DAGTypeLegalizer::PromoteFloatRes_UnaryOp(SDNode *N) {
2076  EVT VT = N->getValueType(0);
2077  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2078  SDValue Op = GetPromotedFloat(N->getOperand(0));
2079 
2080  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op);
2081 }
2082 
2083 // Binary operations where the result and both operands have PromoteFloat type
2084 // action. Construct a new SDNode with the promoted float values of the old
2085 // operands.
2086 SDValue DAGTypeLegalizer::PromoteFloatRes_BinOp(SDNode *N) {
2087  EVT VT = N->getValueType(0);
2088  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2089  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2090  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
2091  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, N->getFlags());
2092 }
2093 
2094 SDValue DAGTypeLegalizer::PromoteFloatRes_FMAD(SDNode *N) {
2095  EVT VT = N->getValueType(0);
2096  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2097  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2098  SDValue Op1 = GetPromotedFloat(N->getOperand(1));
2099  SDValue Op2 = GetPromotedFloat(N->getOperand(2));
2100 
2101  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, Op2);
2102 }
2103 
2104 // Promote the Float (first) operand and retain the Integer (second) operand
2105 SDValue DAGTypeLegalizer::PromoteFloatRes_FPOWI(SDNode *N) {
2106  EVT VT = N->getValueType(0);
2107  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2108  SDValue Op0 = GetPromotedFloat(N->getOperand(0));
2109  SDValue Op1 = N->getOperand(1);
2110 
2111  return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1);
2112 }
2113 
2114 // Explicit operation to reduce precision. Reduce the value to half precision
2115 // and promote it back to the legal type.
2116 SDValue DAGTypeLegalizer::PromoteFloatRes_FP_ROUND(SDNode *N) {
2117  SDLoc DL(N);
2118 
2119  SDValue Op = N->getOperand(0);
2120  EVT VT = N->getValueType(0);
2121  EVT OpVT = Op->getValueType(0);
2122  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2123  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
2124 
2125  // Round promoted float to desired precision
2126  SDValue Round = DAG.getNode(GetPromotionOpcode(OpVT, VT), DL, IVT, Op);
2127  // Promote it back to the legal output type
2128  return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, Round);
2129 }
2130 
2131 SDValue DAGTypeLegalizer::PromoteFloatRes_LOAD(SDNode *N) {
2132  LoadSDNode *L = cast<LoadSDNode>(N);
2133  EVT VT = N->getValueType(0);
2134 
2135  // Load the value as an integer value with the same number of bits.
2136  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
2137  SDValue newL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), IVT,
2138  SDLoc(N), L->getChain(), L->getBasePtr(),
2139  L->getOffset(), L->getPointerInfo(), IVT,
2140  L->getAlignment(),
2141  L->getMemOperand()->getFlags(),
2142  L->getAAInfo());
2143  // Legalize the chain result by replacing uses of the old value chain with the
2144  // new one
2145  ReplaceValueWith(SDValue(N, 1), newL.getValue(1));
2146 
2147  // Convert the integer value to the desired FP type
2148  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2149  return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, newL);
2150 }
2151 
2152 // Construct a new SELECT node with the promoted true- and false- values.
2153 SDValue DAGTypeLegalizer::PromoteFloatRes_SELECT(SDNode *N) {
2154  SDValue TrueVal = GetPromotedFloat(N->getOperand(1));
2155  SDValue FalseVal = GetPromotedFloat(N->getOperand(2));
2156 
2157  return DAG.getNode(ISD::SELECT, SDLoc(N), TrueVal->getValueType(0),
2158  N->getOperand(0), TrueVal, FalseVal);
2159 }
2160 
2161 // Construct a new SELECT_CC node with the promoted true- and false- values.
2162 // The operands used for comparison are promoted by PromoteFloatOp_SELECT_CC.
2163 SDValue DAGTypeLegalizer::PromoteFloatRes_SELECT_CC(SDNode *N) {
2164  SDValue TrueVal = GetPromotedFloat(N->getOperand(2));
2165  SDValue FalseVal = GetPromotedFloat(N->getOperand(3));
2166 
2167  return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2168  TrueVal.getNode()->getValueType(0), N->getOperand(0),
2169  N->getOperand(1), TrueVal, FalseVal, N->getOperand(4));
2170 }
2171 
2172 // Construct a SDNode that transforms the SINT or UINT operand to the promoted
2173 // float type.
2174 SDValue DAGTypeLegalizer::PromoteFloatRes_XINT_TO_FP(SDNode *N) {
2175  SDLoc DL(N);
2176  EVT VT = N->getValueType(0);
2177  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2178  SDValue NV = DAG.getNode(N->getOpcode(), DL, NVT, N->getOperand(0));
2179  // Round the value to the desired precision (that of the source type).
2180  return DAG.getNode(
2181  ISD::FP_EXTEND, DL, NVT,
2182  DAG.getNode(ISD::FP_ROUND, DL, VT, NV, DAG.getIntPtrConstant(0, DL)));
2183 }
2184 
2185 SDValue DAGTypeLegalizer::PromoteFloatRes_UNDEF(SDNode *N) {
2186  return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
2187  N->getValueType(0)));
2188 }
2189 
2190 SDValue DAGTypeLegalizer::BitcastToInt_ATOMIC_SWAP(SDNode *N) {
2191  EVT VT = N->getValueType(0);
2192  EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2193 
2194  AtomicSDNode *AM = cast<AtomicSDNode>(N);
2195  SDLoc SL(N);
2196 
2197  SDValue CastVal = BitConvertToInteger(AM->getVal());
2198  EVT CastVT = CastVal.getValueType();
2199 
2200  SDValue NewAtomic
2201  = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, CastVT,
2202  DAG.getVTList(CastVT, MVT::Other),
2203  { AM->getChain(), AM->getBasePtr(), CastVal },
2204  AM->getMemOperand());
2205 
2206  SDValue ResultCast = DAG.getNode(GetPromotionOpcode(VT, NFPVT), SL, NFPVT,
2207  NewAtomic);
2208  // Legalize the chain result by replacing uses of the old value chain with the
2209  // new one
2210  ReplaceValueWith(SDValue(N, 1), NewAtomic.getValue(1));
2211 
2212  return ResultCast;
2213 
2214 }
2215 
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:570
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:537
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:595
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOffset() const
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:183
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:561
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
DiagnosticInfoOptimizationBase::Argument NV
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC&#39;s if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:942
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:651
This class represents lattice values for constants.
Definition: AllocatorList.h:23
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:606
const SDValue & getVal() const
const SDValue & getBasePtr() const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const SDValue & getValue() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
const SDValue & getBasePtr() const
const SDValue & getChain() const
ISD::MemIndexedMode getAddressingMode() const
Return the addressing mode for this load or store: unindexed, pre-inc, pre-dec, post-inc, or post-dec.
static const fltSemantics & EVTToAPFloatSemantics(EVT VT)
Returns an APFloat semantics tag appropriate for the given type.
unsigned getAlignment() const
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select&#39;s if you just have operands and don&#39;t want to check...
Definition: SelectionDAG.h:955
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) const
Soften the operands of a comparison.
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:211
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:434
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
bool isTruncatingStore() const
Return true if the op does a truncation before store.
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Shift and rotation operations.
Definition: ISDOpcodes.h:409
bool isNormalStore(const SDNode *N)
Returns true if the specified node is a non-truncating and unindexed store.
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
CopyToReg - This node has three operands: a chain, a register number to set to this value...
Definition: ISDOpcodes.h:169
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
SimpleValueType SimpleTy
The memory access is dereferenceable (i.e., doesn&#39;t trap).
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:814
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:403
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
This is an SDNode representing atomic operations.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:477
bool isUNINDEXEDStore(const SDNode *N)
Returns true if the specified node is an unindexed store.
void clearBit(unsigned BitPosition)
Set a given bit to 0.
Definition: APInt.h:1461
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:857
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:968
static RTLIB::Libcall GetFPLibCall(EVT VT, RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128, RTLIB::Libcall Call_PPCF128)
GetFPLibCall - Return the right libcall for the given floating point type.
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true, bool isPostTypeLegalization=false) const
Returns a pair of (return value, chain).
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands...
UNDEF - An undefined node.
Definition: ISDOpcodes.h:177
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:523
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:326
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
const SDValue & getBasePtr() const
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
Definition: ValueTypes.h:234
bool isNormalLoad(const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
Simple binary floating point operators.
Definition: ISDOpcodes.h:282
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:272
const SDValue & getOperand(unsigned Num) const
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
Definition: ValueTypes.h:246
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:723
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:555
Extended Value Type.
Definition: ValueTypes.h:33
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned first
bool isUNINDEXEDLoad(const SDNode *N)
Returns true if the specified node is an unindexed load.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
Definition: APInt.h:554
void dump() const
Dump this node, for debugging.
Returns platform specific canonical encoding of a floating point number.
Definition: ISDOpcodes.h:318
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:338
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:580
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
EVT getMemoryVT() const
Return the type of the in-memory value.
Class for arbitrary precision integers.
Definition: APInt.h:69
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:419
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:467
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:470
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:311
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:674
static const fltSemantics & PPCDoubleDouble() LLVM_READNONE
Definition: APFloat.cpp:134
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:386
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:615
#define N
Flags getFlags() const
Return the raw flags of the source value,.
The memory access always returns the same value (or traps).
uint32_t Size
Definition: Profile.cpp:46
unsigned getOpcode() const
SDValue getValue(unsigned R) const
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:174
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getCondCode(ISD::CondCode Cond)
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input...
const MachinePointerInfo & getPointerInfo() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:301
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC&#39;s if you just have an ISD::CondCode instead of an...
Definition: SelectionDAG.h:967
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
const APFloat & getValueAPF() const
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
Definition: ISDOpcodes.h:305
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:442
APInt bitcastToAPInt() const
Definition: APFloat.h:1093
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
Conversion operators.
Definition: ISDOpcodes.h:464
bool isBigEndian() const
Definition: DataLayout.h:233
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:473
#define LLVM_DEBUG(X)
Definition: Debug.h:122
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:585
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:63
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
static ISD::NodeType GetPromotionOpcode(EVT OpVT, EVT RetVT)
LLVMContext * getContext() const
Definition: SelectionDAG.h:409
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
This class is used to represent ISD::LOAD nodes.