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14 #ifndef LLVM_ADT_PACKEDVECTOR_H
15 #define LLVM_ADT_PACKEDVECTOR_H
23 template <
typename T,
unsigned BitNum,
typename BitVectorTy,
bool isSigned>
28 template <
typename T,
unsigned BitNum,
typename BitVectorTy>
33 for (
unsigned i = 0;
i != BitNum; ++
i)
34 val =
T(
val | ((
Bits[(Idx << (BitNum-1)) +
i] ? 1UL : 0UL) <<
i));
39 assert((
val >> BitNum) == 0 &&
"value is too big");
40 for (
unsigned i = 0;
i != BitNum; ++
i)
41 Bits[(Idx << (BitNum-1)) +
i] =
val & (
T(1) <<
i);
45 template <
typename T,
unsigned BitNum,
typename BitVectorTy>
50 for (
unsigned i = 0;
i != BitNum-1; ++
i)
51 val =
T(
val | ((
Bits[(Idx << (BitNum-1)) +
i] ? 1UL : 0UL) <<
i));
52 if (
Bits[(Idx << (BitNum-1)) + BitNum-1])
60 Bits.set((Idx << (BitNum-1)) + BitNum-1);
62 assert((
val >> (BitNum-1)) == 0 &&
"value is too big");
63 for (
unsigned i = 0;
i != BitNum-1; ++
i)
64 Bits[(Idx << (BitNum-1)) +
i] =
val & (
T(1) <<
i);
75 template <
typename T,
unsigned BitNum,
typename BitVectorTy = BitVector>
77 std::numeric_limits<T>::is_signed> {
80 std::numeric_limits<T>::is_signed>;
92 Vec.setValue(Vec.Bits, Idx,
val);
97 return Vec.getValue(Vec.Bits, Idx);
104 bool empty()
const {
return Bits.empty(); }
106 unsigned size()
const {
return Bits.size() >> (BitNum - 1); }
110 void resize(
unsigned N) { Bits.resize(
N << (BitNum - 1)); }
112 void reserve(
unsigned N) { Bits.reserve(
N << (BitNum-1)); }
129 return base::getValue(Bits, Idx);
133 return Bits ==
RHS.Bits;
137 return Bits !=
RHS.Bits;
147 template <
typename T>
class PackedVector<
T, 0>;
151 #endif // LLVM_ADT_PACKEDVECTOR_H
static T getValue(const BitVectorTy &Bits, unsigned Idx)
This is an optimization pass for GlobalISel generic memory operations.
reference operator[](unsigned Idx)
static void setValue(BitVectorTy &Bits, unsigned Idx, T val)
bool operator==(const PackedVector &RHS) const
reference & operator=(T val)
bool operator!=(const PackedVector &RHS) const
reference(PackedVector &vec, unsigned idx)
The initial backend is deliberately restricted to z10 We should add support for later architectures at some point If an asm ties an i32 r result to an i64 the input will be treated as an leaving the upper bits uninitialised For i64 store i32 val
static void setValue(BitVectorTy &Bits, unsigned Idx, T val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
T operator[](unsigned Idx) const
Store a vector of values using a specific number of bits for each value.
PackedVector & operator|=(const PackedVector &RHS)
static T getValue(const BitVectorTy &Bits, unsigned Idx)
PackedVector(unsigned size)