LLVM  10.0.0svn
AMDGPUInstructionSelector.h
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1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
16 #include "AMDGPU.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/Register.h"
22 #include "llvm/IR/InstrTypes.h"
23 
24 namespace {
25 #define GET_GLOBALISEL_PREDICATE_BITSET
26 #define AMDGPUSubtarget GCNSubtarget
27 #include "AMDGPUGenGlobalISel.inc"
28 #undef GET_GLOBALISEL_PREDICATE_BITSET
29 #undef AMDGPUSubtarget
30 }
31 
32 namespace llvm {
33 
34 class AMDGPUInstrInfo;
35 class AMDGPURegisterBankInfo;
36 class GCNSubtarget;
37 class MachineInstr;
38 class MachineOperand;
39 class MachineRegisterInfo;
40 class SIInstrInfo;
41 class SIMachineFunctionInfo;
42 class SIRegisterInfo;
43 
45 public:
47  const AMDGPURegisterBankInfo &RBI,
48  const AMDGPUTargetMachine &TM);
49 
50  bool select(MachineInstr &I) override;
51  static const char *getName();
52 
53 private:
54  struct GEPInfo {
55  const MachineInstr &GEP;
56  SmallVector<unsigned, 2> SgprParts;
57  SmallVector<unsigned, 2> VgprParts;
58  int64_t Imm;
59  GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
60  };
61 
62  bool isInstrUniform(const MachineInstr &MI) const;
63  bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
64 
65  /// tblgen-erated 'select' implementation.
66  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
67 
68  MachineOperand getSubOperand64(MachineOperand &MO,
69  const TargetRegisterClass &SubRC,
70  unsigned SubIdx) const;
71  bool selectCOPY(MachineInstr &I) const;
72  bool selectPHI(MachineInstr &I) const;
73  bool selectG_TRUNC(MachineInstr &I) const;
74  bool selectG_SZA_EXT(MachineInstr &I) const;
75  bool selectG_CONSTANT(MachineInstr &I) const;
76  bool selectG_AND_OR_XOR(MachineInstr &I) const;
77  bool selectG_ADD_SUB(MachineInstr &I) const;
78  bool selectG_EXTRACT(MachineInstr &I) const;
79  bool selectG_MERGE_VALUES(MachineInstr &I) const;
80  bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
81  bool selectG_GEP(MachineInstr &I) const;
82  bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
83  bool selectG_INSERT(MachineInstr &I) const;
84  bool selectG_INTRINSIC(MachineInstr &I) const;
85  bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
86  int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
87  bool selectG_ICMP(MachineInstr &I) const;
88  bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
89  void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
90  SmallVectorImpl<GEPInfo> &AddrInfo) const;
91  bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
92 
93  void initM0(MachineInstr &I) const;
94  bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const;
95  bool selectG_STORE(MachineInstr &I) const;
96  bool selectG_SELECT(MachineInstr &I) const;
97  bool selectG_BRCOND(MachineInstr &I) const;
98  bool selectG_FRAME_INDEX(MachineInstr &I) const;
99 
100  std::pair<Register, unsigned>
101  selectVOP3ModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
102 
104  selectVCSRC(MachineOperand &Root) const;
105 
107  selectVSRC0(MachineOperand &Root) const;
108 
110  selectVOP3Mods0(MachineOperand &Root) const;
112  selectVOP3OMods(MachineOperand &Root) const;
114  selectVOP3Mods(MachineOperand &Root) const;
115 
117  selectSmrdImm(MachineOperand &Root) const;
119  selectSmrdImm32(MachineOperand &Root) const;
121  selectSmrdSgpr(MachineOperand &Root) const;
122 
123  template <bool Signed>
125  selectFlatOffsetImpl(MachineOperand &Root) const;
127  selectFlatOffset(MachineOperand &Root) const;
128 
130  selectFlatOffsetSigned(MachineOperand &Root) const;
131 
133  selectMUBUFScratchOffen(MachineOperand &Root) const;
135  selectMUBUFScratchOffset(MachineOperand &Root) const;
136 
137  bool isDSOffsetLegal(const MachineRegisterInfo &MRI,
138  const MachineOperand &Base,
139  int64_t Offset, unsigned OffsetBits) const;
140 
142  selectDS1Addr1Offset(MachineOperand &Root) const;
143 
144  const SIInstrInfo &TII;
145  const SIRegisterInfo &TRI;
146  const AMDGPURegisterBankInfo &RBI;
147  const AMDGPUTargetMachine &TM;
148  const GCNSubtarget &STI;
149  bool EnableLateStructurizeCFG;
150 #define GET_GLOBALISEL_PREDICATES_DECL
151 #define AMDGPUSubtarget GCNSubtarget
152 #include "AMDGPUGenGlobalISel.inc"
153 #undef GET_GLOBALISEL_PREDICATES_DECL
154 #undef AMDGPUSubtarget
155 
156 #define GET_GLOBALISEL_TEMPORARIES_DECL
157 #include "AMDGPUGenGlobalISel.inc"
158 #undef GET_GLOBALISEL_TEMPORARIES_DECL
159 };
160 
161 } // End llvm namespace.
162 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
unsigned Reg
unsigned const TargetRegisterInfo * TRI
Hexagon Common GEP
static const char * getName()
AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, const AMDGPUTargetMachine &TM)
const HexagonInstrInfo * TII
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
#define P(N)
unsigned const MachineRegisterInfo * MRI
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:732
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:64
#define I(x, y, z)
Definition: MD5.cpp:58
uint32_t Size
Definition: Profile.cpp:46
IRTranslator LLVM IR MI
Wrapper class representing virtual and physical registers.
Definition: Register.h:19