LLVM  9.0.0svn
AMDGPUInstructionSelector.h
Go to the documentation of this file.
1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
16 #include "AMDGPU.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
21 
22 namespace {
23 #define GET_GLOBALISEL_PREDICATE_BITSET
24 #define AMDGPUSubtarget GCNSubtarget
25 #include "AMDGPUGenGlobalISel.inc"
26 #undef GET_GLOBALISEL_PREDICATE_BITSET
27 #undef AMDGPUSubtarget
28 }
29 
30 namespace llvm {
31 
32 class AMDGPUInstrInfo;
33 class AMDGPURegisterBankInfo;
34 class GCNSubtarget;
35 class MachineInstr;
36 class MachineOperand;
37 class MachineRegisterInfo;
38 class SIInstrInfo;
39 class SIMachineFunctionInfo;
40 class SIRegisterInfo;
41 
43 public:
45  const AMDGPURegisterBankInfo &RBI,
46  const AMDGPUTargetMachine &TM);
47 
48  bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
49  static const char *getName();
50 
51 private:
52  struct GEPInfo {
53  const MachineInstr &GEP;
54  SmallVector<unsigned, 2> SgprParts;
55  SmallVector<unsigned, 2> VgprParts;
56  int64_t Imm;
57  GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
58  };
59 
60  bool isInstrUniform(const MachineInstr &MI) const;
61  /// tblgen-erated 'select' implementation.
62  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
63 
64  MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
65  bool selectCOPY(MachineInstr &I) const;
66  bool selectG_TRUNC(MachineInstr &I) const;
67  bool selectG_SZA_EXT(MachineInstr &I) const;
68  bool selectG_CONSTANT(MachineInstr &I) const;
69  bool selectG_ADD(MachineInstr &I) const;
70  bool selectG_EXTRACT(MachineInstr &I) const;
71  bool selectG_GEP(MachineInstr &I) const;
72  bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
73  bool selectG_INSERT(MachineInstr &I) const;
74  bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
75  bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I,
76  CodeGenCoverage &CoverageInfo) const;
77  bool selectG_ICMP(MachineInstr &I) const;
78  bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
79  void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
80  SmallVectorImpl<GEPInfo> &AddrInfo) const;
81  bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
82  bool selectG_LOAD(MachineInstr &I) const;
83  bool selectG_SELECT(MachineInstr &I) const;
84  bool selectG_STORE(MachineInstr &I) const;
85 
87  selectVCSRC(MachineOperand &Root) const;
88 
90  selectVSRC0(MachineOperand &Root) const;
91 
93  selectVOP3Mods0(MachineOperand &Root) const;
95  selectVOP3OMods(MachineOperand &Root) const;
97  selectVOP3Mods(MachineOperand &Root) const;
98 
100  selectSmrdImm(MachineOperand &Root) const;
102  selectSmrdImm32(MachineOperand &Root) const;
104  selectSmrdSgpr(MachineOperand &Root) const;
105 
106  const SIInstrInfo &TII;
107  const SIRegisterInfo &TRI;
108  const AMDGPURegisterBankInfo &RBI;
109  const AMDGPUTargetMachine &TM;
110  const GCNSubtarget &STI;
111  bool EnableLateStructurizeCFG;
112 #define GET_GLOBALISEL_PREDICATES_DECL
113 #define AMDGPUSubtarget GCNSubtarget
114 #include "AMDGPUGenGlobalISel.inc"
115 #undef GET_GLOBALISEL_PREDICATES_DECL
116 #undef AMDGPUSubtarget
117 
118 #define GET_GLOBALISEL_TEMPORARIES_DECL
119 #include "AMDGPUGenGlobalISel.inc"
120 #undef GET_GLOBALISEL_TEMPORARIES_DECL
121 };
122 
123 } // End llvm namespace.
124 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned const TargetRegisterInfo * TRI
Hexagon Common GEP
static const char * getName()
AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, const AMDGPUTargetMachine &TM)
bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override
Select the (possibly generic) instruction I to only use target-specific opcodes.
const HexagonInstrInfo * TII
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
unsigned const MachineRegisterInfo * MRI
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:63
#define I(x, y, z)
Definition: MD5.cpp:58
IRTranslator LLVM IR MI