LLVM 19.0.0git
X86LowerTileCopy.cpp
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1//===-- X86LowerTileCopy.cpp - Expand Tile Copy Instructions---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the pass which lower AMX tile copy instructions. Since
10// there is no tile copy instruction, we need store tile register to stack
11// and load from stack to another tile register. We need extra GR to hold
12// the stride, and we need stack slot to hold the tile data register.
13// We would run this pass after copy propagation, so that we don't miss copy
14// optimization. And we would run this pass before prolog/epilog insertion,
15// so that we can allocate stack slot.
16//
17//===----------------------------------------------------------------------===//
18
19#include "X86.h"
20#include "X86InstrBuilder.h"
21#include "X86InstrInfo.h"
22#include "X86Subtarget.h"
30#include "llvm/CodeGen/Passes.h"
31#include "llvm/IR/DebugLoc.h"
33#include "llvm/Support/Debug.h"
34
35using namespace llvm;
36
37#define DEBUG_TYPE "x86-lower-tile-copy"
38
39namespace {
40
41class X86LowerTileCopy : public MachineFunctionPass {
42public:
43 static char ID;
44
45 X86LowerTileCopy() : MachineFunctionPass(ID) {}
46
47 void getAnalysisUsage(AnalysisUsage &AU) const override;
48
49 bool runOnMachineFunction(MachineFunction &MF) override;
50
51 StringRef getPassName() const override { return "X86 Lower Tile Copy"; }
52};
53
54} // namespace
55
56char X86LowerTileCopy::ID = 0;
57
58INITIALIZE_PASS_BEGIN(X86LowerTileCopy, "lowertilecopy", "Tile Copy Lowering",
59 false, false)
60INITIALIZE_PASS_END(X86LowerTileCopy, "lowertilecopy", "Tile Copy Lowering",
62
63void X86LowerTileCopy::getAnalysisUsage(AnalysisUsage &AU) const {
64 AU.setPreservesAll();
66}
67
69 return new X86LowerTileCopy();
70}
71
72bool X86LowerTileCopy::runOnMachineFunction(MachineFunction &MF) {
73 const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
74 const X86InstrInfo *TII = ST.getInstrInfo();
75 bool Changed = false;
76
77 for (MachineBasicBlock &MBB : MF) {
79 if (!MI.isCopy())
80 continue;
81 MachineOperand &DstMO = MI.getOperand(0);
82 MachineOperand &SrcMO = MI.getOperand(1);
83 Register SrcReg = SrcMO.getReg();
84 Register DstReg = DstMO.getReg();
85 if (!X86::TILERegClass.contains(DstReg, SrcReg))
86 continue;
87
88 const TargetRegisterInfo *TRI = ST.getRegisterInfo();
89 // Allocate stack slot for tile register
90 unsigned Size = TRI->getSpillSize(X86::TILERegClass);
91 Align Alignment = TRI->getSpillAlign(X86::TILERegClass);
92 int TileSS = MF.getFrameInfo().CreateSpillStackObject(Size, Alignment);
93 // Allocate stack slot for stride register
94 Size = TRI->getSpillSize(X86::GR64RegClass);
95 Alignment = TRI->getSpillAlign(X86::GR64RegClass);
96 int StrideSS = MF.getFrameInfo().CreateSpillStackObject(Size, Alignment);
97
98 // TODO: Pick a killed regiter to avoid save/reload. There is problem
99 // to get live interval in this stage.
100 Register GR64Cand = X86::RAX;
101
102 const DebugLoc &DL = MI.getDebugLoc();
103 // mov %rax (%sp)
104 BuildMI(MBB, MI, DL, TII->get(X86::IMPLICIT_DEF), GR64Cand);
105 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64mr)), StrideSS)
106 .addReg(GR64Cand);
107 // mov 64 %rax
108 BuildMI(MBB, MI, DL, TII->get(X86::MOV64ri), GR64Cand).addImm(64);
109 // tilestored %tmm, (%sp, %idx)
110#define GET_EGPR_IF_ENABLED(OPC) (ST.hasEGPR() ? OPC##_EVEX : OPC)
111 unsigned Opc = GET_EGPR_IF_ENABLED(X86::TILESTORED);
112 MachineInstr *NewMI =
113 addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc)), TileSS)
114 .addReg(SrcReg, getKillRegState(SrcMO.isKill()));
115 MachineOperand &MO = NewMI->getOperand(2);
116 MO.setReg(GR64Cand);
117 MO.setIsKill(true);
118 // tileloadd (%sp, %idx), %tmm
119 Opc = GET_EGPR_IF_ENABLED(X86::TILELOADD);
120#undef GET_EGPR_IF_ENABLED
121 NewMI = addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc), DstReg),
122 TileSS);
123 // restore %rax
124 // mov (%sp) %rax
125 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm), GR64Cand),
126 StrideSS);
127 MI.eraseFromParent();
128 Changed = true;
129 }
130 }
131 return Changed;
132}
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
uint64_t Size
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
lowertilecopy
#define GET_EGPR_IF_ENABLED(OPC)
Tile Copy Lowering
Represent the analysis usage information of a pass.
A debug info location.
Definition: DebugLoc.h:33
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:556
MachineOperand class - Representation of each machine instruction operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
void setIsKill(bool Val=true)
Register getReg() const
getReg - Returns the register number.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:656
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
FunctionPass * createX86LowerTileCopyPass()
Return a pass that lower the tile copy instruction.
unsigned getKillRegState(bool B)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39