LLVM  14.0.0git
X86LowerTileCopy.cpp
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1 //===-- X86LowerTileCopy.cpp - Expand Tile Copy Instructions---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the pass which lower AMX tile copy instructions. Since
10 // there is no tile copy instruction, we need store tile register to stack
11 // and load from stack to another tile register. We need extra GR to hold
12 // the stride, and we need stack slot to hold the tile data register.
13 // We would run this pass after copy propagation, so that we don't miss copy
14 // optimization. And we would run this pass before prolog/epilog insertion,
15 // so that we can allocate stack slot.
16 //
17 //===----------------------------------------------------------------------===//
18 
19 #include "X86.h"
20 #include "X86InstrBuilder.h"
21 #include "X86InstrInfo.h"
22 #include "X86Subtarget.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/IR/DebugLoc.h"
32 #include "llvm/InitializePasses.h"
33 #include "llvm/Support/Debug.h"
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "x86-lower-tile-copy"
38 
39 namespace {
40 
41 class X86LowerTileCopy : public MachineFunctionPass {
42 public:
43  static char ID;
44 
45  X86LowerTileCopy() : MachineFunctionPass(ID) {}
46 
47  void getAnalysisUsage(AnalysisUsage &AU) const override;
48 
49  bool runOnMachineFunction(MachineFunction &MF) override;
50 
51  StringRef getPassName() const override { return "X86 Lower Tile Copy"; }
52 };
53 
54 } // namespace
55 
56 char X86LowerTileCopy::ID = 0;
57 
58 INITIALIZE_PASS_BEGIN(X86LowerTileCopy, "lowertilecopy", "Tile Copy Lowering",
59  false, false)
60 INITIALIZE_PASS_END(X86LowerTileCopy, "lowertilecopy", "Tile Copy Lowering",
62 
63 void X86LowerTileCopy::getAnalysisUsage(AnalysisUsage &AU) const {
64  AU.setPreservesAll();
66 }
67 
69  return new X86LowerTileCopy();
70 }
71 
72 bool X86LowerTileCopy::runOnMachineFunction(MachineFunction &MF) {
74  const X86InstrInfo *TII = ST.getInstrInfo();
75  bool Changed = false;
76 
77  for (MachineBasicBlock &MBB : MF) {
78  for (MachineBasicBlock::iterator MII = MBB.begin(), MIE = MBB.end();
79  MII != MIE;) {
80  MachineInstr &MI = *MII++;
81  if (!MI.isCopy())
82  continue;
83  MachineOperand &DstMO = MI.getOperand(0);
84  MachineOperand &SrcMO = MI.getOperand(1);
85  Register SrcReg = SrcMO.getReg();
86  Register DstReg = DstMO.getReg();
87  if (!X86::TILERegClass.contains(DstReg, SrcReg))
88  continue;
89 
90  const TargetRegisterInfo *TRI = ST.getRegisterInfo();
91  // Allocate stack slot for tile register
92  unsigned Size = TRI->getSpillSize(X86::TILERegClass);
93  Align Alignment = TRI->getSpillAlign(X86::TILERegClass);
94  int TileSS = MF.getFrameInfo().CreateSpillStackObject(Size, Alignment);
95  // Allocate stack slot for stride register
96  Size = TRI->getSpillSize(X86::GR64RegClass);
97  Alignment = TRI->getSpillAlign(X86::GR64RegClass);
98  int StrideSS = MF.getFrameInfo().CreateSpillStackObject(Size, Alignment);
99 
100  // TODO: Pick a killed regiter to avoid save/reload. There is problem
101  // to get live interval in this stage.
102  Register GR64Cand = X86::RAX;
103 
104  const DebugLoc &DL = MI.getDebugLoc();
105  // mov %rax (%sp)
106  BuildMI(MBB, MI, DL, TII->get(X86::IMPLICIT_DEF), GR64Cand);
107  addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64mr)), StrideSS)
108  .addReg(GR64Cand);
109  // mov 64 %rax
110  BuildMI(MBB, MI, DL, TII->get(X86::MOV64ri), GR64Cand).addImm(64);
111  // tilestored %tmm, (%sp, %idx)
112  unsigned Opc = X86::TILESTORED;
113  MachineInstr *NewMI =
114  addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc)), TileSS)
115  .addReg(SrcReg, getKillRegState(SrcMO.isKill()));
116  MachineOperand &MO = NewMI->getOperand(2);
117  MO.setReg(GR64Cand);
118  MO.setIsKill(true);
119  // tileloadd (%sp, %idx), %tmm
120  Opc = X86::TILELOADD;
121  NewMI = addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc), DstReg),
122  TileSS);
123  // restore %rax
124  // mov (%sp) %rax
125  addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm), GR64Cand),
126  StrideSS);
127  MI.eraseFromParent();
128  Changed = true;
129  }
130  }
131  return Changed;
132 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
lowertilecopy
lowertilecopy
Definition: X86LowerTileCopy.cpp:60
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
X86Subtarget.h
X86InstrBuilder.h
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:500
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
X86.h
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
Definition: PPCInstrBuilder.h:32
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
DebugLoc.h
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::createX86LowerTileCopyPass
FunctionPass * createX86LowerTileCopyPass()
Return a pass that lower the tile copy instruction.
Definition: X86LowerTileCopy.cpp:68
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
Passes.h
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:288
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:630
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:282
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
MachineFunctionPass.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::X86InstrInfo
Definition: X86InstrInfo.h:130
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
MachineFrameInfo.h
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
Lowering
Tile Copy Lowering
Definition: X86LowerTileCopy.cpp:60
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
MachineOperand.h
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(X86LowerTileCopy, "lowertilecopy", "Tile Copy Lowering", false, false) INITIALIZE_PASS_END(X86LowerTileCopy
MachineFunction.h
X86InstrInfo.h
llvm::MachineInstrBundleIterator< MachineInstr >
InitializePasses.h
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37