47#define DEBUG_TYPE "asm-printer"
50 "Number of RISC-V Compressed instructions emitted");
62 std::unique_ptr<MCStreamer> Streamer)
96 typedef std::tuple<unsigned, uint32_t> HwasanMemaccessTuple;
97 std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
100 void EmitHwasanMemaccessSymbols(
Module &M);
109 bool emitDirectiveOptionArch();
128 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
132 MCSymbol *MILabel = Ctx.createTempSymbol();
136 assert(NumNOPBytes % NOPBytes == 0 &&
137 "Invalid number of NOP bytes requested!");
143 while (NumNOPBytes > 0) {
144 if (MII ==
MBB.
end() || MII->isCall() ||
145 MII->getOpcode() == RISCV::DBG_VALUE ||
146 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
147 MII->getOpcode() == TargetOpcode::STACKMAP)
154 emitNops(NumNOPBytes / NOPBytes);
161 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
164 MCSymbol *MILabel = Ctx.createTempSymbol();
171 unsigned EncodedBytes = 0;
173 if (CalleeMO.
isImm()) {
176 assert((CallTarget & 0xFFFF'FFFF'FFFF) == CallTarget &&
177 "High 16 bits of call target should be zero.");
181 for (
MCInst &Inst : Seq) {
182 bool Compressed = EmitToStreamer(OutStreamer, Inst);
183 EncodedBytes += Compressed ? 2 : 4;
185 bool Compressed = EmitToStreamer(OutStreamer,
MCInstBuilder(RISCV::JALR)
189 EncodedBytes += Compressed ? 2 : 4;
193 lowerOperand(CalleeMO, CallTargetMCOp);
194 EmitToStreamer(OutStreamer,
200 unsigned NumBytes = Opers.getNumPatchBytes();
201 assert(NumBytes >= EncodedBytes &&
202 "Patchpoint can't request size less than the length of a call.");
203 assert((NumBytes - EncodedBytes) % NOPBytes == 0 &&
204 "Invalid number of NOP bytes requested!");
205 emitNops((NumBytes - EncodedBytes) / NOPBytes);
210 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
213 if (
unsigned PatchBytes = SOpers.getNumPatchBytes()) {
214 assert(PatchBytes % NOPBytes == 0 &&
215 "Invalid number of NOP bytes requested!");
216 emitNops(PatchBytes / NOPBytes);
221 switch (CallTarget.
getType()) {
224 lowerOperand(CallTarget, CallTargetMCOp);
249 MCSymbol *MILabel = Ctx.createTempSymbol();
259 ++RISCVNumInstrsCompressed;
266#include "RISCVGenMCPseudoLowering.inc"
271 if (!STI->hasStdExtZihintntl())
274 if (
MI->memoperands_empty())
281 unsigned NontemporalMode = 0;
283 NontemporalMode += 0b1;
285 NontemporalMode += 0b10;
288 if (STI->hasStdExtCOrZca() && STI->enableRVCHintInstrs())
297 EmitToStreamer(*OutStreamer, Hint);
301 RISCV_MC::verifyInstructionPredicates(
MI->getOpcode(),
302 getSubtargetInfo().getFeatureBits());
307 if (
MCInst OutInst; lowerPseudoInstExpansion(
MI, OutInst)) {
308 EmitToStreamer(*OutStreamer, OutInst);
312 switch (
MI->getOpcode()) {
313 case RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
314 LowerHWASAN_CHECK_MEMACCESS(*
MI);
316 case RISCV::KCFI_CHECK:
317 LowerKCFI_CHECK(*
MI);
319 case TargetOpcode::STACKMAP:
320 return LowerSTACKMAP(*OutStreamer, SM, *
MI);
321 case TargetOpcode::PATCHPOINT:
322 return LowerPATCHPOINT(*OutStreamer, SM, *
MI);
323 case TargetOpcode::STATEPOINT:
324 return LowerSTATEPOINT(*OutStreamer, SM, *
MI);
325 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
328 const Function &
F =
MI->getParent()->getParent()->getFunction();
329 if (
F.hasFnAttribute(
"patchable-function-entry"))
332 LowerPATCHABLE_FUNCTION_ENTER(
MI);
335 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
336 LowerPATCHABLE_FUNCTION_EXIT(
MI);
338 case TargetOpcode::PATCHABLE_TAIL_CALL:
339 LowerPATCHABLE_TAIL_CALL(
MI);
344 if (!lowerToMCInst(
MI, OutInst))
345 EmitToStreamer(*OutStreamer, OutInst);
348bool RISCVAsmPrinter::PrintAsmOperand(
const MachineInstr *
MI,
unsigned OpNo,
355 if (ExtraCode && ExtraCode[0]) {
356 if (ExtraCode[1] != 0)
359 switch (ExtraCode[0]) {
390 PrintSymbolOperand(MO,
OS);
404bool RISCVAsmPrinter::PrintAsmMemoryOperand(
const MachineInstr *
MI,
406 const char *ExtraCode,
412 assert(
MI->getNumOperands() > OpNo + 1 &&
"Expected additional operand");
416 if (!AddrReg.
isReg())
423 if (!lowerOperand(
Offset, MCO))
432 MMI->getContext().registerInlineAsmLabel(
Offset.getMCSymbol());
433 if (
Offset.isBlockAddress()) {
436 MMI->getContext().registerInlineAsmLabel(
Sym);
443bool RISCVAsmPrinter::emitDirectiveOptionArch() {
449 if (STI->hasFeature(Feature.Value) == MCSTI.
hasFeature(Feature.Value))
455 auto Delta = STI->hasFeature(Feature.Value) ? RISCVOptionArchArgType::Plus
456 : RISCVOptionArchArgType::Minus;
459 if (!NeedEmitStdOptionArgs.
empty()) {
473 bool EmittedOptionArch = emitDirectiveOptionArch();
475 SetupMachineFunction(MF);
481 if (EmittedOptionArch)
482 RTS.emitDirectiveOptionPop();
486void RISCVAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(
const MachineInstr *
MI) {
487 emitSled(
MI, SledKind::FUNCTION_ENTER);
490void RISCVAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(
const MachineInstr *
MI) {
491 emitSled(
MI, SledKind::FUNCTION_EXIT);
494void RISCVAsmPrinter::LowerPATCHABLE_TAIL_CALL(
const MachineInstr *
MI) {
495 emitSled(
MI, SledKind::TAIL_CALL);
498void RISCVAsmPrinter::emitSled(
const MachineInstr *
MI, SledKind Kind) {
513 const uint8_t NoopsInSledCount =
519 auto CurSled = OutContext.createTempSymbol(
"xray_sled_",
true);
521 auto Target = OutContext.createTempSymbol();
524 Target, MCSymbolRefExpr::VariantKind::VK_None, OutContext);
530 MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addExpr(TargetExpr));
533 for (int8_t
I = 0;
I < NoopsInSledCount; ++
I)
540 recordSled(CurSled, *
MI, Kind, 2);
543void RISCVAsmPrinter::emitStartOfAsmFile(
Module &M) {
546 if (
const MDString *ModuleTargetABI =
547 dyn_cast_or_null<MDString>(
M.getModuleFlag(
"target-abi")))
553 if (
auto *MD = dyn_cast_or_null<MDNode>(
M.getModuleFlag(
"riscv-isa"))) {
554 for (
auto &ISA : MD->operands()) {
555 if (
auto *ISAString = dyn_cast_or_null<MDString>(ISA)) {
557 ISAString->getString(),
true,
562 if (ISAInfo->hasExtension(Feature.Key) &&
573 if (
TM.getTargetTriple().isOSBinFormatELF())
574 emitAttributes(SubtargetInfo);
577void RISCVAsmPrinter::emitEndOfAsmFile(
Module &M) {
581 if (
TM.getTargetTriple().isOSBinFormatELF())
583 EmitHwasanMemaccessSymbols(M);
586void RISCVAsmPrinter::emitAttributes(
const MCSubtargetInfo &SubtargetInfo) {
595void RISCVAsmPrinter::emitFunctionEntryLabel() {
597 if (RMFI->isVectorCall()) {
611void RISCVAsmPrinter::LowerHWASAN_CHECK_MEMACCESS(
const MachineInstr &
MI) {
613 uint32_t AccessInfo =
MI.getOperand(1).getImm();
615 HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, AccessInfo)];
618 if (!
TM.getTargetTriple().isOSBinFormatELF())
621 std::string SymName =
"__hwasan_check_x" + utostr(Reg - RISCV::X0) +
"_" +
622 utostr(AccessInfo) +
"_short";
623 Sym = OutContext.getOrCreateSymbol(SymName);
628 EmitToStreamer(*OutStreamer,
MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr));
633 assert(std::next(
MI.getIterator())->isCall() &&
634 "KCFI_CHECK not followed by a call instruction");
635 assert(std::next(
MI.getIterator())->getOperand(0).getReg() == AddrReg &&
636 "KCFI_CHECK call target doesn't match call operand");
643 unsigned ScratchRegs[] = {RISCV::X6, RISCV::X7};
644 unsigned NextReg = RISCV::X28;
645 auto isRegAvailable = [&](
unsigned Reg) {
646 return Reg != AddrReg && !STI->isRegisterReservedByUser(Reg);
648 for (
auto &Reg : ScratchRegs) {
649 if (isRegAvailable(Reg))
651 while (!isRegAvailable(NextReg))
654 if (Reg > RISCV::X31)
658 if (AddrReg == RISCV::X0) {
662 .addReg(ScratchRegs[0])
668 int NopSize = STI->hasStdExtCOrZca() ? 2 : 4;
669 int64_t PrefixNops = 0;
672 .getFnAttribute(
"patchable-function-prefix")
674 .getAsInteger(10, PrefixNops);
678 .addReg(ScratchRegs[0])
680 .addImm(-(PrefixNops * NopSize + 4)));
684 const int64_t
Type =
MI.getOperand(1).getImm();
685 const int64_t Hi20 = ((
Type + 0x800) >> 12) & 0xFFFFF;
686 const int64_t Lo12 = SignExtend64<12>(
Type);
690 MCInstBuilder(RISCV::LUI).addReg(ScratchRegs[1]).addImm(Hi20));
692 if (Lo12 || Hi20 == 0) {
693 EmitToStreamer(*OutStreamer,
704 EmitToStreamer(*OutStreamer,
706 .addReg(ScratchRegs[0])
707 .addReg(ScratchRegs[1])
713 emitKCFITrapEntry(*
MI.getMF(),
Trap);
717void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(
Module &M) {
718 if (HwasanMemaccessSymbols.empty())
721 assert(
TM.getTargetTriple().isOSBinFormatELF());
728 OutContext.getOrCreateSymbol(
"__hwasan_tag_mismatch_v2");
740 for (
auto &
P : HwasanMemaccessSymbols) {
741 unsigned Reg = std::get<0>(
P.first);
742 uint32_t AccessInfo = std::get<1>(
P.first);
760 MCInstBuilder(RISCV::SLLI).addReg(RISCV::X6).addReg(Reg).addImm(8),
762 EmitToStreamer(*OutStreamer,
769 EmitToStreamer(*OutStreamer,
777 MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0),
782 MCInstBuilder(RISCV::SRLI).addReg(RISCV::X7).addReg(Reg).addImm(56),
784 MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
786 EmitToStreamer(*OutStreamer,
791 HandleMismatchOrPartialSym, OutContext)),
793 MCSymbol *ReturnSym = OutContext.createTempSymbol();
795 EmitToStreamer(*OutStreamer,
801 OutStreamer->
emitLabel(HandleMismatchOrPartialSym);
803 EmitToStreamer(*OutStreamer,
809 MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
820 MCInstBuilder(RISCV::ANDI).addReg(RISCV::X28).addReg(Reg).addImm(0xF),
824 EmitToStreamer(*OutStreamer,
840 MCInstBuilder(RISCV::ORI).addReg(RISCV::X6).addReg(Reg).addImm(0xF),
844 MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0),
846 EmitToStreamer(*OutStreamer,
853 OutStreamer->
emitLabel(HandleMismatchSym);
890 EmitToStreamer(*OutStreamer,
898 EmitToStreamer(*OutStreamer,
905 EmitToStreamer(*OutStreamer,
915 MCInstBuilder(RISCV::SD).addReg(RISCV::X8).addReg(RISCV::X2).addImm(8 *
921 MCInstBuilder(RISCV::SD).addReg(RISCV::X1).addReg(RISCV::X2).addImm(1 *
924 if (Reg != RISCV::X10)
927 MCInstBuilder(RISCV::ADDI).addReg(RISCV::X10).addReg(Reg).addImm(0),
929 EmitToStreamer(*OutStreamer,
936 EmitToStreamer(*OutStreamer,
MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr),
1058 RISCVVPseudosTable::getPseudoInfo(
MI->getOpcode());
1065 assert(
MBB &&
"MI expected to be in a basic block");
1067 assert(MF &&
"MBB expected to be in a machine function");
1072 assert(
TRI &&
"TargetRegisterInfo expected");
1076 unsigned NumOps =
MI->getNumExplicitOperands();
1090 for (
unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
1093 if (hasVLOutput && OpNo == 1)
1097 if (OpNo ==
MI->getNumExplicitDefs() && MO.
isReg() && MO.
isTied()) {
1099 "Expected tied to first def.");
1116 if (RISCV::VRM2RegClass.
contains(Reg) ||
1117 RISCV::VRM4RegClass.
contains(Reg) ||
1118 RISCV::VRM8RegClass.
contains(Reg)) {
1119 Reg =
TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
1120 assert(Reg &&
"Subregister does not exist");
1121 }
else if (RISCV::FPR16RegClass.
contains(Reg)) {
1123 TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
1124 assert(Reg &&
"Subregister does not exist");
1125 }
else if (RISCV::FPR64RegClass.
contains(Reg)) {
1126 Reg =
TRI->getSubReg(Reg, RISCV::sub_32);
1127 assert(Reg &&
"Superregister does not exist");
1128 }
else if (RISCV::VRN2M1RegClass.
contains(Reg) ||
1129 RISCV::VRN2M2RegClass.
contains(Reg) ||
1130 RISCV::VRN2M4RegClass.
contains(Reg) ||
1131 RISCV::VRN3M1RegClass.
contains(Reg) ||
1132 RISCV::VRN3M2RegClass.
contains(Reg) ||
1133 RISCV::VRN4M1RegClass.
contains(Reg) ||
1134 RISCV::VRN4M2RegClass.
contains(Reg) ||
1135 RISCV::VRN5M1RegClass.
contains(Reg) ||
1136 RISCV::VRN6M1RegClass.
contains(Reg) ||
1137 RISCV::VRN7M1RegClass.
contains(Reg) ||
1138 RISCV::VRN8M1RegClass.
contains(Reg)) {
1139 Reg =
TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
1140 assert(Reg &&
"Subregister does not exist");
1158 RISCV::VMV0RegClassID &&
1159 "Expected only mask operand to be missing");
1175 if (lowerOperand(MO, MCOp))
1180 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
1181 const Function &
F =
MI->getParent()->getParent()->getFunction();
1182 if (
F.hasFnAttribute(
"patchable-function-entry")) {
1184 if (
F.getFnAttribute(
"patchable-function-entry")
1186 .getAsInteger(10, Num))
1197void RISCVAsmPrinter::emitMachineConstantPoolValue(
1202 if (RCPV->isGlobalValue()) {
1203 auto *GV = RCPV->getGlobalValue();
1204 MCSym = getSymbol(GV);
1206 assert(RCPV->isExtSymbol() &&
"unrecognized constant pool type");
1207 auto Sym = RCPV->getSymbol();
1208 MCSym = GetExternalSymbolSymbol(
Sym);
1213 uint64_t Size = getDataLayout().getTypeAllocSize(RCPV->getType());
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
This file implements a class to represent arbitrary precision integral constant values and operations...
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter()
static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, const AsmPrinter &AP)
static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static bool is64Bit(const char *name)
This class is intended to be used as a driving class for all asm writers.
virtual void emitInstruction(const MachineInstr *)
Targets should implement this to emit instructions.
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
virtual void emitStartOfAsmFile(Module &)
This virtual method can be overridden by targets that want to emit something at the start of their fi...
virtual void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV)
virtual void emitEndOfAsmFile(Module &)
This virtual method can be overridden by targets that want to emit something at the end of their file...
MCContext & OutContext
This is the context for the output file that we are streaming.
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
virtual void emitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
The address of a basic block.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
MCInstBuilder & addReg(MCRegister Reg)
Add a new register operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Instances of this class represent operands of the MCInst class.
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createReg(MCRegister Reg)
static MCOperand createImm(int64_t Val)
const MCExpr * getExpr() const
Streaming machine code generation interface.
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
virtual bool emitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
MCContext & getContext() const
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
MCTargetStreamer * getTargetStreamer()
virtual void emitCodeAlignment(Align Alignment, const MCSubtargetInfo *STI, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
virtual void switchSection(MCSection *Section, uint32_t Subsec=0)
Set the current section where code is being emitted to Section.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
Represent a reference to a symbol from inside an expression.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Abstract base class for all machine specific constantpool value subclasses.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Representation of each machine instruction.
A description of a memory reference used in the backend.
bool isNonTemporal() const
Flags getFlags() const
Return the raw flags of the source value,.
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
const BlockAddress * getBlockAddress() const
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
MCSymbol * getMCSymbol() const
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
int64_t getOffset() const
Return the offset from the symbol in this operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
A Module instance is used to store all the information related to an LLVM module.
This class represents success/failure for parsing-like operations that find it important to chain tog...
Pass interface - Implemented by all 'passes'.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
MI-level patchpoint operands.
A RISCV-specific constant pool value.
static bool isSupportedExtensionFeature(StringRef Ext)
static llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseArchString(StringRef Arch, bool EnableExperimentalExtension, bool ExperimentalExtensionVersionCheck=true)
Parse RISC-V ISA info from arch string.
static const char * getRegisterName(MCRegister Reg)
static const RISCVMCExpr * create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx)
@ VK_RISCV_TLSDESC_ADD_LO
@ VK_RISCV_TLSDESC_LOAD_LO
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
virtual void emitDirectiveVariantCC(MCSymbol &Symbol)
void emitTargetAttributes(const MCSubtargetInfo &STI, bool EmitStackAlign)
void setFlagsFromFeatures(const MCSubtargetInfo &STI)
void setTargetABI(RISCVABI::ABI ABI)
virtual void emitDirectiveOptionArch(ArrayRef< RISCVOptionArchArg > Args)
virtual void finishAttributeSection()
virtual void emitDirectiveOptionPush()
Wrapper class representing virtual and physical registers.
reference emplace_back(ArgTypes &&... Args)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MI-level stackmap operands.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
void recordStatepoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Target - Wrapper for Target specific information.
The instances of the Type class are immutable: once they are created, they are never changed.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ABI getTargetABI(StringRef ABIName)
static bool hasRoundModeOp(uint64_t TSFlags)
static bool isTiedPseudo(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static bool hasVecPolicyOp(uint64_t TSFlags)
static bool hasSEWOp(uint64_t TSFlags)
void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI, MCRegister DestReg, SmallVectorImpl< MCInst > &Insts)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool isFaultFirstLoad(const MachineInstr &MI)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
bool errorToBool(Error Err)
Helper for converting an Error to a bool.
static const MachineMemOperand::Flags MONontemporalBit1
Target & getTheRISCV32Target()
static const MachineMemOperand::Flags MONontemporalBit0
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Target & getTheRISCV64Target()
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]
@ MCSA_ELF_TypeFunction
.type _foo, STT_FUNC # aka @function
@ MCSA_Hidden
.hidden (ELF)
Implement std::hash so that hash_code can be used in STL containers.
This struct is a compact representation of a valid (non-zero power of two) alignment.
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...
Used to provide key value pairs for feature and CPU bit flags.