31#define DEBUG_TYPE "mccodeemitter"
33#define GET_INSTRMAP_INFO
34#include "AVRGenInstrInfo.inc"
35#undef GET_INSTRMAP_INFO
68AVRMCCodeEmitter::loadStorePostEncoder(
const MCInst &
MI,
unsigned EncodedValue,
69 const MCSubtargetInfo &STI)
const {
71 assert(
MI.getOperand(0).isReg() &&
MI.getOperand(1).isReg() &&
72 "the load/store operands must be registers");
74 unsigned Opcode =
MI.getOpcode();
77 bool IsRegX =
MI.getOperand(0).getReg() == AVR::R27R26 ||
78 MI.getOperand(1).getReg() == AVR::R27R26;
80 bool IsPredec = Opcode == AVR::LDRdPtrPd || Opcode == AVR::STPtrPdRr;
81 bool IsPostinc = Opcode == AVR::LDRdPtrPi || Opcode == AVR::STPtrPiRr;
84 if (IsRegX || IsPredec || IsPostinc) {
85 EncodedValue |= (1 << 12);
91template <AVR::Fixups Fixup>
93AVRMCCodeEmitter::encodeRelCondBrTarget(
const MCInst &
MI,
unsigned OpNo,
94 SmallVectorImpl<MCFixup> &Fixups,
95 const MCSubtargetInfo &STI)
const {
96 const MCOperand &MO =
MI.getOperand(OpNo);
108 auto target = MO.getImm();
113unsigned AVRMCCodeEmitter::encodeLDSTPtrReg(
const MCInst &
MI,
unsigned OpNo,
114 SmallVectorImpl<MCFixup> &Fixups,
115 const MCSubtargetInfo &STI)
const {
116 auto MO =
MI.getOperand(OpNo);
121 switch (MO.getReg()) {
137unsigned AVRMCCodeEmitter::encodeMemri(
const MCInst &
MI,
unsigned OpNo,
138 SmallVectorImpl<MCFixup> &Fixups,
139 const MCSubtargetInfo &STI)
const {
140 auto RegOp =
MI.getOperand(OpNo);
141 auto OffsetOp =
MI.getOperand(OpNo + 1);
143 assert(RegOp.isReg() &&
"Expected register operand");
147 switch (RegOp.getReg()) {
149 Ctx.
reportError(
MI.getLoc(),
"Expected either Y or Z register");
161 if (OffsetOp.isImm()) {
162 OffsetBits = OffsetOp.getImm();
163 }
else if (OffsetOp.isExpr()) {
171 return (RegBit << 6) | OffsetBits;
174unsigned AVRMCCodeEmitter::encodeComplement(
const MCInst &
MI,
unsigned OpNo,
175 SmallVectorImpl<MCFixup> &Fixups,
176 const MCSubtargetInfo &STI)
const {
178 assert(
MI.getOperand(OpNo).isImm());
180 auto Imm =
MI.getOperand(OpNo).getImm();
184template <AVR::Fixups Fixup,
unsigned Offset>
185unsigned AVRMCCodeEmitter::encodeImm(
const MCInst &
MI,
unsigned OpNo,
186 SmallVectorImpl<MCFixup> &Fixups,
187 const MCSubtargetInfo &STI)
const {
188 auto MO =
MI.getOperand(OpNo);
191 if (isa<AVRMCExpr>(MO.getExpr())) {
196 return getExprOpValue(MO.getExpr(), Fixups, STI);
210unsigned AVRMCCodeEmitter::encodeCallTarget(
const MCInst &
MI,
unsigned OpNo,
211 SmallVectorImpl<MCFixup> &Fixups,
212 const MCSubtargetInfo &STI)
const {
213 auto MO =
MI.getOperand(OpNo);
223 auto Target = MO.getImm();
228unsigned AVRMCCodeEmitter::getExprOpValue(
const MCExpr *Expr,
229 SmallVectorImpl<MCFixup> &Fixups,
230 const MCSubtargetInfo &STI)
const {
235 Expr =
static_cast<const MCBinaryExpr *
>(Expr)->getLHS();
236 Kind = Expr->getKind();
240 AVRMCExpr
const *AVRExpr = cast<AVRMCExpr>(Expr);
242 if (AVRExpr->evaluateAsConstant(Result)) {
255unsigned AVRMCCodeEmitter::getMachineOpValue(
const MCInst &
MI,
257 SmallVectorImpl<MCFixup> &Fixups,
258 const MCSubtargetInfo &STI)
const {
262 return static_cast<unsigned>(MO.getImm());
265 return static_cast<unsigned>(bit_cast<double>(MO.getDFPImm()));
270 return getExprOpValue(MO.getExpr(), Fixups, STI);
273void AVRMCCodeEmitter::emitInstruction(
uint64_t Val,
unsigned Size,
274 const MCSubtargetInfo &STI,
275 raw_ostream &
OS)
const {
276 size_t WordCount =
Size / 2;
278 for (int64_t i = WordCount - 1; i >= 0; --i) {
279 uint16_t Word = (Val >> (i * 16)) & 0xFFFF;
284void AVRMCCodeEmitter::encodeInstruction(
const MCInst &
MI, raw_ostream &
OS,
285 SmallVectorImpl<MCFixup> &Fixups,
286 const MCSubtargetInfo &STI)
const {
287 const MCInstrDesc &Desc = MCII.
get(
MI.getOpcode());
290 unsigned Size = Desc.getSize();
292 assert(
Size > 0 &&
"Instruction size cannot be zero");
294 uint64_t BinaryOpCode = getBinaryCodeForInstr(
MI, Fixups, STI);
295 emitInstruction(BinaryOpCode,
Size, STI,
OS);
300 return new AVRMCCodeEmitter(MCII, Ctx);
303#include "AVRGenMCCodeEmitter.inc"
This file declares a class to represent arbitrary precision floating point values and provide a varie...
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
const MCRegisterInfo * getRegisterInfo() const
void reportError(SMLoc L, const Twine &Msg)
@ SymbolRef
References to labels and assigned expressions.
@ Target
Target specific expression.
@ Binary
Binary expressions.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void adjustBranchTarget(T &val)
Adjusts the value of a branch target.
@ fixup_call
A 22-bit fixup for the target of a CALL k or JMP k instruction.
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
This is an optimization pass for GlobalISel generic memory operations.
MCCodeEmitter * createAVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Creates a machine code emitter for AVR.
MCFixupKind
Extensible enumeration to represent the type of a fixup.