LLVM 22.0.0git
ExecuteStage.h
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1//===---------------------- ExecuteStage.h ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file defines the execution stage of a default instruction pipeline.
11///
12/// The ExecuteStage is responsible for managing the hardware scheduler
13/// and issuing notifications that an instruction has been executed.
14///
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_MCA_STAGES_EXECUTESTAGE_H
18#define LLVM_MCA_STAGES_EXECUTESTAGE_H
19
20#include "llvm/ADT/ArrayRef.h"
24
25namespace llvm {
26namespace mca {
27
28class ExecuteStage final : public Stage {
29 Scheduler &HWS;
30
31 unsigned NumDispatchedOpcodes;
32 unsigned NumIssuedOpcodes;
33
34 // True if this stage should notify listeners of HWPressureEvents.
35 bool EnablePressureEvents;
36
37 Error issueInstruction(InstRef &IR);
38
39 // Called at the beginning of each cycle to issue already dispatched
40 // instructions to the underlying pipelines.
41 Error issueReadyInstructions();
42
43 // Used to notify instructions eliminated at register renaming stage.
44 Error handleInstructionEliminated(InstRef &IR);
45
46 ExecuteStage(const ExecuteStage &Other) = delete;
47 ExecuteStage &operator=(const ExecuteStage &Other) = delete;
48
49public:
50 ExecuteStage(Scheduler &S) : ExecuteStage(S, false) {}
51 ExecuteStage(Scheduler &S, bool ShouldPerformBottleneckAnalysis)
52 : HWS(S), NumDispatchedOpcodes(0), NumIssuedOpcodes(0),
53 EnablePressureEvents(ShouldPerformBottleneckAnalysis) {}
54
55 // This stage works under the assumption that the Pipeline will eventually
56 // execute a retire stage. We don't need to check if pipelines and/or
57 // schedulers have instructions to process, because those instructions are
58 // also tracked by the retire control unit. That means,
59 // RetireControlUnit::hasWorkToComplete() is responsible for checking if there
60 // are still instructions in-flight in the out-of-order backend.
61 bool hasWorkToComplete() const override { return false; }
62 bool isAvailable(const InstRef &IR) const override;
63
64 // Notifies the scheduler that a new cycle just started.
65 //
66 // This method notifies the scheduler that a new cycle started.
67 // This method is also responsible for notifying listeners about instructions
68 // state changes, and processor resources freed by the scheduler.
69 // Instructions that transitioned to the 'Executed' state are automatically
70 // moved to the next stage (i.e. RetireStage).
71 Error cycleStart() override;
72 Error cycleEnd() override;
73 Error execute(InstRef &IR) override;
74
77 void notifyInstructionExecuted(const InstRef &IR) const;
78 void notifyInstructionPending(const InstRef &IR) const;
79 void notifyInstructionReady(const InstRef &IR) const;
80 void notifyResourceAvailable(const ResourceRef &RR) const;
81
82 // Notify listeners that buffered resources have been consumed or freed.
83 void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const;
84};
85
86} // namespace mca
87} // namespace llvm
88
89#endif // LLVM_MCA_STAGES_EXECUTESTAGE_H
Legalize the Machine IR a function s Machine IR
Definition Legalizer.cpp:80
A scheduler for Processor Resource Units and Processor Resource Groups.
This file defines abstractions used by the Pipeline to model register reads, register writes and inst...
This file defines a stage.
Lightweight error class with error context and mandatory checking.
Definition Error.h:159
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition ArrayRef.h:303
void notifyResourceAvailable(const ResourceRef &RR) const
Error cycleStart() override
Called once at the start of each cycle.
bool isAvailable(const InstRef &IR) const override
Returns true if it can execute IR during this cycle.
bool hasWorkToComplete() const override
Returns true if some instructions are still executing this stage.
Error cycleEnd() override
Called once at the end of each cycle.
void notifyInstructionExecuted(const InstRef &IR) const
void notifyInstructionIssued(const InstRef &IR, MutableArrayRef< ResourceUse > Used) const
ExecuteStage(Scheduler &S)
void notifyReservedOrReleasedBuffers(const InstRef &IR, bool Reserved) const
ExecuteStage(Scheduler &S, bool ShouldPerformBottleneckAnalysis)
void notifyInstructionReady(const InstRef &IR) const
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
void notifyInstructionPending(const InstRef &IR) const
An InstRef contains both a SourceMgr index and Instruction pair.
Class Scheduler is responsible for issuing instructions to pipeline resources.
Definition Scheduler.h:71
std::pair< uint64_t, uint64_t > ResourceRef
This is an optimization pass for GlobalISel generic memory operations.
@ Other
Any other memory.
Definition ModRef.h:68