LLVM  17.0.0git
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InOrderIssueStage.cpp File Reference
#include "llvm/MCA/Stages/InOrderIssueStage.h"
#include "llvm/MCA/HardwareUnits/LSUnit.h"
#include "llvm/MCA/HardwareUnits/RegisterFile.h"
#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
#include "llvm/MCA/Instruction.h"
Include dependency graph for InOrderIssueStage.cpp:

Go to the source code of this file.


 This is an optimization pass for GlobalISel generic memory operations.


#define DEBUG_TYPE   "llvm-mca"


static bool llvm::mca::hasResourceHazard (const ResourceManager &RM, const InstRef &IR)
static unsigned llvm::mca::findFirstWriteBackCycle (const InstRef &IR)
static unsigned llvm::mca::checkRegisterHazard (const RegisterFile &PRF, const MCSubtargetInfo &STI, const InstRef &IR)
 Return a number of cycles left until register requirements of the instructions are met. More...
static void llvm::mca::addRegisterReadWrite (RegisterFile &PRF, Instruction &IS, unsigned SourceIndex, const MCSubtargetInfo &STI, SmallVectorImpl< unsigned > &UsedRegs)

Detailed Description

InOrderIssueStage implements an in-order execution pipeline.

Definition in file InOrderIssueStage.cpp.

Macro Definition Documentation


#define DEBUG_TYPE   "llvm-mca"

Definition at line 20 of file InOrderIssueStage.cpp.