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14 #ifndef LLVM_MCA_STAGES_INORDERISSUESTAGE_H
15 #define LLVM_MCA_STAGES_INORDERISSUESTAGE_H
80 unsigned LastWriteBackCycle;
94 void updateIssuedInst();
97 void updateCarriedOver();
101 void notifyStallEvent();
103 void notifyInstructionIssued(
const InstRef &
IR,
105 void notifyInstructionDispatched(
const InstRef &
IR,
unsigned Ops,
107 void notifyInstructionExecuted(
const InstRef &
IR);
108 void notifyInstructionRetired(
const InstRef &
IR,
129 #endif // LLVM_MCA_STAGES_INORDERISSUESTAGE_H
This is an optimization pass for GlobalISel generic memory operations.
StallKind getStallKind() const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
const InstRef & getInstruction() const
A resource manager for processor resource units and groups.
Default Load/Store Unit (LS Unit) for simulated processors.
Statically lint checks LLVM IR
Error cycleEnd() override
Called once at the end of each cycle.
void update(const InstRef &Inst, unsigned Cycles, StallKind SK)
Class which can be overriden by targets to enforce instruction dependencies and behaviours that aren'...
An InstRef contains both a SourceMgr index and Instruction pair.
bool hasWorkToComplete() const override
Returns true if some instructions are still executing this stage.
bool isAvailable(const InstRef &) const override
Returns true if it can execute IR during this cycle.
Manages hardware register files, and tracks register definitions for register renaming purposes.
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
Lightweight error class with error context and mandatory checking.
std::optional< std::vector< StOtherPiece > > Other
InstRef & getInstruction()
unsigned getCyclesLeft() const
Generic base class for all target subtargets.
unsigned getIssueWidth() const
Error cycleStart() override
Called once at the start of each cycle.