LLVM  14.0.0git
X86FixupSetCC.cpp
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1 //===---- X86FixupSetCC.cpp - optimize usage of LEA instructions ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines a pass that fixes zero-extension of setcc patterns.
10 // X86 setcc instructions are modeled to have no input arguments, and a single
11 // GR8 output argument. This is consistent with other similar instructions
12 // (e.g. movb), but means it is impossible to directly generate a setcc into
13 // the lower GR8 of a specified GR32.
14 // This means that ISel must select (zext (setcc)) into something like
15 // seta %al; movzbl %al, %eax.
16 // Unfortunately, this can cause a stall due to the partial register write
17 // performed by the setcc. Instead, we can use:
18 // xor %eax, %eax; seta %al
19 // This both avoids the stall, and encodes shorter.
20 //===----------------------------------------------------------------------===//
21 
22 #include "X86.h"
23 #include "X86InstrInfo.h"
24 #include "X86Subtarget.h"
25 #include "llvm/ADT/Statistic.h"
29 
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "x86-fixup-setcc"
33 
34 STATISTIC(NumSubstZexts, "Number of setcc + zext pairs substituted");
35 
36 namespace {
37 class X86FixupSetCCPass : public MachineFunctionPass {
38 public:
39  static char ID;
40 
41  X86FixupSetCCPass() : MachineFunctionPass(ID) {}
42 
43  StringRef getPassName() const override { return "X86 Fixup SetCC"; }
44 
45  bool runOnMachineFunction(MachineFunction &MF) override;
46 
47 private:
48  MachineRegisterInfo *MRI = nullptr;
49  const X86InstrInfo *TII = nullptr;
50 
51  enum { SearchBound = 16 };
52 };
53 } // end anonymous namespace
54 
55 char X86FixupSetCCPass::ID = 0;
56 
57 INITIALIZE_PASS(X86FixupSetCCPass, DEBUG_TYPE, DEBUG_TYPE, false, false)
58 
59 FunctionPass *llvm::createX86FixupSetCC() { return new X86FixupSetCCPass(); }
60 
61 bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) {
62  bool Changed = false;
63  MRI = &MF.getRegInfo();
64  TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
65 
67 
68  for (auto &MBB : MF) {
69  MachineInstr *FlagsDefMI = nullptr;
70  for (auto &MI : MBB) {
71  // Remember the most recent preceding eflags defining instruction.
72  if (MI.definesRegister(X86::EFLAGS))
73  FlagsDefMI = &MI;
74 
75  // Find a setcc that is used by a zext.
76  // This doesn't have to be the only use, the transformation is safe
77  // regardless.
78  if (MI.getOpcode() != X86::SETCCr)
79  continue;
80 
81  MachineInstr *ZExt = nullptr;
82  for (auto &Use : MRI->use_instructions(MI.getOperand(0).getReg()))
83  if (Use.getOpcode() == X86::MOVZX32rr8)
84  ZExt = &Use;
85 
86  if (!ZExt)
87  continue;
88 
89  if (!FlagsDefMI)
90  continue;
91 
92  // We'd like to put something that clobbers eflags directly before
93  // FlagsDefMI. This can't hurt anything after FlagsDefMI, because
94  // it, itself, by definition, clobbers eflags. But it may happen that
95  // FlagsDefMI also *uses* eflags, in which case the transformation is
96  // invalid.
97  if (FlagsDefMI->readsRegister(X86::EFLAGS))
98  continue;
99 
100  // On 32-bit, we need to be careful to force an ABCD register.
101  const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit()
102  ? &X86::GR32RegClass
103  : &X86::GR32_ABCDRegClass;
104  if (!MRI->constrainRegClass(ZExt->getOperand(0).getReg(), RC)) {
105  // If we cannot constrain the register, we would need an additional copy
106  // and are better off keeping the MOVZX32rr8 we have now.
107  continue;
108  }
109 
110  ++NumSubstZexts;
111  Changed = true;
112 
113  // Initialize a register with 0. This must go before the eflags def
114  Register ZeroReg = MRI->createVirtualRegister(RC);
115  BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0),
116  ZeroReg);
117 
118  // X86 setcc only takes an output GR8, so fake a GR32 input by inserting
119  // the setcc result into the low byte of the zeroed register.
120  BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),
121  TII->get(X86::INSERT_SUBREG), ZExt->getOperand(0).getReg())
122  .addReg(ZeroReg)
123  .addReg(MI.getOperand(0).getReg())
124  .addImm(X86::sub_8bit);
125  ToErase.push_back(ZExt);
126  }
127  }
128 
129  for (auto &I : ToErase)
130  I->eraseFromParent();
131 
132  return Changed;
133 }
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
X86Subtarget.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1019
llvm::SmallVector< MachineInstr *, 4 >
Statistic.h
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::MachineRegisterInfo::use_instructions
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:485
llvm::createX86FixupSetCC
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
Definition: X86FixupSetCC.cpp:59
MachineRegisterInfo.h
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
X86.h
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
DEBUG_TYPE
#define DEBUG_TYPE
Definition: X86FixupSetCC.cpp:32
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
I
#define I(x, y, z)
Definition: MD5.cpp:59
MachineFunctionPass.h
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineInstr::readsRegister
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1363
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::X86InstrInfo
Definition: X86InstrInfo.h:130
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
X86InstrInfo.h
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38