27#define LOONGARCH_PRERA_EXPAND_PSEUDO_NAME \
28 "LoongArch Pre-RA pseudo instruction expansion pass"
58 unsigned FlagsHi,
unsigned SecondOpcode,
84char LoongArchPreRAExpandPseudo::ID = 0;
86bool LoongArchPreRAExpandPseudo::runOnMachineFunction(
MachineFunction &MF) {
108bool LoongArchPreRAExpandPseudo::expandMI(
111 switch (
MBBI->getOpcode()) {
112 case LoongArch::PseudoLA_PCREL:
113 return expandLoadAddressPcrel(
MBB,
MBBI, NextMBBI);
114 case LoongArch::PseudoLA_GOT:
115 return expandLoadAddressGot(
MBB,
MBBI, NextMBBI);
116 case LoongArch::PseudoLA_TLS_LE:
117 return expandLoadAddressTLSLE(
MBB,
MBBI, NextMBBI);
118 case LoongArch::PseudoLA_TLS_IE:
119 return expandLoadAddressTLSIE(
MBB,
MBBI, NextMBBI);
120 case LoongArch::PseudoLA_TLS_LD:
121 return expandLoadAddressTLSLD(
MBB,
MBBI, NextMBBI);
122 case LoongArch::PseudoLA_TLS_GD:
123 return expandLoadAddressTLSGD(
MBB,
MBBI, NextMBBI);
124 case LoongArch::PseudoCALL:
125 return expandFunctionCALL(
MBB,
MBBI, NextMBBI,
false);
126 case LoongArch::PseudoTAIL:
127 return expandFunctionCALL(
MBB,
MBBI, NextMBBI,
true);
132bool LoongArchPreRAExpandPseudo::expandPcalau12iInstPair(
135 unsigned SecondOpcode,
unsigned FlagsLo) {
153 if (
MI.hasOneMemOperand())
156 MI.eraseFromParent();
160bool LoongArchPreRAExpandPseudo::expandLoadAddressPcrel(
168 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
173bool LoongArchPreRAExpandPseudo::expandLoadAddressGot(
181 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
186bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLE(
208 MI.eraseFromParent();
212bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSIE(
220 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
225bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLD(
233 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
238bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSGD(
246 unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
251bool LoongArchPreRAExpandPseudo::expandFunctionCALL(
270 Opcode = IsTailCall ? LoongArch::PseudoB_TAIL : LoongArch::BL;
282 IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
290 if (Func.isSymbol()) {
291 const char *FnName = Func.getSymbolName();
296 assert(Func.isGlobal() &&
"Expected a GlobalValue at this time");
305 CALL.copyImplicitOps(
MI);
308 CALL.setMIFlags(
MI.getFlags());
310 MI.eraseFromParent();
322 return new LoongArchPreRAExpandPseudo();
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const HexagonInstrInfo * TII
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
#define LOONGARCH_PRERA_EXPAND_PSEUDO_NAME
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addDisp(const MachineOperand &Disp, int64_t off, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
MachineOperand class - Representation of each machine instruction operand.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
CodeModel::Model getCodeModel() const
Returns the code model.
virtual const TargetInstrInfo * getInstrInfo() const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void initializeLoongArchPreRAExpandPseudoPass(PassRegistry &)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
FunctionPass * createLoongArchPreRAExpandPseudoPass()