27#define DEBUG_TYPE "spirv-mccodeemitter"
35 SPIRVMCCodeEmitter(
const MCInstrInfo &mcii) : MCII(mcii) {}
36 SPIRVMCCodeEmitter(
const SPIRVMCCodeEmitter &) =
delete;
37 void operator=(
const SPIRVMCCodeEmitter &) =
delete;
38 ~SPIRVMCCodeEmitter()
override =
default;
55 return new SPIRVMCCodeEmitter(MCII);
68 auto &DefOpInfo = MCDesc.
operands()[0];
69 auto &FirstArgOpInfo = MCDesc.
operands()[1];
70 return (DefOpInfo.RegClass == SPIRV::IDRegClassID ||
71 DefOpInfo.RegClass == SPIRV::ANYIDRegClassID) &&
72 FirstArgOpInfo.RegClass == SPIRV::TYPERegClassID;
81 }
else if (Op.isImm()) {
91 unsigned NumOps =
MI.getNumOperands();
94 for (
unsigned i = 2; i < NumOps; ++i)
100 for (
const auto &Op :
MI)
110 const uint64_t OpCode = getBinaryCodeForInstr(
MI, Fixups, STI);
111 const uint32_t NumWords =
MI.getNumOperands() + 1;
112 const uint32_t FirstWord = (NumWords << 16) | OpCode;
122#include "SPIRVGenMCCodeEmitter.inc"
static void emitTypedInstrOperands(const MCInst &MI, EndianWriter &OSE)
static bool hasType(const MCInst &MI, const MCInstrInfo &MII)
static void emitOperand(const MCOperand &Op, EndianWriter &OSE)
static void emitUntypedInstrOperands(const MCInst &MI, EndianWriter &OSE)
MCCodeEmitter - Generic instruction encoding interface.
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Context object for machine code objects.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
Generic base class for all target subtargets.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
MCCodeEmitter * createSPIRVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Adapter to write values to a stream in a particular byte order.
void write(ArrayRef< value_type > Val)