27#define DEBUG_TYPE "spirv-mccodeemitter"
35 SPIRVMCCodeEmitter(
const MCInstrInfo &mcii) : MCII(mcii) {}
36 SPIRVMCCodeEmitter(
const SPIRVMCCodeEmitter &) =
delete;
37 void operator=(
const SPIRVMCCodeEmitter &) =
delete;
38 ~SPIRVMCCodeEmitter()
override =
default;
55 return new SPIRVMCCodeEmitter(MCII);
68 return MCDesc.
operands()[0].RegClass >= 0 &&
69 MCDesc.
operands()[1].RegClass >= 0 &&
70 MCDesc.
operands()[0].RegClass != SPIRV::TYPERegClassID &&
71 MCDesc.
operands()[1].RegClass == SPIRV::TYPERegClassID;
79 support::endian::write<uint32_t>(
81 }
else if (
Op.isImm()) {
93 unsigned NumOps =
MI.getNumOperands();
96 for (
unsigned i = 2; i < NumOps; ++i)
103 for (
const auto &
Op :
MI)
107void SPIRVMCCodeEmitter::encodeInstruction(
const MCInst &
MI,
113 const uint32_t NumWords =
MI.getNumOperands() + 1;
114 const uint32_t FirstWord = (NumWords << 16) | OpCode;
124#include "SPIRVGenMCCodeEmitter.inc"
static void emitUntypedInstrOperands(const MCInst &MI, SmallVectorImpl< char > &CB)
static void emitOperand(const MCOperand &Op, SmallVectorImpl< char > &CB)
static void emitTypedInstrOperands(const MCInst &MI, SmallVectorImpl< char > &CB)
static bool hasType(const MCInst &MI, const MCInstrInfo &MII)
This class represents an Operation in the Expression.
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
Context object for machine code objects.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
Generic base class for all target subtargets.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
This is an optimization pass for GlobalISel generic memory operations.
MCCodeEmitter * createSPIRVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Adapter to write values to a stream in a particular byte order.