LLVM  10.0.0svn
MipsAsmParser.cpp
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1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
14 #include "MipsTargetStreamer.h"
16 #include "llvm/ADT/APFloat.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/BinaryFormat/ELF.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCExpr.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
35 #include "llvm/MC/MCSectionELF.h"
36 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCSymbolELF.h"
40 #include "llvm/MC/MCValue.h"
42 #include "llvm/Support/Casting.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/SMLoc.h"
49 #include "llvm/Support/SourceMgr.h"
52 #include <algorithm>
53 #include <cassert>
54 #include <cstdint>
55 #include <memory>
56 #include <string>
57 #include <utility>
58 
59 using namespace llvm;
60 
61 #define DEBUG_TYPE "mips-asm-parser"
62 
63 namespace llvm {
64 
65 class MCInstrInfo;
66 
67 } // end namespace llvm
68 
70 
71 namespace {
72 
73 class MipsAssemblerOptions {
74 public:
75  MipsAssemblerOptions(const FeatureBitset &Features_) : Features(Features_) {}
76 
77  MipsAssemblerOptions(const MipsAssemblerOptions *Opts) {
78  ATReg = Opts->getATRegIndex();
79  Reorder = Opts->isReorder();
80  Macro = Opts->isMacro();
81  Features = Opts->getFeatures();
82  }
83 
84  unsigned getATRegIndex() const { return ATReg; }
85  bool setATRegIndex(unsigned Reg) {
86  if (Reg > 31)
87  return false;
88 
89  ATReg = Reg;
90  return true;
91  }
92 
93  bool isReorder() const { return Reorder; }
94  void setReorder() { Reorder = true; }
95  void setNoReorder() { Reorder = false; }
96 
97  bool isMacro() const { return Macro; }
98  void setMacro() { Macro = true; }
99  void setNoMacro() { Macro = false; }
100 
101  const FeatureBitset &getFeatures() const { return Features; }
102  void setFeatures(const FeatureBitset &Features_) { Features = Features_; }
103 
104  // Set of features that are either architecture features or referenced
105  // by them (e.g.: FeatureNaN2008 implied by FeatureMips32r6).
106  // The full table can be found in MipsGenSubtargetInfo.inc (MipsFeatureKV[]).
107  // The reason we need this mask is explained in the selectArch function.
108  // FIXME: Ideally we would like TableGen to generate this information.
109  static const FeatureBitset AllArchRelatedMask;
110 
111 private:
112  unsigned ATReg = 1;
113  bool Reorder = true;
114  bool Macro = true;
115  FeatureBitset Features;
116 };
117 
118 } // end anonymous namespace
119 
120 const FeatureBitset MipsAssemblerOptions::AllArchRelatedMask = {
121  Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
122  Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
123  Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
124  Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
125  Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
126  Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
127  Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
128  Mips::FeatureFP64Bit, Mips::FeatureGP64Bit, Mips::FeatureNaN2008
129 };
130 
131 namespace {
132 
133 class MipsAsmParser : public MCTargetAsmParser {
134  MipsTargetStreamer &getTargetStreamer() {
135  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
136  return static_cast<MipsTargetStreamer &>(TS);
137  }
138 
141  MCSymbol *CurrentFn; // Pointer to the function being parsed. It may be a
142  // nullptr, which indicates that no function is currently
143  // selected. This usually happens after an '.end func'
144  // directive.
145  bool IsLittleEndian;
146  bool IsPicEnabled;
147  bool IsCpRestoreSet;
148  int CpRestoreOffset;
149  unsigned GPReg;
150  unsigned CpSaveLocation;
151  /// If true, then CpSaveLocation is a register, otherwise it's an offset.
152  bool CpSaveLocationIsRegister;
153 
154  // Map of register aliases created via the .set directive.
155  StringMap<AsmToken> RegisterSets;
156 
157  // Print a warning along with its fix-it message at the given range.
158  void printWarningWithFixIt(const Twine &Msg, const Twine &FixMsg,
159  SMRange Range, bool ShowColors = true);
160 
161  void ConvertXWPOperands(MCInst &Inst, const OperandVector &Operands);
162 
163 #define GET_ASSEMBLER_HEADER
164 #include "MipsGenAsmMatcher.inc"
165 
166  unsigned
167  checkEarlyTargetMatchPredicate(MCInst &Inst,
168  const OperandVector &Operands) override;
169  unsigned checkTargetMatchPredicate(MCInst &Inst) override;
170 
171  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
172  OperandVector &Operands, MCStreamer &Out,
173  uint64_t &ErrorInfo,
174  bool MatchingInlineAsm) override;
175 
176  /// Parse a register as used in CFI directives
177  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
178 
179  bool parseParenSuffix(StringRef Name, OperandVector &Operands);
180 
181  bool parseBracketSuffix(StringRef Name, OperandVector &Operands);
182 
183  bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);
184 
185  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
186  SMLoc NameLoc, OperandVector &Operands) override;
187 
188  bool ParseDirective(AsmToken DirectiveID) override;
189 
190  OperandMatchResultTy parseMemOperand(OperandVector &Operands);
192  matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
193  StringRef Identifier, SMLoc S);
194  OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands,
195  const AsmToken &Token,
196  SMLoc S);
197  OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands,
198  SMLoc S);
199  OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
200  OperandMatchResultTy parseImm(OperandVector &Operands);
201  OperandMatchResultTy parseJumpTarget(OperandVector &Operands);
202  OperandMatchResultTy parseInvNum(OperandVector &Operands);
203  OperandMatchResultTy parseRegisterList(OperandVector &Operands);
204 
205  bool searchSymbolAlias(OperandVector &Operands);
206 
207  bool parseOperand(OperandVector &, StringRef Mnemonic);
208 
209  enum MacroExpanderResultTy {
210  MER_NotAMacro,
211  MER_Success,
212  MER_Fail,
213  };
214 
215  // Expands assembly pseudo instructions.
216  MacroExpanderResultTy tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
217  MCStreamer &Out,
218  const MCSubtargetInfo *STI);
219 
220  bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
221  const MCSubtargetInfo *STI);
222 
223  bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg,
224  bool Is32BitImm, bool IsAddress, SMLoc IDLoc,
225  MCStreamer &Out, const MCSubtargetInfo *STI);
226 
227  bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
228  unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc,
229  MCStreamer &Out, const MCSubtargetInfo *STI);
230 
231  bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym);
232 
233  bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
234  MCStreamer &Out, const MCSubtargetInfo *STI);
235 
236  bool expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR, bool Is64FPU,
237  SMLoc IDLoc, MCStreamer &Out,
238  const MCSubtargetInfo *STI);
239 
240  bool expandLoadAddress(unsigned DstReg, unsigned BaseReg,
241  const MCOperand &Offset, bool Is32BitAddress,
242  SMLoc IDLoc, MCStreamer &Out,
243  const MCSubtargetInfo *STI);
244 
245  bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
246  const MCSubtargetInfo *STI);
247 
248  void expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
249  const MCSubtargetInfo *STI, bool IsLoad);
250 
251  bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
252  const MCSubtargetInfo *STI);
253 
254  bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
255  const MCSubtargetInfo *STI);
256 
257  bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
258  const MCSubtargetInfo *STI);
259 
260  bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
261  const MCSubtargetInfo *STI);
262 
263  bool expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
264  const MCSubtargetInfo *STI, const bool IsMips64,
265  const bool Signed);
266 
267  bool expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc,
268  MCStreamer &Out, const MCSubtargetInfo *STI);
269 
270  bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out,
271  const MCSubtargetInfo *STI);
272 
273  bool expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
274  const MCSubtargetInfo *STI);
275 
276  bool expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
277  const MCSubtargetInfo *STI);
278 
279  bool expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
280  const MCSubtargetInfo *STI);
281 
282  bool expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
283  const MCSubtargetInfo *STI);
284 
285  bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
286  const MCSubtargetInfo *STI);
287 
288  bool expandRotation(MCInst &Inst, SMLoc IDLoc,
289  MCStreamer &Out, const MCSubtargetInfo *STI);
290  bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
291  const MCSubtargetInfo *STI);
292  bool expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
293  const MCSubtargetInfo *STI);
294  bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
295  const MCSubtargetInfo *STI);
296 
297  bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
298  const MCSubtargetInfo *STI);
299 
300  bool expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
301  const MCSubtargetInfo *STI);
302 
303  bool expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
304  const MCSubtargetInfo *STI);
305 
306  bool expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
307  const MCSubtargetInfo *STI);
308 
309  bool expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
310  const MCSubtargetInfo *STI);
311 
312  bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
313  const MCSubtargetInfo *STI, bool IsLoad);
314 
315  bool expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
316  const MCSubtargetInfo *STI);
317 
318  bool expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
319  const MCSubtargetInfo *STI);
320 
321  bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
322  const MCSubtargetInfo *STI);
323 
324  bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
325  const MCSubtargetInfo *STI);
326 
327  bool reportParseError(Twine ErrorMsg);
328  bool reportParseError(SMLoc Loc, Twine ErrorMsg);
329 
330  bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
331 
332  bool isEvaluated(const MCExpr *Expr);
333  bool parseSetMips0Directive();
334  bool parseSetArchDirective();
335  bool parseSetFeature(uint64_t Feature);
336  bool isPicAndNotNxxAbi(); // Used by .cpload, .cprestore, and .cpsetup.
337  bool parseDirectiveCpLoad(SMLoc Loc);
338  bool parseDirectiveCpLocal(SMLoc Loc);
339  bool parseDirectiveCpRestore(SMLoc Loc);
340  bool parseDirectiveCPSetup();
341  bool parseDirectiveCPReturn();
342  bool parseDirectiveNaN();
343  bool parseDirectiveSet();
344  bool parseDirectiveOption();
345  bool parseInsnDirective();
346  bool parseRSectionDirective(StringRef Section);
347  bool parseSSectionDirective(StringRef Section, unsigned Type);
348 
349  bool parseSetAtDirective();
350  bool parseSetNoAtDirective();
351  bool parseSetMacroDirective();
352  bool parseSetNoMacroDirective();
353  bool parseSetMsaDirective();
354  bool parseSetNoMsaDirective();
355  bool parseSetNoDspDirective();
356  bool parseSetReorderDirective();
357  bool parseSetNoReorderDirective();
358  bool parseSetMips16Directive();
359  bool parseSetNoMips16Directive();
360  bool parseSetFpDirective();
361  bool parseSetOddSPRegDirective();
362  bool parseSetNoOddSPRegDirective();
363  bool parseSetPopDirective();
364  bool parseSetPushDirective();
365  bool parseSetSoftFloatDirective();
366  bool parseSetHardFloatDirective();
367  bool parseSetMtDirective();
368  bool parseSetNoMtDirective();
369  bool parseSetNoCRCDirective();
370  bool parseSetNoVirtDirective();
371  bool parseSetNoGINVDirective();
372 
373  bool parseSetAssignment();
374 
375  bool parseDirectiveGpWord();
376  bool parseDirectiveGpDWord();
377  bool parseDirectiveDtpRelWord();
378  bool parseDirectiveDtpRelDWord();
379  bool parseDirectiveTpRelWord();
380  bool parseDirectiveTpRelDWord();
381  bool parseDirectiveModule();
382  bool parseDirectiveModuleFP();
383  bool parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI,
384  StringRef Directive);
385 
386  bool parseInternalDirectiveReallowModule();
387 
388  bool eatComma(StringRef ErrorStr);
389 
390  int matchCPURegisterName(StringRef Symbol);
391 
392  int matchHWRegsRegisterName(StringRef Symbol);
393 
394  int matchFPURegisterName(StringRef Name);
395 
396  int matchFCCRegisterName(StringRef Name);
397 
398  int matchACRegisterName(StringRef Name);
399 
400  int matchMSA128RegisterName(StringRef Name);
401 
402  int matchMSA128CtrlRegisterName(StringRef Name);
403 
404  unsigned getReg(int RC, int RegNo);
405 
406  /// Returns the internal register number for the current AT. Also checks if
407  /// the current AT is unavailable (set to $0) and gives an error if it is.
408  /// This should be used in pseudo-instruction expansions which need AT.
409  unsigned getATReg(SMLoc Loc);
410 
411  bool canUseATReg();
412 
413  bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
414  const MCSubtargetInfo *STI);
415 
416  // Helper function that checks if the value of a vector index is within the
417  // boundaries of accepted values for each RegisterKind
418  // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
419  bool validateMSAIndex(int Val, int RegKind);
420 
421  // Selects a new architecture by updating the FeatureBits with the necessary
422  // info including implied dependencies.
423  // Internally, it clears all the feature bits related to *any* architecture
424  // and selects the new one using the ToggleFeature functionality of the
425  // MCSubtargetInfo object that handles implied dependencies. The reason we
426  // clear all the arch related bits manually is because ToggleFeature only
427  // clears the features that imply the feature being cleared and not the
428  // features implied by the feature being cleared. This is easier to see
429  // with an example:
430  // --------------------------------------------------
431  // | Feature | Implies |
432  // | -------------------------------------------------|
433  // | FeatureMips1 | None |
434  // | FeatureMips2 | FeatureMips1 |
435  // | FeatureMips3 | FeatureMips2 | FeatureMipsGP64 |
436  // | FeatureMips4 | FeatureMips3 |
437  // | ... | |
438  // --------------------------------------------------
439  //
440  // Setting Mips3 is equivalent to set: (FeatureMips3 | FeatureMips2 |
441  // FeatureMipsGP64 | FeatureMips1)
442  // Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4).
443  void selectArch(StringRef ArchFeature) {
444  MCSubtargetInfo &STI = copySTI();
445  FeatureBitset FeatureBits = STI.getFeatureBits();
446  FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask;
447  STI.setFeatureBits(FeatureBits);
448  setAvailableFeatures(
449  ComputeAvailableFeatures(STI.ToggleFeature(ArchFeature)));
450  AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
451  }
452 
453  void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
454  if (!(getSTI().getFeatureBits()[Feature])) {
455  MCSubtargetInfo &STI = copySTI();
456  setAvailableFeatures(
457  ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
458  AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
459  }
460  }
461 
462  void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
463  if (getSTI().getFeatureBits()[Feature]) {
464  MCSubtargetInfo &STI = copySTI();
465  setAvailableFeatures(
466  ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
467  AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
468  }
469  }
470 
471  void setModuleFeatureBits(uint64_t Feature, StringRef FeatureString) {
472  setFeatureBits(Feature, FeatureString);
473  AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
474  }
475 
476  void clearModuleFeatureBits(uint64_t Feature, StringRef FeatureString) {
477  clearFeatureBits(Feature, FeatureString);
478  AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
479  }
480 
481 public:
482  enum MipsMatchResultTy {
483  Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY,
484  Match_RequiresDifferentOperands,
485  Match_RequiresNoZeroRegister,
486  Match_RequiresSameSrcAndDst,
487  Match_NoFCCRegisterForCurrentISA,
488  Match_NonZeroOperandForSync,
489  Match_NonZeroOperandForMTCX,
490  Match_RequiresPosSizeRange0_32,
491  Match_RequiresPosSizeRange33_64,
492  Match_RequiresPosSizeUImm6,
493 #define GET_OPERAND_DIAGNOSTIC_TYPES
494 #include "MipsGenAsmMatcher.inc"
495 #undef GET_OPERAND_DIAGNOSTIC_TYPES
496  };
497 
498  MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
499  const MCInstrInfo &MII, const MCTargetOptions &Options)
500  : MCTargetAsmParser(Options, sti, MII),
501  ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()),
502  sti.getCPU(), Options)) {
504 
505  parser.addAliasForDirective(".asciiz", ".asciz");
506  parser.addAliasForDirective(".hword", ".2byte");
507  parser.addAliasForDirective(".word", ".4byte");
508  parser.addAliasForDirective(".dword", ".8byte");
509 
510  // Initialize the set of available features.
511  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
512 
513  // Remember the initial assembler options. The user can not modify these.
514  AssemblerOptions.push_back(
515  std::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));
516 
517  // Create an assembler options environment for the user to modify.
518  AssemblerOptions.push_back(
519  std::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));
520 
521  getTargetStreamer().updateABIInfo(*this);
522 
523  if (!isABI_O32() && !useOddSPReg() != 0)
524  report_fatal_error("-mno-odd-spreg requires the O32 ABI");
525 
526  CurrentFn = nullptr;
527 
528  IsPicEnabled = getContext().getObjectFileInfo()->isPositionIndependent();
529 
530  IsCpRestoreSet = false;
531  CpRestoreOffset = -1;
532  GPReg = ABI.GetGlobalPtr();
533 
534  const Triple &TheTriple = sti.getTargetTriple();
535  IsLittleEndian = TheTriple.isLittleEndian();
536 
537  if (getSTI().getCPU() == "mips64r6" && inMicroMipsMode())
538  report_fatal_error("microMIPS64R6 is not supported", false);
539 
540  if (!isABI_O32() && inMicroMipsMode())
541  report_fatal_error("microMIPS64 is not supported", false);
542  }
543 
544  /// True if all of $fcc0 - $fcc7 exist for the current ISA.
545  bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
546 
547  bool isGP64bit() const {
548  return getSTI().getFeatureBits()[Mips::FeatureGP64Bit];
549  }
550 
551  bool isFP64bit() const {
552  return getSTI().getFeatureBits()[Mips::FeatureFP64Bit];
553  }
554 
555  const MipsABIInfo &getABI() const { return ABI; }
556  bool isABI_N32() const { return ABI.IsN32(); }
557  bool isABI_N64() const { return ABI.IsN64(); }
558  bool isABI_O32() const { return ABI.IsO32(); }
559  bool isABI_FPXX() const {
560  return getSTI().getFeatureBits()[Mips::FeatureFPXX];
561  }
562 
563  bool useOddSPReg() const {
564  return !(getSTI().getFeatureBits()[Mips::FeatureNoOddSPReg]);
565  }
566 
567  bool inMicroMipsMode() const {
568  return getSTI().getFeatureBits()[Mips::FeatureMicroMips];
569  }
570 
571  bool hasMips1() const {
572  return getSTI().getFeatureBits()[Mips::FeatureMips1];
573  }
574 
575  bool hasMips2() const {
576  return getSTI().getFeatureBits()[Mips::FeatureMips2];
577  }
578 
579  bool hasMips3() const {
580  return getSTI().getFeatureBits()[Mips::FeatureMips3];
581  }
582 
583  bool hasMips4() const {
584  return getSTI().getFeatureBits()[Mips::FeatureMips4];
585  }
586 
587  bool hasMips5() const {
588  return getSTI().getFeatureBits()[Mips::FeatureMips5];
589  }
590 
591  bool hasMips32() const {
592  return getSTI().getFeatureBits()[Mips::FeatureMips32];
593  }
594 
595  bool hasMips64() const {
596  return getSTI().getFeatureBits()[Mips::FeatureMips64];
597  }
598 
599  bool hasMips32r2() const {
600  return getSTI().getFeatureBits()[Mips::FeatureMips32r2];
601  }
602 
603  bool hasMips64r2() const {
604  return getSTI().getFeatureBits()[Mips::FeatureMips64r2];
605  }
606 
607  bool hasMips32r3() const {
608  return (getSTI().getFeatureBits()[Mips::FeatureMips32r3]);
609  }
610 
611  bool hasMips64r3() const {
612  return (getSTI().getFeatureBits()[Mips::FeatureMips64r3]);
613  }
614 
615  bool hasMips32r5() const {
616  return (getSTI().getFeatureBits()[Mips::FeatureMips32r5]);
617  }
618 
619  bool hasMips64r5() const {
620  return (getSTI().getFeatureBits()[Mips::FeatureMips64r5]);
621  }
622 
623  bool hasMips32r6() const {
624  return getSTI().getFeatureBits()[Mips::FeatureMips32r6];
625  }
626 
627  bool hasMips64r6() const {
628  return getSTI().getFeatureBits()[Mips::FeatureMips64r6];
629  }
630 
631  bool hasDSP() const {
632  return getSTI().getFeatureBits()[Mips::FeatureDSP];
633  }
634 
635  bool hasDSPR2() const {
636  return getSTI().getFeatureBits()[Mips::FeatureDSPR2];
637  }
638 
639  bool hasDSPR3() const {
640  return getSTI().getFeatureBits()[Mips::FeatureDSPR3];
641  }
642 
643  bool hasMSA() const {
644  return getSTI().getFeatureBits()[Mips::FeatureMSA];
645  }
646 
647  bool hasCnMips() const {
648  return (getSTI().getFeatureBits()[Mips::FeatureCnMips]);
649  }
650 
651  bool inPicMode() {
652  return IsPicEnabled;
653  }
654 
655  bool inMips16Mode() const {
656  return getSTI().getFeatureBits()[Mips::FeatureMips16];
657  }
658 
659  bool useTraps() const {
660  return getSTI().getFeatureBits()[Mips::FeatureUseTCCInDIV];
661  }
662 
663  bool useSoftFloat() const {
664  return getSTI().getFeatureBits()[Mips::FeatureSoftFloat];
665  }
666  bool hasMT() const {
667  return getSTI().getFeatureBits()[Mips::FeatureMT];
668  }
669 
670  bool hasCRC() const {
671  return getSTI().getFeatureBits()[Mips::FeatureCRC];
672  }
673 
674  bool hasVirt() const {
675  return getSTI().getFeatureBits()[Mips::FeatureVirt];
676  }
677 
678  bool hasGINV() const {
679  return getSTI().getFeatureBits()[Mips::FeatureGINV];
680  }
681 
682  /// Warn if RegIndex is the same as the current AT.
683  void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
684 
685  void warnIfNoMacro(SMLoc Loc);
686 
687  bool isLittle() const { return IsLittleEndian; }
688 
689  const MCExpr *createTargetUnaryExpr(const MCExpr *E,
690  AsmToken::TokenKind OperatorToken,
691  MCContext &Ctx) override {
692  switch(OperatorToken) {
693  default:
694  llvm_unreachable("Unknown token");
695  return nullptr;
707  return MipsMCExpr::create(MipsMCExpr::MEK_GOT, E, Ctx);
722  case AsmToken::PercentHi:
723  return MipsMCExpr::create(MipsMCExpr::MEK_HI, E, Ctx);
728  case AsmToken::PercentLo:
729  return MipsMCExpr::create(MipsMCExpr::MEK_LO, E, Ctx);
731  return MipsMCExpr::create(MipsMCExpr::MEK_NEG, E, Ctx);
744  }
745  }
746 };
747 
748 /// MipsOperand - Instances of this class represent a parsed Mips machine
749 /// instruction.
750 class MipsOperand : public MCParsedAsmOperand {
751 public:
752  /// Broad categories of register classes
753  /// The exact class is finalized by the render method.
754  enum RegKind {
755  RegKind_GPR = 1, /// GPR32 and GPR64 (depending on isGP64bit())
756  RegKind_FGR = 2, /// FGR32, FGR64, AFGR64 (depending on context and
757  /// isFP64bit())
758  RegKind_FCC = 4, /// FCC
759  RegKind_MSA128 = 8, /// MSA128[BHWD] (makes no difference which)
760  RegKind_MSACtrl = 16, /// MSA control registers
761  RegKind_COP2 = 32, /// COP2
762  RegKind_ACC = 64, /// HI32DSP, LO32DSP, and ACC64DSP (depending on
763  /// context).
764  RegKind_CCR = 128, /// CCR
765  RegKind_HWRegs = 256, /// HWRegs
766  RegKind_COP3 = 512, /// COP3
767  RegKind_COP0 = 1024, /// COP0
768  /// Potentially any (e.g. $1)
769  RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
770  RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
771  RegKind_CCR | RegKind_HWRegs | RegKind_COP3 | RegKind_COP0
772  };
773 
774 private:
775  enum KindTy {
776  k_Immediate, /// An immediate (possibly involving symbol references)
777  k_Memory, /// Base + Offset Memory Address
778  k_RegisterIndex, /// A register index in one or more RegKind.
779  k_Token, /// A simple token
780  k_RegList, /// A physical register list
781  } Kind;
782 
783 public:
784  MipsOperand(KindTy K, MipsAsmParser &Parser)
785  : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {}
786 
787  ~MipsOperand() override {
788  switch (Kind) {
789  case k_Memory:
790  delete Mem.Base;
791  break;
792  case k_RegList:
793  delete RegList.List;
794  break;
795  case k_Immediate:
796  case k_RegisterIndex:
797  case k_Token:
798  break;
799  }
800  }
801 
802 private:
803  /// For diagnostics, and checking the assembler temporary
804  MipsAsmParser &AsmParser;
805 
806  struct Token {
807  const char *Data;
808  unsigned Length;
809  };
810 
811  struct RegIdxOp {
812  unsigned Index; /// Index into the register class
813  RegKind Kind; /// Bitfield of the kinds it could possibly be
814  struct Token Tok; /// The input token this operand originated from.
815  const MCRegisterInfo *RegInfo;
816  };
817 
818  struct ImmOp {
819  const MCExpr *Val;
820  };
821 
822  struct MemOp {
823  MipsOperand *Base;
824  const MCExpr *Off;
825  };
826 
827  struct RegListOp {
829  };
830 
831  union {
832  struct Token Tok;
833  struct RegIdxOp RegIdx;
834  struct ImmOp Imm;
835  struct MemOp Mem;
836  struct RegListOp RegList;
837  };
838 
839  SMLoc StartLoc, EndLoc;
840 
841  /// Internal constructor for register kinds
842  static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, StringRef Str,
844  const MCRegisterInfo *RegInfo,
845  SMLoc S, SMLoc E,
846  MipsAsmParser &Parser) {
847  auto Op = std::make_unique<MipsOperand>(k_RegisterIndex, Parser);
848  Op->RegIdx.Index = Index;
849  Op->RegIdx.RegInfo = RegInfo;
850  Op->RegIdx.Kind = RegKind;
851  Op->RegIdx.Tok.Data = Str.data();
852  Op->RegIdx.Tok.Length = Str.size();
853  Op->StartLoc = S;
854  Op->EndLoc = E;
855  return Op;
856  }
857 
858 public:
859  /// Coerce the register to GPR32 and return the real register for the current
860  /// target.
861  unsigned getGPR32Reg() const {
862  assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
863  AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);
864  unsigned ClassID = Mips::GPR32RegClassID;
865  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
866  }
867 
868  /// Coerce the register to GPR32 and return the real register for the current
869  /// target.
870  unsigned getGPRMM16Reg() const {
871  assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
872  unsigned ClassID = Mips::GPR32RegClassID;
873  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
874  }
875 
876  /// Coerce the register to GPR64 and return the real register for the current
877  /// target.
878  unsigned getGPR64Reg() const {
879  assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
880  unsigned ClassID = Mips::GPR64RegClassID;
881  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
882  }
883 
884 private:
885  /// Coerce the register to AFGR64 and return the real register for the current
886  /// target.
887  unsigned getAFGR64Reg() const {
888  assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
889  if (RegIdx.Index % 2 != 0)
890  AsmParser.Warning(StartLoc, "Float register should be even.");
891  return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
892  .getRegister(RegIdx.Index / 2);
893  }
894 
895  /// Coerce the register to FGR64 and return the real register for the current
896  /// target.
897  unsigned getFGR64Reg() const {
898  assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
899  return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
900  .getRegister(RegIdx.Index);
901  }
902 
903  /// Coerce the register to FGR32 and return the real register for the current
904  /// target.
905  unsigned getFGR32Reg() const {
906  assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
907  return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
908  .getRegister(RegIdx.Index);
909  }
910 
911  /// Coerce the register to FCC and return the real register for the current
912  /// target.
913  unsigned getFCCReg() const {
914  assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
915  return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
916  .getRegister(RegIdx.Index);
917  }
918 
919  /// Coerce the register to MSA128 and return the real register for the current
920  /// target.
921  unsigned getMSA128Reg() const {
922  assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");
923  // It doesn't matter which of the MSA128[BHWD] classes we use. They are all
924  // identical
925  unsigned ClassID = Mips::MSA128BRegClassID;
926  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
927  }
928 
929  /// Coerce the register to MSACtrl and return the real register for the
930  /// current target.
931  unsigned getMSACtrlReg() const {
932  assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
933  unsigned ClassID = Mips::MSACtrlRegClassID;
934  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
935  }
936 
937  /// Coerce the register to COP0 and return the real register for the
938  /// current target.
939  unsigned getCOP0Reg() const {
940  assert(isRegIdx() && (RegIdx.Kind & RegKind_COP0) && "Invalid access!");
941  unsigned ClassID = Mips::COP0RegClassID;
942  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
943  }
944 
945  /// Coerce the register to COP2 and return the real register for the
946  /// current target.
947  unsigned getCOP2Reg() const {
948  assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
949  unsigned ClassID = Mips::COP2RegClassID;
950  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
951  }
952 
953  /// Coerce the register to COP3 and return the real register for the
954  /// current target.
955  unsigned getCOP3Reg() const {
956  assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!");
957  unsigned ClassID = Mips::COP3RegClassID;
958  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
959  }
960 
961  /// Coerce the register to ACC64DSP and return the real register for the
962  /// current target.
963  unsigned getACC64DSPReg() const {
964  assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
965  unsigned ClassID = Mips::ACC64DSPRegClassID;
966  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
967  }
968 
969  /// Coerce the register to HI32DSP and return the real register for the
970  /// current target.
971  unsigned getHI32DSPReg() const {
972  assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
973  unsigned ClassID = Mips::HI32DSPRegClassID;
974  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
975  }
976 
977  /// Coerce the register to LO32DSP and return the real register for the
978  /// current target.
979  unsigned getLO32DSPReg() const {
980  assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
981  unsigned ClassID = Mips::LO32DSPRegClassID;
982  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
983  }
984 
985  /// Coerce the register to CCR and return the real register for the
986  /// current target.
987  unsigned getCCRReg() const {
988  assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!");
989  unsigned ClassID = Mips::CCRRegClassID;
990  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
991  }
992 
993  /// Coerce the register to HWRegs and return the real register for the
994  /// current target.
995  unsigned getHWRegsReg() const {
996  assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!");
997  unsigned ClassID = Mips::HWRegsRegClassID;
998  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
999  }
1000 
1001 public:
1002  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1003  // Add as immediate when possible. Null MCExpr = 0.
1004  if (!Expr)
1006  else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1007  Inst.addOperand(MCOperand::createImm(CE->getValue()));
1008  else
1009  Inst.addOperand(MCOperand::createExpr(Expr));
1010  }
1011 
1012  void addRegOperands(MCInst &Inst, unsigned N) const {
1013  llvm_unreachable("Use a custom parser instead");
1014  }
1015 
1016  /// Render the operand to an MCInst as a GPR32
1017  /// Asserts if the wrong number of operands are requested, or the operand
1018  /// is not a k_RegisterIndex compatible with RegKind_GPR
1019  void addGPR32ZeroAsmRegOperands(MCInst &Inst, unsigned N) const {
1020  assert(N == 1 && "Invalid number of operands!");
1021  Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
1022  }
1023 
1024  void addGPR32NonZeroAsmRegOperands(MCInst &Inst, unsigned N) const {
1025  assert(N == 1 && "Invalid number of operands!");
1026  Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
1027  }
1028 
1029  void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
1030  assert(N == 1 && "Invalid number of operands!");
1031  Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
1032  }
1033 
1034  void addGPRMM16AsmRegOperands(MCInst &Inst, unsigned N) const {
1035  assert(N == 1 && "Invalid number of operands!");
1036  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
1037  }
1038 
1039  void addGPRMM16AsmRegZeroOperands(MCInst &Inst, unsigned N) const {
1040  assert(N == 1 && "Invalid number of operands!");
1041  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
1042  }
1043 
1044  void addGPRMM16AsmRegMovePOperands(MCInst &Inst, unsigned N) const {
1045  assert(N == 1 && "Invalid number of operands!");
1046  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
1047  }
1048 
1049  void addGPRMM16AsmRegMovePPairFirstOperands(MCInst &Inst, unsigned N) const {
1050  assert(N == 1 && "Invalid number of operands!");
1051  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
1052  }
1053 
1054  void addGPRMM16AsmRegMovePPairSecondOperands(MCInst &Inst,
1055  unsigned N) const {
1056  assert(N == 1 && "Invalid number of operands!");
1057  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
1058  }
1059 
1060  /// Render the operand to an MCInst as a GPR64
1061  /// Asserts if the wrong number of operands are requested, or the operand
1062  /// is not a k_RegisterIndex compatible with RegKind_GPR
1063  void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1064  assert(N == 1 && "Invalid number of operands!");
1065  Inst.addOperand(MCOperand::createReg(getGPR64Reg()));
1066  }
1067 
1068  void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1069  assert(N == 1 && "Invalid number of operands!");
1070  Inst.addOperand(MCOperand::createReg(getAFGR64Reg()));
1071  }
1072 
1073  void addStrictlyAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1074  assert(N == 1 && "Invalid number of operands!");
1075  Inst.addOperand(MCOperand::createReg(getAFGR64Reg()));
1076  }
1077 
1078  void addStrictlyFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1079  assert(N == 1 && "Invalid number of operands!");
1080  Inst.addOperand(MCOperand::createReg(getFGR64Reg()));
1081  }
1082 
1083  void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
1084  assert(N == 1 && "Invalid number of operands!");
1085  Inst.addOperand(MCOperand::createReg(getFGR64Reg()));
1086  }
1087 
1088  void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
1089  assert(N == 1 && "Invalid number of operands!");
1090  Inst.addOperand(MCOperand::createReg(getFGR32Reg()));
1091  // FIXME: We ought to do this for -integrated-as without -via-file-asm too.
1092  // FIXME: This should propagate failure up to parseStatement.
1093  if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
1094  AsmParser.getParser().printError(
1095  StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
1096  "registers");
1097  }
1098 
1099  void addStrictlyFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
1100  assert(N == 1 && "Invalid number of operands!");
1101  Inst.addOperand(MCOperand::createReg(getFGR32Reg()));
1102  // FIXME: We ought to do this for -integrated-as without -via-file-asm too.
1103  if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
1104  AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
1105  "registers");
1106  }
1107 
1108  void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
1109  assert(N == 1 && "Invalid number of operands!");
1110  Inst.addOperand(MCOperand::createReg(getFCCReg()));
1111  }
1112 
1113  void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
1114  assert(N == 1 && "Invalid number of operands!");
1115  Inst.addOperand(MCOperand::createReg(getMSA128Reg()));
1116  }
1117 
1118  void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
1119  assert(N == 1 && "Invalid number of operands!");
1120  Inst.addOperand(MCOperand::createReg(getMSACtrlReg()));
1121  }
1122 
1123  void addCOP0AsmRegOperands(MCInst &Inst, unsigned N) const {
1124  assert(N == 1 && "Invalid number of operands!");
1125  Inst.addOperand(MCOperand::createReg(getCOP0Reg()));
1126  }
1127 
1128  void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
1129  assert(N == 1 && "Invalid number of operands!");
1130  Inst.addOperand(MCOperand::createReg(getCOP2Reg()));
1131  }
1132 
1133  void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const {
1134  assert(N == 1 && "Invalid number of operands!");
1135  Inst.addOperand(MCOperand::createReg(getCOP3Reg()));
1136  }
1137 
1138  void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
1139  assert(N == 1 && "Invalid number of operands!");
1140  Inst.addOperand(MCOperand::createReg(getACC64DSPReg()));
1141  }
1142 
1143  void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
1144  assert(N == 1 && "Invalid number of operands!");
1145  Inst.addOperand(MCOperand::createReg(getHI32DSPReg()));
1146  }
1147 
1148  void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
1149  assert(N == 1 && "Invalid number of operands!");
1150  Inst.addOperand(MCOperand::createReg(getLO32DSPReg()));
1151  }
1152 
1153  void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
1154  assert(N == 1 && "Invalid number of operands!");
1155  Inst.addOperand(MCOperand::createReg(getCCRReg()));
1156  }
1157 
1158  void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
1159  assert(N == 1 && "Invalid number of operands!");
1160  Inst.addOperand(MCOperand::createReg(getHWRegsReg()));
1161  }
1162 
1163  template <unsigned Bits, int Offset = 0, int AdjustOffset = 0>
1164  void addConstantUImmOperands(MCInst &Inst, unsigned N) const {
1165  assert(N == 1 && "Invalid number of operands!");
1166  uint64_t Imm = getConstantImm() - Offset;
1167  Imm &= (1ULL << Bits) - 1;
1168  Imm += Offset;
1169  Imm += AdjustOffset;
1170  Inst.addOperand(MCOperand::createImm(Imm));
1171  }
1172 
1173  template <unsigned Bits>
1174  void addSImmOperands(MCInst &Inst, unsigned N) const {
1175  if (isImm() && !isConstantImm()) {
1176  addExpr(Inst, getImm());
1177  return;
1178  }
1179  addConstantSImmOperands<Bits, 0, 0>(Inst, N);
1180  }
1181 
1182  template <unsigned Bits>
1183  void addUImmOperands(MCInst &Inst, unsigned N) const {
1184  if (isImm() && !isConstantImm()) {
1185  addExpr(Inst, getImm());
1186  return;
1187  }
1188  addConstantUImmOperands<Bits, 0, 0>(Inst, N);
1189  }
1190 
1191  template <unsigned Bits, int Offset = 0, int AdjustOffset = 0>
1192  void addConstantSImmOperands(MCInst &Inst, unsigned N) const {
1193  assert(N == 1 && "Invalid number of operands!");
1194  int64_t Imm = getConstantImm() - Offset;
1195  Imm = SignExtend64<Bits>(Imm);
1196  Imm += Offset;
1197  Imm += AdjustOffset;
1198  Inst.addOperand(MCOperand::createImm(Imm));
1199  }
1200 
1201  void addImmOperands(MCInst &Inst, unsigned N) const {
1202  assert(N == 1 && "Invalid number of operands!");
1203  const MCExpr *Expr = getImm();
1204  addExpr(Inst, Expr);
1205  }
1206 
1207  void addMemOperands(MCInst &Inst, unsigned N) const {
1208  assert(N == 2 && "Invalid number of operands!");
1209 
1210  Inst.addOperand(MCOperand::createReg(AsmParser.getABI().ArePtrs64bit()
1211  ? getMemBase()->getGPR64Reg()
1212  : getMemBase()->getGPR32Reg()));
1213 
1214  const MCExpr *Expr = getMemOff();
1215  addExpr(Inst, Expr);
1216  }
1217 
1218  void addMicroMipsMemOperands(MCInst &Inst, unsigned N) const {
1219  assert(N == 2 && "Invalid number of operands!");
1220 
1221  Inst.addOperand(MCOperand::createReg(getMemBase()->getGPRMM16Reg()));
1222 
1223  const MCExpr *Expr = getMemOff();
1224  addExpr(Inst, Expr);
1225  }
1226 
1227  void addRegListOperands(MCInst &Inst, unsigned N) const {
1228  assert(N == 1 && "Invalid number of operands!");
1229 
1230  for (auto RegNo : getRegList())
1231  Inst.addOperand(MCOperand::createReg(RegNo));
1232  }
1233 
1234  bool isReg() const override {
1235  // As a special case until we sort out the definition of div/divu, accept
1236  // $0/$zero here so that MCK_ZERO works correctly.
1237  return isGPRAsmReg() && RegIdx.Index == 0;
1238  }
1239 
1240  bool isRegIdx() const { return Kind == k_RegisterIndex; }
1241  bool isImm() const override { return Kind == k_Immediate; }
1242 
1243  bool isConstantImm() const {
1244  int64_t Res;
1245  return isImm() && getImm()->evaluateAsAbsolute(Res);
1246  }
1247 
1248  bool isConstantImmz() const {
1249  return isConstantImm() && getConstantImm() == 0;
1250  }
1251 
1252  template <unsigned Bits, int Offset = 0> bool isConstantUImm() const {
1253  return isConstantImm() && isUInt<Bits>(getConstantImm() - Offset);
1254  }
1255 
1256  template <unsigned Bits> bool isSImm() const {
1257  return isConstantImm() ? isInt<Bits>(getConstantImm()) : isImm();
1258  }
1259 
1260  template <unsigned Bits> bool isUImm() const {
1261  return isConstantImm() ? isUInt<Bits>(getConstantImm()) : isImm();
1262  }
1263 
1264  template <unsigned Bits> bool isAnyImm() const {
1265  return isConstantImm() ? (isInt<Bits>(getConstantImm()) ||
1266  isUInt<Bits>(getConstantImm()))
1267  : isImm();
1268  }
1269 
1270  template <unsigned Bits, int Offset = 0> bool isConstantSImm() const {
1271  return isConstantImm() && isInt<Bits>(getConstantImm() - Offset);
1272  }
1273 
1274  template <unsigned Bottom, unsigned Top> bool isConstantUImmRange() const {
1275  return isConstantImm() && getConstantImm() >= Bottom &&
1276  getConstantImm() <= Top;
1277  }
1278 
1279  bool isToken() const override {
1280  // Note: It's not possible to pretend that other operand kinds are tokens.
1281  // The matcher emitter checks tokens first.
1282  return Kind == k_Token;
1283  }
1284 
1285  bool isMem() const override { return Kind == k_Memory; }
1286 
1287  bool isConstantMemOff() const {
1288  return isMem() && isa<MCConstantExpr>(getMemOff());
1289  }
1290 
1291  // Allow relocation operators.
1292  // FIXME: This predicate and others need to look through binary expressions
1293  // and determine whether a Value is a constant or not.
1294  template <unsigned Bits, unsigned ShiftAmount = 0>
1295  bool isMemWithSimmOffset() const {
1296  if (!isMem())
1297  return false;
1298  if (!getMemBase()->isGPRAsmReg())
1299  return false;
1300  if (isa<MCTargetExpr>(getMemOff()) ||
1301  (isConstantMemOff() &&
1302  isShiftedInt<Bits, ShiftAmount>(getConstantMemOff())))
1303  return true;
1304  MCValue Res;
1305  bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr);
1306  return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant());
1307  }
1308 
1309  bool isMemWithPtrSizeOffset() const {
1310  if (!isMem())
1311  return false;
1312  if (!getMemBase()->isGPRAsmReg())
1313  return false;
1314  const unsigned PtrBits = AsmParser.getABI().ArePtrs64bit() ? 64 : 32;
1315  if (isa<MCTargetExpr>(getMemOff()) ||
1316  (isConstantMemOff() && isIntN(PtrBits, getConstantMemOff())))
1317  return true;
1318  MCValue Res;
1319  bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr);
1320  return IsReloc && isIntN(PtrBits, Res.getConstant());
1321  }
1322 
1323  bool isMemWithGRPMM16Base() const {
1324  return isMem() && getMemBase()->isMM16AsmReg();
1325  }
1326 
1327  template <unsigned Bits> bool isMemWithUimmOffsetSP() const {
1328  return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
1329  && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP);
1330  }
1331 
1332  template <unsigned Bits> bool isMemWithUimmWordAlignedOffsetSP() const {
1333  return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
1334  && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()
1335  && (getMemBase()->getGPR32Reg() == Mips::SP);
1336  }
1337 
1338  template <unsigned Bits> bool isMemWithSimmWordAlignedOffsetGP() const {
1339  return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff())
1340  && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()
1341  && (getMemBase()->getGPR32Reg() == Mips::GP);
1342  }
1343 
1344  template <unsigned Bits, unsigned ShiftLeftAmount>
1345  bool isScaledUImm() const {
1346  return isConstantImm() &&
1347  isShiftedUInt<Bits, ShiftLeftAmount>(getConstantImm());
1348  }
1349 
1350  template <unsigned Bits, unsigned ShiftLeftAmount>
1351  bool isScaledSImm() const {
1352  if (isConstantImm() &&
1353  isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm()))
1354  return true;
1355  // Operand can also be a symbol or symbol plus
1356  // offset in case of relocations.
1357  if (Kind != k_Immediate)
1358  return false;
1359  MCValue Res;
1360  bool Success = getImm()->evaluateAsRelocatable(Res, nullptr, nullptr);
1361  return Success && isShiftedInt<Bits, ShiftLeftAmount>(Res.getConstant());
1362  }
1363 
1364  bool isRegList16() const {
1365  if (!isRegList())
1366  return false;
1367 
1368  int Size = RegList.List->size();
1369  if (Size < 2 || Size > 5)
1370  return false;
1371 
1372  unsigned R0 = RegList.List->front();
1373  unsigned R1 = RegList.List->back();
1374  if (!((R0 == Mips::S0 && R1 == Mips::RA) ||
1375  (R0 == Mips::S0_64 && R1 == Mips::RA_64)))
1376  return false;
1377 
1378  int PrevReg = *RegList.List->begin();
1379  for (int i = 1; i < Size - 1; i++) {
1380  int Reg = (*(RegList.List))[i];
1381  if ( Reg != PrevReg + 1)
1382  return false;
1383  PrevReg = Reg;
1384  }
1385 
1386  return true;
1387  }
1388 
1389  bool isInvNum() const { return Kind == k_Immediate; }
1390 
1391  bool isLSAImm() const {
1392  if (!isConstantImm())
1393  return false;
1394  int64_t Val = getConstantImm();
1395  return 1 <= Val && Val <= 4;
1396  }
1397 
1398  bool isRegList() const { return Kind == k_RegList; }
1399 
1400  StringRef getToken() const {
1401  assert(Kind == k_Token && "Invalid access!");
1402  return StringRef(Tok.Data, Tok.Length);
1403  }
1404 
1405  unsigned getReg() const override {
1406  // As a special case until we sort out the definition of div/divu, accept
1407  // $0/$zero here so that MCK_ZERO works correctly.
1408  if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
1409  RegIdx.Kind & RegKind_GPR)
1410  return getGPR32Reg(); // FIXME: GPR64 too
1411 
1412  llvm_unreachable("Invalid access!");
1413  return 0;
1414  }
1415 
1416  const MCExpr *getImm() const {
1417  assert((Kind == k_Immediate) && "Invalid access!");
1418  return Imm.Val;
1419  }
1420 
1421  int64_t getConstantImm() const {
1422  const MCExpr *Val = getImm();
1423  int64_t Value = 0;
1424  (void)Val->evaluateAsAbsolute(Value);
1425  return Value;
1426  }
1427 
1428  MipsOperand *getMemBase() const {
1429  assert((Kind == k_Memory) && "Invalid access!");
1430  return Mem.Base;
1431  }
1432 
1433  const MCExpr *getMemOff() const {
1434  assert((Kind == k_Memory) && "Invalid access!");
1435  return Mem.Off;
1436  }
1437 
1438  int64_t getConstantMemOff() const {
1439  return static_cast<const MCConstantExpr *>(getMemOff())->getValue();
1440  }
1441 
1442  const SmallVectorImpl<unsigned> &getRegList() const {
1443  assert((Kind == k_RegList) && "Invalid access!");
1444  return *(RegList.List);
1445  }
1446 
1447  static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S,
1448  MipsAsmParser &Parser) {
1449  auto Op = std::make_unique<MipsOperand>(k_Token, Parser);
1450  Op->Tok.Data = Str.data();
1451  Op->Tok.Length = Str.size();
1452  Op->StartLoc = S;
1453  Op->EndLoc = S;
1454  return Op;
1455  }
1456 
1457  /// Create a numeric register (e.g. $1). The exact register remains
1458  /// unresolved until an instruction successfully matches
1459  static std::unique_ptr<MipsOperand>
1460  createNumericReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1461  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1462  LLVM_DEBUG(dbgs() << "createNumericReg(" << Index << ", ...)\n");
1463  return CreateReg(Index, Str, RegKind_Numeric, RegInfo, S, E, Parser);
1464  }
1465 
1466  /// Create a register that is definitely a GPR.
1467  /// This is typically only used for named registers such as $gp.
1468  static std::unique_ptr<MipsOperand>
1469  createGPRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1470  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1471  return CreateReg(Index, Str, RegKind_GPR, RegInfo, S, E, Parser);
1472  }
1473 
1474  /// Create a register that is definitely a FGR.
1475  /// This is typically only used for named registers such as $f0.
1476  static std::unique_ptr<MipsOperand>
1477  createFGRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1478  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1479  return CreateReg(Index, Str, RegKind_FGR, RegInfo, S, E, Parser);
1480  }
1481 
1482  /// Create a register that is definitely a HWReg.
1483  /// This is typically only used for named registers such as $hwr_cpunum.
1484  static std::unique_ptr<MipsOperand>
1485  createHWRegsReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1486  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1487  return CreateReg(Index, Str, RegKind_HWRegs, RegInfo, S, E, Parser);
1488  }
1489 
1490  /// Create a register that is definitely an FCC.
1491  /// This is typically only used for named registers such as $fcc0.
1492  static std::unique_ptr<MipsOperand>
1493  createFCCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1494  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1495  return CreateReg(Index, Str, RegKind_FCC, RegInfo, S, E, Parser);
1496  }
1497 
1498  /// Create a register that is definitely an ACC.
1499  /// This is typically only used for named registers such as $ac0.
1500  static std::unique_ptr<MipsOperand>
1501  createACCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1502  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1503  return CreateReg(Index, Str, RegKind_ACC, RegInfo, S, E, Parser);
1504  }
1505 
1506  /// Create a register that is definitely an MSA128.
1507  /// This is typically only used for named registers such as $w0.
1508  static std::unique_ptr<MipsOperand>
1509  createMSA128Reg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1510  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1511  return CreateReg(Index, Str, RegKind_MSA128, RegInfo, S, E, Parser);
1512  }
1513 
1514  /// Create a register that is definitely an MSACtrl.
1515  /// This is typically only used for named registers such as $msaaccess.
1516  static std::unique_ptr<MipsOperand>
1517  createMSACtrlReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
1518  SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1519  return CreateReg(Index, Str, RegKind_MSACtrl, RegInfo, S, E, Parser);
1520  }
1521 
1522  static std::unique_ptr<MipsOperand>
1523  CreateImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
1524  auto Op = std::make_unique<MipsOperand>(k_Immediate, Parser);
1525  Op->Imm.Val = Val;
1526  Op->StartLoc = S;
1527  Op->EndLoc = E;
1528  return Op;
1529  }
1530 
1531  static std::unique_ptr<MipsOperand>
1532  CreateMem(std::unique_ptr<MipsOperand> Base, const MCExpr *Off, SMLoc S,
1533  SMLoc E, MipsAsmParser &Parser) {
1534  auto Op = std::make_unique<MipsOperand>(k_Memory, Parser);
1535  Op->Mem.Base = Base.release();
1536  Op->Mem.Off = Off;
1537  Op->StartLoc = S;
1538  Op->EndLoc = E;
1539  return Op;
1540  }
1541 
1542  static std::unique_ptr<MipsOperand>
1543  CreateRegList(SmallVectorImpl<unsigned> &Regs, SMLoc StartLoc, SMLoc EndLoc,
1544  MipsAsmParser &Parser) {
1545  assert(Regs.size() > 0 && "Empty list not allowed");
1546 
1547  auto Op = std::make_unique<MipsOperand>(k_RegList, Parser);
1548  Op->RegList.List = new SmallVector<unsigned, 10>(Regs.begin(), Regs.end());
1549  Op->StartLoc = StartLoc;
1550  Op->EndLoc = EndLoc;
1551  return Op;
1552  }
1553 
1554  bool isGPRZeroAsmReg() const {
1555  return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index == 0;
1556  }
1557 
1558  bool isGPRNonZeroAsmReg() const {
1559  return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index > 0 &&
1560  RegIdx.Index <= 31;
1561  }
1562 
1563  bool isGPRAsmReg() const {
1564  return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
1565  }
1566 
1567  bool isMM16AsmReg() const {
1568  if (!(isRegIdx() && RegIdx.Kind))
1569  return false;
1570  return ((RegIdx.Index >= 2 && RegIdx.Index <= 7)
1571  || RegIdx.Index == 16 || RegIdx.Index == 17);
1572 
1573  }
1574  bool isMM16AsmRegZero() const {
1575  if (!(isRegIdx() && RegIdx.Kind))
1576  return false;
1577  return (RegIdx.Index == 0 ||
1578  (RegIdx.Index >= 2 && RegIdx.Index <= 7) ||
1579  RegIdx.Index == 17);
1580  }
1581 
1582  bool isMM16AsmRegMoveP() const {
1583  if (!(isRegIdx() && RegIdx.Kind))
1584  return false;
1585  return (RegIdx.Index == 0 || (RegIdx.Index >= 2 && RegIdx.Index <= 3) ||
1586  (RegIdx.Index >= 16 && RegIdx.Index <= 20));
1587  }
1588 
1589  bool isMM16AsmRegMovePPairFirst() const {
1590  if (!(isRegIdx() && RegIdx.Kind))
1591  return false;
1592  return RegIdx.Index >= 4 && RegIdx.Index <= 6;
1593  }
1594 
1595  bool isMM16AsmRegMovePPairSecond() const {
1596  if (!(isRegIdx() && RegIdx.Kind))
1597  return false;
1598  return (RegIdx.Index == 21 || RegIdx.Index == 22 ||
1599  (RegIdx.Index >= 5 && RegIdx.Index <= 7));
1600  }
1601 
1602  bool isFGRAsmReg() const {
1603  // AFGR64 is $0-$15 but we handle this in getAFGR64()
1604  return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;
1605  }
1606 
1607  bool isStrictlyFGRAsmReg() const {
1608  // AFGR64 is $0-$15 but we handle this in getAFGR64()
1609  return isRegIdx() && RegIdx.Kind == RegKind_FGR && RegIdx.Index <= 31;
1610  }
1611 
1612  bool isHWRegsAsmReg() const {
1613  return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31;
1614  }
1615 
1616  bool isCCRAsmReg() const {
1617  return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31;
1618  }
1619 
1620  bool isFCCAsmReg() const {
1621  if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC))
1622  return false;
1623  return RegIdx.Index <= 7;
1624  }
1625 
1626  bool isACCAsmReg() const {
1627  return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
1628  }
1629 
1630  bool isCOP0AsmReg() const {
1631  return isRegIdx() && RegIdx.Kind & RegKind_COP0 && RegIdx.Index <= 31;
1632  }
1633 
1634  bool isCOP2AsmReg() const {
1635  return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
1636  }
1637 
1638  bool isCOP3AsmReg() const {
1639  return isRegIdx() && RegIdx.Kind & RegKind_COP3 && RegIdx.Index <= 31;
1640  }
1641 
1642  bool isMSA128AsmReg() const {
1643  return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;
1644  }
1645 
1646  bool isMSACtrlAsmReg() const {
1647  return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
1648  }
1649 
1650  /// getStartLoc - Get the location of the first token of this operand.
1651  SMLoc getStartLoc() const override { return StartLoc; }
1652  /// getEndLoc - Get the location of the last token of this operand.
1653  SMLoc getEndLoc() const override { return EndLoc; }
1654 
1655  void print(raw_ostream &OS) const override {
1656  switch (Kind) {
1657  case k_Immediate:
1658  OS << "Imm<";
1659  OS << *Imm.Val;
1660  OS << ">";
1661  break;
1662  case k_Memory:
1663  OS << "Mem<";
1664  Mem.Base->print(OS);
1665  OS << ", ";
1666  OS << *Mem.Off;
1667  OS << ">";
1668  break;
1669  case k_RegisterIndex:
1670  OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ", "
1671  << StringRef(RegIdx.Tok.Data, RegIdx.Tok.Length) << ">";
1672  break;
1673  case k_Token:
1674  OS << getToken();
1675  break;
1676  case k_RegList:
1677  OS << "RegList< ";
1678  for (auto Reg : (*RegList.List))
1679  OS << Reg << " ";
1680  OS << ">";
1681  break;
1682  }
1683  }
1684 
1685  bool isValidForTie(const MipsOperand &Other) const {
1686  if (Kind != Other.Kind)
1687  return false;
1688 
1689  switch (Kind) {
1690  default:
1691  llvm_unreachable("Unexpected kind");
1692  return false;
1693  case k_RegisterIndex: {
1694  StringRef Token(RegIdx.Tok.Data, RegIdx.Tok.Length);
1695  StringRef OtherToken(Other.RegIdx.Tok.Data, Other.RegIdx.Tok.Length);
1696  return Token == OtherToken;
1697  }
1698  }
1699  }
1700 }; // class MipsOperand
1701 
1702 } // end anonymous namespace
1703 
1704 namespace llvm {
1705 
1706 extern const MCInstrDesc MipsInsts[];
1707 
1708 } // end namespace llvm
1709 
1710 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
1711  return MipsInsts[Opcode];
1712 }
1713 
1714 static bool hasShortDelaySlot(MCInst &Inst) {
1715  switch (Inst.getOpcode()) {
1716  case Mips::BEQ_MM:
1717  case Mips::BNE_MM:
1718  case Mips::BLTZ_MM:
1719  case Mips::BGEZ_MM:
1720  case Mips::BLEZ_MM:
1721  case Mips::BGTZ_MM:
1722  case Mips::JRC16_MM:
1723  case Mips::JALS_MM:
1724  case Mips::JALRS_MM:
1725  case Mips::JALRS16_MM:
1726  case Mips::BGEZALS_MM:
1727  case Mips::BLTZALS_MM:
1728  return true;
1729  case Mips::J_MM:
1730  return !Inst.getOperand(0).isReg();
1731  default:
1732  return false;
1733  }
1734 }
1735 
1736 static const MCSymbol *getSingleMCSymbol(const MCExpr *Expr) {
1737  if (const MCSymbolRefExpr *SRExpr = dyn_cast<MCSymbolRefExpr>(Expr)) {
1738  return &SRExpr->getSymbol();
1739  }
1740 
1741  if (const MCBinaryExpr *BExpr = dyn_cast<MCBinaryExpr>(Expr)) {
1742  const MCSymbol *LHSSym = getSingleMCSymbol(BExpr->getLHS());
1743  const MCSymbol *RHSSym = getSingleMCSymbol(BExpr->getRHS());
1744 
1745  if (LHSSym)
1746  return LHSSym;
1747 
1748  if (RHSSym)
1749  return RHSSym;
1750 
1751  return nullptr;
1752  }
1753 
1754  if (const MCUnaryExpr *UExpr = dyn_cast<MCUnaryExpr>(Expr))
1755  return getSingleMCSymbol(UExpr->getSubExpr());
1756 
1757  return nullptr;
1758 }
1759 
1760 static unsigned countMCSymbolRefExpr(const MCExpr *Expr) {
1761  if (isa<MCSymbolRefExpr>(Expr))
1762  return 1;
1763 
1764  if (const MCBinaryExpr *BExpr = dyn_cast<MCBinaryExpr>(Expr))
1765  return countMCSymbolRefExpr(BExpr->getLHS()) +
1766  countMCSymbolRefExpr(BExpr->getRHS());
1767 
1768  if (const MCUnaryExpr *UExpr = dyn_cast<MCUnaryExpr>(Expr))
1769  return countMCSymbolRefExpr(UExpr->getSubExpr());
1770 
1771  return 0;
1772 }
1773 
1774 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
1775  MCStreamer &Out,
1776  const MCSubtargetInfo *STI) {
1777  MipsTargetStreamer &TOut = getTargetStreamer();
1778  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
1779  bool ExpandedJalSym = false;
1780 
1781  Inst.setLoc(IDLoc);
1782 
1783  if (MCID.isBranch() || MCID.isCall()) {
1784  const unsigned Opcode = Inst.getOpcode();
1785  MCOperand Offset;
1786 
1787  switch (Opcode) {
1788  default:
1789  break;
1790  case Mips::BBIT0:
1791  case Mips::BBIT032:
1792  case Mips::BBIT1:
1793  case Mips::BBIT132:
1794  assert(hasCnMips() && "instruction only valid for octeon cpus");
1796 
1797  case Mips::BEQ:
1798  case Mips::BNE:
1799  case Mips::BEQ_MM:
1800  case Mips::BNE_MM:
1801  assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
1802  Offset = Inst.getOperand(2);
1803  if (!Offset.isImm())
1804  break; // We'll deal with this situation later on when applying fixups.
1805  if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm()))
1806  return Error(IDLoc, "branch target out of range");
1807  if (OffsetToAlignment(Offset.getImm(),
1808  1LL << (inMicroMipsMode() ? 1 : 2)))
1809  return Error(IDLoc, "branch to misaligned address");
1810  break;
1811  case Mips::BGEZ:
1812  case Mips::BGTZ:
1813  case Mips::BLEZ:
1814  case Mips::BLTZ:
1815  case Mips::BGEZAL:
1816  case Mips::BLTZAL:
1817  case Mips::BC1F:
1818  case Mips::BC1T:
1819  case Mips::BGEZ_MM:
1820  case Mips::BGTZ_MM:
1821  case Mips::BLEZ_MM:
1822  case Mips::BLTZ_MM:
1823  case Mips::BGEZAL_MM:
1824  case Mips::BLTZAL_MM:
1825  case Mips::BC1F_MM:
1826  case Mips::BC1T_MM:
1827  case Mips::BC1EQZC_MMR6:
1828  case Mips::BC1NEZC_MMR6:
1829  case Mips::BC2EQZC_MMR6:
1830  case Mips::BC2NEZC_MMR6:
1831  assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
1832  Offset = Inst.getOperand(1);
1833  if (!Offset.isImm())
1834  break; // We'll deal with this situation later on when applying fixups.
1835  if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm()))
1836  return Error(IDLoc, "branch target out of range");
1837  if (OffsetToAlignment(Offset.getImm(),
1838  1LL << (inMicroMipsMode() ? 1 : 2)))
1839  return Error(IDLoc, "branch to misaligned address");
1840  break;
1841  case Mips::BGEC: case Mips::BGEC_MMR6:
1842  case Mips::BLTC: case Mips::BLTC_MMR6:
1843  case Mips::BGEUC: case Mips::BGEUC_MMR6:
1844  case Mips::BLTUC: case Mips::BLTUC_MMR6:
1845  case Mips::BEQC: case Mips::BEQC_MMR6:
1846  case Mips::BNEC: case Mips::BNEC_MMR6:
1847  assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
1848  Offset = Inst.getOperand(2);
1849  if (!Offset.isImm())
1850  break; // We'll deal with this situation later on when applying fixups.
1851  if (!isIntN(18, Offset.getImm()))
1852  return Error(IDLoc, "branch target out of range");
1853  if (OffsetToAlignment(Offset.getImm(), 1LL << 2))
1854  return Error(IDLoc, "branch to misaligned address");
1855  break;
1856  case Mips::BLEZC: case Mips::BLEZC_MMR6:
1857  case Mips::BGEZC: case Mips::BGEZC_MMR6:
1858  case Mips::BGTZC: case Mips::BGTZC_MMR6:
1859  case Mips::BLTZC: case Mips::BLTZC_MMR6:
1860  assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
1861  Offset = Inst.getOperand(1);
1862  if (!Offset.isImm())
1863  break; // We'll deal with this situation later on when applying fixups.
1864  if (!isIntN(18, Offset.getImm()))
1865  return Error(IDLoc, "branch target out of range");
1866  if (OffsetToAlignment(Offset.getImm(), 1LL << 2))
1867  return Error(IDLoc, "branch to misaligned address");
1868  break;
1869  case Mips::BEQZC: case Mips::BEQZC_MMR6:
1870  case Mips::BNEZC: case Mips::BNEZC_MMR6:
1871  assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
1872  Offset = Inst.getOperand(1);
1873  if (!Offset.isImm())
1874  break; // We'll deal with this situation later on when applying fixups.
1875  if (!isIntN(23, Offset.getImm()))
1876  return Error(IDLoc, "branch target out of range");
1877  if (OffsetToAlignment(Offset.getImm(), 1LL << 2))
1878  return Error(IDLoc, "branch to misaligned address");
1879  break;
1880  case Mips::BEQZ16_MM:
1881  case Mips::BEQZC16_MMR6:
1882  case Mips::BNEZ16_MM:
1883  case Mips::BNEZC16_MMR6:
1884  assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
1885  Offset = Inst.getOperand(1);
1886  if (!Offset.isImm())
1887  break; // We'll deal with this situation later on when applying fixups.
1888  if (!isInt<8>(Offset.getImm()))
1889  return Error(IDLoc, "branch target out of range");
1890  if (OffsetToAlignment(Offset.getImm(), 2LL))
1891  return Error(IDLoc, "branch to misaligned address");
1892  break;
1893  }
1894  }
1895 
1896  // SSNOP is deprecated on MIPS32r6/MIPS64r6
1897  // We still accept it but it is a normal nop.
1898  if (hasMips32r6() && Inst.getOpcode() == Mips::SSNOP) {
1899  std::string ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
1900  Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a "
1901  "nop instruction");
1902  }
1903 
1904  if (hasCnMips()) {
1905  const unsigned Opcode = Inst.getOpcode();
1906  MCOperand Opnd;
1907  int Imm;
1908 
1909  switch (Opcode) {
1910  default:
1911  break;
1912 
1913  case Mips::BBIT0:
1914  case Mips::BBIT032:
1915  case Mips::BBIT1:
1916  case Mips::BBIT132:
1917  assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
1918  // The offset is handled above
1919  Opnd = Inst.getOperand(1);
1920  if (!Opnd.isImm())
1921  return Error(IDLoc, "expected immediate operand kind");
1922  Imm = Opnd.getImm();
1923  if (Imm < 0 || Imm > (Opcode == Mips::BBIT0 ||
1924  Opcode == Mips::BBIT1 ? 63 : 31))
1925  return Error(IDLoc, "immediate operand value out of range");
1926  if (Imm > 31) {
1927  Inst.setOpcode(Opcode == Mips::BBIT0 ? Mips::BBIT032
1928  : Mips::BBIT132);
1929  Inst.getOperand(1).setImm(Imm - 32);
1930  }
1931  break;
1932 
1933  case Mips::SEQi:
1934  case Mips::SNEi:
1935  assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
1936  Opnd = Inst.getOperand(2);
1937  if (!Opnd.isImm())
1938  return Error(IDLoc, "expected immediate operand kind");
1939  Imm = Opnd.getImm();
1940  if (!isInt<10>(Imm))
1941  return Error(IDLoc, "immediate operand value out of range");
1942  break;
1943  }
1944  }
1945 
1946  // Warn on division by zero. We're checking here as all instructions get
1947  // processed here, not just the macros that need expansion.
1948  //
1949  // The MIPS backend models most of the divison instructions and macros as
1950  // three operand instructions. The pre-R6 divide instructions however have
1951  // two operands and explicitly define HI/LO as part of the instruction,
1952  // not in the operands.
1953  unsigned FirstOp = 1;
1954  unsigned SecondOp = 2;
1955  switch (Inst.getOpcode()) {
1956  default:
1957  break;
1958  case Mips::SDivIMacro:
1959  case Mips::UDivIMacro:
1960  case Mips::DSDivIMacro:
1961  case Mips::DUDivIMacro:
1962  if (Inst.getOperand(2).getImm() == 0) {
1963  if (Inst.getOperand(1).getReg() == Mips::ZERO ||
1964  Inst.getOperand(1).getReg() == Mips::ZERO_64)
1965  Warning(IDLoc, "dividing zero by zero");
1966  else
1967  Warning(IDLoc, "division by zero");
1968  }
1969  break;
1970  case Mips::DSDIV:
1971  case Mips::SDIV:
1972  case Mips::UDIV:
1973  case Mips::DUDIV:
1974  case Mips::UDIV_MM:
1975  case Mips::SDIV_MM:
1976  FirstOp = 0;
1977  SecondOp = 1;
1979  case Mips::SDivMacro:
1980  case Mips::DSDivMacro:
1981  case Mips::UDivMacro:
1982  case Mips::DUDivMacro:
1983  case Mips::DIV:
1984  case Mips::DIVU:
1985  case Mips::DDIV:
1986  case Mips::DDIVU:
1987  case Mips::DIVU_MMR6:
1988  case Mips::DIV_MMR6:
1989  if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO ||
1990  Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) {
1991  if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO ||
1992  Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64)
1993  Warning(IDLoc, "dividing zero by zero");
1994  else
1995  Warning(IDLoc, "division by zero");
1996  }
1997  break;
1998  }
1999 
2000  // For PIC code convert unconditional jump to unconditional branch.
2001  if ((Inst.getOpcode() == Mips::J || Inst.getOpcode() == Mips::J_MM) &&
2002  inPicMode()) {
2003  MCInst BInst;
2004  BInst.setOpcode(inMicroMipsMode() ? Mips::BEQ_MM : Mips::BEQ);
2005  BInst.addOperand(MCOperand::createReg(Mips::ZERO));
2006  BInst.addOperand(MCOperand::createReg(Mips::ZERO));
2007  BInst.addOperand(Inst.getOperand(0));
2008  Inst = BInst;
2009  }
2010 
2011  // This expansion is not in a function called by tryExpandInstruction()
2012  // because the pseudo-instruction doesn't have a distinct opcode.
2013  if ((Inst.getOpcode() == Mips::JAL || Inst.getOpcode() == Mips::JAL_MM) &&
2014  inPicMode()) {
2015  warnIfNoMacro(IDLoc);
2016 
2017  const MCExpr *JalExpr = Inst.getOperand(0).getExpr();
2018 
2019  // We can do this expansion if there's only 1 symbol in the argument
2020  // expression.
2021  if (countMCSymbolRefExpr(JalExpr) > 1)
2022  return Error(IDLoc, "jal doesn't support multiple symbols in PIC mode");
2023 
2024  // FIXME: This is checking the expression can be handled by the later stages
2025  // of the assembler. We ought to leave it to those later stages.
2026  const MCSymbol *JalSym = getSingleMCSymbol(JalExpr);
2027 
2028  // FIXME: Add support for label+offset operands (currently causes an error).
2029  // FIXME: Add support for forward-declared local symbols.
2030  // FIXME: Add expansion for when the LargeGOT option is enabled.
2031  if (JalSym->isInSection() || JalSym->isTemporary() ||
2032  (JalSym->isELF() &&
2033  cast<MCSymbolELF>(JalSym)->getBinding() == ELF::STB_LOCAL)) {
2034  if (isABI_O32()) {
2035  // If it's a local symbol and the O32 ABI is being used, we expand to:
2036  // lw $25, 0($gp)
2037  // R_(MICRO)MIPS_GOT16 label
2038  // addiu $25, $25, 0
2039  // R_(MICRO)MIPS_LO16 label
2040  // jalr $25
2041  const MCExpr *Got16RelocExpr =
2042  MipsMCExpr::create(MipsMCExpr::MEK_GOT, JalExpr, getContext());
2043  const MCExpr *Lo16RelocExpr =
2044  MipsMCExpr::create(MipsMCExpr::MEK_LO, JalExpr, getContext());
2045 
2046  TOut.emitRRX(Mips::LW, Mips::T9, GPReg,
2047  MCOperand::createExpr(Got16RelocExpr), IDLoc, STI);
2048  TOut.emitRRX(Mips::ADDiu, Mips::T9, Mips::T9,
2049  MCOperand::createExpr(Lo16RelocExpr), IDLoc, STI);
2050  } else if (isABI_N32() || isABI_N64()) {
2051  // If it's a local symbol and the N32/N64 ABIs are being used,
2052  // we expand to:
2053  // lw/ld $25, 0($gp)
2054  // R_(MICRO)MIPS_GOT_DISP label
2055  // jalr $25
2056  const MCExpr *GotDispRelocExpr =
2057  MipsMCExpr::create(MipsMCExpr::MEK_GOT_DISP, JalExpr, getContext());
2058 
2059  TOut.emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9,
2060  GPReg, MCOperand::createExpr(GotDispRelocExpr), IDLoc,
2061  STI);
2062  }
2063  } else {
2064  // If it's an external/weak symbol, we expand to:
2065  // lw/ld $25, 0($gp)
2066  // R_(MICRO)MIPS_CALL16 label
2067  // jalr $25
2068  const MCExpr *Call16RelocExpr =
2069  MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, JalExpr, getContext());
2070 
2071  TOut.emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, GPReg,
2072  MCOperand::createExpr(Call16RelocExpr), IDLoc, STI);
2073  }
2074 
2075  MCInst JalrInst;
2076  if (IsCpRestoreSet && inMicroMipsMode())
2077  JalrInst.setOpcode(Mips::JALRS_MM);
2078  else
2079  JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR);
2081  JalrInst.addOperand(MCOperand::createReg(Mips::T9));
2082 
2083  if (EmitJalrReloc) {
2084  // As an optimization hint for the linker, before the JALR we add:
2085  // .reloc tmplabel, R_{MICRO}MIPS_JALR, symbol
2086  // tmplabel:
2087  MCSymbol *TmpLabel = getContext().createTempSymbol();
2088  const MCExpr *TmpExpr = MCSymbolRefExpr::create(TmpLabel, getContext());
2089  const MCExpr *RelocJalrExpr =
2091  getContext(), IDLoc);
2092 
2093  TOut.getStreamer().EmitRelocDirective(*TmpExpr,
2094  inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR",
2095  RelocJalrExpr, IDLoc, *STI);
2096  TOut.getStreamer().EmitLabel(TmpLabel);
2097  }
2098 
2099  Inst = JalrInst;
2100  ExpandedJalSym = true;
2101  }
2102 
2103  bool IsPCRelativeLoad = (MCID.TSFlags & MipsII::IsPCRelativeLoad) != 0;
2104  if ((MCID.mayLoad() || MCID.mayStore()) && !IsPCRelativeLoad) {
2105  // Check the offset of memory operand, if it is a symbol
2106  // reference or immediate we may have to expand instructions.
2107  for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
2108  const MCOperandInfo &OpInfo = MCID.OpInfo[i];
2109  if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
2110  (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
2111  MCOperand &Op = Inst.getOperand(i);
2112  if (Op.isImm()) {
2113  int64_t MemOffset = Op.getImm();
2114  if (MemOffset < -32768 || MemOffset > 32767) {
2115  // Offset can't exceed 16bit value.
2116  expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad());
2117  return getParser().hasPendingError();
2118  }
2119  } else if (Op.isExpr()) {
2120  const MCExpr *Expr = Op.getExpr();
2121  if (Expr->getKind() == MCExpr::SymbolRef) {
2122  const MCSymbolRefExpr *SR =
2123  static_cast<const MCSymbolRefExpr *>(Expr);
2124  if (SR->getKind() == MCSymbolRefExpr::VK_None) {
2125  // Expand symbol.
2126  expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad());
2127  return getParser().hasPendingError();
2128  }
2129  } else if (!isEvaluated(Expr)) {
2130  expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad());
2131  return getParser().hasPendingError();
2132  }
2133  }
2134  }
2135  } // for
2136  } // if load/store
2137 
2138  if (inMicroMipsMode()) {
2139  if (MCID.mayLoad() && Inst.getOpcode() != Mips::LWP_MM) {
2140  // Try to create 16-bit GP relative load instruction.
2141  for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
2142  const MCOperandInfo &OpInfo = MCID.OpInfo[i];
2143  if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
2144  (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
2145  MCOperand &Op = Inst.getOperand(i);
2146  if (Op.isImm()) {
2147  int MemOffset = Op.getImm();
2148  MCOperand &DstReg = Inst.getOperand(0);
2149  MCOperand &BaseReg = Inst.getOperand(1);
2150  if (isInt<9>(MemOffset) && (MemOffset % 4 == 0) &&
2151  getContext().getRegisterInfo()->getRegClass(
2152  Mips::GPRMM16RegClassID).contains(DstReg.getReg()) &&
2153  (BaseReg.getReg() == Mips::GP ||
2154  BaseReg.getReg() == Mips::GP_64)) {
2155 
2156  TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset,
2157  IDLoc, STI);
2158  return false;
2159  }
2160  }
2161  }
2162  } // for
2163  } // if load
2164 
2165  // TODO: Handle this with the AsmOperandClass.PredicateMethod.
2166 
2167  MCOperand Opnd;
2168  int Imm;
2169 
2170  switch (Inst.getOpcode()) {
2171  default:
2172  break;
2173  case Mips::ADDIUSP_MM:
2174  Opnd = Inst.getOperand(0);
2175  if (!Opnd.isImm())
2176  return Error(IDLoc, "expected immediate operand kind");
2177  Imm = Opnd.getImm();
2178  if (Imm < -1032 || Imm > 1028 || (Imm < 8 && Imm > -12) ||
2179  Imm % 4 != 0)
2180  return Error(IDLoc, "immediate operand value out of range");
2181  break;
2182  case Mips::SLL16_MM:
2183  case Mips::SRL16_MM:
2184  Opnd = Inst.getOperand(2);
2185  if (!Opnd.isImm())
2186  return Error(IDLoc, "expected immediate operand kind");
2187  Imm = Opnd.getImm();
2188  if (Imm < 1 || Imm > 8)
2189  return Error(IDLoc, "immediate operand value out of range");
2190  break;
2191  case Mips::LI16_MM:
2192  Opnd = Inst.getOperand(1);
2193  if (!Opnd.isImm())
2194  return Error(IDLoc, "expected immediate operand kind");
2195  Imm = Opnd.getImm();
2196  if (Imm < -1 || Imm > 126)
2197  return Error(IDLoc, "immediate operand value out of range");
2198  break;
2199  case Mips::ADDIUR2_MM:
2200  Opnd = Inst.getOperand(2);
2201  if (!Opnd.isImm())
2202  return Error(IDLoc, "expected immediate operand kind");
2203  Imm = Opnd.getImm();
2204  if (!(Imm == 1 || Imm == -1 ||
2205  ((Imm % 4 == 0) && Imm < 28 && Imm > 0)))
2206  return Error(IDLoc, "immediate operand value out of range");
2207  break;
2208  case Mips::ANDI16_MM:
2209  Opnd = Inst.getOperand(2);
2210  if (!Opnd.isImm())
2211  return Error(IDLoc, "expected immediate operand kind");
2212  Imm = Opnd.getImm();
2213  if (!(Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
2214  Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
2215  Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535))
2216  return Error(IDLoc, "immediate operand value out of range");
2217  break;
2218  case Mips::LBU16_MM:
2219  Opnd = Inst.getOperand(2);
2220  if (!Opnd.isImm())
2221  return Error(IDLoc, "expected immediate operand kind");
2222  Imm = Opnd.getImm();
2223  if (Imm < -1 || Imm > 14)
2224  return Error(IDLoc, "immediate operand value out of range");
2225  break;
2226  case Mips::SB16_MM:
2227  case Mips::SB16_MMR6:
2228  Opnd = Inst.getOperand(2);
2229  if (!Opnd.isImm())
2230  return Error(IDLoc, "expected immediate operand kind");
2231  Imm = Opnd.getImm();
2232  if (Imm < 0 || Imm > 15)
2233  return Error(IDLoc, "immediate operand value out of range");
2234  break;
2235  case Mips::LHU16_MM:
2236  case Mips::SH16_MM:
2237  case Mips::SH16_MMR6:
2238  Opnd = Inst.getOperand(2);
2239  if (!Opnd.isImm())
2240  return Error(IDLoc, "expected immediate operand kind");
2241  Imm = Opnd.getImm();
2242  if (Imm < 0 || Imm > 30 || (Imm % 2 != 0))
2243  return Error(IDLoc, "immediate operand value out of range");
2244  break;
2245  case Mips::LW16_MM:
2246  case Mips::SW16_MM:
2247  case Mips::SW16_MMR6:
2248  Opnd = Inst.getOperand(2);
2249  if (!Opnd.isImm())
2250  return Error(IDLoc, "expected immediate operand kind");
2251  Imm = Opnd.getImm();
2252  if (Imm < 0 || Imm > 60 || (Imm % 4 != 0))
2253  return Error(IDLoc, "immediate operand value out of range");
2254  break;
2255  case Mips::ADDIUPC_MM:
2256  Opnd = Inst.getOperand(1);
2257  if (!Opnd.isImm())
2258  return Error(IDLoc, "expected immediate operand kind");
2259  Imm = Opnd.getImm();
2260  if ((Imm % 4 != 0) || !isInt<25>(Imm))
2261  return Error(IDLoc, "immediate operand value out of range");
2262  break;
2263  case Mips::LWP_MM:
2264  case Mips::SWP_MM:
2265  if (Inst.getOperand(0).getReg() == Mips::RA)
2266  return Error(IDLoc, "invalid operand for instruction");
2267  break;
2268  case Mips::MOVEP_MM:
2269  case Mips::MOVEP_MMR6: {
2270  unsigned R0 = Inst.getOperand(0).getReg();
2271  unsigned R1 = Inst.getOperand(1).getReg();
2272  bool RegPair = ((R0 == Mips::A1 && R1 == Mips::A2) ||
2273  (R0 == Mips::A1 && R1 == Mips::A3) ||
2274  (R0 == Mips::A2 && R1 == Mips::A3) ||
2275  (R0 == Mips::A0 && R1 == Mips::S5) ||
2276  (R0 == Mips::A0 && R1 == Mips::S6) ||
2277  (R0 == Mips::A0 && R1 == Mips::A1) ||
2278  (R0 == Mips::A0 && R1 == Mips::A2) ||
2279  (R0 == Mips::A0 && R1 == Mips::A3));
2280  if (!RegPair)
2281  return Error(IDLoc, "invalid operand for instruction");
2282  break;
2283  }
2284  }
2285  }
2286 
2287  bool FillDelaySlot =
2288  MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder();
2289  if (FillDelaySlot)
2291 
2292  MacroExpanderResultTy ExpandResult =
2293  tryExpandInstruction(Inst, IDLoc, Out, STI);
2294  switch (ExpandResult) {
2295  case MER_NotAMacro:
2296  Out.EmitInstruction(Inst, *STI);
2297  break;
2298  case MER_Success:
2299  break;
2300  case MER_Fail:
2301  return true;
2302  }
2303 
2304  // We know we emitted an instruction on the MER_NotAMacro or MER_Success path.
2305  // If we're in microMIPS mode then we must also set EF_MIPS_MICROMIPS.
2306  if (inMicroMipsMode()) {
2307  TOut.setUsesMicroMips();
2308  TOut.updateABIInfo(*this);
2309  }
2310 
2311  // If this instruction has a delay slot and .set reorder is active,
2312  // emit a NOP after it.
2313  if (FillDelaySlot) {
2314  TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, STI);
2315  TOut.emitDirectiveSetReorder();
2316  }
2317 
2318  if ((Inst.getOpcode() == Mips::JalOneReg ||
2319  Inst.getOpcode() == Mips::JalTwoReg || ExpandedJalSym) &&
2320  isPicAndNotNxxAbi()) {
2321  if (IsCpRestoreSet) {
2322  // We need a NOP between the JALR and the LW:
2323  // If .set reorder has been used, we've already emitted a NOP.
2324  // If .set noreorder has been used, we need to emit a NOP at this point.
2325  if (!AssemblerOptions.back()->isReorder())
2326  TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc,
2327  STI);
2328 
2329  // Load the $gp from the stack.
2330  TOut.emitGPRestore(CpRestoreOffset, IDLoc, STI);
2331  } else
2332  Warning(IDLoc, "no .cprestore used in PIC mode");
2333  }
2334 
2335  return false;
2336 }
2337 
2338 MipsAsmParser::MacroExpanderResultTy
2339 MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
2340  const MCSubtargetInfo *STI) {
2341  switch (Inst.getOpcode()) {
2342  default:
2343  return MER_NotAMacro;
2344  case Mips::LoadImm32:
2345  return expandLoadImm(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2346  case Mips::LoadImm64:
2347  return expandLoadImm(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2348  case Mips::LoadAddrImm32:
2349  case Mips::LoadAddrImm64:
2350  assert(Inst.getOperand(0).isReg() && "expected register operand kind");
2351  assert((Inst.getOperand(1).isImm() || Inst.getOperand(1).isExpr()) &&
2352  "expected immediate operand kind");
2353 
2354  return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister,
2355  Inst.getOperand(1),
2356  Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc,
2357  Out, STI)
2358  ? MER_Fail
2359  : MER_Success;
2360  case Mips::LoadAddrReg32:
2361  case Mips::LoadAddrReg64:
2362  assert(Inst.getOperand(0).isReg() && "expected register operand kind");
2363  assert(Inst.getOperand(1).isReg() && "expected register operand kind");
2364  assert((Inst.getOperand(2).isImm() || Inst.getOperand(2).isExpr()) &&
2365  "expected immediate operand kind");
2366 
2367  return expandLoadAddress(Inst.getOperand(0).getReg(),
2368  Inst.getOperand(1).getReg(), Inst.getOperand(2),
2369  Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc,
2370  Out, STI)
2371  ? MER_Fail
2372  : MER_Success;
2373  case Mips::B_MM_Pseudo:
2374  case Mips::B_MMR6_Pseudo:
2375  return expandUncondBranchMMPseudo(Inst, IDLoc, Out, STI) ? MER_Fail
2376  : MER_Success;
2377  case Mips::SWM_MM:
2378  case Mips::LWM_MM:
2379  return expandLoadStoreMultiple(Inst, IDLoc, Out, STI) ? MER_Fail
2380  : MER_Success;
2381  case Mips::JalOneReg:
2382  case Mips::JalTwoReg:
2383  return expandJalWithRegs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2384  case Mips::BneImm:
2385  case Mips::BeqImm:
2386  case Mips::BEQLImmMacro:
2387  case Mips::BNELImmMacro:
2388  return expandBranchImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2389  case Mips::BLT:
2390  case Mips::BLE:
2391  case Mips::BGE:
2392  case Mips::BGT:
2393  case Mips::BLTU:
2394  case Mips::BLEU:
2395  case Mips::BGEU:
2396  case Mips::BGTU:
2397  case Mips::BLTL:
2398  case Mips::BLEL:
2399  case Mips::BGEL:
2400  case Mips::BGTL:
2401  case Mips::BLTUL:
2402  case Mips::BLEUL:
2403  case Mips::BGEUL:
2404  case Mips::BGTUL:
2405  case Mips::BLTImmMacro:
2406  case Mips::BLEImmMacro:
2407  case Mips::BGEImmMacro:
2408  case Mips::BGTImmMacro:
2409  case Mips::BLTUImmMacro:
2410  case Mips::BLEUImmMacro:
2411  case Mips::BGEUImmMacro:
2412  case Mips::BGTUImmMacro:
2413  case Mips::BLTLImmMacro:
2414  case Mips::BLELImmMacro:
2415  case Mips::BGELImmMacro:
2416  case Mips::BGTLImmMacro:
2417  case Mips::BLTULImmMacro:
2418  case Mips::BLEULImmMacro:
2419  case Mips::BGEULImmMacro:
2420  case Mips::BGTULImmMacro:
2421  return expandCondBranches(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2422  case Mips::SDivMacro:
2423  case Mips::SDivIMacro:
2424  case Mips::SRemMacro:
2425  case Mips::SRemIMacro:
2426  return expandDivRem(Inst, IDLoc, Out, STI, false, true) ? MER_Fail
2427  : MER_Success;
2428  case Mips::DSDivMacro:
2429  case Mips::DSDivIMacro:
2430  case Mips::DSRemMacro:
2431  case Mips::DSRemIMacro:
2432  return expandDivRem(Inst, IDLoc, Out, STI, true, true) ? MER_Fail
2433  : MER_Success;
2434  case Mips::UDivMacro:
2435  case Mips::UDivIMacro:
2436  case Mips::URemMacro:
2437  case Mips::URemIMacro:
2438  return expandDivRem(Inst, IDLoc, Out, STI, false, false) ? MER_Fail
2439  : MER_Success;
2440  case Mips::DUDivMacro:
2441  case Mips::DUDivIMacro:
2442  case Mips::DURemMacro:
2443  case Mips::DURemIMacro:
2444  return expandDivRem(Inst, IDLoc, Out, STI, true, false) ? MER_Fail
2445  : MER_Success;
2446  case Mips::PseudoTRUNC_W_S:
2447  return expandTrunc(Inst, false, false, IDLoc, Out, STI) ? MER_Fail
2448  : MER_Success;
2449  case Mips::PseudoTRUNC_W_D32:
2450  return expandTrunc(Inst, true, false, IDLoc, Out, STI) ? MER_Fail
2451  : MER_Success;
2452  case Mips::PseudoTRUNC_W_D:
2453  return expandTrunc(Inst, true, true, IDLoc, Out, STI) ? MER_Fail
2454  : MER_Success;
2455 
2456  case Mips::LoadImmSingleGPR:
2457  return expandLoadImmReal(Inst, true, true, false, IDLoc, Out, STI)
2458  ? MER_Fail
2459  : MER_Success;
2460  case Mips::LoadImmSingleFGR:
2461  return expandLoadImmReal(Inst, true, false, false, IDLoc, Out, STI)
2462  ? MER_Fail
2463  : MER_Success;
2464  case Mips::LoadImmDoubleGPR:
2465  return expandLoadImmReal(Inst, false, true, false, IDLoc, Out, STI)
2466  ? MER_Fail
2467  : MER_Success;
2468  case Mips::LoadImmDoubleFGR:
2469  return expandLoadImmReal(Inst, false, false, true, IDLoc, Out, STI)
2470  ? MER_Fail
2471  : MER_Success;
2472  case Mips::LoadImmDoubleFGR_32:
2473  return expandLoadImmReal(Inst, false, false, false, IDLoc, Out, STI)
2474  ? MER_Fail
2475  : MER_Success;
2476  case Mips::Ulh:
2477  return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2478  case Mips::Ulhu:
2479  return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2480  case Mips::Ush:
2481  return expandUsh(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2482  case Mips::Ulw:
2483  case Mips::Usw:
2484  return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2485  case Mips::NORImm:
2486  case Mips::NORImm64:
2487  return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2488  case Mips::SGE:
2489  case Mips::SGEU:
2490  return expandSge(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2491  case Mips::SGEImm:
2492  case Mips::SGEUImm:
2493  case Mips::SGEImm64:
2494  case Mips::SGEUImm64:
2495  return expandSgeImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2496  case Mips::SGTImm:
2497  case Mips::SGTUImm:
2498  case Mips::SGTImm64:
2499  case Mips::SGTUImm64:
2500  return expandSgtImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2501  case Mips::SLTImm64:
2502  if (isInt<16>(Inst.getOperand(2).getImm())) {
2503  Inst.setOpcode(Mips::SLTi64);
2504  return MER_NotAMacro;
2505  }
2506  return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2507  case Mips::SLTUImm64:
2508  if (isInt<16>(Inst.getOperand(2).getImm())) {
2509  Inst.setOpcode(Mips::SLTiu64);
2510  return MER_NotAMacro;
2511  }
2512  return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2513  case Mips::ADDi: case Mips::ADDi_MM:
2514  case Mips::ADDiu: case Mips::ADDiu_MM:
2515  case Mips::SLTi: case Mips::SLTi_MM:
2516  case Mips::SLTiu: case Mips::SLTiu_MM:
2517  if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
2518  Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
2519  int64_t ImmValue = Inst.getOperand(2).getImm();
2520  if (isInt<16>(ImmValue))
2521  return MER_NotAMacro;
2522  return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail
2523  : MER_Success;
2524  }
2525  return MER_NotAMacro;
2526  case Mips::ANDi: case Mips::ANDi_MM: case Mips::ANDi64:
2527  case Mips::ORi: case Mips::ORi_MM: case Mips::ORi64:
2528  case Mips::XORi: case Mips::XORi_MM: case Mips::XORi64:
2529  if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
2530  Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
2531  int64_t ImmValue = Inst.getOperand(2).getImm();
2532  if (isUInt<16>(ImmValue))
2533  return MER_NotAMacro;
2534  return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail
2535  : MER_Success;
2536  }
2537  return MER_NotAMacro;
2538  case Mips::ROL:
2539  case Mips::ROR:
2540  return expandRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2541  case Mips::ROLImm:
2542  case Mips::RORImm:
2543  return expandRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2544  case Mips::DROL:
2545  case Mips::DROR:
2546  return expandDRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2547  case Mips::DROLImm:
2548  case Mips::DRORImm:
2549  return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2550  case Mips::ABSMacro:
2551  return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2552  case Mips::MULImmMacro:
2553  case Mips::DMULImmMacro:
2554  return expandMulImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2555  case Mips::MULOMacro:
2556  case Mips::DMULOMacro:
2557  return expandMulO(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2558  case Mips::MULOUMacro:
2559  case Mips::DMULOUMacro:
2560  return expandMulOU(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2561  case Mips::DMULMacro:
2562  return expandDMULMacro(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2563  case Mips::LDMacro:
2564  case Mips::SDMacro:
2565  return expandLoadStoreDMacro(Inst, IDLoc, Out, STI,
2566  Inst.getOpcode() == Mips::LDMacro)
2567  ? MER_Fail
2568  : MER_Success;
2569  case Mips::SDC1_M1:
2570  return expandStoreDM1Macro(Inst, IDLoc, Out, STI)
2571  ? MER_Fail
2572  : MER_Success;
2573  case Mips::SEQMacro:
2574  return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2575  case Mips::SEQIMacro:
2576  return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2577  case Mips::MFTC0: case Mips::MTTC0:
2578  case Mips::MFTGPR: case Mips::MTTGPR:
2579  case Mips::MFTLO: case Mips::MTTLO:
2580  case Mips::MFTHI: case Mips::MTTHI:
2581  case Mips::MFTACX: case Mips::MTTACX:
2582  case Mips::MFTDSP: case Mips::MTTDSP:
2583  case Mips::MFTC1: case Mips::MTTC1:
2584  case Mips::MFTHC1: case Mips::MTTHC1:
2585  case Mips::CFTC1: case Mips::CTTC1:
2586  return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
2587  }
2588 }
2589 
2590 bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
2591  MCStreamer &Out,
2592  const MCSubtargetInfo *STI) {
2593  MipsTargetStreamer &TOut = getTargetStreamer();
2594 
2595  // Create a JALR instruction which is going to replace the pseudo-JAL.
2596  MCInst JalrInst;
2597  JalrInst.setLoc(IDLoc);
2598  const MCOperand FirstRegOp = Inst.getOperand(0);
2599  const unsigned Opcode = Inst.getOpcode();
2600 
2601  if (Opcode == Mips::JalOneReg) {
2602  // jal $rs => jalr $rs
2603  if (IsCpRestoreSet && inMicroMipsMode()) {
2604  JalrInst.setOpcode(Mips::JALRS16_MM);
2605  JalrInst.addOperand(FirstRegOp);
2606  } else if (inMicroMipsMode()) {
2607  JalrInst.setOpcode(hasMips32r6() ? Mips::JALRC16_MMR6 : Mips::JALR16_MM);
2608  JalrInst.addOperand(FirstRegOp);
2609  } else {
2610  JalrInst.setOpcode(Mips::JALR);
2612  JalrInst.addOperand(FirstRegOp);
2613  }
2614  } else if (Opcode == Mips::JalTwoReg) {
2615  // jal $rd, $rs => jalr $rd, $rs
2616  if (IsCpRestoreSet && inMicroMipsMode())
2617  JalrInst.setOpcode(Mips::JALRS_MM);
2618  else
2619  JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR);
2620  JalrInst.addOperand(FirstRegOp);
2621  const MCOperand SecondRegOp = Inst.getOperand(1);
2622  JalrInst.addOperand(SecondRegOp);
2623  }
2624  Out.EmitInstruction(JalrInst, *STI);
2625 
2626  // If .set reorder is active and branch instruction has a delay slot,
2627  // emit a NOP after it.
2628  const MCInstrDesc &MCID = getInstDesc(JalrInst.getOpcode());
2629  if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
2630  TOut.emitEmptyDelaySlot(hasShortDelaySlot(JalrInst), IDLoc,
2631  STI);
2632 
2633  return false;
2634 }
2635 
2636 /// Can the value be represented by a unsigned N-bit value and a shift left?
2637 template <unsigned N> static bool isShiftedUIntAtAnyPosition(uint64_t x) {
2638  unsigned BitNum = findFirstSet(x);
2639 
2640  return (x == x >> BitNum << BitNum) && isUInt<N>(x >> BitNum);
2641 }
2642 
2643 /// Load (or add) an immediate into a register.
2644 ///
2645 /// @param ImmValue The immediate to load.
2646 /// @param DstReg The register that will hold the immediate.
2647 /// @param SrcReg A register to add to the immediate or Mips::NoRegister
2648 /// for a simple initialization.
2649 /// @param Is32BitImm Is ImmValue 32-bit or 64-bit?
2650 /// @param IsAddress True if the immediate represents an address. False if it
2651 /// is an integer.
2652 /// @param IDLoc Location of the immediate in the source file.
2653 bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
2654  unsigned SrcReg, bool Is32BitImm,
2655  bool IsAddress, SMLoc IDLoc, MCStreamer &Out,
2656  const MCSubtargetInfo *STI) {
2657  MipsTargetStreamer &TOut = getTargetStreamer();
2658 
2659  if (!Is32BitImm && !isGP64bit()) {
2660  Error(IDLoc, "instruction requires a 64-bit architecture");
2661  return true;
2662  }
2663 
2664  if (Is32BitImm) {
2665  if (isInt<32>(ImmValue) || isUInt<32>(ImmValue)) {
2666  // Sign extend up to 64-bit so that the predicates match the hardware
2667  // behaviour. In particular, isInt<16>(0xffff8000) and similar should be
2668  // true.
2669  ImmValue = SignExtend64<32>(ImmValue);
2670  } else {
2671  Error(IDLoc, "instruction requires a 32-bit immediate");
2672  return true;
2673  }
2674  }
2675 
2676  unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg();
2677  unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu;
2678 
2679  bool UseSrcReg = false;
2680  if (SrcReg != Mips::NoRegister)
2681  UseSrcReg = true;
2682 
2683  unsigned TmpReg = DstReg;
2684  if (UseSrcReg &&
2685  getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) {
2686  // At this point we need AT to perform the expansions and we exit if it is
2687  // not available.
2688  unsigned ATReg = getATReg(IDLoc);
2689  if (!ATReg)
2690  return true;
2691  TmpReg = ATReg;
2692  }
2693 
2694  if (isInt<16>(ImmValue)) {
2695  if (!UseSrcReg)
2696  SrcReg = ZeroReg;
2697 
2698  // This doesn't quite follow the usual ABI expectations for N32 but matches
2699  // traditional assembler behaviour. N32 would normally use addiu for both
2700  // integers and addresses.
2701  if (IsAddress && !Is32BitImm) {
2702  TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
2703  return false;
2704  }
2705 
2706  TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
2707  return false;
2708  }
2709 
2710  if (isUInt<16>(ImmValue)) {
2711  unsigned TmpReg = DstReg;
2712  if (SrcReg == DstReg) {
2713  TmpReg = getATReg(IDLoc);
2714  if (!TmpReg)
2715  return true;
2716  }
2717 
2718  TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI);
2719  if (UseSrcReg)
2720  TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI);
2721  return false;
2722  }
2723 
2724  if (isInt<32>(ImmValue) || isUInt<32>(ImmValue)) {
2725  warnIfNoMacro(IDLoc);
2726 
2727  uint16_t Bits31To16 = (ImmValue >> 16) & 0xffff;
2728  uint16_t Bits15To0 = ImmValue & 0xffff;
2729  if (!Is32BitImm && !isInt<32>(ImmValue)) {
2730  // Traditional behaviour seems to special case this particular value. It's
2731  // not clear why other masks are handled differently.
2732  if (ImmValue == 0xffffffff) {
2733  TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI);
2734  TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI);
2735  if (UseSrcReg)
2736  TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2737  return false;
2738  }
2739 
2740  // Expand to an ORi instead of a LUi to avoid sign-extending into the
2741  // upper 32 bits.
2742  TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI);
2743  TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
2744  if (Bits15To0)
2745  TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
2746  if (UseSrcReg)
2747  TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2748  return false;
2749  }
2750 
2751  TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI);
2752  if (Bits15To0)
2753  TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
2754  if (UseSrcReg)
2755  TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2756  return false;
2757  }
2758 
2759  if (isShiftedUIntAtAnyPosition<16>(ImmValue)) {
2760  if (Is32BitImm) {
2761  Error(IDLoc, "instruction requires a 32-bit immediate");
2762  return true;
2763  }
2764 
2765  // Traditionally, these immediates are shifted as little as possible and as
2766  // such we align the most significant bit to bit 15 of our temporary.
2767  unsigned FirstSet = findFirstSet((uint64_t)ImmValue);
2768  unsigned LastSet = findLastSet((uint64_t)ImmValue);
2769  unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet));
2770  uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff;
2771  TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI);
2772  TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI);
2773 
2774  if (UseSrcReg)
2775  TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2776 
2777  return false;
2778  }
2779 
2780  warnIfNoMacro(IDLoc);
2781 
2782  // The remaining case is packed with a sequence of dsll and ori with zeros
2783  // being omitted and any neighbouring dsll's being coalesced.
2784  // The highest 32-bit's are equivalent to a 32-bit immediate load.
2785 
2786  // Load bits 32-63 of ImmValue into bits 0-31 of the temporary register.
2787  if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false,
2788  IDLoc, Out, STI))
2789  return false;
2790 
2791  // Shift and accumulate into the register. If a 16-bit chunk is zero, then
2792  // skip it and defer the shift to the next chunk.
2793  unsigned ShiftCarriedForwards = 16;
2794  for (int BitNum = 16; BitNum >= 0; BitNum -= 16) {
2795  uint16_t ImmChunk = (ImmValue >> BitNum) & 0xffff;
2796 
2797  if (ImmChunk != 0) {
2798  TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);
2799  TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI);
2800  ShiftCarriedForwards = 0;
2801  }
2802 
2803  ShiftCarriedForwards += 16;
2804  }
2805  ShiftCarriedForwards -= 16;
2806 
2807  // Finish any remaining shifts left by trailing zeros.
2808  if (ShiftCarriedForwards)
2809  TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);
2810 
2811  if (UseSrcReg)
2812  TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2813 
2814  return false;
2815 }
2816 
2817 bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
2818  MCStreamer &Out, const MCSubtargetInfo *STI) {
2819  const MCOperand &ImmOp = Inst.getOperand(1);
2820  assert(ImmOp.isImm() && "expected immediate operand kind");
2821  const MCOperand &DstRegOp = Inst.getOperand(0);
2822  assert(DstRegOp.isReg() && "expected register operand kind");
2823 
2824  if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
2825  Is32BitImm, false, IDLoc, Out, STI))
2826  return true;
2827 
2828  return false;
2829 }
2830 
2831 bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg,
2832  const MCOperand &Offset,
2833  bool Is32BitAddress, SMLoc IDLoc,
2834  MCStreamer &Out,
2835  const MCSubtargetInfo *STI) {
2836  // la can't produce a usable address when addresses are 64-bit.
2837  if (Is32BitAddress && ABI.ArePtrs64bit()) {
2838  // FIXME: Demote this to a warning and continue as if we had 'dla' instead.
2839  // We currently can't do this because we depend on the equality
2840  // operator and N64 can end up with a GPR32/GPR64 mismatch.
2841  Error(IDLoc, "la used to load 64-bit address");
2842  // Continue as if we had 'dla' instead.
2843  Is32BitAddress = false;
2844  return true;
2845  }
2846 
2847  // dla requires 64-bit addresses.
2848  if (!Is32BitAddress && !hasMips3()) {
2849  Error(IDLoc, "instruction requires a 64-bit architecture");
2850  return true;
2851  }
2852 
2853  if (!Offset.isImm())
2854  return loadAndAddSymbolAddress(Offset.getExpr(), DstReg, BaseReg,
2855  Is32BitAddress, IDLoc, Out, STI);
2856 
2857  if (!ABI.ArePtrs64bit()) {
2858  // Continue as if we had 'la' whether we had 'la' or 'dla'.
2859  Is32BitAddress = true;
2860  }
2861 
2862  return loadImmediate(Offset.getImm(), DstReg, BaseReg, Is32BitAddress, true,
2863  IDLoc, Out, STI);
2864 }
2865 
2866 bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
2867  unsigned DstReg, unsigned SrcReg,
2868  bool Is32BitSym, SMLoc IDLoc,
2869  MCStreamer &Out,
2870  const MCSubtargetInfo *STI) {
2871  // FIXME: These expansions do not respect -mxgot.
2872  MipsTargetStreamer &TOut = getTargetStreamer();
2873  bool UseSrcReg = SrcReg != Mips::NoRegister;
2874  warnIfNoMacro(IDLoc);
2875 
2876  if (inPicMode() && ABI.IsO32()) {
2877  MCValue Res;
2878  if (!SymExpr->evaluateAsRelocatable(Res, nullptr, nullptr)) {
2879  Error(IDLoc, "expected relocatable expression");
2880  return true;
2881  }
2882  if (Res.getSymB() != nullptr) {
2883  Error(IDLoc, "expected relocatable expression with only one symbol");
2884  return true;
2885  }
2886 
2887  // The case where the result register is $25 is somewhat special. If the
2888  // symbol in the final relocation is external and not modified with a
2889  // constant then we must use R_MIPS_CALL16 instead of R_MIPS_GOT16.
2890  if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg &&
2891  Res.getConstant() == 0 &&
2892  !(Res.getSymA()->getSymbol().isInSection() ||
2893  Res.getSymA()->getSymbol().isTemporary() ||
2894  (Res.getSymA()->getSymbol().isELF() &&
2895  cast<MCSymbolELF>(Res.getSymA()->getSymbol()).getBinding() ==
2896  ELF::STB_LOCAL))) {
2897  const MCExpr *CallExpr =
2898  MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, SymExpr, getContext());
2899  TOut.emitRRX(Mips::LW, DstReg, GPReg, MCOperand::createExpr(CallExpr),
2900  IDLoc, STI);
2901  return false;
2902  }
2903 
2904  // The remaining cases are:
2905  // External GOT: lw $tmp, %got(symbol+offset)($gp)
2906  // >addiu $tmp, $tmp, %lo(offset)
2907  // >addiu $rd, $tmp, $rs
2908  // Local GOT: lw $tmp, %got(symbol+offset)($gp)
2909  // addiu $tmp, $tmp, %lo(symbol+offset)($gp)
2910  // >addiu $rd, $tmp, $rs
2911  // The addiu's marked with a '>' may be omitted if they are redundant. If
2912  // this happens then the last instruction must use $rd as the result
2913  // register.
2914  const MipsMCExpr *GotExpr =
2915  MipsMCExpr::create(MipsMCExpr::MEK_GOT, SymExpr, getContext());
2916  const MCExpr *LoExpr = nullptr;
2917  if (Res.getSymA()->getSymbol().isInSection() ||
2918  Res.getSymA()->getSymbol().isTemporary())
2919  LoExpr = MipsMCExpr::create(MipsMCExpr::MEK_LO, SymExpr, getContext());
2920  else if (Res.getConstant() != 0) {
2921  // External symbols fully resolve the symbol with just the %got(symbol)
2922  // but we must still account for any offset to the symbol for expressions
2923  // like symbol+8.
2924  LoExpr = MCConstantExpr::create(Res.getConstant(), getContext());
2925  }
2926 
2927  unsigned TmpReg = DstReg;
2928  if (UseSrcReg &&
2929  getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg,
2930  SrcReg)) {
2931  // If $rs is the same as $rd, we need to use AT.
2932  // If it is not available we exit.
2933  unsigned ATReg = getATReg(IDLoc);
2934  if (!ATReg)
2935  return true;
2936  TmpReg = ATReg;
2937  }
2938 
2939  TOut.emitRRX(Mips::LW, TmpReg, GPReg, MCOperand::createExpr(GotExpr), IDLoc,
2940  STI);
2941 
2942  if (LoExpr)
2943  TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
2944  IDLoc, STI);
2945 
2946  if (UseSrcReg)
2947  TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
2948 
2949  return false;
2950  }
2951 
2952  if (inPicMode() && ABI.ArePtrs64bit()) {
2953  MCValue Res;
2954  if (!SymExpr->evaluateAsRelocatable(Res, nullptr, nullptr)) {
2955  Error(IDLoc, "expected relocatable expression");
2956  return true;
2957  }
2958  if (Res.getSymB() != nullptr) {
2959  Error(IDLoc, "expected relocatable expression with only one symbol");
2960  return true;
2961  }
2962 
2963  // The case where the result register is $25 is somewhat special. If the
2964  // symbol in the final relocation is external and not modified with a
2965  // constant then we must use R_MIPS_CALL16 instead of R_MIPS_GOT_DISP.
2966  if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg &&
2967  Res.getConstant() == 0 &&
2968  !(Res.getSymA()->getSymbol().isInSection() ||
2969  Res.getSymA()->getSymbol().isTemporary() ||
2970  (Res.getSymA()->getSymbol().isELF() &&
2971  cast<MCSymbolELF>(Res.getSymA()->getSymbol()).getBinding() ==
2972  ELF::STB_LOCAL))) {
2973  const MCExpr *CallExpr =
2974  MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, SymExpr, getContext());
2975  TOut.emitRRX(Mips::LD, DstReg, GPReg, MCOperand::createExpr(CallExpr),
2976  IDLoc, STI);
2977  return false;
2978  }
2979 
2980  // The remaining cases are:
2981  // Small offset: ld $tmp, %got_disp(symbol)($gp)
2982  // >daddiu $tmp, $tmp, offset
2983  // >daddu $rd, $tmp, $rs
2984  // The daddiu's marked with a '>' may be omitted if they are redundant. If
2985  // this happens then the last instruction must use $rd as the result
2986  // register.
2988  Res.getSymA(),
2989  getContext());
2990  const MCExpr *LoExpr = nullptr;
2991  if (Res.getConstant() != 0) {
2992  // Symbols fully resolve with just the %got_disp(symbol) but we
2993  // must still account for any offset to the symbol for
2994  // expressions like symbol+8.
2995  LoExpr = MCConstantExpr::create(Res.getConstant(), getContext());
2996 
2997  // FIXME: Offsets greater than 16 bits are not yet implemented.
2998  // FIXME: The correct range is a 32-bit sign-extended number.
2999  if (Res.getConstant() < -0x8000 || Res.getConstant() > 0x7fff) {
3000  Error(IDLoc, "macro instruction uses large offset, which is not "
3001  "currently supported");
3002  return true;
3003  }
3004  }
3005 
3006  unsigned TmpReg = DstReg;
3007  if (UseSrcReg &&
3008  getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg,
3009  SrcReg)) {
3010  // If $rs is the same as $rd, we need to use AT.
3011  // If it is not available we exit.
3012  unsigned ATReg = getATReg(IDLoc);
3013  if (!ATReg)
3014  return true;
3015  TmpReg = ATReg;
3016  }
3017 
3018  TOut.emitRRX(Mips::LD, TmpReg, GPReg, MCOperand::createExpr(GotExpr), IDLoc,
3019  STI);
3020 
3021  if (LoExpr)
3022  TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
3023  IDLoc, STI);
3024 
3025  if (UseSrcReg)
3026  TOut.emitRRR(Mips::DADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
3027 
3028  return false;
3029  }
3030 
3031  const MipsMCExpr *HiExpr =
3032  MipsMCExpr::create(MipsMCExpr::MEK_HI, SymExpr, getContext());
3033  const MipsMCExpr *LoExpr =
3034  MipsMCExpr::create(MipsMCExpr::MEK_LO, SymExpr, getContext());
3035 
3036  // This is the 64-bit symbol address expansion.
3037  if (ABI.ArePtrs64bit() && isGP64bit()) {
3038  // We need AT for the 64-bit expansion in the cases where the optional
3039  // source register is the destination register and for the superscalar
3040  // scheduled form.
3041  //
3042  // If it is not available we exit if the destination is the same as the
3043  // source register.
3044 
3045  const MipsMCExpr *HighestExpr =
3046  MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, SymExpr, getContext());
3047  const MipsMCExpr *HigherExpr =
3048  MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, SymExpr, getContext());
3049 
3050  bool RdRegIsRsReg =
3051  getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg);
3052 
3053  if (canUseATReg() && UseSrcReg && RdRegIsRsReg) {
3054  unsigned ATReg = getATReg(IDLoc);
3055 
3056  // If $rs is the same as $rd:
3057  // (d)la $rd, sym($rd) => lui $at, %highest(sym)
3058  // daddiu $at, $at, %higher(sym)
3059  // dsll $at, $at, 16
3060  // daddiu $at, $at, %hi(sym)
3061  // dsll $at, $at, 16
3062  // daddiu $at, $at, %lo(sym)
3063  // daddu $rd, $at, $rd
3064  TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
3065  STI);
3066  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,
3067  MCOperand::createExpr(HigherExpr), IDLoc, STI);
3068  TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3069  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr),
3070  IDLoc, STI);
3071  TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3072  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
3073  IDLoc, STI);
3074  TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI);
3075 
3076  return false;
3077  } else if (canUseATReg() && !RdRegIsRsReg) {
3078  unsigned ATReg = getATReg(IDLoc);
3079 
3080  // If the $rs is different from $rd or if $rs isn't specified and we
3081  // have $at available:
3082  // (d)la $rd, sym/sym($rs) => lui $rd, %highest(sym)
3083  // lui $at, %hi(sym)
3084  // daddiu $rd, $rd, %higher(sym)
3085  // daddiu $at, $at, %lo(sym)
3086  // dsll32 $rd, $rd, 0
3087  // daddu $rd, $rd, $at
3088  // (daddu $rd, $rd, $rs)
3089  //
3090  // Which is preferred for superscalar issue.
3091  TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc,
3092  STI);
3093  TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
3094  TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
3095  MCOperand::createExpr(HigherExpr), IDLoc, STI);
3096  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
3097  IDLoc, STI);
3098  TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI);
3099  TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI);
3100  if (UseSrcReg)
3101  TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);
3102 
3103  return false;
3104  } else if (!canUseATReg() && !RdRegIsRsReg) {
3105  // Otherwise, synthesize the address in the destination register
3106  // serially:
3107  // (d)la $rd, sym/sym($rs) => lui $rd, %highest(sym)
3108  // daddiu $rd, $rd, %higher(sym)
3109  // dsll $rd, $rd, 16
3110  // daddiu $rd, $rd, %hi(sym)
3111  // dsll $rd, $rd, 16
3112  // daddiu $rd, $rd, %lo(sym)
3113  TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc,
3114  STI);
3115  TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
3116  MCOperand::createExpr(HigherExpr), IDLoc, STI);
3117  TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI);
3118  TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
3119  MCOperand::createExpr(HiExpr), IDLoc, STI);
3120  TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI);
3121  TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
3122  MCOperand::createExpr(LoExpr), IDLoc, STI);
3123  if (UseSrcReg)
3124  TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);
3125 
3126  return false;
3127  } else {
3128  // We have a case where SrcReg == DstReg and we don't have $at
3129  // available. We can't expand this case, so error out appropriately.
3130  assert(SrcReg == DstReg && !canUseATReg() &&
3131  "Could have expanded dla but didn't?");
3132  reportParseError(IDLoc,
3133  "pseudo-instruction requires $at, which is not available");
3134  return true;
3135  }
3136  }
3137 
3138  // And now, the 32-bit symbol address expansion:
3139  // If $rs is the same as $rd:
3140  // (d)la $rd, sym($rd) => lui $at, %hi(sym)
3141  // ori $at, $at, %lo(sym)
3142  // addu $rd, $at, $rd
3143  // Otherwise, if the $rs is different from $rd or if $rs isn't specified:
3144  // (d)la $rd, sym/sym($rs) => lui $rd, %hi(sym)
3145  // ori $rd, $rd, %lo(sym)
3146  // (addu $rd, $rd, $rs)
3147  unsigned TmpReg = DstReg;
3148  if (UseSrcReg &&
3149  getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) {
3150  // If $rs is the same as $rd, we need to use AT.
3151  // If it is not available we exit.
3152  unsigned ATReg = getATReg(IDLoc);
3153  if (!ATReg)
3154  return true;
3155  TmpReg = ATReg;
3156  }
3157 
3158  TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
3159  TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
3160  IDLoc, STI);
3161 
3162  if (UseSrcReg)
3163  TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
3164  else
3165  assert(
3166  getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg));
3167 
3168  return false;
3169 }
3170 
3171 // Each double-precision register DO-D15 overlaps with two of the single
3172 // precision registers F0-F31. As an example, all of the following hold true:
3173 // D0 + 1 == F1, F1 + 1 == D1, F1 + 1 == F2, depending on the context.
3174 static unsigned nextReg(unsigned Reg) {
3175  if (MipsMCRegisterClasses[Mips::FGR32RegClassID].contains(Reg))
3176  return Reg == (unsigned)Mips::F31 ? (unsigned)Mips::F0 : Reg + 1;
3177  switch (Reg) {
3178  default: llvm_unreachable("Unknown register in assembly macro expansion!");
3179  case Mips::ZERO: return Mips::AT;
3180  case Mips::AT: return Mips::V0;
3181  case Mips::V0: return Mips::V1;
3182  case Mips::V1: return Mips::A0;
3183  case Mips::A0: return Mips::A1;
3184  case Mips::A1: return Mips::A2;
3185  case Mips::A2: return Mips::A3;
3186  case Mips::A3: return Mips::T0;
3187  case Mips::T0: return Mips::T1;
3188  case Mips::T1: return Mips::T2;
3189  case Mips::T2: return Mips::T3;
3190  case Mips::T3: return Mips::T4;
3191  case Mips::T4: return Mips::T5;
3192  case Mips::T5: return Mips::T6;
3193  case Mips::T6: return Mips::T7;
3194  case Mips::T7: return Mips::S0;
3195  case Mips::S0: return Mips::S1;
3196  case Mips::S1: return Mips::S2;
3197  case Mips::S2: return Mips::S3;
3198  case Mips::S3: return Mips::S4;
3199  case Mips::S4: return Mips::S5;
3200  case Mips::S5: return Mips::S6;
3201  case Mips::S6: return Mips::S7;
3202  case Mips::S7: return Mips::T8;
3203  case Mips::T8: return Mips::T9;
3204  case Mips::T9: return Mips::K0;
3205  case Mips::K0: return Mips::K1;
3206  case Mips::K1: return Mips::GP;
3207  case Mips::GP: return Mips::SP;
3208  case Mips::SP: return Mips::FP;
3209  case Mips::FP: return Mips::RA;
3210  case Mips::RA: return Mips::ZERO;
3211  case Mips::D0: return Mips::F1;
3212  case Mips::D1: return Mips::F3;
3213  case Mips::D2: return Mips::F5;
3214  case Mips::D3: return Mips::F7;
3215  case Mips::D4: return Mips::F9;
3216  case Mips::D5: return Mips::F11;
3217  case Mips::D6: return Mips::F13;
3218  case Mips::D7: return Mips::F15;
3219  case Mips::D8: return Mips::F17;
3220  case Mips::D9: return Mips::F19;
3221  case Mips::D10: return Mips::F21;
3222  case Mips::D11: return Mips::F23;
3223  case Mips::D12: return Mips::F25;
3224  case Mips::D13: return Mips::F27;
3225  case Mips::D14: return Mips::F29;
3226  case Mips::D15: return Mips::F31;
3227  }
3228 }
3229 
3230 // FIXME: This method is too general. In principle we should compute the number
3231 // of instructions required to synthesize the immediate inline compared to
3232 // synthesizing the address inline and relying on non .text sections.
3233 // For static O32 and N32 this may yield a small benefit, for static N64 this is
3234 // likely to yield a much larger benefit as we have to synthesize a 64bit
3235 // address to load a 64 bit value.
3236 bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc,
3237  MCSymbol *Sym) {
3238  unsigned ATReg = getATReg(IDLoc);
3239  if (!ATReg)
3240  return true;
3241 
3242  if(IsPicEnabled) {
3243  const MCExpr *GotSym =
3245  const MipsMCExpr *GotExpr =
3246  MipsMCExpr::create(MipsMCExpr::MEK_GOT, GotSym, getContext());
3247 
3248  if(isABI_O32() || isABI_N32()) {
3249  TOut.emitRRX(Mips::LW, ATReg, GPReg, MCOperand::createExpr(GotExpr),
3250  IDLoc, STI);
3251  } else { //isABI_N64()
3252  TOut.emitRRX(Mips::LD, ATReg, GPReg, MCOperand::createExpr(GotExpr),
3253  IDLoc, STI);
3254  }
3255  } else { //!IsPicEnabled
3256  const MCExpr *HiSym =
3258  const MipsMCExpr *HiExpr =
3259  MipsMCExpr::create(MipsMCExpr::MEK_HI, HiSym, getContext());
3260 
3261  // FIXME: This is technically correct but gives a different result to gas,
3262  // but gas is incomplete there (it has a fixme noting it doesn't work with
3263  // 64-bit addresses).
3264  // FIXME: With -msym32 option, the address expansion for N64 should probably
3265  // use the O32 / N32 case. It's safe to use the 64 address expansion as the
3266  // symbol's value is considered sign extended.
3267  if(isABI_O32() || isABI_N32()) {
3268  TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
3269  } else { //isABI_N64()
3270  const MCExpr *HighestSym =
3272  const MipsMCExpr *HighestExpr =
3273  MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, HighestSym, getContext());
3274  const MCExpr *HigherSym =
3276  const MipsMCExpr *HigherExpr =
3277  MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, HigherSym, getContext());
3278 
3279  TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
3280  STI);
3281  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,
3282  MCOperand::createExpr(HigherExpr), IDLoc, STI);
3283  TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3284  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr),
3285  IDLoc, STI);
3286  TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3287  }
3288  }
3289  return false;
3290 }
3291 
3292 bool MipsAsmParser::expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR,
3293  bool Is64FPU, SMLoc IDLoc,
3294  MCStreamer &Out,
3295  const MCSubtargetInfo *STI) {
3296  MipsTargetStreamer &TOut = getTargetStreamer();
3297  assert(Inst.getNumOperands() == 2 && "Invalid operand count");
3298  assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&
3299  "Invalid instruction operand.");
3300 
3301  unsigned FirstReg = Inst.getOperand(0).getReg();
3302  uint64_t ImmOp64 = Inst.getOperand(1).getImm();
3303 
3304  uint32_t HiImmOp64 = (ImmOp64 & 0xffffffff00000000) >> 32;
3305  // If ImmOp64 is AsmToken::Integer type (all bits set to zero in the
3306  // exponent field), convert it to double (e.g. 1 to 1.0)
3307  if ((HiImmOp64 & 0x7ff00000) == 0) {
3308  APFloat RealVal(APFloat::IEEEdouble(), ImmOp64);
3309  ImmOp64 = RealVal.bitcastToAPInt().getZExtValue();
3310  }
3311 
3312  uint32_t LoImmOp64 = ImmOp64 & 0xffffffff;
3313  HiImmOp64 = (ImmOp64 & 0xffffffff00000000) >> 32;
3314 
3315  if (IsSingle) {
3316  // Conversion of a double in an uint64_t to a float in a uint32_t,
3317  // retaining the bit pattern of a float.
3318  uint32_t ImmOp32;
3319  double doubleImm = BitsToDouble(ImmOp64);
3320  float tmp_float = static_cast<float>(doubleImm);
3321  ImmOp32 = FloatToBits(tmp_float);
3322 
3323  if (IsGPR) {
3324  if (loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, true, IDLoc,
3325  Out, STI))
3326  return true;
3327  return false;
3328  } else {
3329  unsigned ATReg = getATReg(IDLoc);
3330  if (!ATReg)
3331  return true;
3332  if (LoImmOp64 == 0) {
3333  if (loadImmediate(ImmOp32, ATReg, Mips::NoRegister, true, true, IDLoc,
3334  Out, STI))
3335  return true;
3336  TOut.emitRR(Mips::MTC1, FirstReg, ATReg, IDLoc, STI);
3337  return false;
3338  }
3339 
3340  MCSection *CS = getStreamer().getCurrentSectionOnly();
3341  // FIXME: Enhance this expansion to use the .lit4 & .lit8 sections
3342  // where appropriate.
3343  MCSection *ReadOnlySection = getContext().getELFSection(
3344  ".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
3345 
3346  MCSymbol *Sym = getContext().createTempSymbol();
3347  const MCExpr *LoSym =
3349  const MipsMCExpr *LoExpr =
3350  MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());
3351 
3352  getStreamer().SwitchSection(ReadOnlySection);
3353  getStreamer().EmitLabel(Sym, IDLoc);
3354  getStreamer().EmitIntValue(ImmOp32, 4);
3355  getStreamer().SwitchSection(CS);
3356 
3357  if(emitPartialAddress(TOut, IDLoc, Sym))
3358  return true;
3359  TOut.emitRRX(Mips::LWC1, FirstReg, ATReg,
3360  MCOperand::createExpr(LoExpr), IDLoc, STI);
3361  }
3362  return false;
3363  }
3364 
3365  // if(!IsSingle)
3366  unsigned ATReg = getATReg(IDLoc);
3367  if (!ATReg)
3368  return true;
3369 
3370  if (IsGPR) {
3371  if (LoImmOp64 == 0) {
3372  if(isABI_N32() || isABI_N64()) {
3373  if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, false, true,
3374  IDLoc, Out, STI))
3375  return true;
3376  return false;
3377  } else {
3378  if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, true, true,
3379  IDLoc, Out, STI))
3380  return true;
3381 
3382  if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, true,
3383  IDLoc, Out, STI))
3384  return true;
3385  return false;
3386  }
3387  }
3388 
3389  MCSection *CS = getStreamer().getCurrentSectionOnly();
3390  MCSection *ReadOnlySection = getContext().getELFSection(
3391  ".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
3392 
3393  MCSymbol *Sym = getContext().createTempSymbol();
3394  const MCExpr *LoSym =
3396  const MipsMCExpr *LoExpr =
3397  MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());
3398 
3399  getStreamer().SwitchSection(ReadOnlySection);
3400  getStreamer().EmitLabel(Sym, IDLoc);
3401  getStreamer().EmitIntValue(HiImmOp64, 4);
3402  getStreamer().EmitIntValue(LoImmOp64, 4);
3403  getStreamer().SwitchSection(CS);
3404 
3405  if(emitPartialAddress(TOut, IDLoc, Sym))
3406  return true;
3407  if(isABI_N64())
3408  TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,
3409  MCOperand::createExpr(LoExpr), IDLoc, STI);
3410  else
3411  TOut.emitRRX(Mips::ADDiu, ATReg, ATReg,
3412  MCOperand::createExpr(LoExpr), IDLoc, STI);
3413 
3414  if(isABI_N32() || isABI_N64())
3415  TOut.emitRRI(Mips::LD, FirstReg, ATReg, 0, IDLoc, STI);
3416  else {
3417  TOut.emitRRI(Mips::LW, FirstReg, ATReg, 0, IDLoc, STI);
3418  TOut.emitRRI(Mips::LW, nextReg(FirstReg), ATReg, 4, IDLoc, STI);
3419  }
3420  return false;
3421  } else { // if(!IsGPR && !IsSingle)
3422  if ((LoImmOp64 == 0) &&
3423  !((HiImmOp64 & 0xffff0000) && (HiImmOp64 & 0x0000ffff))) {
3424  // FIXME: In the case where the constant is zero, we can load the
3425  // register directly from the zero register.
3426  if (loadImmediate(HiImmOp64, ATReg, Mips::NoRegister, true, true, IDLoc,
3427  Out, STI))
3428  return true;
3429  if (isABI_N32() || isABI_N64())
3430  TOut.emitRR(Mips::DMTC1, FirstReg, ATReg, IDLoc, STI);
3431  else if (hasMips32r2()) {
3432  TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
3433  TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, ATReg, IDLoc, STI);
3434  } else {
3435  TOut.emitRR(Mips::MTC1, nextReg(FirstReg), ATReg, IDLoc, STI);
3436  TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
3437  }
3438  return false;
3439  }
3440 
3441  MCSection *CS = getStreamer().getCurrentSectionOnly();
3442  // FIXME: Enhance this expansion to use the .lit4 & .lit8 sections
3443  // where appropriate.
3444  MCSection *ReadOnlySection = getContext().getELFSection(
3445  ".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);
3446 
3447  MCSymbol *Sym = getContext().createTempSymbol();
3448  const MCExpr *LoSym =
3450  const MipsMCExpr *LoExpr =
3451  MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());
3452 
3453  getStreamer().SwitchSection(ReadOnlySection);
3454  getStreamer().EmitLabel(Sym, IDLoc);
3455  getStreamer().EmitIntValue(HiImmOp64, 4);
3456  getStreamer().EmitIntValue(LoImmOp64, 4);
3457  getStreamer().SwitchSection(CS);
3458 
3459  if(emitPartialAddress(TOut, IDLoc, Sym))
3460  return true;
3461  TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, ATReg,
3462  MCOperand::createExpr(LoExpr), IDLoc, STI);
3463  }
3464  return false;
3465 }
3466 
3467 bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
3468  MCStreamer &Out,
3469  const MCSubtargetInfo *STI) {
3470  MipsTargetStreamer &TOut = getTargetStreamer();
3471 
3472  assert(getInstDesc(Inst.getOpcode()).getNumOperands() == 1 &&
3473  "unexpected number of operands");
3474 
3475  MCOperand Offset = Inst.getOperand(0);
3476  if (Offset.isExpr()) {
3477  Inst.clear();
3478  Inst.setOpcode(Mips::BEQ_MM);
3479  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3480  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3481  Inst.addOperand(MCOperand::createExpr(Offset.getExpr()));
3482  } else {
3483  assert(Offset.isImm() && "expected immediate operand kind");
3484  if (isInt<11>(Offset.getImm())) {
3485  // If offset fits into 11 bits then this instruction becomes microMIPS
3486  // 16-bit unconditional branch instruction.
3487  if (inMicroMipsMode())
3488  Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM);
3489  } else {
3490  if (!isInt<17>(Offset.getImm()))
3491  return Error(IDLoc, "branch target out of range");
3492  if (OffsetToAlignment(Offset.getImm(), 1LL << 1))
3493  return Error(IDLoc, "branch to misaligned address");
3494  Inst.clear();
3495  Inst.setOpcode(Mips::BEQ_MM);
3496  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3497  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3498  Inst.addOperand(MCOperand::createImm(Offset.getImm()));
3499  }
3500  }
3501  Out.EmitInstruction(Inst, *STI);
3502 
3503  // If .set reorder is active and branch instruction has a delay slot,
3504  // emit a NOP after it.
3505  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3506  if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
3507  TOut.emitEmptyDelaySlot(true, IDLoc, STI);
3508 
3509  return false;
3510 }
3511 
3512 bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
3513  const MCSubtargetInfo *STI) {
3514  MipsTargetStreamer &TOut = getTargetStreamer();
3515  const MCOperand &DstRegOp = Inst.getOperand(0);
3516  assert(DstRegOp.isReg() && "expected register operand kind");
3517 
3518  const MCOperand &ImmOp = Inst.getOperand(1);
3519  assert(ImmOp.isImm() && "expected immediate operand kind");
3520 
3521  const MCOperand &MemOffsetOp = Inst.getOperand(2);
3522  assert((MemOffsetOp.isImm() || MemOffsetOp.isExpr()) &&
3523  "expected immediate or expression operand");
3524 
3525  bool IsLikely = false;
3526 
3527  unsigned OpCode = 0;
3528  switch(Inst.getOpcode()) {
3529  case Mips::BneImm:
3530  OpCode = Mips::BNE;
3531  break;
3532  case Mips::BeqImm:
3533  OpCode = Mips::BEQ;
3534  break;
3535  case Mips::BEQLImmMacro:
3536  OpCode = Mips::BEQL;
3537  IsLikely = true;
3538  break;
3539  case Mips::BNELImmMacro:
3540  OpCode = Mips::BNEL;
3541  IsLikely = true;
3542  break;
3543  default:
3544  llvm_unreachable("Unknown immediate branch pseudo-instruction.");
3545  break;
3546  }
3547 
3548  int64_t ImmValue = ImmOp.getImm();
3549  if (ImmValue == 0) {
3550  if (IsLikely) {
3551  TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO,
3552  MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI);
3553  TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
3554  } else
3555  TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
3556  STI);
3557  } else {
3558  warnIfNoMacro(IDLoc);
3559 
3560  unsigned ATReg = getATReg(IDLoc);
3561  if (!ATReg)
3562  return true;
3563 
3564  if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true,
3565  IDLoc, Out, STI))
3566  return true;
3567 
3568  if (IsLikely) {
3569  TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg,
3570  MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI);
3571  TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
3572  } else
3573  TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);
3574  }
3575  return false;
3576 }
3577 
3578 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
3579  const MCSubtargetInfo *STI, bool IsLoad) {
3580  const MCOperand &DstRegOp = Inst.getOperand(0);
3581  assert(DstRegOp.isReg() && "expected register operand kind");
3582  const MCOperand &BaseRegOp = Inst.getOperand(1);
3583  assert(BaseRegOp.isReg() && "expected register operand kind");
3584 
3585  MipsTargetStreamer &TOut = getTargetStreamer();
3586  unsigned DstReg = DstRegOp.getReg();
3587  unsigned BaseReg = BaseRegOp.getReg();
3588  unsigned TmpReg = DstReg;
3589 
3590  const MCInstrDesc &Desc = getInstDesc(Inst.getOpcode());
3591  int16_t DstRegClass = Desc.OpInfo[0].RegClass;
3592  unsigned DstRegClassID =
3593  getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
3594  bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
3595  (DstRegClassID == Mips::GPR64RegClassID);
3596 
3597  if (!IsLoad || !IsGPR || (BaseReg == DstReg)) {
3598  // At this point we need AT to perform the expansions
3599  // and we exit if it is not available.
3600  TmpReg = getATReg(IDLoc);
3601  if (!TmpReg)
3602  return;
3603  }
3604 
3605  if (Inst.getNumOperands() > 3) {
3606  const MCOperand &BaseRegOp = Inst.getOperand(2);
3607  assert(BaseRegOp.isReg() && "expected register operand kind");
3608  const MCOperand &ExprOp = Inst.getOperand(3);
3609  assert(ExprOp.isExpr() && "expected expression oprand kind");
3610 
3611  unsigned BaseReg = BaseRegOp.getReg();
3612  const MCExpr *ExprOffset = ExprOp.getExpr();
3613 
3614  MCOperand LoOperand = MCOperand::createExpr(
3615  MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext()));
3616  MCOperand HiOperand = MCOperand::createExpr(
3617  MipsMCExpr::create(MipsMCExpr::MEK_HI, ExprOffset, getContext()));
3618  TOut.emitSCWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand,
3619  LoOperand, TmpReg, IDLoc, STI);
3620  return;
3621  }
3622 
3623  const MCOperand &OffsetOp = Inst.getOperand(2);
3624 
3625  if (OffsetOp.isImm()) {
3626  int64_t LoOffset = OffsetOp.getImm() & 0xffff;
3627  int64_t HiOffset = OffsetOp.getImm() & ~0xffff;
3628 
3629  // If msb of LoOffset is 1(negative number) we must increment
3630  // HiOffset to account for the sign-extension of the low part.
3631  if (LoOffset & 0x8000)
3632  HiOffset += 0x10000;
3633 
3634  bool IsLargeOffset = HiOffset != 0;
3635 
3636  if (IsLargeOffset) {
3637  bool Is32BitImm = (HiOffset >> 32) == 0;
3638  if (loadImmediate(HiOffset, TmpReg, Mips::NoRegister, Is32BitImm, true,
3639  IDLoc, Out, STI))
3640  return;
3641  }
3642 
3643  if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)
3644  TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg,
3645  BaseReg, IDLoc, STI);
3646  TOut.emitRRI(Inst.getOpcode(), DstReg, TmpReg, LoOffset, IDLoc, STI);
3647  return;
3648  }
3649 
3650  if (OffsetOp.isExpr()) {
3651  if (inPicMode()) {
3652  // FIXME:
3653  // a) Fix lw/sw $reg, symbol($reg) instruction expanding.
3654  // b) If expression includes offset (sym + number), do not
3655  // encode the offset into a relocation. Take it in account
3656  // in the last load/store instruction.
3657  // c) Check that immediates of R_MIPS_GOT16/R_MIPS_LO16 relocations
3658  // do not exceed 16-bit.
3659  // d) Use R_MIPS_GOT_PAGE/R_MIPS_GOT_OFST relocations instead
3660  // of R_MIPS_GOT_DISP in appropriate cases to reduce number
3661  // of GOT entries.
3662  loadAndAddSymbolAddress(OffsetOp.getExpr(), TmpReg, Mips::NoRegister,
3663  !ABI.ArePtrs64bit(), IDLoc, Out, STI);
3664  TOut.emitRRI(Inst.getOpcode(), DstReg, TmpReg, 0, IDLoc, STI);
3665  } else {
3666  const MCExpr *ExprOffset = OffsetOp.getExpr();
3667  MCOperand LoOperand = MCOperand::createExpr(
3668  MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext()));
3669  MCOperand HiOperand = MCOperand::createExpr(
3670  MipsMCExpr::create(MipsMCExpr::MEK_HI, ExprOffset, getContext()));
3671 
3672  if (IsLoad)
3673  TOut.emitLoadWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand,
3674  LoOperand, TmpReg, IDLoc, STI);
3675  else
3676  TOut.emitStoreWithSymOffset(Inst.getOpcode(), DstReg, BaseReg,
3677  HiOperand, LoOperand, TmpReg, IDLoc, STI);
3678  }
3679  return;
3680  }
3681 
3682  llvm_unreachable("unexpected operand type");
3683 }
3684 
3685 bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
3686  MCStreamer &Out,
3687  const MCSubtargetInfo *STI) {
3688  unsigned OpNum = Inst.getNumOperands();
3689  unsigned Opcode = Inst.getOpcode();
3690  unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM;
3691 
3692  assert(Inst.getOperand(OpNum - 1).isImm() &&
3693  Inst.getOperand(OpNum - 2).isReg() &&
3694  Inst.getOperand(OpNum - 3).isReg() && "Invalid instruction operand.");
3695 
3696  if (OpNum < 8 && Inst.getOperand(OpNum - 1).getImm() <= 60 &&
3697  Inst.getOperand(OpNum - 1).getImm() >= 0 &&
3698  (Inst.getOperand(OpNum - 2).getReg() == Mips::SP ||
3699  Inst.getOperand(OpNum - 2).getReg() == Mips::SP_64) &&
3700  (Inst.getOperand(OpNum - 3).getReg() == Mips::RA ||
3701  Inst.getOperand(OpNum - 3).getReg() == Mips::RA_64)) {
3702  // It can be implemented as SWM16 or LWM16 instruction.
3703  if (inMicroMipsMode() && hasMips32r6())
3704  NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6;
3705  else
3706  NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM;
3707  }
3708 
3709  Inst.setOpcode(NewOpcode);
3710  Out.EmitInstruction(Inst, *STI);
3711  return false;
3712 }
3713 
3714 bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
3715  MCStreamer &Out,
3716  const MCSubtargetInfo *STI) {
3717  MipsTargetStreamer &TOut = getTargetStreamer();
3718  bool EmittedNoMacroWarning = false;
3719  unsigned PseudoOpcode = Inst.getOpcode();
3720  unsigned SrcReg = Inst.getOperand(0).getReg();
3721  const MCOperand &TrgOp = Inst.getOperand(1);
3722  const MCExpr *OffsetExpr = Inst.getOperand(2).getExpr();
3723 
3724  unsigned ZeroSrcOpcode, ZeroTrgOpcode;
3725  bool ReverseOrderSLT, IsUnsigned, IsLikely, AcceptsEquality;
3726 
3727  unsigned TrgReg;
3728  if (TrgOp.isReg())
3729  TrgReg = TrgOp.getReg();
3730  else if (TrgOp.isImm()) {
3731  warnIfNoMacro(IDLoc);
3732  EmittedNoMacroWarning = true;
3733 
3734  TrgReg = getATReg(IDLoc);
3735  if (!TrgReg)
3736  return true;
3737 
3738  switch(PseudoOpcode) {
3739  default:
3740  llvm_unreachable("unknown opcode for branch pseudo-instruction");
3741  case Mips::BLTImmMacro:
3742  PseudoOpcode = Mips::BLT;
3743  break;
3744  case Mips::BLEImmMacro:
3745  PseudoOpcode = Mips::BLE;
3746  break;
3747  case Mips::BGEImmMacro:
3748  PseudoOpcode = Mips::BGE;
3749  break;
3750  case Mips::BGTImmMacro:
3751  PseudoOpcode = Mips::BGT;
3752  break;
3753  case Mips::BLTUImmMacro:
3754  PseudoOpcode = Mips::BLTU;
3755  break;
3756  case Mips::BLEUImmMacro:
3757  PseudoOpcode = Mips::BLEU;
3758  break;
3759  case Mips::BGEUImmMacro:
3760  PseudoOpcode = Mips::BGEU;
3761  break;
3762  case Mips::BGTUImmMacro:
3763  PseudoOpcode = Mips::BGTU;
3764  break;
3765  case Mips::BLTLImmMacro:
3766  PseudoOpcode = Mips::BLTL;
3767  break;
3768  case Mips::BLELImmMacro:
3769  PseudoOpcode = Mips::BLEL;
3770  break;
3771  case Mips::BGELImmMacro:
3772  PseudoOpcode = Mips::BGEL;
3773  break;
3774  case Mips::BGTLImmMacro:
3775  PseudoOpcode = Mips::BGTL;
3776  break;
3777  case Mips::BLTULImmMacro:
3778  PseudoOpcode = Mips::BLTUL;
3779  break;
3780  case Mips::BLEULImmMacro:
3781  PseudoOpcode = Mips::BLEUL;
3782  break;
3783  case Mips::BGEULImmMacro:
3784  PseudoOpcode = Mips::BGEUL;
3785  break;
3786  case Mips::BGTULImmMacro:
3787  PseudoOpcode = Mips::BGTUL;
3788  break;
3789  }
3790 
3791  if (loadImmediate(TrgOp.getImm(), TrgReg, Mips::NoRegister, !isGP64bit(),
3792  false, IDLoc, Out, STI))
3793  return true;
3794  }
3795 
3796  switch (PseudoOpcode) {
3797  case Mips::BLT:
3798  case Mips::BLTU:
3799  case Mips::BLTL:
3800  case Mips::BLTUL:
3801  AcceptsEquality = false;
3802  ReverseOrderSLT = false;
3803  IsUnsigned =
3804  ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL));
3805  IsLikely = ((PseudoOpcode == Mips::BLTL) || (PseudoOpcode == Mips::BLTUL));
3806  ZeroSrcOpcode = Mips::BGTZ;
3807  ZeroTrgOpcode = Mips::BLTZ;
3808  break;
3809  case Mips::BLE:
3810  case Mips::BLEU:
3811  case Mips::BLEL:
3812  case Mips::BLEUL:
3813  AcceptsEquality = true;
3814  ReverseOrderSLT = true;
3815  IsUnsigned =
3816  ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL));
3817  IsLikely = ((PseudoOpcode == Mips::BLEL) || (PseudoOpcode == Mips::BLEUL));
3818  ZeroSrcOpcode = Mips::BGEZ;
3819  ZeroTrgOpcode = Mips::BLEZ;
3820  break;
3821  case Mips::BGE:
3822  case Mips::BGEU:
3823  case Mips::BGEL:
3824  case Mips::BGEUL:
3825  AcceptsEquality = true;
3826  ReverseOrderSLT = false;
3827  IsUnsigned =
3828  ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL));
3829  IsLikely = ((PseudoOpcode == Mips::BGEL) || (PseudoOpcode == Mips::BGEUL));
3830  ZeroSrcOpcode = Mips::BLEZ;
3831  ZeroTrgOpcode = Mips::BGEZ;
3832  break;
3833  case Mips::BGT:
3834  case Mips::BGTU:
3835  case Mips::BGTL:
3836  case Mips::BGTUL:
3837  AcceptsEquality = false;
3838  ReverseOrderSLT = true;
3839  IsUnsigned =
3840  ((PseudoOpcode == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL));
3841  IsLikely = ((PseudoOpcode == Mips::BGTL) || (PseudoOpcode == Mips::BGTUL));
3842  ZeroSrcOpcode = Mips::BLTZ;
3843  ZeroTrgOpcode = Mips::BGTZ;
3844  break;
3845  default:
3846  llvm_unreachable("unknown opcode for branch pseudo-instruction");
3847  }
3848 
3849  bool IsTrgRegZero = (TrgReg == Mips::ZERO);
3850  bool IsSrcRegZero = (SrcReg == Mips::ZERO);
3851  if (IsSrcRegZero && IsTrgRegZero) {
3852  // FIXME: All of these Opcode-specific if's are needed for compatibility
3853  // with GAS' behaviour. However, they may not generate the most efficient
3854  // code in some circumstances.
3855  if (PseudoOpcode == Mips::BLT) {
3856  TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
3857  IDLoc, STI);
3858  return false;
3859  }
3860  if (PseudoOpcode == Mips::BLE) {
3861  TOut.emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
3862  IDLoc, STI);
3863  Warning(IDLoc, "branch is always taken");
3864  return false;
3865  }
3866  if (PseudoOpcode == Mips::BGE) {
3867  TOut.emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
3868  IDLoc, STI);
3869  Warning(IDLoc, "branch is always taken");
3870  return false;
3871  }
3872  if (PseudoOpcode == Mips::BGT) {
3873  TOut.emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
3874  IDLoc, STI);
3875  return false;
3876  }
3877  if (PseudoOpcode == Mips::BGTU) {
3878  TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO,
3879  MCOperand::createExpr(OffsetExpr), IDLoc, STI);
3880  return false;
3881  }
3882  if (AcceptsEquality) {
3883  // If both registers are $0 and the pseudo-branch accepts equality, it
3884  // will always be taken, so we emit an unconditional branch.
3885  TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
3886  MCOperand::createExpr(OffsetExpr), IDLoc, STI);
3887  Warning(IDLoc, "branch is always taken");
3888  return false;
3889  }
3890  // If both registers are $0 and the pseudo-branch does not accept
3891  // equality, it will never be taken, so we don't have to emit anything.
3892  return false;
3893  }
3894  if (IsSrcRegZero || IsTrgRegZero) {
3895  if ((IsSrcRegZero && PseudoOpcode == Mips::BGTU) ||
3896  (IsTrgRegZero && PseudoOpcode == Mips::BLTU)) {
3897  // If the $rs is $0 and the pseudo-branch is BGTU (0 > x) or
3898  // if the $rt is $0 and the pseudo-branch is BLTU (x < 0),
3899  // the pseudo-branch will never be taken, so we don't emit anything.
3900  // This only applies to unsigned pseudo-branches.
3901  return false;
3902  }
3903  if ((IsSrcRegZero && PseudoOpcode == Mips::BLEU) ||
3904  (IsTrgRegZero && PseudoOpcode == Mips::BGEU)) {
3905  // If the $rs is $0 and the pseudo-branch is BLEU (0 <= x) or
3906  // if the $rt is $0 and the pseudo-branch is BGEU (x >= 0),
3907  // the pseudo-branch will always be taken, so we emit an unconditional
3908  // branch.
3909  // This only applies to unsigned pseudo-branches.
3910  TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
3911  MCOperand::createExpr(OffsetExpr), IDLoc, STI);
3912  Warning(IDLoc, "branch is always taken");
3913  return false;
3914  }
3915  if (IsUnsigned) {
3916  // If the $rs is $0 and the pseudo-branch is BLTU (0 < x) or
3917  // if the $rt is $0 and the pseudo-branch is BGTU (x > 0),
3918  // the pseudo-branch will be taken only when the non-zero register is
3919  // different from 0, so we emit a BNEZ.
3920  //
3921  // If the $rs is $0 and the pseudo-branch is BGEU (0 >= x) or
3922  // if the $rt is $0 and the pseudo-branch is BLEU (x <= 0),
3923  // the pseudo-branch will be taken only when the non-zero register is
3924  // equal to 0, so we emit a BEQZ.
3925  //
3926  // Because only BLEU and BGEU branch on equality, we can use the
3927  // AcceptsEquality variable to decide when to emit the BEQZ.
3928  TOut.emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE,
3929  IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO,
3930  MCOperand::createExpr(OffsetExpr), IDLoc, STI);
3931  return false;
3932  }
3933  // If we have a signed pseudo-branch and one of the registers is $0,
3934  // we can use an appropriate compare-to-zero branch. We select which one
3935  // to use in the switch statement above.
3936  TOut.emitRX(IsSrcRegZero ? ZeroSrcOpcode : ZeroTrgOpcode,
3937  IsSrcRegZero ? TrgReg : SrcReg,
3938  MCOperand::createExpr(OffsetExpr), IDLoc, STI);
3939  return false;
3940  }
3941 
3942  // If neither the SrcReg nor the TrgReg are $0, we need AT to perform the
3943  // expansions. If it is not available, we return.
3944  unsigned ATRegNum = getATReg(IDLoc);
3945  if (!ATRegNum)
3946  return true;
3947 
3948  if (!EmittedNoMacroWarning)
3949  warnIfNoMacro(IDLoc);
3950 
3951  // SLT fits well with 2 of our 4 pseudo-branches:
3952  // BLT, where $rs < $rt, translates into "slt $at, $rs, $rt" and
3953  // BGT, where $rs > $rt, translates into "slt $at, $rt, $rs".
3954  // If the result of the SLT is 1, we branch, and if it's 0, we don't.
3955  // This is accomplished by using a BNEZ with the result of the SLT.
3956  //
3957  // The other 2 pseudo-branches are opposites of the above 2 (BGE with BLT
3958  // and BLE with BGT), so we change the BNEZ into a BEQZ.
3959  // Because only BGE and BLE branch on equality, we can use the
3960  // AcceptsEquality variable to decide when to emit the BEQZ.
3961  // Note that the order of the SLT arguments doesn't change between
3962  // opposites.
3963  //
3964  // The same applies to the unsigned variants, except that SLTu is used
3965  // instead of SLT.
3966  TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum,
3967  ReverseOrderSLT ? TrgReg : SrcReg,
3968  ReverseOrderSLT ? SrcReg : TrgReg, IDLoc, STI);
3969 
3970  TOut.emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL)
3971  : (AcceptsEquality ? Mips::BEQ : Mips::BNE),
3972  ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
3973  STI);
3974  return false;
3975 }
3976 
3977 // Expand a integer division macro.
3978 //
3979 // Notably we don't have to emit a warning when encountering $rt as the $zero
3980 // register, or 0 as an immediate. processInstruction() has already done that.
3981 //
3982 // The destination register can only be $zero when expanding (S)DivIMacro or
3983 // D(S)DivMacro.
3984 
3985 bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
3986  const MCSubtargetInfo *STI, const bool IsMips64,
3987  const bool Signed) {
3988  MipsTargetStreamer &TOut = getTargetStreamer();
3989 
3990  warnIfNoMacro(IDLoc);
3991 
3992  const MCOperand &RdRegOp = Inst.getOperand(0);
3993  assert(RdRegOp.isReg() && "expected register operand kind");
3994  unsigned RdReg = RdRegOp.getReg();
3995 
3996  const MCOperand &RsRegOp = Inst.getOperand(1);
3997  assert(RsRegOp.isReg() && "expected register operand kind");
3998  unsigned RsReg = RsRegOp.getReg();
3999 
4000  unsigned RtReg;
4001  int64_t ImmValue;
4002 
4003  const MCOperand &RtOp = Inst.getOperand(2);
4004  assert((RtOp.isReg() || RtOp.isImm()) &&
4005  "expected register or immediate operand kind");
4006  if (RtOp.isReg())
4007  RtReg = RtOp.getReg();
4008  else
4009  ImmValue = RtOp.getImm();
4010 
4011  unsigned DivOp;
4012  unsigned ZeroReg;
4013  unsigned SubOp;
4014 
4015  if (IsMips64) {
4016  DivOp = Signed ? Mips::DSDIV : Mips::DUDIV;
4017  ZeroReg = Mips::ZERO_64;
4018  SubOp = Mips::DSUB;
4019  } else {
4020  DivOp = Signed ? Mips::SDIV : Mips::UDIV;
4021  ZeroReg = Mips::ZERO;
4022  SubOp = Mips::SUB;
4023  }
4024 
4025  bool UseTraps = useTraps();
4026 
4027  unsigned Opcode = Inst.getOpcode();
4028  bool isDiv = Opcode == Mips::SDivMacro || Opcode == Mips::SDivIMacro ||
4029  Opcode == Mips::UDivMacro || Opcode == Mips::UDivIMacro ||
4030  Opcode == Mips::DSDivMacro || Opcode == Mips::DSDivIMacro ||
4031  Opcode == Mips::DUDivMacro || Opcode == Mips::DUDivIMacro;
4032 
4033  bool isRem = Opcode == Mips::SRemMacro || Opcode == Mips::SRemIMacro ||
4034  Opcode == Mips::URemMacro || Opcode == Mips::URemIMacro ||
4035  Opcode == Mips::DSRemMacro || Opcode == Mips::DSRemIMacro ||
4036  Opcode == Mips::DURemMacro || Opcode == Mips::DURemIMacro;
4037 
4038  if (RtOp.isImm()) {
4039  unsigned ATReg = getATReg(IDLoc);
4040  if (!ATReg)
4041  return true;
4042 
4043  if (ImmValue == 0) {
4044  if (UseTraps)
4045  TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
4046  else
4047  TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
4048  return false;
4049  }
4050 
4051  if (isRem && (ImmValue == 1 || (Signed && (ImmValue == -1)))) {
4052  TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI);
4053  return false;
4054  } else if (isDiv && ImmValue == 1) {
4055  TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI);
4056  return false;
4057  } else if (isDiv && Signed && ImmValue == -1) {
4058  TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI);
4059  return false;
4060  } else {
4061  if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue),
4062  false, Inst.getLoc(), Out, STI))
4063  return true;
4064  TOut.emitRR(DivOp, RsReg, ATReg, IDLoc, STI);
4065  TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
4066  return false;
4067  }
4068  return true;
4069  }
4070 
4071  // If the macro expansion of (d)div(u) or (d)rem(u) would always trap or
4072  // break, insert the trap/break and exit. This gives a different result to
4073  // GAS. GAS has an inconsistency/missed optimization in that not all cases
4074  // are handled equivalently. As the observed behaviour is the same, we're ok.
4075  if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) {
4076  if (UseTraps) {
4077  TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
4078  return false;
4079  }
4080  TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
4081  return false;
4082  }
4083 
4084  // (d)rem(u) $0, $X, $Y is a special case. Like div $zero, $X, $Y, it does
4085  // not expand to macro sequence.
4086  if (isRem && (RdReg == Mips::ZERO || RdReg == Mips::ZERO_64)) {
4087  TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
4088  return false;
4089  }
4090 
4091  // Temporary label for first branch traget
4093  MCSymbol *BrTarget;
4094  MCOperand LabelOp;
4095 
4096  if (UseTraps) {
4097  TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
4098  } else {
4099  // Branch to the li instruction.
4100  BrTarget = Context.createTempSymbol();
4101  LabelOp = MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
4102  TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI);
4103  }
4104 
4105  TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
4106 
4107  if (!UseTraps)
4108  TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
4109 
4110  if (!Signed) {
4111  if (!UseTraps)
4112  TOut.getStreamer().EmitLabel(BrTarget);
4113 
4114  TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
4115  return false;
4116  }
4117 
4118  unsigned ATReg = getATReg(IDLoc);
4119  if (!ATReg)
4120  return true;
4121 
4122  if (!UseTraps)
4123  TOut.getStreamer().EmitLabel(BrTarget);
4124 
4125  TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI);
4126 
4127  // Temporary label for the second branch target.
4128  MCSymbol *BrTargetEnd = Context.createTempSymbol();
4129  MCOperand LabelOpEnd =
4130  MCOperand::createExpr(MCSymbolRefExpr::create(BrTargetEnd, Context));
4131 
4132  // Branch to the mflo instruction.
4133  TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI);
4134 
4135  if (IsMips64) {
4136  TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI);
4137  TOut.emitDSLL(ATReg, ATReg, 63, IDLoc, STI);
4138  } else {
4139  TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI);
4140  }
4141 
4142  if (UseTraps)
4143  TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI);
4144  else {
4145  // Branch to the mflo instruction.
4146  TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI);
4147  TOut.emitNop(IDLoc, STI);
4148  TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI);
4149  }
4150 
4151  TOut.getStreamer().EmitLabel(BrTargetEnd);
4152  TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
4153  return false;
4154 }
4155 
4156 bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU,
4157  SMLoc IDLoc, MCStreamer &Out,
4158  const MCSubtargetInfo *STI) {
4159  MipsTargetStreamer &TOut = getTargetStreamer();
4160 
4161  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
4162  assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
4163  Inst.getOperand(2).isReg() && "Invalid instruction operand.");
4164 
4165  unsigned FirstReg = Inst.getOperand(0).getReg();
4166  unsigned SecondReg = Inst.getOperand(1).getReg();
4167  unsigned ThirdReg = Inst.getOperand(2).getReg();
4168 
4169  if (hasMips1() && !hasMips2()) {
4170  unsigned ATReg = getATReg(IDLoc);
4171  if (!ATReg)
4172  return true;
4173  TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
4174  TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
4175  TOut.emitNop(IDLoc, STI);
4176  TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI);
4177  TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI);
4178  TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI);
4179  TOut.emitNop(IDLoc, STI);
4180  TOut.emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32)
4181  : Mips::CVT_W_S,
4182  FirstReg, SecondReg, IDLoc, STI);
4183  TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI);
4184  TOut.emitNop(IDLoc, STI);
4185  return false;
4186  }
4187 
4188  TOut.emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32)
4189  : Mips::TRUNC_W_S,
4190  FirstReg, SecondReg, IDLoc, STI);
4191 
4192  return false;
4193 }
4194 
4195 bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
4196  MCStreamer &Out, const MCSubtargetInfo *STI) {
4197  if (hasMips32r6() || hasMips64r6()) {
4198  return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
4199  }
4200 
4201  const MCOperand &DstRegOp = Inst.getOperand(0);
4202  assert(DstRegOp.isReg() && "expected register operand kind");
4203  const MCOperand &SrcRegOp = Inst.getOperand(1);
4204  assert(SrcRegOp.isReg() && "expected register operand kind");
4205  const MCOperand &OffsetImmOp = Inst.getOperand(2);
4206  assert(OffsetImmOp.isImm() && "expected immediate operand kind");
4207 
4208  MipsTargetStreamer &TOut = getTargetStreamer();
4209  unsigned DstReg = DstRegOp.getReg();
4210  unsigned SrcReg = SrcRegOp.getReg();
4211  int64_t OffsetValue = OffsetImmOp.getImm();
4212 
4213  // NOTE: We always need AT for ULHU, as it is always used as the source
4214  // register for one of the LBu's.
4215  warnIfNoMacro(IDLoc);
4216  unsigned ATReg = getATReg(IDLoc);
4217  if (!ATReg)
4218  return true;
4219 
4220  bool IsLargeOffset = !(isInt<16>(OffsetValue + 1) && isInt<16>(OffsetValue));
4221  if (IsLargeOffset) {
4222  if (loadImmediate(OffsetValue, ATReg, SrcReg, !ABI.ArePtrs64bit(), true,
4223  IDLoc, Out, STI))
4224  return true;
4225  }
4226 
4227  int64_t FirstOffset = IsLargeOffset ? 0 : OffsetValue;
4228  int64_t SecondOffset = IsLargeOffset ? 1 : (OffsetValue + 1);
4229  if (isLittle())
4230  std::swap(FirstOffset, SecondOffset);
4231 
4232  unsigned FirstLbuDstReg = IsLargeOffset ? DstReg : ATReg;
4233  unsigned SecondLbuDstReg = IsLargeOffset ? ATReg : DstReg;
4234 
4235  unsigned LbuSrcReg = IsLargeOffset ? ATReg : SrcReg;
4236  unsigned SllReg = IsLargeOffset ? DstReg : ATReg;
4237 
4238  TOut.emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg,
4239  FirstOffset, IDLoc, STI);
4240  TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondOffset, IDLoc, STI);
4241  TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI);
4242  TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);
4243 
4244  return false;
4245 }
4246 
4247 bool MipsAsmParser::expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4248  const MCSubtargetInfo *STI) {
4249  if (hasMips32r6() || hasMips64r6()) {
4250  return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
4251  }
4252 
4253  const MCOperand &DstRegOp = Inst.getOperand(0);
4254  assert(DstRegOp.isReg() && "expected register operand kind");
4255  const MCOperand &SrcRegOp = Inst.getOperand(1);
4256  assert(SrcRegOp.isReg() && "expected register operand kind");
4257  const MCOperand &OffsetImmOp = Inst.getOperand(2);
4258  assert(OffsetImmOp.isImm() && "expected immediate operand kind");
4259 
4260  MipsTargetStreamer &TOut = getTargetStreamer();
4261  unsigned DstReg = DstRegOp.getReg();
4262  unsigned SrcReg = SrcRegOp.getReg();
4263  int64_t OffsetValue = OffsetImmOp.getImm();
4264 
4265  warnIfNoMacro(IDLoc);
4266  unsigned ATReg = getATReg(IDLoc);
4267  if (!ATReg)
4268  return true;
4269 
4270  bool IsLargeOffset = !(isInt<16>(OffsetValue + 1) && isInt<16>(OffsetValue));
4271  if (IsLargeOffset) {
4272  if (loadImmediate(OffsetValue, ATReg, SrcReg, !ABI.ArePtrs64bit(), true,
4273  IDLoc, Out, STI))
4274  return true;
4275  }
4276 
4277  int64_t FirstOffset = IsLargeOffset ? 1 : (OffsetValue + 1);
4278  int64_t SecondOffset = IsLargeOffset ? 0 : OffsetValue;
4279  if (isLittle())
4280  std::swap(FirstOffset, SecondOffset);
4281 
4282  if (IsLargeOffset) {
4283  TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI);
4284  TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI);
4285  TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI);
4286  TOut.emitRRI(Mips::LBu, ATReg, ATReg, 0, IDLoc, STI);
4287  TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI);
4288  TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);
4289  } else {
4290  TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI);
4291  TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI);
4292  TOut.emitRRI(Mips::SB, ATReg, SrcReg, SecondOffset, IDLoc, STI);
4293  }
4294 
4295  return false;
4296 }
4297 
4298 bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4299  const MCSubtargetInfo *STI) {
4300  if (hasMips32r6() || hasMips64r6()) {
4301  return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
4302  }
4303 
4304  const MCOperand &DstRegOp = Inst.getOperand(0);
4305  assert(DstRegOp.isReg() && "expected register operand kind");
4306  const MCOperand &SrcRegOp = Inst.getOperand(1);
4307  assert(SrcRegOp.isReg() && "expected register operand kind");
4308  const MCOperand &OffsetImmOp = Inst.getOperand(2);
4309  assert(OffsetImmOp.isImm() && "expected immediate operand kind");
4310 
4311  MipsTargetStreamer &TOut = getTargetStreamer();
4312  unsigned DstReg = DstRegOp.getReg();
4313  unsigned SrcReg = SrcRegOp.getReg();
4314  int64_t OffsetValue = OffsetImmOp.getImm();
4315 
4316  // Compute left/right load/store offsets.
4317  bool IsLargeOffset = !(isInt<16>(OffsetValue + 3) && isInt<16>(OffsetValue));
4318  int64_t LxlOffset = IsLargeOffset ? 0 : OffsetValue;
4319  int64_t LxrOffset = IsLargeOffset ? 3 : (OffsetValue + 3);
4320  if (isLittle())
4321  std::swap(LxlOffset, LxrOffset);
4322 
4323  bool IsLoadInst = (Inst.getOpcode() == Mips::Ulw);
4324  bool DoMove = IsLoadInst && (SrcReg == DstReg) && !IsLargeOffset;
4325  unsigned TmpReg = SrcReg;
4326  if (IsLargeOffset || DoMove) {
4327  warnIfNoMacro(IDLoc);
4328  TmpReg = getATReg(IDLoc);
4329  if (!TmpReg)
4330  return true;
4331  }
4332 
4333  if (IsLargeOffset) {
4334  if (loadImmediate(OffsetValue, TmpReg, SrcReg, !ABI.ArePtrs64bit(), true,
4335  IDLoc, Out, STI))
4336  return true;
4337  }
4338 
4339  if (DoMove)
4340  std::swap(DstReg, TmpReg);
4341 
4342  unsigned XWL = IsLoadInst ? Mips::LWL : Mips::SWL;
4343  unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR;
4344  TOut.emitRRI(XWL, DstReg, TmpReg, LxlOffset, IDLoc, STI);
4345  TOut.emitRRI(XWR, DstReg, TmpReg, LxrOffset, IDLoc, STI);
4346 
4347  if (DoMove)
4348  TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI);
4349 
4350  return false;
4351 }
4352 
4353 bool MipsAsmParser::expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4354  const MCSubtargetInfo *STI) {
4355  MipsTargetStreamer &TOut = getTargetStreamer();
4356 
4357  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
4358  assert(Inst.getOperand(0).isReg() &&
4359  Inst.getOperand(1).isReg() &&
4360  Inst.getOperand(2).isReg() && "Invalid instruction operand.");
4361 
4362  unsigned DstReg = Inst.getOperand(0).getReg();
4363  unsigned SrcReg = Inst.getOperand(1).getReg();
4364  unsigned OpReg = Inst.getOperand(2).getReg();
4365  unsigned OpCode;
4366 
4367  warnIfNoMacro(IDLoc);
4368 
4369  switch (Inst.getOpcode()) {
4370  case Mips::SGE:
4371  OpCode = Mips::SLT;
4372  break;
4373  case Mips::SGEU:
4374  OpCode = Mips::SLTu;
4375  break;
4376  default:
4377  llvm_unreachable("unexpected 'sge' opcode");
4378  }
4379 
4380  // $SrcReg >= $OpReg is equal to (not ($SrcReg < $OpReg))
4381  TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI);
4382  TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4383 
4384  return false;
4385 }
4386 
4387 bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4388  const MCSubtargetInfo *STI) {
4389  MipsTargetStreamer &TOut = getTargetStreamer();
4390 
4391  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
4392  assert(Inst.getOperand(0).isReg() &&
4393  Inst.getOperand(1).isReg() &&
4394  Inst.getOperand(2).isImm() && "Invalid instruction operand.");
4395 
4396  unsigned DstReg = Inst.getOperand(0).getReg();
4397  unsigned SrcReg = Inst.getOperand(1).getReg();
4398  int64_t ImmValue = Inst.getOperand(2).getImm();
4399  unsigned OpRegCode, OpImmCode;
4400 
4401  warnIfNoMacro(IDLoc);
4402 
4403  switch (Inst.getOpcode()) {
4404  case Mips::SGEImm:
4405  case Mips::SGEImm64:
4406  OpRegCode = Mips::SLT;
4407  OpImmCode = Mips::SLTi;
4408  break;
4409  case Mips::SGEUImm:
4410  case Mips::SGEUImm64:
4411  OpRegCode = Mips::SLTu;
4412  OpImmCode = Mips::SLTiu;
4413  break;
4414  default:
4415  llvm_unreachable("unexpected 'sge' opcode with immediate");
4416  }
4417 
4418  // $SrcReg >= Imm is equal to (not ($SrcReg < Imm))
4419  if (isInt<16>(ImmValue)) {
4420  // Use immediate version of STL.
4421  TOut.emitRRI(OpImmCode, DstReg, SrcReg, ImmValue, IDLoc, STI);
4422  TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4423  } else {
4424  unsigned ImmReg = DstReg;
4425  if (DstReg == SrcReg) {
4426  unsigned ATReg = getATReg(Inst.getLoc());
4427  if (!ATReg)
4428  return true;
4429  ImmReg = ATReg;
4430  }
4431 
4432  if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
4433  false, IDLoc, Out, STI))
4434  return true;
4435 
4436  TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI);
4437  TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4438  }
4439 
4440  return false;
4441 }
4442 
4443 bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4444  const MCSubtargetInfo *STI) {
4445  MipsTargetStreamer &TOut = getTargetStreamer();
4446 
4447  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
4448  assert(Inst.getOperand(0).isReg() &&
4449  Inst.getOperand(1).isReg() &&
4450  Inst.getOperand(2).isImm() && "Invalid instruction operand.");
4451 
4452  unsigned DstReg = Inst.getOperand(0).getReg();
4453  unsigned SrcReg = Inst.getOperand(1).getReg();
4454  unsigned ImmReg = DstReg;
4455  int64_t ImmValue = Inst.getOperand(2).getImm();
4456  unsigned OpCode;
4457 
4458  warnIfNoMacro(IDLoc);
4459 
4460  switch (Inst.getOpcode()) {
4461  case Mips::SGTImm:
4462  case Mips::SGTImm64:
4463  OpCode = Mips::SLT;
4464  break;
4465  case Mips::SGTUImm:
4466  case Mips::SGTUImm64:
4467  OpCode = Mips::SLTu;
4468  break;
4469  default:
4470  llvm_unreachable("unexpected 'sgt' opcode with immediate");
4471  }
4472 
4473  if (DstReg == SrcReg) {
4474  unsigned ATReg = getATReg(Inst.getLoc());
4475  if (!ATReg)
4476  return true;
4477  ImmReg = ATReg;
4478  }
4479 
4480  if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
4481  false, IDLoc, Out, STI))
4482  return true;
4483 
4484  // $SrcReg > $ImmReg is equal to $ImmReg < $SrcReg
4485  TOut.emitRRR(OpCode, DstReg, ImmReg, SrcReg, IDLoc, STI);
4486 
4487  return false;
4488 }
4489 
4490 bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
4491  MCStreamer &Out,
4492  const MCSubtargetInfo *STI) {
4493  MipsTargetStreamer &TOut = getTargetStreamer();
4494 
4495  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
4496  assert(Inst.getOperand(0).isReg() &&
4497  Inst.getOperand(1).isReg() &&
4498  Inst.getOperand(2).isImm() && "Invalid instruction operand.");
4499 
4500  unsigned ATReg = Mips::NoRegister;
4501  unsigned FinalDstReg = Mips::NoRegister;
4502  unsigned DstReg = Inst.getOperand(0).getReg();
4503  unsigned SrcReg = Inst.getOperand(1).getReg();
4504  int64_t ImmValue = Inst.getOperand(2).getImm();
4505 
4506  bool Is32Bit = isInt<32>(ImmValue) || (!isGP64bit() && isUInt<32>(ImmValue));
4507 
4508  unsigned FinalOpcode = Inst.getOpcode();
4509 
4510  if (DstReg == SrcReg) {
4511  ATReg = getATReg(Inst.getLoc());
4512  if (!ATReg)
4513  return true;
4514  FinalDstReg = DstReg;
4515  DstReg = ATReg;
4516  }
4517 
4518  if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false,
4519  Inst.getLoc(), Out, STI)) {
4520  switch (FinalOpcode) {
4521  default:
4522  llvm_unreachable("unimplemented expansion");
4523  case Mips::ADDi:
4524  FinalOpcode = Mips::ADD;
4525  break;
4526  case Mips::ADDiu:
4527  FinalOpcode = Mips::ADDu;
4528  break;
4529  case Mips::ANDi:
4530  FinalOpcode = Mips::AND;
4531  break;
4532  case Mips::NORImm:
4533  FinalOpcode = Mips::NOR;
4534  break;
4535  case Mips::ORi:
4536  FinalOpcode = Mips::OR;
4537  break;
4538  case Mips::SLTi:
4539  FinalOpcode = Mips::SLT;
4540  break;
4541  case Mips::SLTiu:
4542  FinalOpcode = Mips::SLTu;
4543  break;
4544  case Mips::XORi:
4545  FinalOpcode = Mips::XOR;
4546  break;
4547  case Mips::ADDi_MM:
4548  FinalOpcode = Mips::ADD_MM;
4549  break;
4550  case Mips::ADDiu_MM:
4551  FinalOpcode = Mips::ADDu_MM;
4552  break;
4553  case Mips::ANDi_MM:
4554  FinalOpcode = Mips::AND_MM;
4555  break;
4556  case Mips::ORi_MM:
4557  FinalOpcode = Mips::OR_MM;
4558  break;
4559  case Mips::SLTi_MM:
4560  FinalOpcode = Mips::SLT_MM;
4561  break;
4562  case Mips::SLTiu_MM:
4563  FinalOpcode = Mips::SLTu_MM;
4564  break;
4565  case Mips::XORi_MM:
4566  FinalOpcode = Mips::XOR_MM;
4567  break;
4568  case Mips::ANDi64:
4569  FinalOpcode = Mips::AND64;
4570  break;
4571  case Mips::NORImm64:
4572  FinalOpcode = Mips::NOR64;
4573  break;
4574  case Mips::ORi64:
4575  FinalOpcode = Mips::OR64;
4576  break;
4577  case Mips::SLTImm64:
4578  FinalOpcode = Mips::SLT64;
4579  break;
4580  case Mips::SLTUImm64:
4581  FinalOpcode = Mips::SLTu64;
4582  break;
4583  case Mips::XORi64:
4584  FinalOpcode = Mips::XOR64;
4585  break;
4586  }
4587 
4588  if (FinalDstReg == Mips::NoRegister)
4589  TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI);
4590  else
4591  TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI);
4592  return false;
4593  }
4594  return true;
4595 }
4596 
4597 bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4598  const MCSubtargetInfo *STI) {
4599  MipsTargetStreamer &TOut = getTargetStreamer();
4600  unsigned ATReg = Mips::NoRegister;
4601  unsigned DReg = Inst.getOperand(0).getReg();
4602  unsigned SReg = Inst.getOperand(1).getReg();
4603  unsigned TReg = Inst.getOperand(2).getReg();
4604  unsigned TmpReg = DReg;
4605 
4606  unsigned FirstShift = Mips::NOP;
4607  unsigned SecondShift = Mips::NOP;
4608 
4609  if (hasMips32r2()) {
4610  if (DReg == SReg) {
4611  TmpReg = getATReg(Inst.getLoc());
4612  if (!TmpReg)
4613  return true;
4614  }
4615 
4616  if (Inst.getOpcode() == Mips::ROL) {
4617  TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4618  TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
4619  return false;
4620  }
4621 
4622  if (Inst.getOpcode() == Mips::ROR) {
4623  TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
4624  return false;
4625  }
4626 
4627  return true;
4628  }
4629 
4630  if (hasMips32()) {
4631  switch (Inst.getOpcode()) {
4632  default:
4633  llvm_unreachable("unexpected instruction opcode");
4634  case Mips::ROL:
4635  FirstShift = Mips::SRLV;
4636  SecondShift = Mips::SLLV;
4637  break;
4638  case Mips::ROR:
4639  FirstShift = Mips::SLLV;
4640  SecondShift = Mips::SRLV;
4641  break;
4642  }
4643 
4644  ATReg = getATReg(Inst.getLoc());
4645  if (!ATReg)
4646  return true;
4647 
4648  TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4649  TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
4650  TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
4651  TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
4652 
4653  return false;
4654  }
4655 
4656  return true;
4657 }
4658 
4659 bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc,
4660  MCStreamer &Out,
4661  const MCSubtargetInfo *STI) {
4662  MipsTargetStreamer &TOut = getTargetStreamer();
4663  unsigned ATReg = Mips::NoRegister;
4664  unsigned DReg = Inst.getOperand(0).getReg();
4665  unsigned SReg = Inst.getOperand(1).getReg();
4666  int64_t ImmValue = Inst.getOperand(2).getImm();
4667 
4668  unsigned FirstShift = Mips::NOP;
4669  unsigned SecondShift = Mips::NOP;
4670 
4671  if (hasMips32r2()) {
4672  if (Inst.getOpcode() == Mips::ROLImm) {
4673  uint64_t MaxShift = 32;
4674  uint64_t ShiftValue = ImmValue;
4675  if (ImmValue != 0)
4676  ShiftValue = MaxShift - ImmValue;
4677  TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
4678  return false;
4679  }
4680 
4681  if (Inst.getOpcode() == Mips::RORImm) {
4682  TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI);
4683  return false;
4684  }
4685 
4686  return true;
4687  }
4688 
4689  if (hasMips32()) {
4690  if (ImmValue == 0) {
4691  TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI);
4692  return false;
4693  }
4694 
4695  switch (Inst.getOpcode()) {
4696  default:
4697  llvm_unreachable("unexpected instruction opcode");
4698  case Mips::ROLImm:
4699  FirstShift = Mips::SLL;
4700  SecondShift = Mips::SRL;
4701  break;
4702  case Mips::RORImm:
4703  FirstShift = Mips::SRL;
4704  SecondShift = Mips::SLL;
4705  break;
4706  }
4707 
4708  ATReg = getATReg(Inst.getLoc());
4709  if (!ATReg)
4710  return true;
4711 
4712  TOut.emitRRI(FirstShift, ATReg, SReg, ImmValue, Inst.getLoc(), STI);
4713  TOut.emitRRI(SecondShift, DReg, SReg, 32 - ImmValue, Inst.getLoc(), STI);
4714  TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
4715 
4716  return false;
4717  }
4718 
4719  return true;
4720 }
4721 
4722 bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4723  const MCSubtargetInfo *STI) {
4724  MipsTargetStreamer &TOut = getTargetStreamer();
4725  unsigned ATReg = Mips::NoRegister;
4726  unsigned DReg = Inst.getOperand(0).getReg();
4727  unsigned SReg = Inst.getOperand(1).getReg();
4728  unsigned TReg = Inst.getOperand(2).getReg();
4729  unsigned TmpReg = DReg;
4730 
4731  unsigned FirstShift = Mips::NOP;
4732  unsigned SecondShift = Mips::NOP;
4733 
4734  if (hasMips64r2()) {
4735  if (TmpReg == SReg) {
4736  TmpReg = getATReg(Inst.getLoc());
4737  if (!TmpReg)
4738  return true;
4739  }
4740 
4741  if (Inst.getOpcode() == Mips::DROL) {
4742  TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4743  TOut.emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
4744  return false;
4745  }
4746 
4747  if (Inst.getOpcode() == Mips::DROR) {
4748  TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
4749  return false;
4750  }
4751 
4752  return true;
4753  }
4754 
4755  if (hasMips64()) {
4756  switch (Inst.getOpcode()) {
4757  default:
4758  llvm_unreachable("unexpected instruction opcode");
4759  case Mips::DROL:
4760  FirstShift = Mips::DSRLV;
4761  SecondShift = Mips::DSLLV;
4762  break;
4763  case Mips::DROR:
4764  FirstShift = Mips::DSLLV;
4765  SecondShift = Mips::DSRLV;
4766  break;
4767  }
4768 
4769  ATReg = getATReg(Inst.getLoc());
4770  if (!ATReg)
4771  return true;
4772 
4773  TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4774  TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
4775  TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
4776  TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
4777 
4778  return false;
4779  }
4780 
4781  return true;
4782 }
4783 
4784 bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
4785  MCStreamer &Out,
4786  const MCSubtargetInfo *STI) {
4787  MipsTargetStreamer &TOut = getTargetStreamer();
4788  unsigned ATReg = Mips::NoRegister;
4789  unsigned DReg = Inst.getOperand(0).getReg();
4790  unsigned SReg = Inst.getOperand(1).getReg();
4791  int64_t ImmValue = Inst.getOperand(2).getImm() % 64;
4792 
4793  unsigned FirstShift = Mips::NOP;
4794  unsigned SecondShift = Mips::NOP;
4795 
4796  MCInst TmpInst;
4797 
4798  if (hasMips64r2()) {
4799  unsigned FinalOpcode = Mips::NOP;
4800  if (ImmValue == 0)
4801  FinalOpcode = Mips::DROTR;
4802  else if (ImmValue % 32 == 0)
4803  FinalOpcode = Mips::DROTR32;
4804  else if ((ImmValue >= 1) && (ImmValue <= 32)) {
4805  if (Inst.getOpcode() == Mips::DROLImm)
4806  FinalOpcode = Mips::DROTR32;
4807  else
4808  FinalOpcode = Mips::DROTR;
4809  } else if (ImmValue >= 33) {
4810  if (Inst.getOpcode() == Mips::DROLImm)
4811  FinalOpcode = Mips::DROTR;
4812  else
4813  FinalOpcode = Mips::DROTR32;
4814  }
4815 
4816  uint64_t ShiftValue = ImmValue % 32;
4817  if (Inst.getOpcode() == Mips::DROLImm)
4818  ShiftValue = (32 - ImmValue % 32) % 32;
4819 
4820  TOut.emitRRI(FinalOpcode, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
4821 
4822  return false;
4823  }
4824 
4825  if (hasMips64()) {
4826  if (ImmValue == 0) {
4827  TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI);
4828  return false;
4829  }
4830 
4831  switch (Inst.getOpcode()) {
4832  default:
4833  llvm_unreachable("unexpected instruction opcode");
4834  case Mips::DROLImm:
4835  if ((ImmValue >= 1) && (ImmValue <= 31)) {
4836  FirstShift = Mips::DSLL;
4837  SecondShift = Mips::DSRL32;
4838  }
4839  if (ImmValue == 32) {
4840  FirstShift = Mips::DSLL32;
4841  SecondShift = Mips::DSRL32;
4842  }
4843  if ((ImmValue >= 33) && (ImmValue <= 63)) {
4844  FirstShift = Mips::DSLL32;
4845  SecondShift = Mips::DSRL;
4846  }
4847  break;
4848  case Mips::DRORImm:
4849  if ((ImmValue >= 1) && (ImmValue <= 31)) {
4850  FirstShift = Mips::DSRL;
4851  SecondShift = Mips::DSLL32;
4852  }
4853  if (ImmValue == 32) {
4854  FirstShift = Mips::DSRL32;
4855  SecondShift = Mips::DSLL32;
4856  }
4857  if ((ImmValue >= 33) && (ImmValue <= 63)) {
4858  FirstShift = Mips::DSRL32;
4859  SecondShift = Mips::DSLL;
4860  }
4861  break;
4862  }
4863 
4864  ATReg = getATReg(Inst.getLoc());
4865  if (!ATReg)
4866  return true;
4867 
4868  TOut.emitRRI(FirstShift, ATReg, SReg, ImmValue % 32, Inst.getLoc(), STI);
4869  TOut.emitRRI(SecondShift, DReg, SReg, (32 - ImmValue % 32) % 32,
4870  Inst.getLoc(), STI);
4871  TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
4872 
4873  return false;
4874  }
4875 
4876  return true;
4877 }
4878 
4879 bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4880  const MCSubtargetInfo *STI) {
4881  MipsTargetStreamer &TOut = getTargetStreamer();
4882  unsigned FirstRegOp = Inst.getOperand(0).getReg();
4883  unsigned SecondRegOp = Inst.getOperand(1).getReg();
4884 
4885  TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI);
4886  if (FirstRegOp != SecondRegOp)
4887  TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI);
4888  else
4889  TOut.emitEmptyDelaySlot(false, IDLoc, STI);
4890  TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI);
4891 
4892  return false;
4893 }
4894 
4895 bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4896  const MCSubtargetInfo *STI) {
4897  MipsTargetStreamer &TOut = getTargetStreamer();
4898  unsigned ATReg = Mips::NoRegister;
4899  unsigned DstReg = Inst.getOperand(0).getReg();
4900  unsigned SrcReg = Inst.getOperand(1).getReg();
4901  int32_t ImmValue = Inst.getOperand(2).getImm();
4902 
4903  ATReg = getATReg(IDLoc);
4904  if (!ATReg)
4905  return true;
4906 
4907  loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out,
4908  STI);
4909 
4910  TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT,
4911  SrcReg, ATReg, IDLoc, STI);
4912 
4913  TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
4914 
4915  return false;
4916 }
4917 
4918 bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4919  const MCSubtargetInfo *STI) {
4920  MipsTargetStreamer &TOut = getTargetStreamer();
4921  unsigned ATReg = Mips::NoRegister;
4922  unsigned DstReg = Inst.getOperand(0).getReg();
4923  unsigned SrcReg = Inst.getOperand(1).getReg();
4924  unsigned TmpReg = Inst.getOperand(2).getReg();
4925 
4926  ATReg = getATReg(Inst.getLoc());
4927  if (!ATReg)
4928  return true;
4929 
4930  TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT,
4931  SrcReg, TmpReg, IDLoc, STI);
4932 
4933  TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
4934 
4935  TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32,
4936  DstReg, DstReg, 0x1F, IDLoc, STI);
4937 
4938  TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI);
4939 
4940  if (useTraps()) {
4941  TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI);
4942  } else {
4943  MCContext & Context = TOut.getStreamer().getContext();
4944  MCSymbol * BrTarget = Context.createTempSymbol();
4945  MCOperand LabelOp =
4946  MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
4947 
4948  TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI);
4949  if (AssemblerOptions.back()->isReorder())
4950  TOut.emitNop(IDLoc, STI);
4951  TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI);
4952 
4953  TOut.getStreamer().EmitLabel(BrTarget);
4954  }
4955  TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
4956 
4957  return false;
4958 }
4959 
4960 bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4961  const MCSubtargetInfo *STI) {
4962  MipsTargetStreamer &TOut = getTargetStreamer();
4963  unsigned ATReg = Mips::NoRegister;
4964  unsigned DstReg = Inst.getOperand(0).getReg();
4965  unsigned SrcReg = Inst.getOperand(1).getReg();
4966  unsigned TmpReg = Inst.getOperand(2).getReg();
4967 
4968  ATReg = getATReg(IDLoc);
4969  if (!ATReg)
4970  return true;
4971 
4972  TOut.emitRR(Inst.getOpcode() == Mips::MULOUMacro ? Mips::MULTu : Mips::DMULTu,
4973  SrcReg, TmpReg, IDLoc, STI);
4974 
4975  TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI);
4976  TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
4977  if (useTraps()) {
4978  TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI);
4979  } else {
4980  MCContext & Context = TOut.getStreamer().getContext();
4981  MCSymbol * BrTarget = Context.createTempSymbol();
4982  MCOperand LabelOp =
4983  MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
4984 
4985  TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI);
4986  if (AssemblerOptions.back()->isReorder())
4987  TOut.emitNop(IDLoc, STI);
4988  TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI);
4989 
4990  TOut.getStreamer().EmitLabel(BrTarget);
4991  }
4992 
4993  return false;
4994 }
4995 
4996 bool MipsAsmParser::expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
4997  const MCSubtargetInfo *STI) {
4998  MipsTargetStreamer &TOut = getTargetStreamer();
4999  unsigned DstReg = Inst.getOperand(0).getReg();
5000  unsigned SrcReg = Inst.getOperand(1).getReg();
5001  unsigned TmpReg = Inst.getOperand(2).getReg();
5002 
5003  TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI);
5004  TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
5005 
5006  return false;
5007 }
5008 
5009 // Expand 'ld $<reg> offset($reg2)' to 'lw $<reg>, offset($reg2);
5010 // lw $<reg+1>>, offset+4($reg2)'
5011 // or expand 'sd $<reg> offset($reg2)' to 'sw $<reg>, offset($reg2);
5012 // sw $<reg+1>>, offset+4($reg2)'
5013 // for O32.
5014 bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc,
5015  MCStreamer &Out,
5016  const MCSubtargetInfo *STI,
5017  bool IsLoad) {
5018  if (!isABI_O32())
5019  return true;
5020 
5021  warnIfNoMacro(IDLoc);
5022 
5023  MipsTargetStreamer &TOut = getTargetStreamer();
5024  unsigned Opcode = IsLoad ? Mips::LW : Mips::SW;
5025  unsigned FirstReg = Inst.getOperand(0).getReg();
5026  unsigned SecondReg = nextReg(FirstReg);
5027  unsigned BaseReg = Inst.getOperand(1).getReg();
5028  if (!SecondReg)
5029  return true;
5030 
5031  warnIfRegIndexIsAT(FirstReg, IDLoc);
5032 
5033  assert(Inst.getOperand(2).isImm() &&
5034  "Offset for load macro is not immediate!");
5035 
5036  MCOperand &FirstOffset = Inst.getOperand(2);
5037  signed NextOffset = FirstOffset.getImm() + 4;
5038  MCOperand SecondOffset = MCOperand::createImm(NextOffset);
5039 
5040  if (!isInt<16>(FirstOffset.getImm()) || !isInt<16>(NextOffset))
5041  return true;
5042 
5043  // For loads, clobber the base register with the second load instead of the
5044  // first if the BaseReg == FirstReg.
5045  if (FirstReg != BaseReg || !IsLoad) {
5046  TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
5047  TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
5048  } else {
5049  TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
5050  TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
5051  }
5052 
5053  return false;
5054 }
5055 
5056 
5057 // Expand 's.d $<reg> offset($reg2)' to 'swc1 $<reg+1>, offset($reg2);
5058 // swc1 $<reg>, offset+4($reg2)'
5059 // or if little endian to 'swc1 $<reg>, offset($reg2);
5060 // swc1 $<reg+1>, offset+4($reg2)'
5061 // for Mips1.
5062 bool MipsAsmParser::expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc,
5063  MCStreamer &Out,
5064  const MCSubtargetInfo *STI) {
5065  if (!isABI_O32())
5066  return true;
5067 
5068  warnIfNoMacro(IDLoc);
5069 
5070  MipsTargetStreamer &TOut = getTargetStreamer();
5071  unsigned Opcode = Mips::SWC1;
5072  unsigned FirstReg = Inst.getOperand(0).getReg();
5073  unsigned SecondReg = nextReg(FirstReg);
5074  unsigned BaseReg = Inst.getOperand(1).getReg();
5075  if (!SecondReg)
5076  return true;
5077 
5078  warnIfRegIndexIsAT(FirstReg, IDLoc);
5079 
5080  assert(Inst.getOperand(2).isImm() &&
5081  "Offset for macro is not immediate!");
5082 
5083  MCOperand &FirstOffset = Inst.getOperand(2);
5084  signed NextOffset = FirstOffset.getImm() + 4;
5085  MCOperand SecondOffset = MCOperand::createImm(NextOffset);
5086 
5087  if (!isInt<16>(FirstOffset.getImm()) || !isInt<16>(NextOffset))
5088  return true;
5089 
5090  if (!IsLittleEndian)
5091  std::swap(FirstReg, SecondReg);
5092 
5093  TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
5094  TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
5095 
5096  return false;
5097 }
5098 
5099 bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5100  const MCSubtargetInfo *STI) {
5101  MipsTargetStreamer &TOut = getTargetStreamer();
5102 
5103  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
5104  assert(Inst.getOperand(0).isReg() &&
5105  Inst.getOperand(1).isReg() &&
5106  Inst.getOperand(2).isReg() && "Invalid instruction operand.");
5107 
5108  unsigned DstReg = Inst.getOperand(0).getReg();
5109  unsigned SrcReg = Inst.getOperand(1).getReg();
5110  unsigned OpReg = Inst.getOperand(2).getReg();
5111 
5112  warnIfNoMacro(IDLoc);
5113 
5114  if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) {
5115  TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI);
5116  TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
5117  return false;
5118  }
5119 
5120  unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
5121  TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI);
5122  return false;
5123 }
5124 
5125 bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5126  const MCSubtargetInfo *STI) {
5127  MipsTargetStreamer &TOut = getTargetStreamer();
5128 
5129  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
5130  assert(Inst.getOperand(0).isReg() &&
5131  Inst.getOperand(1).isReg() &&
5132  Inst.getOperand(2).isImm() && "Invalid instruction operand.");
5133 
5134  unsigned DstReg = Inst.getOperand(0).getReg();
5135  unsigned SrcReg = Inst.getOperand(1).getReg();
5136  int64_t Imm = Inst.getOperand(2).getImm();
5137 
5138  warnIfNoMacro(IDLoc);
5139 
5140  if (Imm == 0) {
5141  TOut.emitRRI(Mips::SLTiu, DstReg, SrcReg, 1, IDLoc, STI);
5142  return false;
5143  }
5144 
5145  if (SrcReg == Mips::ZERO) {
5146  Warning(IDLoc, "comparison is always false");
5147  TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu,
5148  DstReg, SrcReg, SrcReg, IDLoc, STI);
5149  return false;
5150  }
5151 
5152  unsigned Opc;
5153  if (Imm > -0x8000 && Imm < 0) {
5154  Imm = -Imm;
5155  Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu;
5156  } else {
5157  Opc = Mips::XORi;
5158  }
5159 
5160  if (!isUInt<16>(Imm)) {
5161  unsigned ATReg = getATReg(IDLoc);
5162  if (!ATReg)
5163  return true;
5164 
5165  if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc,
5166  Out, STI))
5167  return true;
5168 
5169  TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI);
5170  TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
5171  return false;
5172  }
5173 
5174  TOut.emitRRI(Opc, DstReg, SrcReg, Imm, IDLoc, STI);
5175  TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
5176  return false;
5177 }
5178 
5179 // Map the DSP accumulator and control register to the corresponding gpr
5180 // operand. Unlike the other alias, the m(f|t)t(lo|hi|acx) instructions
5181 // do not map the DSP registers contigously to gpr registers.
5182 static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
5183  switch (Inst.getOpcode()) {
5184  case Mips::MFTLO:
5185  case Mips::MTTLO:
5186  switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
5187  case Mips::AC0:
5188  return Mips::ZERO;
5189  case Mips::AC1:
5190  return Mips::A0;
5191  case Mips::AC2:
5192  return Mips::T0;
5193  case Mips::AC3:
5194  return Mips::T4;
5195  default:
5196  llvm_unreachable("Unknown register for 'mttr' alias!");
5197  }
5198  case Mips::MFTHI:
5199  case Mips::MTTHI:
5200  switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
5201  case Mips::AC0:
5202  return Mips::AT;
5203  case Mips::AC1:
5204  return Mips::A1;
5205  case Mips::AC2:
5206  return Mips::T1;
5207  case Mips::AC3:
5208  return Mips::T5;
5209  default:
5210  llvm_unreachable("Unknown register for 'mttr' alias!");
5211  }
5212  case Mips::MFTACX:
5213  case Mips::MTTACX:
5214  switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
5215  case Mips::AC0:
5216  return Mips::V0;
5217  case Mips::AC1:
5218  return Mips::A2;
5219  case Mips::AC2:
5220  return Mips::T2;
5221  case Mips::AC3:
5222  return Mips::T6;
5223  default:
5224  llvm_unreachable("Unknown register for 'mttr' alias!");
5225  }
5226  case Mips::MFTDSP:
5227  case Mips::MTTDSP:
5228  return Mips::S0;
5229  default:
5230  llvm_unreachable("Unknown instruction for 'mttr' dsp alias!");
5231  }
5232 }
5233 
5234 // Map the floating point register operand to the corresponding register
5235 // operand.
5236 static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) {
5237  switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg()) {
5238  case Mips::F0: return Mips::ZERO;
5239  case Mips::F1: return Mips::AT;
5240  case Mips::F2: return Mips::V0;
5241  case Mips::F3: return Mips::V1;
5242  case Mips::F4: return Mips::A0;
5243  case Mips::F5: return Mips::A1;
5244  case Mips::F6: return Mips::A2;
5245  case Mips::F7: return Mips::A3;
5246  case Mips::F8: return Mips::T0;
5247  case Mips::F9: return Mips::T1;
5248  case Mips::F10: return Mips::T2;
5249  case Mips::F11: return Mips::T3;
5250  case Mips::F12: return Mips::T4;
5251  case Mips::F13: return Mips::T5;
5252  case Mips::F14: return Mips::T6;
5253  case Mips::F15: return Mips::T7;
5254  case Mips::F16: return Mips::S0;
5255  case Mips::F17: return Mips::S1;
5256  case Mips::F18: return Mips::S2;
5257  case Mips::F19: return Mips::S3;
5258  case Mips::F20: return Mips::S4;
5259  case Mips::F21: return Mips::S5;
5260  case Mips::F22: return Mips::S6;
5261  case Mips::F23: return Mips::S7;
5262  case Mips::F24: return Mips::T8;
5263  case Mips::F25: return Mips::T9;
5264  case Mips::F26: return Mips::K0;
5265  case Mips::F27: return Mips::K1;
5266  case Mips::F28: return Mips::GP;
5267  case Mips::F29: return Mips::SP;
5268  case Mips::F30: return Mips::FP;
5269  case Mips::F31: return Mips::RA;
5270  default: llvm_unreachable("Unknown register for mttc1 alias!");
5271  }
5272 }
5273 
5274 // Map the coprocessor operand the corresponding gpr register operand.
5275 static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) {
5276  switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg()) {
5277  case Mips::COP00: return Mips::ZERO;
5278  case Mips::COP01: return Mips::AT;
5279  case Mips::COP02: return Mips::V0;
5280  case Mips::COP03: return Mips::V1;
5281  case Mips::COP04: return Mips::A0;
5282  case Mips::COP05: return Mips::A1;
5283  case Mips::COP06: return Mips::A2;
5284  case Mips::COP07: return Mips::A3;
5285  case Mips::COP08: return Mips::T0;
5286  case Mips::COP09: return Mips::T1;
5287  case Mips::COP010: return Mips::T2;
5288  case Mips::COP011: return Mips::T3;
5289  case Mips::COP012: return Mips::T4;
5290  case Mips::COP013: return Mips::T5;
5291  case Mips::COP014: return Mips::T6;
5292  case Mips::COP015: return Mips::T7;
5293  case Mips::COP016: return Mips::S0;
5294  case Mips::COP017: return Mips::S1;
5295  case Mips::COP018: return Mips::S2;
5296  case Mips::COP019: return Mips::S3;
5297  case Mips::COP020: return Mips::S4;
5298  case Mips::COP021: return Mips::S5;
5299  case Mips::COP022: return Mips::S6;
5300  case Mips::COP023: return Mips::S7;
5301  case Mips::COP024: return Mips::T8;
5302  case Mips::COP025: return Mips::T9;
5303  case Mips::COP026: return Mips::K0;
5304  case Mips::COP027: return Mips::K1;
5305  case Mips::COP028: return Mips::GP;
5306  case Mips::COP029: return Mips::SP;
5307  case Mips::COP030: return Mips::FP;
5308  case Mips::COP031: return Mips::RA;
5309  default: llvm_unreachable("Unknown register for mttc0 alias!");
5310  }
5311 }
5312 
5313 /// Expand an alias of 'mftr' or 'mttr' into the full instruction, by producing
5314 /// an mftr or mttr with the correctly mapped gpr register, u, sel and h bits.
5315 bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
5316  const MCSubtargetInfo *STI) {
5317  MipsTargetStreamer &TOut = getTargetStreamer();
5318  unsigned rd = 0;
5319  unsigned u = 1;
5320  unsigned sel = 0;
5321  unsigned h = 0;
5322  bool IsMFTR = false;
5323  switch (Inst.getOpcode()) {
5324  case Mips::MFTC0:
5325  IsMFTR = true;
5327  case Mips::MTTC0:
5328  u = 0;
5329  rd = getRegisterForMxtrC0(Inst, IsMFTR);
5330  sel = Inst.getOperand(2).getImm();
5331  break;
5332  case Mips::MFTGPR:
5333  IsMFTR = true;
5335  case Mips::MTTGPR:
5336  rd = Inst.getOperand(IsMFTR ? 1 : 0).getReg();
5337  break;
5338  case Mips::MFTLO:
5339  case Mips::MFTHI:
5340  case Mips::MFTACX:
5341  case Mips::MFTDSP:
5342  IsMFTR = true;
5344  case Mips::MTTLO:
5345  case Mips::MTTHI:
5346  case Mips::MTTACX:
5347  case Mips::MTTDSP:
5348  rd = getRegisterForMxtrDSP(Inst, IsMFTR);
5349  sel = 1;
5350  break;
5351  case Mips::MFTHC1:
5352  h = 1;
5354  case Mips::MFTC1:
5355  IsMFTR = true;
5356  rd = getRegisterForMxtrFP(Inst, IsMFTR);
5357  sel = 2;
5358  break;
5359  case Mips::MTTHC1:
5360  h = 1;
5362  case Mips::MTTC1:
5363  rd = getRegisterForMxtrFP(Inst, IsMFTR);
5364  sel = 2;
5365  break;
5366  case Mips::CFTC1:
5367  IsMFTR = true;
5369  case Mips::CTTC1:
5370  rd = getRegisterForMxtrFP(Inst, IsMFTR);
5371  sel = 3;
5372  break;
5373  }
5374  unsigned Op0 = IsMFTR ? Inst.getOperand(0).getReg() : rd;
5375  unsigned Op1 =
5376  IsMFTR ? rd
5377  : (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg()
5378  : Inst.getOperand(0).getReg());
5379 
5380  TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc,
5381  STI);
5382  return false;
5383 }
5384 
5385 unsigned
5386 MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
5387  const OperandVector &Operands) {
5388  switch (Inst.getOpcode()) {
5389  default:
5390  return Match_Success;
5391  case Mips::DATI:
5392  case Mips::DAHI:
5393  if (static_cast<MipsOperand &>(*Operands[1])
5394  .isValidForTie(static_cast<MipsOperand &>(*Operands[2])))
5395  return Match_Success;
5396  return Match_RequiresSameSrcAndDst;
5397  }
5398 }
5399 
5400 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
5401  switch (Inst.getOpcode()) {
5402  // As described by the MIPSR6 spec, daui must not use the zero operand for
5403  // its source operand.
5404  case Mips::DAUI:
5405  if (Inst.getOperand(1).getReg() == Mips::ZERO ||
5406  Inst.getOperand(1).getReg() == Mips::ZERO_64)
5407  return Match_RequiresNoZeroRegister;
5408  return Match_Success;
5409  // As described by the Mips32r2 spec, the registers Rd and Rs for
5410  // jalr.hb must be different.
5411  // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction
5412  // and registers Rd and Base for microMIPS lwp instruction
5413  case Mips::JALR_HB:
5414  case Mips::JALR_HB64:
5415  case Mips::JALRC_HB_MMR6:
5416  case Mips::JALRC_MMR6:
5417  if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
5418  return Match_RequiresDifferentSrcAndDst;
5419  return Match_Success;
5420  case Mips::LWP_MM:
5421  if (Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg())
5422  return Match_RequiresDifferentSrcAndDst;
5423  return Match_Success;
5424  case Mips::SYNC:
5425  if (Inst.getOperand(0).getImm() != 0 && !hasMips32())
5426  return Match_NonZeroOperandForSync;
5427  return Match_Success;
5428  case Mips::MFC0:
5429  case Mips::MTC0:
5430  case Mips::MTC2:
5431  case Mips::MFC2:
5432  if (Inst.getOperand(2).getImm() != 0 && !hasMips32())
5433  return Match_NonZeroOperandForMTCX;
5434  return Match_Success;
5435  // As described the MIPSR6 spec, the compact branches that compare registers
5436  // must:
5437  // a) Not use the zero register.
5438  // b) Not use the same register twice.
5439  // c) rs < rt for bnec, beqc.
5440  // NB: For this case, the encoding will swap the operands as their
5441  // ordering doesn't matter. GAS performs this transformation too.
5442  // Hence, that constraint does not have to be enforced.
5443  //
5444  // The compact branches that branch iff the signed addition of two registers
5445  // would overflow must have rs >= rt. That can be handled like beqc/bnec with
5446  // operand swapping. They do not have restriction of using the zero register.
5447  case Mips::BLEZC: case Mips::BLEZC_MMR6:
5448  case Mips::BGEZC: case Mips::BGEZC_MMR6:
5449  case Mips::BGTZC: case Mips::BGTZC_MMR6:
5450  case Mips::BLTZC: case Mips::BLTZC_MMR6:
5451  case Mips::BEQZC: case Mips::BEQZC_MMR6:
5452  case Mips::BNEZC: case Mips::BNEZC_MMR6:
5453  case Mips::BLEZC64:
5454  case Mips::BGEZC64:
5455  case Mips::BGTZC64:
5456  case Mips::BLTZC64:
5457  case Mips::BEQZC64:
5458  case Mips::BNEZC64:
5459  if (Inst.getOperand(0).getReg() == Mips::ZERO ||
5460  Inst.getOperand(0).getReg() == Mips::ZERO_64)
5461  return Match_RequiresNoZeroRegister;
5462  return Match_Success;
5463  case Mips::BGEC: case Mips::BGEC_MMR6:
5464  case Mips::BLTC: case Mips::BLTC_MMR6:
5465  case Mips::BGEUC: case Mips::BGEUC_MMR6:
5466  case Mips::BLTUC: case Mips::BLTUC_MMR6:
5467  case Mips::BEQC: case Mips::BEQC_MMR6:
5468  case Mips::BNEC: case Mips::BNEC_MMR6:
5469  case Mips::BGEC64:
5470  case Mips::BLTC64:
5471  case Mips::BGEUC64:
5472  case Mips::BLTUC64:
5473  case Mips::BEQC64:
5474  case Mips::BNEC64:
5475  if (Inst.getOperand(0).getReg() == Mips::ZERO ||
5476  Inst.getOperand(0).getReg() == Mips::ZERO_64)
5477  return Match_RequiresNoZeroRegister;
5478  if (Inst.getOperand(1).getReg() == Mips::ZERO ||
5479  Inst.getOperand(1).getReg() == Mips::ZERO_64)
5480  return Match_RequiresNoZeroRegister;
5481  if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
5482  return Match_RequiresDifferentOperands;
5483  return Match_Success;
5484  case Mips::DINS: {
5485  assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
5486  "Operands must be immediates for dins!");
5487  const signed Pos = Inst.getOperand(2).getImm();
5488  const signed Size = Inst.getOperand(3).getImm();
5489  if ((0 > (Pos + Size)) || ((Pos + Size) > 32))
5490  return Match_RequiresPosSizeRange0_32;
5491  return Match_Success;
5492  }
5493  case Mips::DINSM:
5494  case Mips::DINSU: {
5495  assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
5496  "Operands must be immediates for dinsm/dinsu!");
5497  const signed Pos = Inst.getOperand(2).getImm();
5498  const signed Size = Inst.getOperand(3).getImm();
5499  if ((32 >= (Pos + Size)) || ((Pos + Size) > 64))
5500  return Match_RequiresPosSizeRange33_64;
5501  return Match_Success;
5502  }
5503  case Mips::DEXT: {
5504  assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
5505  "Operands must be immediates for DEXTM!");
5506  const signed Pos = Inst.getOperand(2).getImm();
5507  const signed Size = Inst.getOperand(3).getImm();
5508  if ((1 > (Pos + Size)) || ((Pos + Size) > 63))
5509  return Match_RequiresPosSizeUImm6;
5510  return Match_Success;
5511  }
5512  case Mips::DEXTM:
5513  case Mips::DEXTU: {
5514  assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
5515  "Operands must be immediates for dextm/dextu!");
5516  const signed Pos = Inst.getOperand(2).getImm();
5517  const signed Size = Inst.getOperand(3).getImm();
5518  if ((32 > (Pos + Size)) || ((Pos + Size) > 64))
5519  return Match_RequiresPosSizeRange33_64;
5520  return Match_Success;
5521  }
5522  case Mips::CRC32B: case Mips::CRC32CB:
5523  case Mips::CRC32H: case Mips::CRC32CH:
5524  case Mips::CRC32W: case Mips::CRC32CW:
5525  case Mips::CRC32D: case Mips::CRC32CD:
5526  if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg())
5527  return Match_RequiresSameSrcAndDst;
5528  return Match_Success;
5529  }
5530 
5531  uint64_t TSFlags = getInstDesc(Inst.getOpcode()).TSFlags;
5532  if ((TSFlags & MipsII::HasFCCRegOperand) &&
5533  (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters())
5534  return Match_NoFCCRegisterForCurrentISA;
5535 
5536  return Match_Success;
5537 
5538 }
5539 
5540 static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands,
5541  uint64_t ErrorInfo) {
5542  if (ErrorInfo != ~0ULL && ErrorInfo < Operands.size()) {
5543  SMLoc ErrorLoc = Operands[ErrorInfo]->getStartLoc();
5544  if (ErrorLoc == SMLoc())
5545  return Loc;
5546  return ErrorLoc;
5547  }
5548  return Loc;
5549 }
5550 
5551 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
5552  OperandVector &Operands,
5553  MCStreamer &Out,
5554  uint64_t &ErrorInfo,
5555  bool MatchingInlineAsm) {
5556  MCInst Inst;
5557  unsigned MatchResult =
5558  MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
5559 
5560  switch (MatchResult) {
5561  case Match_Success:
5562  if (processInstruction(Inst, IDLoc, Out, STI))
5563  return true;
5564  return false;
5565  case Match_MissingFeature:
5566  Error(IDLoc, "instruction requires a CPU feature not currently enabled");
5567  return true;
5568  case Match_InvalidOperand: {
5569  SMLoc ErrorLoc = IDLoc;
5570  if (ErrorInfo != ~0ULL) {
5571  if (ErrorInfo >= Operands.size())
5572  return Error(IDLoc, "too few operands for instruction");
5573 
5574  ErrorLoc = Operands[ErrorInfo]->getStartLoc();
5575  if (ErrorLoc == SMLoc())
5576  ErrorLoc = IDLoc;
5577  }
5578 
5579  return Error(ErrorLoc, "invalid operand for instruction");
5580  }
5581  case Match_NonZeroOperandForSync:
5582  return Error(IDLoc,
5583  "s-type must be zero or unspecified for pre-MIPS32 ISAs");
5584  case Match_NonZeroOperandForMTCX:
5585  return Error(IDLoc, "selector must be zero for pre-MIPS32 ISAs");
5586  case Match_MnemonicFail:
5587  return Error(IDLoc, "invalid instruction");
5588  case Match_RequiresDifferentSrcAndDst:
5589  return Error(IDLoc, "source and destination must be different");
5590  case Match_RequiresDifferentOperands:
5591  return Error(IDLoc, "registers must be different");
5592  case Match_RequiresNoZeroRegister:
5593  return Error(IDLoc, "invalid operand ($zero) for instruction");
5594  case Match_RequiresSameSrcAndDst:
5595  return Error(IDLoc, "source and destination must match");
5596  case Match_NoFCCRegisterForCurrentISA:
5597  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5598  "non-zero fcc register doesn't exist in current ISA level");
5599  case Match_Immz:
5600  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'");
5601  case Match_UImm1_0:
5602  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5603  "expected 1-bit unsigned immediate");
5604  case Match_UImm2_0:
5605  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5606  "expected 2-bit unsigned immediate");
5607  case Match_UImm2_1:
5608  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5609  "expected immediate in range 1 .. 4");
5610  case Match_UImm3_0:
5611  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5612  "expected 3-bit unsigned immediate");
5613  case Match_UImm4_0:
5614  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5615  "expected 4-bit unsigned immediate");
5616  case Match_SImm4_0:
5617  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5618  "expected 4-bit signed immediate");
5619  case Match_UImm5_0:
5620  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5621  "expected 5-bit unsigned immediate");
5622  case Match_SImm5_0:
5623  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5624  "expected 5-bit signed immediate");
5625  case Match_UImm5_1:
5626  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5627  "expected immediate in range 1 .. 32");
5628  case Match_UImm5_32:
5629  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5630  "expected immediate in range 32 .. 63");
5631  case Match_UImm5_33:
5632  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5633  "expected immediate in range 33 .. 64");
5634  case Match_UImm5_0_Report_UImm6:
5635  // This is used on UImm5 operands that have a corresponding UImm5_32
5636  // operand to avoid confusing the user.
5637  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5638  "expected 6-bit unsigned immediate");
5639  case Match_UImm5_Lsl2:
5640  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5641  "expected both 7-bit unsigned immediate and multiple of 4");
5642  case Match_UImmRange2_64:
5643  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5644  "expected immediate in range 2 .. 64");
5645  case Match_UImm6_0:
5646  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5647  "expected 6-bit unsigned immediate");
5648  case Match_UImm6_Lsl2:
5649  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5650  "expected both 8-bit unsigned immediate and multiple of 4");
5651  case Match_SImm6_0:
5652  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5653  "expected 6-bit signed immediate");
5654  case Match_UImm7_0:
5655  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5656  "expected 7-bit unsigned immediate");
5657  case Match_UImm7_N1:
5658  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5659  "expected immediate in range -1 .. 126");
5660  case Match_SImm7_Lsl2:
5661  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5662  "expected both 9-bit signed immediate and multiple of 4");
5663  case Match_UImm8_0:
5664  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5665  "expected 8-bit unsigned immediate");
5666  case Match_UImm10_0:
5667  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5668  "expected 10-bit unsigned immediate");
5669  case Match_SImm10_0:
5670  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5671  "expected 10-bit signed immediate");
5672  case Match_SImm11_0:
5673  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5674  "expected 11-bit signed immediate");
5675  case Match_UImm16:
5676  case Match_UImm16_Relaxed:
5677  case Match_UImm16_AltRelaxed:
5678  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5679  "expected 16-bit unsigned immediate");
5680  case Match_SImm16:
5681  case Match_SImm16_Relaxed:
5682  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5683  "expected 16-bit signed immediate");
5684  case Match_SImm19_Lsl2:
5685  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5686  "expected both 19-bit signed immediate and multiple of 4");
5687  case Match_UImm20_0:
5688  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5689  "expected 20-bit unsigned immediate");
5690  case Match_UImm26_0:
5691  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5692  "expected 26-bit unsigned immediate");
5693  case Match_SImm32:
5694  case Match_SImm32_Relaxed:
5695  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5696  "expected 32-bit signed immediate");
5697  case Match_UImm32_Coerced:
5698  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5699  "expected 32-bit immediate");
5700  case Match_MemSImm9:
5701  return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
5702