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14 #ifndef LLVM_LIB_CODEGEN_INTERFERENCECACHE_H
15 #define LLVM_LIB_CODEGEN_INTERFERENCECACHE_H
29 class MachineFunction;
30 class TargetRegisterInfo;
35 struct BlockInterference {
40 BlockInterference() =
default;
54 unsigned RefCount = 0;
86 VirtI.setMap(LIU.
getMap());
98 void update(
unsigned MBBNum);
104 assert(!hasRefs() &&
"Cannot clear cache entry with references");
111 MCRegister getPhysReg()
const {
return PhysReg; }
113 void addRef(
int Delta) { RefCount += Delta; }
115 bool hasRefs()
const {
return RefCount > 0; }
127 BlockInterference *
get(
unsigned MBBNum) {
128 if (Blocks[MBBNum].
Tag !=
Tag)
130 return &Blocks[MBBNum];
137 enum { CacheEntries = 32 };
145 unsigned char* PhysRegEntries =
nullptr;
146 size_t PhysRegEntriesCount = 0;
149 unsigned RoundRobin = 0;
152 Entry Entries[CacheEntries];
161 free(PhysRegEntries);
164 void reinitPhysRegEntries();
177 Entry *CacheEntry =
nullptr;
178 const BlockInterference *Current =
nullptr;
179 static const BlockInterference NoInterference;
181 void setEntry(Entry *
E) {
186 CacheEntry->addRef(-1);
189 CacheEntry->addRef(+1);
197 setEntry(
O.CacheEntry);
201 setEntry(
O.CacheEntry);
213 setEntry(Cache.get(PhysReg));
218 Current = CacheEntry ? CacheEntry->get(MBBNum) : &NoInterference;
223 return Current->First.isValid();
229 return Current->First;
235 return Current->Last;
242 #endif // LLVM_LIB_CODEGEN_INTERFERENCECACHE_H
This is an optimization pass for GlobalISel generic memory operations.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static constexpr unsigned NoRegister
unsigned const TargetRegisterInfo * TRI
static void clear(coro::Shape &Shape)
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
Cursor & operator=(const Cursor &O)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
unsigned getTag() const
getTag - Return an opaque tag representing the current state of the union.
const Map & getMap() const
into llvm powi allowing the code generator to produce balanced multiplication trees First
void setPhysReg(InterferenceCache &Cache, MCRegister PhysReg)
setPhysReg - Point this cursor to PhysReg's interference.
SlotIndex first()
first - Return the starting index of the first interfering range in the current block.
SlotIndex - An opaque wrapper around machine indexes.
This class represents the liveness of a register, stack slot, etc.
initializer< Ty > init(const Ty &Val)
void moveToBlock(unsigned MBBNum)
moveTo - Move cursor to basic block MBBNum.
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SlotIndex last()
last - Return the ending index of the last interfering range in the current block.
LiveSegments::iterator SegmentIter
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library,...
Cursor - The primary query interface for the block interference cache.
Segments::iterator iterator
unsigned getMaxCursors() const
getMaxCursors - Return the maximum number of concurrent cursors that can be supported.
bool hasInterference()
hasInterference - Return true if the current block has any interference.
Wrapper class representing physical registers. Should be passed by value.