LLVM 19.0.0git
NVPTXProxyRegErasure.cpp
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1//===- NVPTXProxyRegErasure.cpp - NVPTX Proxy Register Instruction Erasure -==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// The pass is needed to remove ProxyReg instructions and restore related
10// registers. The instructions were needed at instruction selection stage to
11// make sure that callseq_end nodes won't be removed as "dead nodes". This can
12// happen when we expand instructions into libcalls and the call site doesn't
13// care about the libcall chain. Call site cares about data flow only, and the
14// latest data flow node happens to be before callseq_end. Therefore the node
15// becomes dangling and "dead". The ProxyReg acts like an additional data flow
16// node *after* the callseq_end in the chain and ensures that everything will be
17// preserved.
18//
19//===----------------------------------------------------------------------===//
20
21#include "NVPTX.h"
27
28using namespace llvm;
29
30namespace llvm {
32}
33
34namespace {
35
36struct NVPTXProxyRegErasure : public MachineFunctionPass {
37public:
38 static char ID;
39 NVPTXProxyRegErasure() : MachineFunctionPass(ID) {
41 }
42
43 bool runOnMachineFunction(MachineFunction &MF) override;
44
45 StringRef getPassName() const override {
46 return "NVPTX Proxy Register Instruction Erasure";
47 }
48
49 void getAnalysisUsage(AnalysisUsage &AU) const override {
51 }
52
53private:
54 void replaceMachineInstructionUsage(MachineFunction &MF, MachineInstr &MI);
55
56 void replaceRegisterUsage(MachineInstr &Instr, MachineOperand &From,
57 MachineOperand &To);
58};
59
60} // namespace
61
62char NVPTXProxyRegErasure::ID = 0;
63
64INITIALIZE_PASS(NVPTXProxyRegErasure, "nvptx-proxyreg-erasure", "NVPTX ProxyReg Erasure", false, false)
65
66bool NVPTXProxyRegErasure::runOnMachineFunction(MachineFunction &MF) {
68
69 for (auto &BB : MF) {
70 for (auto &MI : BB) {
71 switch (MI.getOpcode()) {
72 case NVPTX::ProxyRegI1:
73 case NVPTX::ProxyRegI16:
74 case NVPTX::ProxyRegI32:
75 case NVPTX::ProxyRegI64:
76 case NVPTX::ProxyRegF32:
77 case NVPTX::ProxyRegF64:
78 replaceMachineInstructionUsage(MF, MI);
79 RemoveList.push_back(&MI);
80 break;
81 }
82 }
83 }
84
85 for (auto *MI : RemoveList) {
86 MI->eraseFromParent();
87 }
88
89 return !RemoveList.empty();
90}
91
92void NVPTXProxyRegErasure::replaceMachineInstructionUsage(MachineFunction &MF,
94 auto &InOp = *MI.uses().begin();
95 auto &OutOp = *MI.defs().begin();
96
97 assert(InOp.isReg() && "ProxyReg input operand should be a register.");
98 assert(OutOp.isReg() && "ProxyReg output operand should be a register.");
99
100 for (auto &BB : MF) {
101 for (auto &I : BB) {
102 replaceRegisterUsage(I, OutOp, InOp);
103 }
104 }
105}
106
107void NVPTXProxyRegErasure::replaceRegisterUsage(MachineInstr &Instr,
109 MachineOperand &To) {
110 for (auto &Op : Instr.uses()) {
111 if (Op.isReg() && Op.getReg() == From.getReg()) {
112 Op.setReg(To.getReg());
113 }
114 }
115}
116
118 return new NVPTXProxyRegErasure();
119}
BlockVerifier::State From
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Represent the analysis usage information of a pass.
This class represents an Operation in the Expression.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
getReg - Returns the register number.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
NodeAddr< InstrNode * > Instr
Definition: RDFGraph.h:389
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineFunctionPass * createNVPTXProxyRegErasurePass()
void initializeNVPTXProxyRegErasurePass(PassRegistry &)