LLVM  9.0.0svn
RISCVTargetMachine.cpp
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1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about RISCV target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCV.h"
14 #include "RISCVTargetMachine.h"
15 #include "RISCVTargetObjectFile.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Passes.h"
24 using namespace llvm;
25 
26 extern "C" void LLVMInitializeRISCVTarget() {
31 }
32 
33 static StringRef computeDataLayout(const Triple &TT) {
34  if (TT.isArch64Bit()) {
35  return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
36  } else {
37  assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
38  return "e-m:e-p:32:32-i64:64-n32-S128";
39  }
40 }
41 
44  if (!RM.hasValue())
45  return Reloc::Static;
46  return *RM;
47 }
48 
50  StringRef CPU, StringRef FS,
51  const TargetOptions &Options,
54  CodeGenOpt::Level OL, bool JIT)
55  : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
56  getEffectiveRelocModel(TT, RM),
57  getEffectiveCodeModel(CM, CodeModel::Small), OL),
59  Subtarget(TT, CPU, FS, Options.MCOptions.getABIName(), *this) {
60  initAsmInfo();
61 }
62 
63 namespace {
64 class RISCVPassConfig : public TargetPassConfig {
65 public:
66  RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
67  : TargetPassConfig(TM, PM) {}
68 
69  RISCVTargetMachine &getRISCVTargetMachine() const {
70  return getTM<RISCVTargetMachine>();
71  }
72 
73  void addIRPasses() override;
74  bool addInstSelector() override;
75  void addPreEmitPass() override;
76  void addPreEmitPass2() override;
77  void addPreRegAlloc() override;
78 };
79 }
80 
82  return new RISCVPassConfig(*this, PM);
83 }
84 
85 void RISCVPassConfig::addIRPasses() {
86  addPass(createAtomicExpandPass());
88 }
89 
90 bool RISCVPassConfig::addInstSelector() {
91  addPass(createRISCVISelDag(getRISCVTargetMachine()));
92 
93  return false;
94 }
95 
96 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
97 
98 void RISCVPassConfig::addPreEmitPass2() {
99  // Schedule the expansion of AMOs at the last possible moment, avoiding the
100  // possibility for other passes to break the requirements for forward
101  // progress in the LR/SC block.
102  addPass(createRISCVExpandPseudoPass());
103 }
104 
105 void RISCVPassConfig::addPreRegAlloc() {
107 }
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
void initializeRISCVExpandPseudoPass(PassRegistry &)
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
std::enable_if<!std::is_array< T >::value, std::unique_ptr< T > >::type make_unique(Args &&... args)
Constructs a new T() with the given args and returns a unique_ptr<T> which owns the object...
Definition: STLExtras.h:1403
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
Target & getTheRISCV32Target()
Target-Independent Code Generator Pass Configuration Options.
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM)
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1280
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
void LLVMInitializeRISCVTarget()
Target & getTheRISCV64Target()
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Target - Wrapper for Target specific information.
bool hasValue() const
Definition: Optional.h:259
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1276
static StringRef computeDataLayout(const Triple &TT)
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
FunctionPass * createRISCVExpandPseudoPass()
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
This implementation is used for RISCV ELF targets.
FunctionPass * createAtomicExpandPass()