LLVM  10.0.0svn
RISCVTargetMachine.cpp
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1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about RISCV target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVTargetMachine.h"
14 #include "RISCV.h"
15 #include "RISCVTargetObjectFile.h"
18 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/Passes.h"
27 using namespace llvm;
28 
29 extern "C" void LLVMInitializeRISCVTarget() {
34 }
35 
37  if (TT.isArch64Bit()) {
38  return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
39  } else {
40  assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
41  return "e-m:e-p:32:32-i64:64-n32-S128";
42  }
43 }
44 
47  if (!RM.hasValue())
48  return Reloc::Static;
49  return *RM;
50 }
51 
53  StringRef CPU, StringRef FS,
54  const TargetOptions &Options,
57  CodeGenOpt::Level OL, bool JIT)
58  : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
59  getEffectiveRelocModel(TT, RM),
60  getEffectiveCodeModel(CM, CodeModel::Small), OL),
61  TLOF(std::make_unique<RISCVELFTargetObjectFile>()),
62  Subtarget(TT, CPU, FS, Options.MCOptions.getABIName(), *this) {
63  initAsmInfo();
64 }
65 
68  return TargetTransformInfo(RISCVTTIImpl(this, F));
69 }
70 
71 namespace {
72 class RISCVPassConfig : public TargetPassConfig {
73 public:
74  RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
75  : TargetPassConfig(TM, PM) {}
76 
77  RISCVTargetMachine &getRISCVTargetMachine() const {
78  return getTM<RISCVTargetMachine>();
79  }
80 
81  void addIRPasses() override;
82  bool addInstSelector() override;
83  void addPreEmitPass() override;
84  void addPreEmitPass2() override;
85  void addPreRegAlloc() override;
86 };
87 }
88 
90  return new RISCVPassConfig(*this, PM);
91 }
92 
93 void RISCVPassConfig::addIRPasses() {
94  addPass(createAtomicExpandPass());
96 }
97 
98 bool RISCVPassConfig::addInstSelector() {
99  addPass(createRISCVISelDag(getRISCVTargetMachine()));
100 
101  return false;
102 }
103 
104 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
105 
106 void RISCVPassConfig::addPreEmitPass2() {
107  // Schedule the expansion of AMOs at the last possible moment, avoiding the
108  // possibility for other passes to break the requirements for forward
109  // progress in the LR/SC block.
110  addPass(createRISCVExpandPseudoPass());
111 }
112 
113 void RISCVPassConfig::addPreRegAlloc() {
115 }
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
void initializeRISCVExpandPseudoPass(PassRegistry &)
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
F(f)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
Definition: BitVector.h:937
Target & getTheRISCV32Target()
Target-Independent Code Generator Pass Configuration Options.
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM)
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1296
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
void LLVMInitializeRISCVTarget()
Target & getTheRISCV64Target()
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Target - Wrapper for Target specific information.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
bool hasValue() const
Definition: Optional.h:259
This file defines a TargetTransformInfo::Concept conforming object specific to the RISC-V target mach...
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1292
static StringRef computeDataLayout(const Triple &TT)
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
FunctionPass * createRISCVExpandPseudoPass()
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
This implementation is used for RISCV ELF targets.
This pass exposes codegen information to IR-level passes.
FunctionPass * createAtomicExpandPass()