LLVM  9.0.0svn
X86TargetMachine.cpp
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1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "X86CallLowering.h"
17 #include "X86LegalizerInfo.h"
18 #include "X86MacroFusion.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetObjectFile.h"
21 #include "X86TargetTransformInfo.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/Triple.h"
35 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/Pass.h"
41 #include "llvm/Support/CodeGen.h"
47 #include <memory>
48 #include <string>
49 
50 using namespace llvm;
51 
52 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
53  cl::desc("Enable the machine combiner pass"),
54  cl::init(true), cl::Hidden);
55 
56 static cl::opt<bool> EnableCondBrFoldingPass("x86-condbr-folding",
57  cl::desc("Enable the conditional branch "
58  "folding pass"),
59  cl::init(false), cl::Hidden);
60 
61 extern "C" void LLVMInitializeX86Target() {
62  // Register the target.
65 
81 }
82 
83 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
84  if (TT.isOSBinFormatMachO()) {
85  if (TT.getArch() == Triple::x86_64)
86  return llvm::make_unique<X86_64MachoTargetObjectFile>();
87  return llvm::make_unique<TargetLoweringObjectFileMachO>();
88  }
89 
90  if (TT.isOSFreeBSD())
91  return llvm::make_unique<X86FreeBSDTargetObjectFile>();
92  if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
93  return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
94  if (TT.isOSSolaris())
95  return llvm::make_unique<X86SolarisTargetObjectFile>();
96  if (TT.isOSFuchsia())
97  return llvm::make_unique<X86FuchsiaTargetObjectFile>();
98  if (TT.isOSBinFormatELF())
99  return llvm::make_unique<X86ELFTargetObjectFile>();
100  if (TT.isOSBinFormatCOFF())
101  return llvm::make_unique<TargetLoweringObjectFileCOFF>();
102  llvm_unreachable("unknown subtarget type");
103 }
104 
105 static std::string computeDataLayout(const Triple &TT) {
106  // X86 is little endian
107  std::string Ret = "e";
108 
110  // X86 and x32 have 32 bit pointers.
111  if ((TT.isArch64Bit() &&
112  (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
113  !TT.isArch64Bit())
114  Ret += "-p:32:32";
115 
116  // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
117  if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
118  Ret += "-i64:64";
119  else if (TT.isOSIAMCU())
120  Ret += "-i64:32-f64:32";
121  else
122  Ret += "-f64:32:64";
123 
124  // Some ABIs align long double to 128 bits, others to 32.
125  if (TT.isOSNaCl() || TT.isOSIAMCU())
126  ; // No f80
127  else if (TT.isArch64Bit() || TT.isOSDarwin())
128  Ret += "-f80:128";
129  else
130  Ret += "-f80:32";
131 
132  if (TT.isOSIAMCU())
133  Ret += "-f128:32";
134 
135  // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
136  if (TT.isArch64Bit())
137  Ret += "-n8:16:32:64";
138  else
139  Ret += "-n8:16:32";
140 
141  // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
142  if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
143  Ret += "-a:0:32-S32";
144  else
145  Ret += "-S128";
146 
147  return Ret;
148 }
149 
151  bool JIT,
153  bool is64Bit = TT.getArch() == Triple::x86_64;
154  if (!RM.hasValue()) {
155  // JIT codegen should use static relocations by default, since it's
156  // typically executed in process and not relocatable.
157  if (JIT)
158  return Reloc::Static;
159 
160  // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
161  // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
162  // use static relocation model by default.
163  if (TT.isOSDarwin()) {
164  if (is64Bit)
165  return Reloc::PIC_;
166  return Reloc::DynamicNoPIC;
167  }
168  if (TT.isOSWindows() && is64Bit)
169  return Reloc::PIC_;
170  return Reloc::Static;
171  }
172 
173  // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
174  // is defined as a model for code which may be used in static or dynamic
175  // executables but not necessarily a shared library. On X86-32 we just
176  // compile in -static mode, in x86-64 we use PIC.
177  if (*RM == Reloc::DynamicNoPIC) {
178  if (is64Bit)
179  return Reloc::PIC_;
180  if (!TT.isOSDarwin())
181  return Reloc::Static;
182  }
183 
184  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
185  // the Mach-O file format doesn't support it.
186  if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
187  return Reloc::PIC_;
188 
189  return *RM;
190 }
191 
193  bool JIT, bool Is64Bit) {
194  if (CM) {
195  if (*CM == CodeModel::Tiny)
196  report_fatal_error("Target does not support the tiny CodeModel");
197  return *CM;
198  }
199  if (JIT)
200  return Is64Bit ? CodeModel::Large : CodeModel::Small;
201  return CodeModel::Small;
202 }
203 
204 /// Create an X86 target.
205 ///
207  StringRef CPU, StringRef FS,
208  const TargetOptions &Options,
211  CodeGenOpt::Level OL, bool JIT)
213  T, computeDataLayout(TT), TT, CPU, FS, Options,
214  getEffectiveRelocModel(TT, JIT, RM),
215  getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
216  OL),
217  TLOF(createTLOF(getTargetTriple())) {
218  // Windows stack unwinder gets confused when execution flow "falls through"
219  // after a call to 'noreturn' function.
220  // To prevent that, we emit a trap for 'unreachable' IR instructions.
221  // (which on X86, happens to be the 'ud2' instruction)
222  // On PS4, the "return address" of a 'noreturn' call must still be within
223  // the calling function, and TrapUnreachable is an easy way to get that.
224  // The check here for 64-bit windows is a bit icky, but as we're unlikely
225  // to ever want to mix 32 and 64-bit windows code in a single module
226  // this should be fine.
227  if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4() ||
228  TT.isOSBinFormatMachO()) {
229  this->Options.TrapUnreachable = true;
230  this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
231  }
232 
233  // Outlining is available for x86-64.
234  if (TT.getArch() == Triple::x86_64)
235  setMachineOutliner(true);
236 
237  initAsmInfo();
238 }
239 
241 
242 const X86Subtarget *
244  Attribute CPUAttr = F.getFnAttribute("target-cpu");
245  Attribute FSAttr = F.getFnAttribute("target-features");
246 
247  StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
248  ? CPUAttr.getValueAsString()
249  : (StringRef)TargetCPU;
251  ? FSAttr.getValueAsString()
252  : (StringRef)TargetFS;
253 
255  Key.reserve(CPU.size() + FS.size());
256  Key += CPU;
257  Key += FS;
258 
259  // FIXME: This is related to the code below to reset the target options,
260  // we need to know whether or not the soft float flag is set on the
261  // function before we can generate a subtarget. We also need to use
262  // it as a key for the subtarget since that can be the only difference
263  // between two functions.
264  bool SoftFloat =
265  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
266  // If the soft float attribute is set on the function turn on the soft float
267  // subtarget feature.
268  if (SoftFloat)
269  Key += FS.empty() ? "+soft-float" : ",+soft-float";
270 
271  // Keep track of the key width after all features are added so we can extract
272  // the feature string out later.
273  unsigned CPUFSWidth = Key.size();
274 
275  // Extract prefer-vector-width attribute.
276  unsigned PreferVectorWidthOverride = 0;
277  if (F.hasFnAttribute("prefer-vector-width")) {
278  StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
279  unsigned Width;
280  if (!Val.getAsInteger(0, Width)) {
281  Key += ",prefer-vector-width=";
282  Key += Val;
283  PreferVectorWidthOverride = Width;
284  }
285  }
286 
287  // Extract min-legal-vector-width attribute.
288  unsigned RequiredVectorWidth = UINT32_MAX;
289  if (F.hasFnAttribute("min-legal-vector-width")) {
290  StringRef Val =
291  F.getFnAttribute("min-legal-vector-width").getValueAsString();
292  unsigned Width;
293  if (!Val.getAsInteger(0, Width)) {
294  Key += ",min-legal-vector-width=";
295  Key += Val;
296  RequiredVectorWidth = Width;
297  }
298  }
299 
300  // Extracted here so that we make sure there is backing for the StringRef. If
301  // we assigned earlier, its possible the SmallString reallocated leaving a
302  // dangling StringRef.
303  FS = Key.slice(CPU.size(), CPUFSWidth);
304 
305  auto &I = SubtargetMap[Key];
306  if (!I) {
307  // This needs to be done before we create a new subtarget since any
308  // creation will depend on the TM and the code generation flags on the
309  // function that reside in TargetOptions.
311  I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
313  PreferVectorWidthOverride,
314  RequiredVectorWidth);
315  }
316  return I.get();
317 }
318 
319 //===----------------------------------------------------------------------===//
320 // Command line options for x86
321 //===----------------------------------------------------------------------===//
322 static cl::opt<bool>
323 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
324  cl::desc("Minimize AVX to SSE transition penalty"),
325  cl::init(true));
326 
327 //===----------------------------------------------------------------------===//
328 // X86 TTI query.
329 //===----------------------------------------------------------------------===//
330 
333  return TargetTransformInfo(X86TTIImpl(this, F));
334 }
335 
336 //===----------------------------------------------------------------------===//
337 // Pass Pipeline Configuration
338 //===----------------------------------------------------------------------===//
339 
340 namespace {
341 
342 /// X86 Code Generator Pass Configuration Options.
343 class X86PassConfig : public TargetPassConfig {
344 public:
345  X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
346  : TargetPassConfig(TM, PM) {}
347 
348  X86TargetMachine &getX86TargetMachine() const {
349  return getTM<X86TargetMachine>();
350  }
351 
353  createMachineScheduler(MachineSchedContext *C) const override {
356  return DAG;
357  }
358 
359  void addIRPasses() override;
360  bool addInstSelector() override;
361  bool addIRTranslator() override;
362  bool addLegalizeMachineIR() override;
363  bool addRegBankSelect() override;
364  bool addGlobalInstructionSelect() override;
365  bool addILPOpts() override;
366  bool addPreISel() override;
367  void addMachineSSAOptimization() override;
368  void addPreRegAlloc() override;
369  void addPostRegAlloc() override;
370  void addPreEmitPass() override;
371  void addPreEmitPass2() override;
372  void addPreSched2() override;
373 };
374 
375 class X86ExecutionDomainFix : public ExecutionDomainFix {
376 public:
377  static char ID;
378  X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
379  StringRef getPassName() const override {
380  return "X86 Execution Dependency Fix";
381  }
382 };
384 
385 } // end anonymous namespace
386 
387 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
388  "X86 Execution Domain Fix", false, false)
390 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
391  "X86 Execution Domain Fix", false, false)
392 
394  return new X86PassConfig(*this, PM);
395 }
396 
397 void X86PassConfig::addIRPasses() {
398  addPass(createAtomicExpandPass());
399 
401 
402  if (TM->getOptLevel() != CodeGenOpt::None)
403  addPass(createInterleavedAccessPass());
404 
405  // Add passes that handle indirect branch removal and insertion of a retpoline
406  // thunk. These will be a no-op unless a function subtarget has the retpoline
407  // feature enabled.
408  addPass(createIndirectBrExpandPass());
409 }
410 
411 bool X86PassConfig::addInstSelector() {
412  // Install an instruction selector.
413  addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
414 
415  // For ELF, cleanup any local-dynamic TLS accesses.
416  if (TM->getTargetTriple().isOSBinFormatELF() &&
419 
420  addPass(createX86GlobalBaseRegPass());
421  return false;
422 }
423 
424 bool X86PassConfig::addIRTranslator() {
425  addPass(new IRTranslator());
426  return false;
427 }
428 
429 bool X86PassConfig::addLegalizeMachineIR() {
430  addPass(new Legalizer());
431  return false;
432 }
433 
434 bool X86PassConfig::addRegBankSelect() {
435  addPass(new RegBankSelect());
436  return false;
437 }
438 
439 bool X86PassConfig::addGlobalInstructionSelect() {
440  addPass(new InstructionSelect());
441  return false;
442 }
443 
444 bool X86PassConfig::addILPOpts() {
446  addPass(createX86CondBrFolding());
447  addPass(&EarlyIfConverterID);
449  addPass(&MachineCombinerID);
450  addPass(createX86CmovConverterPass());
451  return true;
452 }
453 
454 bool X86PassConfig::addPreISel() {
455  // Only add this pass for 32-bit x86 Windows.
456  const Triple &TT = TM->getTargetTriple();
457  if (TT.isOSWindows() && TT.getArch() == Triple::x86)
458  addPass(createX86WinEHStatePass());
459  return true;
460 }
461 
462 void X86PassConfig::addPreRegAlloc() {
463  if (getOptLevel() != CodeGenOpt::None) {
464  addPass(&LiveRangeShrinkID);
465  addPass(createX86FixupSetCC());
466  addPass(createX86OptimizeLEAs());
469  }
470 
473  addPass(createX86WinAllocaExpander());
474 }
475 void X86PassConfig::addMachineSSAOptimization() {
478 }
479 
480 void X86PassConfig::addPostRegAlloc() {
482 }
483 
484 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
485 
486 void X86PassConfig::addPreEmitPass() {
487  if (getOptLevel() != CodeGenOpt::None) {
488  addPass(new X86ExecutionDomainFix());
489  addPass(createBreakFalseDeps());
490  }
491 
492  addPass(createShadowCallStackPass());
494 
495  if (UseVZeroUpper)
496  addPass(createX86IssueVZeroUpperPass());
497 
498  if (getOptLevel() != CodeGenOpt::None) {
499  addPass(createX86FixupBWInsts());
500  addPass(createX86PadShortFunctions());
501  addPass(createX86FixupLEAs());
502  addPass(createX86EvexToVexInsts());
503  }
505  addPass(createX86InsertPrefetchPass());
506 }
507 
508 void X86PassConfig::addPreEmitPass2() {
509  addPass(createX86RetpolineThunksPass());
510  // Verify basic block incoming and outgoing cfa offset and register values and
511  // correct CFA calculation rule where needed by inserting appropriate CFI
512  // instructions.
513  const Triple &TT = TM->getTargetTriple();
514  if (!TT.isOSDarwin() && !TT.isOSWindows())
515  addPass(createCFIInstrInserter());
516 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:474
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
void LLVMInitializeX86Target()
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
void initializeFixupBWInstPassPass(PassRegistry &)
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:602
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:77
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
This file a TargetTransformInfo::Concept conforming object specific to the X86 target machine...
static std::string computeDataLayout(const Triple &TT)
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:570
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:320
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86CallFrameOptimizationPass(PassRegistry &)
F(f)
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
bool isOSFuchsia() const
Definition: Triple.h:494
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
void reserve(size_type N)
Definition: SmallVector.h:368
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for &#39;unreachable&#39; IR instructions behind noreturn calls, even if TrapUnreachable is true.
FunctionPass * createShadowCallStackPass()
This pass instruments the function prolog to save the return address to a &#39;shadow call stack&#39; and the...
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:156
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another, when profitable.
void initializeX86CmovConverterPassPass(PassRegistry &)
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
This class provides the reaching def analysis.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:71
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
bool isOSSolaris() const
Definition: Triple.h:500
Target-Independent Code Generator Pass Configuration Options.
void initializeX86AvoidSFBPassPass(PassRegistry &)
Key
PAL metadata keys.
static cl::opt< bool > EnableCondBrFoldingPass("x86-condbr-folding", cl::desc("Enable the conditional branch " "folding pass"), cl::init(false), cl::Hidden)
StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: SmallString.h:259
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
void initializeX86CondBrFoldingPassPass(PassRegistry &)
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:289
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
void initializeEvexToVexInstPassPass(PassRegistry &)
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec...
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix", "X86 Execution Domain Fix", false, false) INITIALIZE_PASS_END(X86ExecutionDomainFix
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
bool isPS4() const
Tests whether the target is the PS4 platform.
Definition: Triple.h:629
speculative execution
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:527
char & LiveRangeShrinkID
LiveRangeShrink pass.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:201
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
void initializeX86ExecutionDomainFixPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:90
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:607
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
static bool is64Bit(const char *name)
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
const X86Subtarget * getSubtargetImpl() const =delete
void initializeFixupLEAPassPass(PassRegistry &)
This class describes a target machine that is implemented with the LLVM target-independent code gener...
void setMachineOutliner(bool Enable)
x86 execution domain fix
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:612
static CodeModel::Model getEffectiveX86CodeModel(Optional< CodeModel::Model > CM, bool JIT, bool Is64Bit)
size_t size() const
Definition: SmallVector.h:52
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
~X86TargetMachine() override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
void initializeX86DomainReassignmentPass(PassRegistry &)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
FunctionPass * createIndirectBrExpandPass()
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
bool isOSIAMCU() const
Definition: Triple.h:504
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:575
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:307
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
x86 execution domain X86 Execution Domain Fix
unsigned StackAlignmentOverride
StackAlignmentOverride - Override default stack alignment for target.
FunctionPass * createX86SpeculativeLoadHardeningPass()
bool isOSFreeBSD() const
Definition: Triple.h:490
This pass is responsible for selecting generic machine instructions to target-specific instructions...
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
Target - Wrapper for Target specific information.
This file describes how to lower LLVM calls to machine code calls.
std::string TargetCPU
Definition: TargetMachine.h:78
static cl::opt< bool > UseVZeroUpper("x86-use-vzeroupper", cl::Hidden, cl::desc("Minimize AVX to SSE transition penalty"), cl::init(true))
FunctionPass * createX86WinAllocaExpander()
Return a pass that expands WinAlloca pseudo-instructions.
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasValue() const
Definition: Optional.h:259
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an X86 target.
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1268
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling...
TargetOptions Options
Definition: TargetMachine.h:96
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
void initializeShadowCallStackPass(PassRegistry &)
Target & getTheX86_32Target()
FunctionPass * createX86CondBrFolding()
Return a pass that folds conditional branch jumps.
std::string TargetFS
Definition: TargetMachine.h:79
FunctionPass * createX86RetpolineThunksPass()
This pass creates the thunks for the retpoline feature.
void initializeWinEHStatePassPass(PassRegistry &)
This file declares the IRTranslator pass.
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for X86.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:330
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
unsigned TrapUnreachable
Emit target-specific trap instruction for &#39;unreachable&#39; IR instructions.
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber, Discriminator> (with respect to eachother)
This pass exposes codegen information to IR-level passes.
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates...
FunctionPass * createAtomicExpandPass()
Target & getTheX86_64Target()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.