LLVM  9.0.0svn
X86TargetMachine.cpp
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1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
36 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
49 #include <memory>
50 #include <string>
51 
52 using namespace llvm;
53 
54 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
55  cl::desc("Enable the machine combiner pass"),
56  cl::init(true), cl::Hidden);
57 
58 static cl::opt<bool> EnableCondBrFoldingPass("x86-condbr-folding",
59  cl::desc("Enable the conditional branch "
60  "folding pass"),
61  cl::init(false), cl::Hidden);
62 
63 extern "C" void LLVMInitializeX86Target() {
64  // Register the target.
67 
84 }
85 
86 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
87  if (TT.isOSBinFormatMachO()) {
88  if (TT.getArch() == Triple::x86_64)
89  return llvm::make_unique<X86_64MachoTargetObjectFile>();
90  return llvm::make_unique<TargetLoweringObjectFileMachO>();
91  }
92 
93  if (TT.isOSFreeBSD())
94  return llvm::make_unique<X86FreeBSDTargetObjectFile>();
95  if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
96  return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
97  if (TT.isOSSolaris())
98  return llvm::make_unique<X86SolarisTargetObjectFile>();
99  if (TT.isOSFuchsia())
100  return llvm::make_unique<X86FuchsiaTargetObjectFile>();
101  if (TT.isOSBinFormatELF())
102  return llvm::make_unique<X86ELFTargetObjectFile>();
103  if (TT.isOSBinFormatCOFF())
104  return llvm::make_unique<TargetLoweringObjectFileCOFF>();
105  llvm_unreachable("unknown subtarget type");
106 }
107 
108 static std::string computeDataLayout(const Triple &TT) {
109  // X86 is little endian
110  std::string Ret = "e";
111 
113  // X86 and x32 have 32 bit pointers.
114  if ((TT.isArch64Bit() &&
115  (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
116  !TT.isArch64Bit())
117  Ret += "-p:32:32";
118 
119  // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
120  if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
121  Ret += "-i64:64";
122  else if (TT.isOSIAMCU())
123  Ret += "-i64:32-f64:32";
124  else
125  Ret += "-f64:32:64";
126 
127  // Some ABIs align long double to 128 bits, others to 32.
128  if (TT.isOSNaCl() || TT.isOSIAMCU())
129  ; // No f80
130  else if (TT.isArch64Bit() || TT.isOSDarwin())
131  Ret += "-f80:128";
132  else
133  Ret += "-f80:32";
134 
135  if (TT.isOSIAMCU())
136  Ret += "-f128:32";
137 
138  // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
139  if (TT.isArch64Bit())
140  Ret += "-n8:16:32:64";
141  else
142  Ret += "-n8:16:32";
143 
144  // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
145  if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
146  Ret += "-a:0:32-S32";
147  else
148  Ret += "-S128";
149 
150  return Ret;
151 }
152 
154  bool JIT,
156  bool is64Bit = TT.getArch() == Triple::x86_64;
157  if (!RM.hasValue()) {
158  // JIT codegen should use static relocations by default, since it's
159  // typically executed in process and not relocatable.
160  if (JIT)
161  return Reloc::Static;
162 
163  // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
164  // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
165  // use static relocation model by default.
166  if (TT.isOSDarwin()) {
167  if (is64Bit)
168  return Reloc::PIC_;
169  return Reloc::DynamicNoPIC;
170  }
171  if (TT.isOSWindows() && is64Bit)
172  return Reloc::PIC_;
173  return Reloc::Static;
174  }
175 
176  // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
177  // is defined as a model for code which may be used in static or dynamic
178  // executables but not necessarily a shared library. On X86-32 we just
179  // compile in -static mode, in x86-64 we use PIC.
180  if (*RM == Reloc::DynamicNoPIC) {
181  if (is64Bit)
182  return Reloc::PIC_;
183  if (!TT.isOSDarwin())
184  return Reloc::Static;
185  }
186 
187  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
188  // the Mach-O file format doesn't support it.
189  if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
190  return Reloc::PIC_;
191 
192  return *RM;
193 }
194 
196  bool JIT, bool Is64Bit) {
197  if (CM) {
198  if (*CM == CodeModel::Tiny)
199  report_fatal_error("Target does not support the tiny CodeModel", false);
200  return *CM;
201  }
202  if (JIT)
203  return Is64Bit ? CodeModel::Large : CodeModel::Small;
204  return CodeModel::Small;
205 }
206 
207 /// Create an X86 target.
208 ///
210  StringRef CPU, StringRef FS,
211  const TargetOptions &Options,
214  CodeGenOpt::Level OL, bool JIT)
216  T, computeDataLayout(TT), TT, CPU, FS, Options,
217  getEffectiveRelocModel(TT, JIT, RM),
218  getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
219  OL),
220  TLOF(createTLOF(getTargetTriple())) {
221  // Windows stack unwinder gets confused when execution flow "falls through"
222  // after a call to 'noreturn' function.
223  // To prevent that, we emit a trap for 'unreachable' IR instructions.
224  // (which on X86, happens to be the 'ud2' instruction)
225  // On PS4, the "return address" of a 'noreturn' call must still be within
226  // the calling function, and TrapUnreachable is an easy way to get that.
227  // The check here for 64-bit windows is a bit icky, but as we're unlikely
228  // to ever want to mix 32 and 64-bit windows code in a single module
229  // this should be fine.
230  if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4() ||
231  TT.isOSBinFormatMachO()) {
232  this->Options.TrapUnreachable = true;
233  this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
234  }
235 
236  // Outlining is available for x86-64.
237  if (TT.getArch() == Triple::x86_64)
238  setMachineOutliner(true);
239 
240  initAsmInfo();
241 }
242 
244 
245 const X86Subtarget *
247  Attribute CPUAttr = F.getFnAttribute("target-cpu");
248  Attribute FSAttr = F.getFnAttribute("target-features");
249 
250  StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
251  ? CPUAttr.getValueAsString()
252  : (StringRef)TargetCPU;
254  ? FSAttr.getValueAsString()
255  : (StringRef)TargetFS;
256 
258  Key.reserve(CPU.size() + FS.size());
259  Key += CPU;
260  Key += FS;
261 
262  // FIXME: This is related to the code below to reset the target options,
263  // we need to know whether or not the soft float flag is set on the
264  // function before we can generate a subtarget. We also need to use
265  // it as a key for the subtarget since that can be the only difference
266  // between two functions.
267  bool SoftFloat =
268  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
269  // If the soft float attribute is set on the function turn on the soft float
270  // subtarget feature.
271  if (SoftFloat)
272  Key += FS.empty() ? "+soft-float" : ",+soft-float";
273 
274  // Keep track of the key width after all features are added so we can extract
275  // the feature string out later.
276  unsigned CPUFSWidth = Key.size();
277 
278  // Extract prefer-vector-width attribute.
279  unsigned PreferVectorWidthOverride = 0;
280  if (F.hasFnAttribute("prefer-vector-width")) {
281  StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
282  unsigned Width;
283  if (!Val.getAsInteger(0, Width)) {
284  Key += ",prefer-vector-width=";
285  Key += Val;
286  PreferVectorWidthOverride = Width;
287  }
288  }
289 
290  // Extract min-legal-vector-width attribute.
291  unsigned RequiredVectorWidth = UINT32_MAX;
292  if (F.hasFnAttribute("min-legal-vector-width")) {
293  StringRef Val =
294  F.getFnAttribute("min-legal-vector-width").getValueAsString();
295  unsigned Width;
296  if (!Val.getAsInteger(0, Width)) {
297  Key += ",min-legal-vector-width=";
298  Key += Val;
299  RequiredVectorWidth = Width;
300  }
301  }
302 
303  // Extracted here so that we make sure there is backing for the StringRef. If
304  // we assigned earlier, its possible the SmallString reallocated leaving a
305  // dangling StringRef.
306  FS = Key.slice(CPU.size(), CPUFSWidth);
307 
308  auto &I = SubtargetMap[Key];
309  if (!I) {
310  // This needs to be done before we create a new subtarget since any
311  // creation will depend on the TM and the code generation flags on the
312  // function that reside in TargetOptions.
314  I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
316  PreferVectorWidthOverride,
317  RequiredVectorWidth);
318  }
319  return I.get();
320 }
321 
322 //===----------------------------------------------------------------------===//
323 // Command line options for x86
324 //===----------------------------------------------------------------------===//
325 static cl::opt<bool>
326 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
327  cl::desc("Minimize AVX to SSE transition penalty"),
328  cl::init(true));
329 
330 //===----------------------------------------------------------------------===//
331 // X86 TTI query.
332 //===----------------------------------------------------------------------===//
333 
336  return TargetTransformInfo(X86TTIImpl(this, F));
337 }
338 
339 //===----------------------------------------------------------------------===//
340 // Pass Pipeline Configuration
341 //===----------------------------------------------------------------------===//
342 
343 namespace {
344 
345 /// X86 Code Generator Pass Configuration Options.
346 class X86PassConfig : public TargetPassConfig {
347 public:
348  X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
349  : TargetPassConfig(TM, PM) {}
350 
351  X86TargetMachine &getX86TargetMachine() const {
352  return getTM<X86TargetMachine>();
353  }
354 
356  createMachineScheduler(MachineSchedContext *C) const override {
359  return DAG;
360  }
361 
363  createPostMachineScheduler(MachineSchedContext *C) const override {
366  return DAG;
367  }
368 
369  void addIRPasses() override;
370  bool addInstSelector() override;
371  bool addIRTranslator() override;
372  bool addLegalizeMachineIR() override;
373  bool addRegBankSelect() override;
374  bool addGlobalInstructionSelect() override;
375  bool addILPOpts() override;
376  bool addPreISel() override;
377  void addMachineSSAOptimization() override;
378  void addPreRegAlloc() override;
379  void addPostRegAlloc() override;
380  void addPreEmitPass() override;
381  void addPreEmitPass2() override;
382  void addPreSched2() override;
383 
384  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
385 };
386 
387 class X86ExecutionDomainFix : public ExecutionDomainFix {
388 public:
389  static char ID;
390  X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
391  StringRef getPassName() const override {
392  return "X86 Execution Dependency Fix";
393  }
394 };
396 
397 } // end anonymous namespace
398 
399 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
400  "X86 Execution Domain Fix", false, false)
402 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
403  "X86 Execution Domain Fix", false, false)
404 
406  return new X86PassConfig(*this, PM);
407 }
408 
409 void X86PassConfig::addIRPasses() {
410  addPass(createAtomicExpandPass());
411 
413 
414  if (TM->getOptLevel() != CodeGenOpt::None)
415  addPass(createInterleavedAccessPass());
416 
417  // Add passes that handle indirect branch removal and insertion of a retpoline
418  // thunk. These will be a no-op unless a function subtarget has the retpoline
419  // feature enabled.
420  addPass(createIndirectBrExpandPass());
421 }
422 
423 bool X86PassConfig::addInstSelector() {
424  // Install an instruction selector.
425  addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
426 
427  // For ELF, cleanup any local-dynamic TLS accesses.
428  if (TM->getTargetTriple().isOSBinFormatELF() &&
431 
432  addPass(createX86GlobalBaseRegPass());
433  return false;
434 }
435 
436 bool X86PassConfig::addIRTranslator() {
437  addPass(new IRTranslator());
438  return false;
439 }
440 
441 bool X86PassConfig::addLegalizeMachineIR() {
442  addPass(new Legalizer());
443  return false;
444 }
445 
446 bool X86PassConfig::addRegBankSelect() {
447  addPass(new RegBankSelect());
448  return false;
449 }
450 
451 bool X86PassConfig::addGlobalInstructionSelect() {
452  addPass(new InstructionSelect());
453  return false;
454 }
455 
456 bool X86PassConfig::addILPOpts() {
458  addPass(createX86CondBrFolding());
459  addPass(&EarlyIfConverterID);
461  addPass(&MachineCombinerID);
462  addPass(createX86CmovConverterPass());
463  return true;
464 }
465 
466 bool X86PassConfig::addPreISel() {
467  // Only add this pass for 32-bit x86 Windows.
468  const Triple &TT = TM->getTargetTriple();
469  if (TT.isOSWindows() && TT.getArch() == Triple::x86)
470  addPass(createX86WinEHStatePass());
471  return true;
472 }
473 
474 void X86PassConfig::addPreRegAlloc() {
475  if (getOptLevel() != CodeGenOpt::None) {
476  addPass(&LiveRangeShrinkID);
477  addPass(createX86FixupSetCC());
478  addPass(createX86OptimizeLEAs());
481  }
482 
485  addPass(createX86WinAllocaExpander());
486 }
487 void X86PassConfig::addMachineSSAOptimization() {
490 }
491 
492 void X86PassConfig::addPostRegAlloc() {
494 }
495 
496 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
497 
498 void X86PassConfig::addPreEmitPass() {
499  if (getOptLevel() != CodeGenOpt::None) {
500  addPass(new X86ExecutionDomainFix());
501  addPass(createBreakFalseDeps());
502  }
503 
505 
506  if (UseVZeroUpper)
507  addPass(createX86IssueVZeroUpperPass());
508 
509  if (getOptLevel() != CodeGenOpt::None) {
510  addPass(createX86FixupBWInsts());
511  addPass(createX86PadShortFunctions());
512  addPass(createX86FixupLEAs());
513  addPass(createX86EvexToVexInsts());
514  }
516  addPass(createX86InsertPrefetchPass());
517 }
518 
519 void X86PassConfig::addPreEmitPass2() {
520  addPass(createX86RetpolineThunksPass());
521  // Verify basic block incoming and outgoing cfa offset and register values and
522  // correct CFA calculation rule where needed by inserting appropriate CFI
523  // instructions.
524  const Triple &TT = TM->getTargetTriple();
525  const MCAsmInfo *MAI = TM->getMCAsmInfo();
526  if (!TT.isOSDarwin() &&
527  (!TT.isOSWindows() ||
529  addPass(createCFIInstrInserter());
530 }
531 
532 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
533  return getStandardCSEConfigForOpt(TM->getOptLevel());
534 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:480
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
void LLVMInitializeX86Target()
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
void initializeFixupBWInstPassPass(PassRegistry &)
void initializeFPSPass(PassRegistry &)
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:618
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:84
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
This file a TargetTransformInfo::Concept conforming object specific to the X86 target machine...
static std::string computeDataLayout(const Triple &TT)
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:576
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86CallFrameOptimizationPass(PassRegistry &)
F(f)
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
bool isOSFuchsia() const
Definition: Triple.h:500
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
void reserve(size_type N)
Definition: SmallVector.h:369
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for &#39;unreachable&#39; IR instructions behind noreturn calls, even if TrapUnreachable is true.
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:156
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another, when profitable.
void initializeX86CmovConverterPassPass(PassRegistry &)
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
This class provides the reaching def analysis.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:71
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
bool isOSSolaris() const
Definition: Triple.h:506
Target-Independent Code Generator Pass Configuration Options.
void initializeX86AvoidSFBPassPass(PassRegistry &)
Key
PAL metadata keys.
static cl::opt< bool > EnableCondBrFoldingPass("x86-condbr-folding", cl::desc("Enable the conditional branch " "folding pass"), cl::init(false), cl::Hidden)
StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: SmallString.h:259
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
void initializeX86CondBrFoldingPassPass(PassRegistry &)
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:295
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
void initializeEvexToVexInstPassPass(PassRegistry &)
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec...
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix", "X86 Execution Domain Fix", false, false) INITIALIZE_PASS_END(X86ExecutionDomainFix
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
bool isPS4() const
Tests whether the target is the PS4 platform.
Definition: Triple.h:650
speculative execution
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:533
char & LiveRangeShrinkID
LiveRangeShrink pass.
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:65
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:238
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
void initializeX86ExecutionDomainFixPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:90
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:623
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
static bool is64Bit(const char *name)
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
const X86Subtarget * getSubtargetImpl() const =delete
void initializeFixupLEAPassPass(PassRegistry &)
void initializeX86ExpandPseudoPass(PassRegistry &)
This class describes a target machine that is implemented with the LLVM target-independent code gener...
void setMachineOutliner(bool Enable)
x86 execution domain fix
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:628
static CodeModel::Model getEffectiveX86CodeModel(Optional< CodeModel::Model > CM, bool JIT, bool Is64Bit)
size_t size() const
Definition: SmallVector.h:52
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
~X86TargetMachine() override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
void initializeX86DomainReassignmentPass(PassRegistry &)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
FunctionPass * createIndirectBrExpandPass()
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
bool isOSIAMCU() const
Definition: Triple.h:510
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:581
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:313
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
x86 execution domain X86 Execution Domain Fix
unsigned StackAlignmentOverride
StackAlignmentOverride - Override default stack alignment for target.
FunctionPass * createX86SpeculativeLoadHardeningPass()
bool isOSFreeBSD() const
Definition: Triple.h:496
This pass is responsible for selecting generic machine instructions to target-specific instructions...
Target - Wrapper for Target specific information.
This file describes how to lower LLVM calls to machine code calls.
std::string TargetCPU
Definition: TargetMachine.h:85
static cl::opt< bool > UseVZeroUpper("x86-use-vzeroupper", cl::Hidden, cl::desc("Minimize AVX to SSE transition penalty"), cl::init(true))
FunctionPass * createX86WinAllocaExpander()
Return a pass that expands WinAlloca pseudo-instructions.
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasValue() const
Definition: Optional.h:259
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an X86 target.
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:223
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1290
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling...
TargetOptions Options
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
Target & getTheX86_32Target()
FunctionPass * createX86CondBrFolding()
Return a pass that folds conditional branch jumps.
std::string TargetFS
Definition: TargetMachine.h:86
FunctionPass * createX86RetpolineThunksPass()
This pass creates the thunks for the retpoline feature.
void initializeWinEHStatePassPass(PassRegistry &)
This file declares the IRTranslator pass.
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for X86.
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:576
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
unsigned TrapUnreachable
Emit target-specific trap instruction for &#39;unreachable&#39; IR instructions.
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber, Discriminator> (with respect to eachother)
This pass exposes codegen information to IR-level passes.
DWARF-like instruction based exceptions.
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates...
FunctionPass * createAtomicExpandPass()
Target & getTheX86_64Target()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.