LLVM  7.0.0svn
X86TargetMachine.cpp
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1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
36 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
48 #include <memory>
49 #include <string>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
54  cl::desc("Enable the machine combiner pass"),
55  cl::init(true), cl::Hidden);
56 
58  "x86-speculative-load-hardening",
59  cl::desc("Enable speculative load hardening"), cl::init(false), cl::Hidden);
60 
61 namespace llvm {
62 
72 
73 } // end namespace llvm
74 
75 extern "C" void LLVMInitializeX86Target() {
76  // Register the target.
79 
93 }
94 
95 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
96  if (TT.isOSBinFormatMachO()) {
97  if (TT.getArch() == Triple::x86_64)
98  return llvm::make_unique<X86_64MachoTargetObjectFile>();
99  return llvm::make_unique<TargetLoweringObjectFileMachO>();
100  }
101 
102  if (TT.isOSFreeBSD())
103  return llvm::make_unique<X86FreeBSDTargetObjectFile>();
104  if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
105  return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
106  if (TT.isOSSolaris())
107  return llvm::make_unique<X86SolarisTargetObjectFile>();
108  if (TT.isOSFuchsia())
109  return llvm::make_unique<X86FuchsiaTargetObjectFile>();
110  if (TT.isOSBinFormatELF())
111  return llvm::make_unique<X86ELFTargetObjectFile>();
112  if (TT.isOSBinFormatCOFF())
113  return llvm::make_unique<TargetLoweringObjectFileCOFF>();
114  llvm_unreachable("unknown subtarget type");
115 }
116 
117 static std::string computeDataLayout(const Triple &TT) {
118  // X86 is little endian
119  std::string Ret = "e";
120 
122  // X86 and x32 have 32 bit pointers.
123  if ((TT.isArch64Bit() &&
124  (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
125  !TT.isArch64Bit())
126  Ret += "-p:32:32";
127 
128  // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
129  if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
130  Ret += "-i64:64";
131  else if (TT.isOSIAMCU())
132  Ret += "-i64:32-f64:32";
133  else
134  Ret += "-f64:32:64";
135 
136  // Some ABIs align long double to 128 bits, others to 32.
137  if (TT.isOSNaCl() || TT.isOSIAMCU())
138  ; // No f80
139  else if (TT.isArch64Bit() || TT.isOSDarwin())
140  Ret += "-f80:128";
141  else
142  Ret += "-f80:32";
143 
144  if (TT.isOSIAMCU())
145  Ret += "-f128:32";
146 
147  // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
148  if (TT.isArch64Bit())
149  Ret += "-n8:16:32:64";
150  else
151  Ret += "-n8:16:32";
152 
153  // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
154  if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
155  Ret += "-a:0:32-S32";
156  else
157  Ret += "-S128";
158 
159  return Ret;
160 }
161 
164  bool is64Bit = TT.getArch() == Triple::x86_64;
165  if (!RM.hasValue()) {
166  // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
167  // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
168  // use static relocation model by default.
169  if (TT.isOSDarwin()) {
170  if (is64Bit)
171  return Reloc::PIC_;
172  return Reloc::DynamicNoPIC;
173  }
174  if (TT.isOSWindows() && is64Bit)
175  return Reloc::PIC_;
176  return Reloc::Static;
177  }
178 
179  // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
180  // is defined as a model for code which may be used in static or dynamic
181  // executables but not necessarily a shared library. On X86-32 we just
182  // compile in -static mode, in x86-64 we use PIC.
183  if (*RM == Reloc::DynamicNoPIC) {
184  if (is64Bit)
185  return Reloc::PIC_;
186  if (!TT.isOSDarwin())
187  return Reloc::Static;
188  }
189 
190  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
191  // the Mach-O file format doesn't support it.
192  if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
193  return Reloc::PIC_;
194 
195  return *RM;
196 }
197 
199  bool JIT, bool Is64Bit) {
200  if (CM)
201  return *CM;
202  if (JIT)
203  return Is64Bit ? CodeModel::Large : CodeModel::Small;
204  return CodeModel::Small;
205 }
206 
207 /// Create an X86 target.
208 ///
210  StringRef CPU, StringRef FS,
211  const TargetOptions &Options,
214  CodeGenOpt::Level OL, bool JIT)
216  T, computeDataLayout(TT), TT, CPU, FS, Options,
217  getEffectiveRelocModel(TT, RM),
218  getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL),
219  TLOF(createTLOF(getTargetTriple())) {
220  // Windows stack unwinder gets confused when execution flow "falls through"
221  // after a call to 'noreturn' function.
222  // To prevent that, we emit a trap for 'unreachable' IR instructions.
223  // (which on X86, happens to be the 'ud2' instruction)
224  // On PS4, the "return address" of a 'noreturn' call must still be within
225  // the calling function, and TrapUnreachable is an easy way to get that.
226  // The check here for 64-bit windows is a bit icky, but as we're unlikely
227  // to ever want to mix 32 and 64-bit windows code in a single module
228  // this should be fine.
229  if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4() ||
230  TT.isOSBinFormatMachO()) {
231  this->Options.TrapUnreachable = true;
232  this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
233  }
234 
235  // Outlining is available for x86-64.
236  if (TT.getArch() == Triple::x86_64)
237  setMachineOutliner(true);
238 
239  initAsmInfo();
240 }
241 
243 
244 const X86Subtarget *
246  Attribute CPUAttr = F.getFnAttribute("target-cpu");
247  Attribute FSAttr = F.getFnAttribute("target-features");
248 
249  StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
250  ? CPUAttr.getValueAsString()
251  : (StringRef)TargetCPU;
253  ? FSAttr.getValueAsString()
254  : (StringRef)TargetFS;
255 
257  Key.reserve(CPU.size() + FS.size());
258  Key += CPU;
259  Key += FS;
260 
261  // FIXME: This is related to the code below to reset the target options,
262  // we need to know whether or not the soft float flag is set on the
263  // function before we can generate a subtarget. We also need to use
264  // it as a key for the subtarget since that can be the only difference
265  // between two functions.
266  bool SoftFloat =
267  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
268  // If the soft float attribute is set on the function turn on the soft float
269  // subtarget feature.
270  if (SoftFloat)
271  Key += FS.empty() ? "+soft-float" : ",+soft-float";
272 
273  // Keep track of the key width after all features are added so we can extract
274  // the feature string out later.
275  unsigned CPUFSWidth = Key.size();
276 
277  // Extract prefer-vector-width attribute.
278  unsigned PreferVectorWidthOverride = 0;
279  if (F.hasFnAttribute("prefer-vector-width")) {
280  StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
281  unsigned Width;
282  if (!Val.getAsInteger(0, Width)) {
283  Key += ",prefer-vector-width=";
284  Key += Val;
285  PreferVectorWidthOverride = Width;
286  }
287  }
288 
289  // Extract required-vector-width attribute.
290  unsigned RequiredVectorWidth = UINT32_MAX;
291  if (F.hasFnAttribute("required-vector-width")) {
292  StringRef Val = F.getFnAttribute("required-vector-width").getValueAsString();
293  unsigned Width;
294  if (!Val.getAsInteger(0, Width)) {
295  Key += ",required-vector-width=";
296  Key += Val;
297  RequiredVectorWidth = Width;
298  }
299  }
300 
301  // Extracted here so that we make sure there is backing for the StringRef. If
302  // we assigned earlier, its possible the SmallString reallocated leaving a
303  // dangling StringRef.
304  FS = Key.slice(CPU.size(), CPUFSWidth);
305 
306  auto &I = SubtargetMap[Key];
307  if (!I) {
308  // This needs to be done before we create a new subtarget since any
309  // creation will depend on the TM and the code generation flags on the
310  // function that reside in TargetOptions.
312  I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
314  PreferVectorWidthOverride,
315  RequiredVectorWidth);
316  }
317  return I.get();
318 }
319 
320 //===----------------------------------------------------------------------===//
321 // Command line options for x86
322 //===----------------------------------------------------------------------===//
323 static cl::opt<bool>
324 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
325  cl::desc("Minimize AVX to SSE transition penalty"),
326  cl::init(true));
327 
328 //===----------------------------------------------------------------------===//
329 // X86 TTI query.
330 //===----------------------------------------------------------------------===//
331 
334  return TargetTransformInfo(X86TTIImpl(this, F));
335 }
336 
337 //===----------------------------------------------------------------------===//
338 // Pass Pipeline Configuration
339 //===----------------------------------------------------------------------===//
340 
341 namespace {
342 
343 /// X86 Code Generator Pass Configuration Options.
344 class X86PassConfig : public TargetPassConfig {
345 public:
346  X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
347  : TargetPassConfig(TM, PM) {}
348 
349  X86TargetMachine &getX86TargetMachine() const {
350  return getTM<X86TargetMachine>();
351  }
352 
354  createMachineScheduler(MachineSchedContext *C) const override {
357  return DAG;
358  }
359 
360  void addIRPasses() override;
361  bool addInstSelector() override;
362  bool addIRTranslator() override;
363  bool addLegalizeMachineIR() override;
364  bool addRegBankSelect() override;
365  bool addGlobalInstructionSelect() override;
366  bool addILPOpts() override;
367  bool addPreISel() override;
368  void addMachineSSAOptimization() override;
369  void addPreRegAlloc() override;
370  void addPostRegAlloc() override;
371  void addPreEmitPass() override;
372  void addPreEmitPass2() override;
373  void addPreSched2() override;
374 };
375 
376 class X86ExecutionDomainFix : public ExecutionDomainFix {
377 public:
378  static char ID;
379  X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
380  StringRef getPassName() const override {
381  return "X86 Execution Dependency Fix";
382  }
383 };
385 
386 } // end anonymous namespace
387 
388 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
389  "X86 Execution Domain Fix", false, false)
391 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
392  "X86 Execution Domain Fix", false, false)
393 
395  return new X86PassConfig(*this, PM);
396 }
397 
398 void X86PassConfig::addIRPasses() {
399  addPass(createAtomicExpandPass());
400 
402 
403  if (TM->getOptLevel() != CodeGenOpt::None)
404  addPass(createInterleavedAccessPass());
405 
406  // Add passes that handle indirect branch removal and insertion of a retpoline
407  // thunk. These will be a no-op unless a function subtarget has the retpoline
408  // feature enabled.
409  addPass(createIndirectBrExpandPass());
410 }
411 
412 bool X86PassConfig::addInstSelector() {
413  // Install an instruction selector.
414  addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
415 
416  // For ELF, cleanup any local-dynamic TLS accesses.
417  if (TM->getTargetTriple().isOSBinFormatELF() &&
420 
421  addPass(createX86GlobalBaseRegPass());
422  return false;
423 }
424 
425 bool X86PassConfig::addIRTranslator() {
426  addPass(new IRTranslator());
427  return false;
428 }
429 
430 bool X86PassConfig::addLegalizeMachineIR() {
431  addPass(new Legalizer());
432  return false;
433 }
434 
435 bool X86PassConfig::addRegBankSelect() {
436  addPass(new RegBankSelect());
437  return false;
438 }
439 
440 bool X86PassConfig::addGlobalInstructionSelect() {
441  addPass(new InstructionSelect());
442  return false;
443 }
444 
445 bool X86PassConfig::addILPOpts() {
446  addPass(&EarlyIfConverterID);
448  addPass(&MachineCombinerID);
449  addPass(createX86CmovConverterPass());
450  return true;
451 }
452 
453 bool X86PassConfig::addPreISel() {
454  // Only add this pass for 32-bit x86 Windows.
455  const Triple &TT = TM->getTargetTriple();
456  if (TT.isOSWindows() && TT.getArch() == Triple::x86)
457  addPass(createX86WinEHStatePass());
458  return true;
459 }
460 
461 void X86PassConfig::addPreRegAlloc() {
462  if (getOptLevel() != CodeGenOpt::None) {
463  addPass(&LiveRangeShrinkID);
464  addPass(createX86FixupSetCC());
465  addPass(createX86OptimizeLEAs());
468  }
469 
472 
474  addPass(createX86WinAllocaExpander());
475 }
476 void X86PassConfig::addMachineSSAOptimization() {
479 }
480 
481 void X86PassConfig::addPostRegAlloc() {
483 }
484 
485 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
486 
487 void X86PassConfig::addPreEmitPass() {
488  if (getOptLevel() != CodeGenOpt::None) {
489  addPass(new X86ExecutionDomainFix());
490  addPass(createBreakFalseDeps());
491  }
492 
493  addPass(createShadowCallStackPass());
495 
496  if (UseVZeroUpper)
497  addPass(createX86IssueVZeroUpperPass());
498 
499  if (getOptLevel() != CodeGenOpt::None) {
500  addPass(createX86FixupBWInsts());
501  addPass(createX86PadShortFunctions());
502  addPass(createX86FixupLEAs());
503  addPass(createX86EvexToVexInsts());
504  }
505 }
506 
507 void X86PassConfig::addPreEmitPass2() {
508  addPass(createX86RetpolineThunksPass());
509  // Verify basic block incoming and outgoing cfa offset and register values and
510  // correct CFA calculation rule where needed by inserting appropriate CFI
511  // instructions.
512  const Triple &TT = TM->getTargetTriple();
513  if (!TT.isOSDarwin() && !TT.isOSWindows())
514  addPass(createCFIInstrInserter());
515 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:470
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
void LLVMInitializeX86Target()
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:137
void initializeFixupBWInstPassPass(PassRegistry &)
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:588
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:78
static cl::opt< bool > EnableSpeculativeLoadHardening("x86-speculative-load-hardening", cl::desc("Enable speculative load hardening"), cl::init(false), cl::Hidden)
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
This file a TargetTransformInfo::Concept conforming object specific to the X86 target machine...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
static std::string computeDataLayout(const Triple &TT)
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:567
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:307
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86CallFrameOptimizationPass(PassRegistry &)
F(f)
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
bool isOSFuchsia() const
Definition: Triple.h:490
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
void reserve(size_type N)
Definition: SmallVector.h:377
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for &#39;unreachable&#39; IR instructions behind noreturn calls, even if TrapUnreachable is true.
FunctionPass * createShadowCallStackPass()
This pass instruments the function prolog to save the return address to a &#39;shadow call stack&#39; and the...
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:157
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another, when profitable.
void initializeX86CmovConverterPassPass(PassRegistry &)
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
This class provides the reaching def analysis.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:72
bool isOSSolaris() const
Definition: Triple.h:496
Target-Independent Code Generator Pass Configuration Options.
void initializeX86AvoidSFBPassPass(PassRegistry &)
Key
PAL metadata keys.
StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: SmallString.h:260
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:285
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
void initializeEvexToVexInstPassPass(PassRegistry &)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix", "X86 Execution Domain Fix", false, false) INITIALIZE_PASS_END(X86ExecutionDomainFix
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
bool isPS4() const
Tests whether the target is the PS4 platform.
Definition: Triple.h:615
static CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM)
speculative execution
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:562
char & LiveRangeShrinkID
LiveRangeShrink pass.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:202
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
void initializeX86ExecutionDomainFixPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:593
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
static bool is64Bit(const char *name)
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
const X86Subtarget * getSubtargetImpl() const =delete
void initializeFixupLEAPassPass(PassRegistry &)
This class describes a target machine that is implemented with the LLVM target-independent code gener...
void setMachineOutliner(bool Enable)
x86 execution domain fix
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:598
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
~X86TargetMachine() override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
void initializeX86DomainReassignmentPass(PassRegistry &)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
FunctionPass * createIndirectBrExpandPass()
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:497
bool isOSIAMCU() const
Definition: Triple.h:500
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:572
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:303
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
x86 execution domain X86 Execution Domain Fix
unsigned StackAlignmentOverride
StackAlignmentOverride - Override default stack alignment for target.
FunctionPass * createX86SpeculativeLoadHardeningPass()
bool isOSFreeBSD() const
Definition: Triple.h:486
This pass is responsible for selecting generic machine instructions to target-specific instructions...
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
Target - Wrapper for Target specific information.
This file describes how to lower LLVM calls to machine code calls.
std::string TargetCPU
Definition: TargetMachine.h:79
static cl::opt< bool > UseVZeroUpper("x86-use-vzeroupper", cl::Hidden, cl::desc("Minimize AVX to SSE transition penalty"), cl::init(true))
FunctionPass * createX86WinAllocaExpander()
Return a pass that expands WinAlloca pseudo-instructions.
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasValue() const
Definition: Optional.h:183
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an X86 target.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1245
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling...
TargetOptions Options
Definition: TargetMachine.h:98
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
void initializeShadowCallStackPass(PassRegistry &)
Target & getTheX86_32Target()
std::string TargetFS
Definition: TargetMachine.h:80
FunctionPass * createX86RetpolineThunksPass()
This pass creates the thunks for the retpoline feature.
void initializeWinEHStatePassPass(PassRegistry &)
This file declares the IRTranslator pass.
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for X86.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:317
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
unsigned TrapUnreachable
Emit target-specific trap instruction for &#39;unreachable&#39; IR instructions.
This pass exposes codegen information to IR-level passes.
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates...
FunctionPass * createAtomicExpandPass()
Target & getTheX86_64Target()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:19
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.