LLVM  7.0.0svn
X86TargetMachine.cpp
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1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
36 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
48 #include <memory>
49 #include <string>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
54  cl::desc("Enable the machine combiner pass"),
55  cl::init(true), cl::Hidden);
56 
57 namespace llvm {
58 
68 
69 } // end namespace llvm
70 
71 extern "C" void LLVMInitializeX86Target() {
72  // Register the target.
75 
89 }
90 
91 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
92  if (TT.isOSBinFormatMachO()) {
93  if (TT.getArch() == Triple::x86_64)
94  return llvm::make_unique<X86_64MachoTargetObjectFile>();
95  return llvm::make_unique<TargetLoweringObjectFileMachO>();
96  }
97 
98  if (TT.isOSFreeBSD())
99  return llvm::make_unique<X86FreeBSDTargetObjectFile>();
100  if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
101  return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
102  if (TT.isOSSolaris())
103  return llvm::make_unique<X86SolarisTargetObjectFile>();
104  if (TT.isOSFuchsia())
105  return llvm::make_unique<X86FuchsiaTargetObjectFile>();
106  if (TT.isOSBinFormatELF())
107  return llvm::make_unique<X86ELFTargetObjectFile>();
109  return llvm::make_unique<X86WindowsTargetObjectFile>();
110  if (TT.isOSBinFormatCOFF())
111  return llvm::make_unique<TargetLoweringObjectFileCOFF>();
112  llvm_unreachable("unknown subtarget type");
113 }
114 
115 static std::string computeDataLayout(const Triple &TT) {
116  // X86 is little endian
117  std::string Ret = "e";
118 
120  // X86 and x32 have 32 bit pointers.
121  if ((TT.isArch64Bit() &&
122  (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
123  !TT.isArch64Bit())
124  Ret += "-p:32:32";
125 
126  // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
127  if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
128  Ret += "-i64:64";
129  else if (TT.isOSIAMCU())
130  Ret += "-i64:32-f64:32";
131  else
132  Ret += "-f64:32:64";
133 
134  // Some ABIs align long double to 128 bits, others to 32.
135  if (TT.isOSNaCl() || TT.isOSIAMCU())
136  ; // No f80
137  else if (TT.isArch64Bit() || TT.isOSDarwin())
138  Ret += "-f80:128";
139  else
140  Ret += "-f80:32";
141 
142  if (TT.isOSIAMCU())
143  Ret += "-f128:32";
144 
145  // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
146  if (TT.isArch64Bit())
147  Ret += "-n8:16:32:64";
148  else
149  Ret += "-n8:16:32";
150 
151  // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
152  if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
153  Ret += "-a:0:32-S32";
154  else
155  Ret += "-S128";
156 
157  return Ret;
158 }
159 
162  bool is64Bit = TT.getArch() == Triple::x86_64;
163  if (!RM.hasValue()) {
164  // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
165  // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
166  // use static relocation model by default.
167  if (TT.isOSDarwin()) {
168  if (is64Bit)
169  return Reloc::PIC_;
170  return Reloc::DynamicNoPIC;
171  }
172  if (TT.isOSWindows() && is64Bit)
173  return Reloc::PIC_;
174  return Reloc::Static;
175  }
176 
177  // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
178  // is defined as a model for code which may be used in static or dynamic
179  // executables but not necessarily a shared library. On X86-32 we just
180  // compile in -static mode, in x86-64 we use PIC.
181  if (*RM == Reloc::DynamicNoPIC) {
182  if (is64Bit)
183  return Reloc::PIC_;
184  if (!TT.isOSDarwin())
185  return Reloc::Static;
186  }
187 
188  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
189  // the Mach-O file format doesn't support it.
190  if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
191  return Reloc::PIC_;
192 
193  return *RM;
194 }
195 
197  bool JIT, bool Is64Bit) {
198  if (CM)
199  return *CM;
200  if (JIT)
201  return Is64Bit ? CodeModel::Large : CodeModel::Small;
202  return CodeModel::Small;
203 }
204 
205 /// Create an X86 target.
206 ///
208  StringRef CPU, StringRef FS,
209  const TargetOptions &Options,
212  CodeGenOpt::Level OL, bool JIT)
214  T, computeDataLayout(TT), TT, CPU, FS, Options,
215  getEffectiveRelocModel(TT, RM),
216  getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL),
217  TLOF(createTLOF(getTargetTriple())) {
218  // Windows stack unwinder gets confused when execution flow "falls through"
219  // after a call to 'noreturn' function.
220  // To prevent that, we emit a trap for 'unreachable' IR instructions.
221  // (which on X86, happens to be the 'ud2' instruction)
222  // On PS4, the "return address" of a 'noreturn' call must still be within
223  // the calling function, and TrapUnreachable is an easy way to get that.
224  // The check here for 64-bit windows is a bit icky, but as we're unlikely
225  // to ever want to mix 32 and 64-bit windows code in a single module
226  // this should be fine.
227  if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4() ||
228  TT.isOSBinFormatMachO())
229  this->Options.TrapUnreachable = true;
230 
231  initAsmInfo();
232 }
233 
235 
236 const X86Subtarget *
238  Attribute CPUAttr = F.getFnAttribute("target-cpu");
239  Attribute FSAttr = F.getFnAttribute("target-features");
240 
241  StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
242  ? CPUAttr.getValueAsString()
243  : (StringRef)TargetCPU;
245  ? FSAttr.getValueAsString()
246  : (StringRef)TargetFS;
247 
249  Key.reserve(CPU.size() + FS.size());
250  Key += CPU;
251  Key += FS;
252 
253  // FIXME: This is related to the code below to reset the target options,
254  // we need to know whether or not the soft float flag is set on the
255  // function before we can generate a subtarget. We also need to use
256  // it as a key for the subtarget since that can be the only difference
257  // between two functions.
258  bool SoftFloat =
259  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
260  // If the soft float attribute is set on the function turn on the soft float
261  // subtarget feature.
262  if (SoftFloat)
263  Key += FS.empty() ? "+soft-float" : ",+soft-float";
264 
265  // Keep track of the key width after all features are added so we can extract
266  // the feature string out later.
267  unsigned CPUFSWidth = Key.size();
268 
269  // Extract prefer-vector-width attribute.
270  unsigned PreferVectorWidthOverride = 0;
271  if (F.hasFnAttribute("prefer-vector-width")) {
272  StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
273  unsigned Width;
274  if (!Val.getAsInteger(0, Width)) {
275  Key += ",prefer-vector-width=";
276  Key += Val;
277  PreferVectorWidthOverride = Width;
278  }
279  }
280 
281  // Extract required-vector-width attribute.
282  unsigned RequiredVectorWidth = UINT32_MAX;
283  if (F.hasFnAttribute("required-vector-width")) {
284  StringRef Val = F.getFnAttribute("required-vector-width").getValueAsString();
285  unsigned Width;
286  if (!Val.getAsInteger(0, Width)) {
287  Key += ",required-vector-width=";
288  Key += Val;
289  RequiredVectorWidth = Width;
290  }
291  }
292 
293  // Extracted here so that we make sure there is backing for the StringRef. If
294  // we assigned earlier, its possible the SmallString reallocated leaving a
295  // dangling StringRef.
296  FS = Key.slice(CPU.size(), CPUFSWidth);
297 
298  auto &I = SubtargetMap[Key];
299  if (!I) {
300  // This needs to be done before we create a new subtarget since any
301  // creation will depend on the TM and the code generation flags on the
302  // function that reside in TargetOptions.
304  I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
306  PreferVectorWidthOverride,
307  RequiredVectorWidth);
308  }
309  return I.get();
310 }
311 
312 //===----------------------------------------------------------------------===//
313 // Command line options for x86
314 //===----------------------------------------------------------------------===//
315 static cl::opt<bool>
316 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
317  cl::desc("Minimize AVX to SSE transition penalty"),
318  cl::init(true));
319 
320 //===----------------------------------------------------------------------===//
321 // X86 TTI query.
322 //===----------------------------------------------------------------------===//
323 
326  return TargetTransformInfo(X86TTIImpl(this, F));
327 }
328 
329 //===----------------------------------------------------------------------===//
330 // Pass Pipeline Configuration
331 //===----------------------------------------------------------------------===//
332 
333 namespace {
334 
335 /// X86 Code Generator Pass Configuration Options.
336 class X86PassConfig : public TargetPassConfig {
337 public:
338  X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
339  : TargetPassConfig(TM, PM) {}
340 
341  X86TargetMachine &getX86TargetMachine() const {
342  return getTM<X86TargetMachine>();
343  }
344 
346  createMachineScheduler(MachineSchedContext *C) const override {
349  return DAG;
350  }
351 
352  void addIRPasses() override;
353  bool addInstSelector() override;
354  bool addIRTranslator() override;
355  bool addLegalizeMachineIR() override;
356  bool addRegBankSelect() override;
357  bool addGlobalInstructionSelect() override;
358  bool addILPOpts() override;
359  bool addPreISel() override;
360  void addMachineSSAOptimization() override;
361  void addPreRegAlloc() override;
362  void addPostRegAlloc() override;
363  void addPreEmitPass() override;
364  void addPreEmitPass2() override;
365  void addPreSched2() override;
366 };
367 
368 class X86ExecutionDomainFix : public ExecutionDomainFix {
369 public:
370  static char ID;
371  X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
372  StringRef getPassName() const override {
373  return "X86 Execution Dependency Fix";
374  }
375 };
377 
378 } // end anonymous namespace
379 
380 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
381  "X86 Execution Domain Fix", false, false)
383 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
384  "X86 Execution Domain Fix", false, false)
385 
387  return new X86PassConfig(*this, PM);
388 }
389 
390 void X86PassConfig::addIRPasses() {
391  addPass(createAtomicExpandPass());
392 
394 
395  if (TM->getOptLevel() != CodeGenOpt::None)
396  addPass(createInterleavedAccessPass());
397 
398  // Add passes that handle indirect branch removal and insertion of a retpoline
399  // thunk. These will be a no-op unless a function subtarget has the retpoline
400  // feature enabled.
401  addPass(createIndirectBrExpandPass());
402 }
403 
404 bool X86PassConfig::addInstSelector() {
405  // Install an instruction selector.
406  addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
407 
408  // For ELF, cleanup any local-dynamic TLS accesses.
409  if (TM->getTargetTriple().isOSBinFormatELF() &&
412 
413  addPass(createX86GlobalBaseRegPass());
414  return false;
415 }
416 
417 bool X86PassConfig::addIRTranslator() {
418  addPass(new IRTranslator());
419  return false;
420 }
421 
422 bool X86PassConfig::addLegalizeMachineIR() {
423  addPass(new Legalizer());
424  return false;
425 }
426 
427 bool X86PassConfig::addRegBankSelect() {
428  addPass(new RegBankSelect());
429  return false;
430 }
431 
432 bool X86PassConfig::addGlobalInstructionSelect() {
433  addPass(new InstructionSelect());
434  return false;
435 }
436 
437 bool X86PassConfig::addILPOpts() {
438  addPass(&EarlyIfConverterID);
440  addPass(&MachineCombinerID);
441  addPass(createX86CmovConverterPass());
442  return true;
443 }
444 
445 bool X86PassConfig::addPreISel() {
446  // Only add this pass for 32-bit x86 Windows.
447  const Triple &TT = TM->getTargetTriple();
448  if (TT.isOSWindows() && TT.getArch() == Triple::x86)
449  addPass(createX86WinEHStatePass());
450  return true;
451 }
452 
453 void X86PassConfig::addPreRegAlloc() {
454  if (getOptLevel() != CodeGenOpt::None) {
455  addPass(&LiveRangeShrinkID);
456  addPass(createX86FixupSetCC());
457  addPass(createX86OptimizeLEAs());
460  }
461 
463  addPass(createX86WinAllocaExpander());
464 }
465 void X86PassConfig::addMachineSSAOptimization() {
468 }
469 
470 void X86PassConfig::addPostRegAlloc() {
472 }
473 
474 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
475 
476 void X86PassConfig::addPreEmitPass() {
477  if (getOptLevel() != CodeGenOpt::None) {
478  addPass(new X86ExecutionDomainFix());
479  addPass(createBreakFalseDeps());
480  }
481 
482  addPass(createShadowCallStackPass());
484 
485  if (UseVZeroUpper)
486  addPass(createX86IssueVZeroUpperPass());
487 
488  if (getOptLevel() != CodeGenOpt::None) {
489  addPass(createX86FixupBWInsts());
490  addPass(createX86PadShortFunctions());
491  addPass(createX86FixupLEAs());
492  addPass(createX86EvexToVexInsts());
493  }
494 }
495 
496 void X86PassConfig::addPreEmitPass2() {
497  addPass(createX86RetpolineThunksPass());
498 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:468
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
void LLVMInitializeX86Target()
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
void initializeFixupBWInstPassPass(PassRegistry &)
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:586
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:78
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
This file a TargetTransformInfo::Concept conforming object specific to the X86 target machine...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
static std::string computeDataLayout(const Triple &TT)
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:565
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:302
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86CallFrameOptimizationPass(PassRegistry &)
F(f)
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
bool isOSFuchsia() const
Definition: Triple.h:488
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
void reserve(size_type N)
Definition: SmallVector.h:378
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
FunctionPass * createShadowCallStackPass()
This pass instruments the function prolog to save the return address to a &#39;shadow call stack&#39; and the...
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:157
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another, when profitable.
void initializeX86CmovConverterPassPass(PassRegistry &)
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
This class provides the reaching def analysis.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:51
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
bool isKnownWindowsMSVCEnvironment() const
Checks if the environment is MSVC.
Definition: Triple.h:528
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:71
bool isOSSolaris() const
Definition: Triple.h:494
Target-Independent Code Generator Pass Configuration Options.
void initializeX86AvoidSFBPassPass(PassRegistry &)
Key
PAL metadata keys.
StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: SmallString.h:260
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:283
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
void initializeEvexToVexInstPassPass(PassRegistry &)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix", "X86 Execution Domain Fix", false, false) INITIALIZE_PASS_END(X86ExecutionDomainFix
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
bool isPS4() const
Tests whether the target is the PS4 platform.
Definition: Triple.h:613
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:532
static CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM)
speculative execution
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:560
char & LiveRangeShrinkID
LiveRangeShrink pass.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:201
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
void initializeX86ExecutionDomainFixPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:591
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
static bool is64Bit(const char *name)
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
const X86Subtarget * getSubtargetImpl() const =delete
void initializeFixupLEAPassPass(PassRegistry &)
This class describes a target machine that is implemented with the LLVM target-independent code gener...
x86 execution domain fix
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:596
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
~X86TargetMachine() override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
void initializeX86DomainReassignmentPass(PassRegistry &)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
FunctionPass * createIndirectBrExpandPass()
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:497
bool isOSIAMCU() const
Definition: Triple.h:498
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:570
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:301
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
x86 execution domain X86 Execution Domain Fix
unsigned StackAlignmentOverride
StackAlignmentOverride - Override default stack alignment for target.
bool isOSFreeBSD() const
Definition: Triple.h:484
This pass is responsible for selecting generic machine instructions to target-specific instructions...
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
Target - Wrapper for Target specific information.
This file describes how to lower LLVM calls to machine code calls.
std::string TargetCPU
Definition: TargetMachine.h:79
static cl::opt< bool > UseVZeroUpper("x86-use-vzeroupper", cl::Hidden, cl::desc("Minimize AVX to SSE transition penalty"), cl::init(true))
FunctionPass * createX86WinAllocaExpander()
Return a pass that expands WinAlloca pseudo-instructions.
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasValue() const
Definition: Optional.h:183
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an X86 target.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1241
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling...
TargetOptions Options
Definition: TargetMachine.h:98
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
void initializeShadowCallStackPass(PassRegistry &)
Target & getTheX86_32Target()
std::string TargetFS
Definition: TargetMachine.h:80
FunctionPass * createX86RetpolineThunksPass()
This pass creates the thunks for the retpoline feature.
void initializeWinEHStatePassPass(PassRegistry &)
This file declares the IRTranslator pass.
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for X86.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:312
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
unsigned TrapUnreachable
Emit target-specific trap instruction for &#39;unreachable&#39; IR instructions.
This pass exposes codegen information to IR-level passes.
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates...
FunctionPass * createAtomicExpandPass()
Target & getTheX86_64Target()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:19
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.