LLVM 17.0.0git
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1//===- AggressiveInstCombineInternal.h --------------------------*- C++ -*-===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9// This file implements the instruction pattern combiner classes.
10// Currently, it handles pattern expressions for:
11// * Truncate instruction
18#include "llvm/ADT/MapVector.h"
23using namespace llvm;
26// TruncInstCombine - looks for expression graphs dominated by trunc
27// instructions and for each eligible graph, it will create a reduced bit-width
28// expression and replace the old expression with this new one and remove the
29// old one. Eligible expression graph is such that:
30// 1. Contains only supported instructions.
31// 2. Supported leaves: ZExtInst, SExtInst, TruncInst and Constant value.
32// 3. Can be evaluated into type with reduced legal bit-width (or Trunc type).
33// 4. All instructions in the graph must not have users outside the graph.
34// Only exception is for {ZExt, SExt}Inst with operand type equal to the
35// new reduced type chosen in (3).
37// The motivation for this optimization is that evaluating and expression using
38// smaller bit-width is preferable, especially for vectorization where we can
39// fit more values in one vectorized instruction. In addition, this optimization
40// may decrease the number of cast instructions, but will not increase it.
43namespace llvm {
44class AssumptionCache;
45class DataLayout;
46class DominatorTree;
47class Function;
48class Instruction;
50class TruncInst;
51class Type;
52class Value;
57 const DataLayout &DL;
58 const DominatorTree &DT;
60 /// List of all TruncInst instructions to be processed.
63 /// Current processed TruncInst instruction.
64 TruncInst *CurrentTruncInst = nullptr;
66 /// Information per each instruction in the expression graph.
67 struct Info {
68 /// Number of LSBs that are needed to generate a valid expression.
69 unsigned ValidBitWidth = 0;
70 /// Minimum number of LSBs needed to generate the ValidBitWidth.
71 unsigned MinBitWidth = 0;
72 /// The reduced value generated to replace the old instruction.
73 Value *NewValue = nullptr;
74 };
75 /// An ordered map representing expression graph post-dominated by current
76 /// processed TruncInst. It maps each instruction in the graph to its Info
77 /// structure. The map is ordered such that each instruction appears before
78 /// all other instructions in the graph that uses it.
83 const DataLayout &DL, const DominatorTree &DT)
84 : AC(AC), TLI(TLI), DL(DL), DT(DT) {}
86 /// Perform TruncInst pattern optimization on given function.
87 bool run(Function &F);
90 /// Build expression graph dominated by the /p CurrentTruncInst and append it
91 /// to the InstInfoMap container.
92 ///
93 /// \return true only if succeed to generate an eligible sub expression graph.
94 bool buildTruncExpressionGraph();
96 /// Calculate the minimal allowed bit-width of the chain ending with the
97 /// currently visited truncate's operand.
98 ///
99 /// \return minimum number of bits to which the chain ending with the
100 /// truncate's operand can be shrunk to.
101 unsigned getMinBitWidth();
103 /// Build an expression graph dominated by the current processed TruncInst and
104 /// Check if it is eligible to be reduced to a smaller type.
105 ///
106 /// \return the scalar version of the new type to be used for the reduced
107 /// expression graph, or nullptr if the expression graph is not
108 /// eligible to be reduced.
109 Type *getBestTruncatedType();
111 KnownBits computeKnownBits(const Value *V) const {
112 return llvm::computeKnownBits(V, DL, /*Depth=*/0, &AC,
113 /*CtxI=*/cast<Instruction>(CurrentTruncInst),
114 &DT);
115 }
117 unsigned ComputeNumSignBits(const Value *V) const {
119 V, DL, /*Depth=*/0, &AC, /*CtxI=*/cast<Instruction>(CurrentTruncInst),
120 &DT);
121 }
123 /// Given a \p V value and a \p SclTy scalar type return the generated reduced
124 /// value of \p V based on the type \p SclTy.
125 ///
126 /// \param V value to be reduced.
127 /// \param SclTy scalar version of new type to reduce to.
128 /// \return the new reduced value.
129 Value *getReducedOperand(Value *V, Type *SclTy);
131 /// Create a new expression graph using the reduced /p SclTy type and replace
132 /// the old expression graph with it. Also erase all instructions in the old
133 /// graph, except those that are still needed outside the graph.
134 ///
135 /// \param SclTy scalar version of new type to reduce expression graph into.
136 void ReduceExpressionGraph(Type *SclTy);
138} // end namespace llvm.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define F(x, y, z)
Definition: MD5.cpp:55
This file implements a map that provides insertion order iteration.
This file defines the SmallVector class.
A cache of @llvm.assume calls within a function.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:114
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:166
This class implements a map that also provides access to all stored values in a deterministic order.
Definition: MapVector.h:37
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
Provides information about what library functions are available for the current target.
TruncInstCombine(AssumptionCache &AC, TargetLibraryInfo &TLI, const DataLayout &DL, const DominatorTree &DT)
bool run(Function &F)
Perform TruncInst pattern optimization on given function.
This class represents a truncation of integer types.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void computeKnownBits(const Value *V, KnownBits &Known, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, OptimizationRemarkEmitter *ORE=nullptr, bool UseInstrInfo=true)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
unsigned ComputeNumSignBits(const Value *Op, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return the number of times the sign bit of the register is replicated into the other bits.