19#define DEBUG_TYPE "llvm-mca"
26 : LQSize(LQ), SQSize(SQ), UsedLQEntries(0), UsedSQEntries(0),
27 NoAlias(AssumeNoAlias) {
45 for (
const std::pair<
unsigned, std::unique_ptr<MemoryGroup>> &
G :
Groups)
46 G.second->cycleEvent();
56 for (
const auto &GroupIt :
Groups) {
58 dbgs() <<
"[LSUnit] Group (" << GroupIt.first <<
"): "
81 unsigned NewGID = createMemoryGroup();
86 unsigned ImmediateLoadDominator =
88 if (ImmediateLoadDominator) {
89 MemoryGroup &IDom = getGroup(ImmediateLoadDominator);
90 LLVM_DEBUG(
dbgs() <<
"[LSUnit]: GROUP DEP: (" << ImmediateLoadDominator
91 <<
") --> (" << NewGID <<
")\n");
109 <<
") --> (" << NewGID <<
")\n");
128 unsigned ImmediateLoadDominator =
143 bool ShouldCreateANewGroup =
144 IsLoadBarrier || !ImmediateLoadDominator ||
149 if (ShouldCreateANewGroup) {
150 unsigned NewGID = createMemoryGroup();
159 <<
") --> (" << NewGID <<
")\n");
165 if (ImmediateLoadDominator) {
166 MemoryGroup &LoadGroup = getGroup(ImmediateLoadDominator);
167 LLVM_DEBUG(
dbgs() <<
"[LSUnit]: GROUP DEP: (" << ImmediateLoadDominator
168 <<
") --> (" << NewGID <<
")\n");
207 assert((IsALoad || IsAStore) &&
"Expected a memory operation!");
212 <<
" has been removed from the load queue.\n");
218 <<
" has been removed from the store queue.\n");
228 auto It =
Groups.find(GroupID);
229 assert(It !=
Groups.end() &&
"Instruction not dispatched to the LS unit");
230 It->second->onInstructionExecuted(
IR);
231 if (It->second->isExecuted())
234 if (!isValidGroupID(GroupID)) {
A Load/Store unit class that models load/store queues and that implements a simple weak memory consis...
Legalize the Machine IR a function s Machine IR
This file defines abstractions used by the Pipeline to model register reads, register writes and inst...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
An InstRef contains both a SourceMgr index and Instruction pair.
bool isAStoreBarrier() const
bool isALoadBarrier() const
An instruction propagated through the simulated instruction pipeline.
unsigned getLSUTokenID() const
unsigned getUsedSQEntries() const
unsigned getUsedLQEntries() const
bool assumeNoAlias() const
unsigned getLoadQueueSize() const
Returns the total number of entries in the load queue.
LSUnitBase(const MCSchedModel &SM, unsigned LoadQueueSize, unsigned StoreQueueSize, bool AssumeNoAlias)
unsigned getStoreQueueSize() const
Returns the total number of entries in the store queue.
A node of a memory dependency graph.
unsigned getNumInstructions() const
unsigned getNumExecutingPredecessors() const
unsigned getNumExecuting() const
unsigned getNumPredecessors() const
void addSuccessor(MemoryGroup *Group, bool IsDataDependent)
unsigned getNumExecuted() const
unsigned getNumExecutedPredecessors() const
virtual void dump() const override
unsigned CurrentLoadGroupID
Status isAvailable(const InstRef &IR) const override
Returns LSU_AVAILABLE if there are enough load/store queue entries to accomodate instruction IR.
DenseMap< unsigned, std::unique_ptr< MemoryGroup > > Groups
Used to map group identifiers to MemoryGroups.
unsigned CurrentStoreGroupID
virtual void cycleEvent() override
virtual void onInstructionExecuted(const InstRef &IR) override
unsigned CurrentLoadBarrierGroupID
virtual void onInstructionRetired(const InstRef &IR) override
unsigned dispatch(const InstRef &IR) override
Allocates LS resources for instruction IR.
unsigned CurrentStoreBarrierGroupID
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Define a kind of processor resource that will be modeled by the scheduler.
Machine model for scheduling, bundling, and heuristics.
bool hasExtraProcessorInfo() const
const MCExtraProcessorInfo & getExtraProcessorInfo() const
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const