19#define DEBUG_TYPE "llvm-mca"
26 : LQSize(LQ), SQSize(SQ), UsedLQEntries(0), UsedSQEntries(0),
27 NoAlias(AssumeNoAlias), NextGroupID(1) {
45 for (
const std::pair<
unsigned, std::unique_ptr<MemoryGroup>> &
G : Groups)
46 G.second->cycleEvent();
56 for (
const auto &GroupIt : Groups) {
58 dbgs() <<
"[LSUnit] Group (" << GroupIt.first <<
"): "
86 unsigned ImmediateLoadDominator =
87 std::max(CurrentLoadGroupID, CurrentLoadBarrierGroupID);
88 if (ImmediateLoadDominator) {
90 LLVM_DEBUG(
dbgs() <<
"[LSUnit]: GROUP DEP: (" << ImmediateLoadDominator
91 <<
") --> (" << NewGID <<
")\n");
96 if (CurrentStoreBarrierGroupID) {
99 << CurrentStoreBarrierGroupID
100 <<
") --> (" << NewGID <<
")\n");
105 if (CurrentStoreGroupID &&
106 (CurrentStoreGroupID != CurrentStoreBarrierGroupID)) {
108 LLVM_DEBUG(
dbgs() <<
"[LSUnit]: GROUP DEP: (" << CurrentStoreGroupID
109 <<
") --> (" << NewGID <<
")\n");
114 CurrentStoreGroupID = NewGID;
116 CurrentStoreBarrierGroupID = NewGID;
119 CurrentLoadGroupID = NewGID;
121 CurrentLoadBarrierGroupID = NewGID;
129 unsigned ImmediateLoadDominator =
130 std::max(CurrentLoadGroupID, CurrentLoadBarrierGroupID);
144 bool ShouldCreateANewGroup =
145 IsLoadBarrier || !ImmediateLoadDominator ||
146 CurrentLoadBarrierGroupID == ImmediateLoadDominator ||
147 ImmediateLoadDominator <= CurrentStoreGroupID ||
150 if (ShouldCreateANewGroup) {
159 LLVM_DEBUG(
dbgs() <<
"[LSUnit]: GROUP DEP: (" << CurrentStoreGroupID
160 <<
") --> (" << NewGID <<
")\n");
166 if (ImmediateLoadDominator) {
169 << ImmediateLoadDominator
170 <<
") --> (" << NewGID <<
")\n");
175 if (CurrentLoadBarrierGroupID) {
178 << CurrentLoadBarrierGroupID
179 <<
") --> (" << NewGID <<
")\n");
184 CurrentLoadGroupID = NewGID;
186 CurrentLoadBarrierGroupID = NewGID;
193 return CurrentLoadGroupID;
206 unsigned GroupID =
IR.getInstruction()->getLSUTokenID();
207 auto It = Groups.find(GroupID);
208 assert(It != Groups.end() &&
"Instruction not dispatched to the LS unit");
209 It->second->onInstructionExecuted(
IR);
210 if (It->second->isExecuted())
218 assert((IsALoad || IsAStore) &&
"Expected a memory operation!");
223 <<
" has been removed from the load queue.\n");
229 <<
" has been removed from the store queue.\n");
241 if (GroupID == CurrentLoadGroupID)
242 CurrentLoadGroupID = 0;
243 if (GroupID == CurrentStoreGroupID)
244 CurrentStoreGroupID = 0;
245 if (GroupID == CurrentLoadBarrierGroupID)
246 CurrentLoadBarrierGroupID = 0;
247 if (GroupID == CurrentStoreBarrierGroupID)
248 CurrentStoreBarrierGroupID = 0;
A Load/Store unit class that models load/store queues and that implements a simple weak memory consis...
Legalize the Machine IR a function s Machine IR
This file defines abstractions used by the Pipeline to model register reads, register writes and inst...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
An InstRef contains both a SourceMgr index and Instruction pair.
bool isAStoreBarrier() const
bool isALoadBarrier() const
An instruction propagated through the simulated instruction pipeline.
unsigned getLSUTokenID() const
virtual void onInstructionExecuted(const InstRef &IR)
unsigned getUsedSQEntries() const
bool isValidGroupID(unsigned Index) const
const MemoryGroup & getGroup(unsigned Index) const
unsigned createMemoryGroup()
virtual void cycleEvent()
unsigned getUsedLQEntries() const
bool assumeNoAlias() const
virtual void onInstructionRetired(const InstRef &IR)
unsigned getLoadQueueSize() const
Returns the total number of entries in the load queue.
LSUnitBase(const MCSchedModel &SM, unsigned LoadQueueSize, unsigned StoreQueueSize, bool AssumeNoAlias)
unsigned getStoreQueueSize() const
Returns the total number of entries in the store queue.
Status isAvailable(const InstRef &IR) const override
Returns LSU_AVAILABLE if there are enough load/store queue entries to accomodate instruction IR.
void onInstructionExecuted(const InstRef &IR) override
unsigned dispatch(const InstRef &IR) override
Allocates LS resources for instruction IR.
A node of a memory dependency graph.
unsigned getNumExecuted() const
unsigned getNumExecutingPredecessors() const
unsigned getNumExecuting() const
unsigned getNumExecutedPredecessors() const
unsigned getNumInstructions() const
unsigned getNumPredecessors() const
void addSuccessor(MemoryGroup *Group, bool IsDataDependent)
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Define a kind of processor resource that will be modeled by the scheduler.
Machine model for scheduling, bundling, and heuristics.
bool hasExtraProcessorInfo() const
const MCExtraProcessorInfo & getExtraProcessorInfo() const
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const