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A15SDOptimizer.cpp
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1 //=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The Cortex-A15 processor employs a tracking scheme in its register renaming
10 // in order to process each instruction's micro-ops speculatively and
11 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
12 // instructions to read and write 32-bit S-registers. Each S-register
13 // corresponds to one half (upper or lower) of an overlaid 64-bit D-register.
14 //
15 // There are several instruction patterns which can be used to provide this
16 // capability which can provide higher performance than other, potentially more
17 // direct patterns, specifically around when one micro-op reads a D-register
18 // operand that has recently been written as one or more S-register results.
19 //
20 // This file defines a pre-regalloc pass which looks for SPR producers which
21 // are going to be used by a DPR (or QPR) consumers and creates the more
22 // optimized access pattern.
23 //
24 //===----------------------------------------------------------------------===//
25 
26 #include "ARM.h"
27 #include "ARMBaseInstrInfo.h"
28 #include "ARMBaseRegisterInfo.h"
29 #include "ARMSubtarget.h"
30 #include "llvm/ADT/Statistic.h"
38 #include "llvm/Support/Debug.h"
40 #include <map>
41 #include <set>
42 
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "a15-sd-optimizer"
46 
47 namespace {
48  struct A15SDOptimizer : public MachineFunctionPass {
49  static char ID;
50  A15SDOptimizer() : MachineFunctionPass(ID) {}
51 
52  bool runOnMachineFunction(MachineFunction &Fn) override;
53 
54  StringRef getPassName() const override { return "ARM A15 S->D optimizer"; }
55 
56  private:
57  const ARMBaseInstrInfo *TII;
58  const TargetRegisterInfo *TRI;
60 
61  bool runOnInstruction(MachineInstr *MI);
62 
63  //
64  // Instruction builder helpers
65  //
66  unsigned createDupLane(MachineBasicBlock &MBB,
67  MachineBasicBlock::iterator InsertBefore,
68  const DebugLoc &DL, unsigned Reg, unsigned Lane,
69  bool QPR = false);
70 
71  unsigned createExtractSubreg(MachineBasicBlock &MBB,
72  MachineBasicBlock::iterator InsertBefore,
73  const DebugLoc &DL, unsigned DReg,
74  unsigned Lane, const TargetRegisterClass *TRC);
75 
76  unsigned createVExt(MachineBasicBlock &MBB,
77  MachineBasicBlock::iterator InsertBefore,
78  const DebugLoc &DL, unsigned Ssub0, unsigned Ssub1);
79 
80  unsigned createRegSequence(MachineBasicBlock &MBB,
81  MachineBasicBlock::iterator InsertBefore,
82  const DebugLoc &DL, unsigned Reg1,
83  unsigned Reg2);
84 
85  unsigned createInsertSubreg(MachineBasicBlock &MBB,
86  MachineBasicBlock::iterator InsertBefore,
87  const DebugLoc &DL, unsigned DReg,
88  unsigned Lane, unsigned ToInsert);
89 
90  unsigned createImplicitDef(MachineBasicBlock &MBB,
91  MachineBasicBlock::iterator InsertBefore,
92  const DebugLoc &DL);
93 
94  //
95  // Various property checkers
96  //
97  bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
98  bool hasPartialWrite(MachineInstr *MI);
99  SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
100  unsigned getDPRLaneFromSPR(unsigned SReg);
101 
102  //
103  // Methods used for getting the definitions of partial registers
104  //
105 
106  MachineInstr *elideCopies(MachineInstr *MI);
107  void elideCopiesAndPHIs(MachineInstr *MI,
109 
110  //
111  // Pattern optimization methods
112  //
113  unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
114  unsigned optimizeSDPattern(MachineInstr *MI);
115  unsigned getPrefSPRLane(unsigned SReg);
116 
117  //
118  // Sanitizing method - used to make sure if don't leave dead code around.
119  //
120  void eraseInstrWithNoUses(MachineInstr *MI);
121 
122  //
123  // A map used to track the changes done by this pass.
124  //
125  std::map<MachineInstr*, unsigned> Replacements;
126  std::set<MachineInstr *> DeadInstr;
127  };
128  char A15SDOptimizer::ID = 0;
129 } // end anonymous namespace
130 
131 // Returns true if this is a use of a SPR register.
132 bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
133  const TargetRegisterClass *TRC) {
134  if (!MO.isReg())
135  return false;
136  Register Reg = MO.getReg();
137 
139  return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
140  else
141  return TRC->contains(Reg);
142 }
143 
144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
145  unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
146  &ARM::DPRRegClass);
147  if (DReg != ARM::NoRegister) return ARM::ssub_1;
148  return ARM::ssub_0;
149 }
150 
151 // Get the subreg type that is most likely to be coalesced
152 // for an SPR register that will be used in VDUP32d pseudo.
153 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
154  if (!Register::isVirtualRegister(SReg))
155  return getDPRLaneFromSPR(SReg);
156 
157  MachineInstr *MI = MRI->getVRegDef(SReg);
158  if (!MI) return ARM::ssub_0;
159  MachineOperand *MO = MI->findRegisterDefOperand(SReg);
160  if (!MO) return ARM::ssub_0;
161  assert(MO->isReg() && "Non-register operand found!");
162 
163  if (MI->isCopy() && usesRegClass(MI->getOperand(1),
164  &ARM::SPRRegClass)) {
165  SReg = MI->getOperand(1).getReg();
166  }
167 
168  if (Register::isVirtualRegister(SReg)) {
169  if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
170  return ARM::ssub_0;
171  }
172  return getDPRLaneFromSPR(SReg);
173 }
174 
175 // MI is known to be dead. Figure out what instructions
176 // are also made dead by this and mark them for removal.
177 void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
179  DeadInstr.insert(MI);
180 
181  LLVM_DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
182  Front.push_back(MI);
183 
184  while (Front.size() != 0) {
185  MI = Front.back();
186  Front.pop_back();
187 
188  // MI is already known to be dead. We need to see
189  // if other instructions can also be removed.
190  for (MachineOperand &MO : MI->operands()) {
191  if ((!MO.isReg()) || (!MO.isUse()))
192  continue;
193  Register Reg = MO.getReg();
194  if (!Register::isVirtualRegister(Reg))
195  continue;
197 
198  if (!Op)
199  continue;
200 
201  MachineInstr *Def = Op->getParent();
202 
203  // We don't need to do anything if we have already marked
204  // this instruction as being dead.
205  if (DeadInstr.find(Def) != DeadInstr.end())
206  continue;
207 
208  // Check if all the uses of this instruction are marked as
209  // dead. If so, we can also mark this instruction as being
210  // dead.
211  bool IsDead = true;
212  for (MachineOperand &MODef : Def->operands()) {
213  if ((!MODef.isReg()) || (!MODef.isDef()))
214  continue;
215  Register DefReg = MODef.getReg();
216  if (!Register::isVirtualRegister(DefReg)) {
217  IsDead = false;
218  break;
219  }
220  for (MachineInstr &Use : MRI->use_instructions(Reg)) {
221  // We don't care about self references.
222  if (&Use == Def)
223  continue;
224  if (DeadInstr.find(&Use) == DeadInstr.end()) {
225  IsDead = false;
226  break;
227  }
228  }
229  }
230 
231  if (!IsDead) continue;
232 
233  LLVM_DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
234  DeadInstr.insert(Def);
235  }
236  }
237 }
238 
239 // Creates the more optimized patterns and generally does all the code
240 // transformations in this pass.
241 unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
242  if (MI->isCopy()) {
243  return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
244  }
245 
246  if (MI->isInsertSubreg()) {
247  Register DPRReg = MI->getOperand(1).getReg();
248  Register SPRReg = MI->getOperand(2).getReg();
249 
251  MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
252  MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
253 
254  if (DPRMI && SPRMI) {
255  // See if the first operand of this insert_subreg is IMPLICIT_DEF
256  MachineInstr *ECDef = elideCopies(DPRMI);
257  if (ECDef && ECDef->isImplicitDef()) {
258  // Another corner case - if we're inserting something that is purely
259  // a subreg copy of a DPR, just use that DPR.
260 
261  MachineInstr *EC = elideCopies(SPRMI);
262  // Is it a subreg copy of ssub_0?
263  if (EC && EC->isCopy() &&
264  EC->getOperand(1).getSubReg() == ARM::ssub_0) {
265  LLVM_DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
266 
267  // Find the thing we're subreg copying out of - is it of the same
268  // regclass as DPRMI? (i.e. a DPR or QPR).
269  Register FullReg = SPRMI->getOperand(1).getReg();
270  const TargetRegisterClass *TRC =
271  MRI->getRegClass(MI->getOperand(1).getReg());
272  if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
273  LLVM_DEBUG(dbgs() << "Subreg copy is compatible - returning ");
274  LLVM_DEBUG(dbgs() << printReg(FullReg) << "\n");
275  eraseInstrWithNoUses(MI);
276  return FullReg;
277  }
278  }
279 
280  return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
281  }
282  }
283  }
284  return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
285  }
286 
287  if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
288  &ARM::SPRRegClass)) {
289  // See if all bar one of the operands are IMPLICIT_DEF and insert the
290  // optimizer pattern accordingly.
291  unsigned NumImplicit = 0, NumTotal = 0;
292  unsigned NonImplicitReg = ~0U;
293 
294  for (unsigned I = 1; I < MI->getNumExplicitOperands(); ++I) {
295  if (!MI->getOperand(I).isReg())
296  continue;
297  ++NumTotal;
298  Register OpReg = MI->getOperand(I).getReg();
299 
300  if (!Register::isVirtualRegister(OpReg))
301  break;
302 
303  MachineInstr *Def = MRI->getVRegDef(OpReg);
304  if (!Def)
305  break;
306  if (Def->isImplicitDef())
307  ++NumImplicit;
308  else
309  NonImplicitReg = MI->getOperand(I).getReg();
310  }
311 
312  if (NumImplicit == NumTotal - 1)
313  return optimizeAllLanesPattern(MI, NonImplicitReg);
314  else
315  return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
316  }
317 
318  llvm_unreachable("Unhandled update pattern!");
319 }
320 
321 // Return true if this MachineInstr inserts a scalar (SPR) value into
322 // a D or Q register.
323 bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
324  // The only way we can do a partial register update is through a COPY,
325  // INSERT_SUBREG or REG_SEQUENCE.
326  if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
327  return true;
328 
329  if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
330  &ARM::SPRRegClass))
331  return true;
332 
333  if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
334  return true;
335 
336  return false;
337 }
338 
339 // Looks through full copies to get the instruction that defines the input
340 // operand for MI.
341 MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
342  if (!MI->isFullCopy())
343  return MI;
345  return nullptr;
346  MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
347  if (!Def)
348  return nullptr;
349  return elideCopies(Def);
350 }
351 
352 // Look through full copies and PHIs to get the set of non-copy MachineInstrs
353 // that can produce MI.
354 void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
356  // Looking through PHIs may create loops so we need to track what
357  // instructions we have visited before.
358  std::set<MachineInstr *> Reached;
360  Front.push_back(MI);
361  while (Front.size() != 0) {
362  MI = Front.back();
363  Front.pop_back();
364 
365  // If we have already explored this MachineInstr, ignore it.
366  if (Reached.find(MI) != Reached.end())
367  continue;
368  Reached.insert(MI);
369  if (MI->isPHI()) {
370  for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
371  Register Reg = MI->getOperand(I).getReg();
372  if (!Register::isVirtualRegister(Reg)) {
373  continue;
374  }
375  MachineInstr *NewMI = MRI->getVRegDef(Reg);
376  if (!NewMI)
377  continue;
378  Front.push_back(NewMI);
379  }
380  } else if (MI->isFullCopy()) {
382  continue;
383  MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
384  if (!NewMI)
385  continue;
386  Front.push_back(NewMI);
387  } else {
388  LLVM_DEBUG(dbgs() << "Found partial copy" << *MI << "\n");
389  Outs.push_back(MI);
390  }
391  }
392 }
393 
394 // Return the DPR virtual registers that are read by this machine instruction
395 // (if any).
396 SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
397  if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() ||
398  MI->isKill())
399  return SmallVector<unsigned, 8>();
400 
402  for (MachineOperand &MO : MI->operands()) {
403  if (!MO.isReg() || !MO.isUse())
404  continue;
405  if (!usesRegClass(MO, &ARM::DPRRegClass) &&
406  !usesRegClass(MO, &ARM::QPRRegClass) &&
407  !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
408  continue;
409 
410  Defs.push_back(MO.getReg());
411  }
412  return Defs;
413 }
414 
415 // Creates a DPR register from an SPR one by using a VDUP.
416 unsigned A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
417  MachineBasicBlock::iterator InsertBefore,
418  const DebugLoc &DL, unsigned Reg,
419  unsigned Lane, bool QPR) {
420  Register Out =
421  MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass);
422  BuildMI(MBB, InsertBefore, DL,
423  TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out)
424  .addReg(Reg)
425  .addImm(Lane)
426  .add(predOps(ARMCC::AL));
427 
428  return Out;
429 }
430 
431 // Creates a SPR register from a DPR by copying the value in lane 0.
432 unsigned A15SDOptimizer::createExtractSubreg(
434  const DebugLoc &DL, unsigned DReg, unsigned Lane,
435  const TargetRegisterClass *TRC) {
436  Register Out = MRI->createVirtualRegister(TRC);
437  BuildMI(MBB,
438  InsertBefore,
439  DL,
440  TII->get(TargetOpcode::COPY), Out)
441  .addReg(DReg, 0, Lane);
442 
443  return Out;
444 }
445 
446 // Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
447 unsigned A15SDOptimizer::createRegSequence(
449  const DebugLoc &DL, unsigned Reg1, unsigned Reg2) {
450  Register Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
451  BuildMI(MBB,
452  InsertBefore,
453  DL,
454  TII->get(TargetOpcode::REG_SEQUENCE), Out)
455  .addReg(Reg1)
456  .addImm(ARM::dsub_0)
457  .addReg(Reg2)
458  .addImm(ARM::dsub_1);
459  return Out;
460 }
461 
462 // Takes two DPR registers that have previously been VDUPed (Ssub0 and Ssub1)
463 // and merges them into one DPR register.
464 unsigned A15SDOptimizer::createVExt(MachineBasicBlock &MBB,
465  MachineBasicBlock::iterator InsertBefore,
466  const DebugLoc &DL, unsigned Ssub0,
467  unsigned Ssub1) {
468  Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
469  BuildMI(MBB, InsertBefore, DL, TII->get(ARM::VEXTd32), Out)
470  .addReg(Ssub0)
471  .addReg(Ssub1)
472  .addImm(1)
473  .add(predOps(ARMCC::AL));
474  return Out;
475 }
476 
477 unsigned A15SDOptimizer::createInsertSubreg(
479  const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) {
480  Register Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
481  BuildMI(MBB,
482  InsertBefore,
483  DL,
484  TII->get(TargetOpcode::INSERT_SUBREG), Out)
485  .addReg(DReg)
486  .addReg(ToInsert)
487  .addImm(Lane);
488 
489  return Out;
490 }
491 
492 unsigned
493 A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
494  MachineBasicBlock::iterator InsertBefore,
495  const DebugLoc &DL) {
496  Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
497  BuildMI(MBB,
498  InsertBefore,
499  DL,
500  TII->get(TargetOpcode::IMPLICIT_DEF), Out);
501  return Out;
502 }
503 
504 // This function inserts instructions in order to optimize interactions between
505 // SPR registers and DPR/QPR registers. It does so by performing VDUPs on all
506 // lanes, and the using VEXT instructions to recompose the result.
507 unsigned
508 A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
509  MachineBasicBlock::iterator InsertPt(MI);
510  DebugLoc DL = MI->getDebugLoc();
511  MachineBasicBlock &MBB = *MI->getParent();
512  InsertPt++;
513  unsigned Out;
514 
515  // DPair has the same length as QPR and also has two DPRs as subreg.
516  // Treat DPair as QPR.
517  if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
518  MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
519  unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
520  ARM::dsub_0, &ARM::DPRRegClass);
521  unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
522  ARM::dsub_1, &ARM::DPRRegClass);
523 
524  unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
525  unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
526  Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
527 
528  unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
529  unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
530  Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
531 
532  Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
533 
534  } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
535  unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
536  unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
537  Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
538 
539  } else {
540  assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
541  "Found unexpected regclass!");
542 
543  unsigned PrefLane = getPrefSPRLane(Reg);
544  unsigned Lane;
545  switch (PrefLane) {
546  case ARM::ssub_0: Lane = 0; break;
547  case ARM::ssub_1: Lane = 1; break;
548  default: llvm_unreachable("Unknown preferred lane!");
549  }
550 
551  // Treat DPair as QPR
552  bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
553  usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
554 
555  Out = createImplicitDef(MBB, InsertPt, DL);
556  Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
557  Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
558  eraseInstrWithNoUses(MI);
559  }
560  return Out;
561 }
562 
563 bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
564  // We look for instructions that write S registers that are then read as
565  // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and
566  // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
567  // merge two SPR values to form a DPR register. In order avoid false
568  // positives we make sure that there is an SPR producer so we look past
569  // COPY and PHI nodes to find it.
570  //
571  // The best code pattern for when an SPR producer is going to be used by a
572  // DPR or QPR consumer depends on whether the other lanes of the
573  // corresponding DPR/QPR are currently defined.
574  //
575  // We can handle these efficiently, depending on the type of
576  // pseudo-instruction that is producing the pattern
577  //
578  // * COPY: * VDUP all lanes and merge the results together
579  // using VEXTs.
580  //
581  // * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
582  // lane, and the other lane(s) of the DPR/QPR register
583  // that we are inserting in are undefined, use the
584  // original DPR/QPR value.
585  // * Otherwise, fall back on the same stategy as COPY.
586  //
587  // * REG_SEQUENCE: * If all except one of the input operands are
588  // IMPLICIT_DEFs, insert the VDUP pattern for just the
589  // defined input operand
590  // * Otherwise, fall back on the same stategy as COPY.
591  //
592 
593  // First, get all the reads of D-registers done by this instruction.
594  SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
595  bool Modified = false;
596 
597  for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
598  I != E; ++I) {
599  // Follow the def-use chain for this DPR through COPYs, and also through
600  // PHIs (which are essentially multi-way COPYs). It is because of PHIs that
601  // we can end up with multiple defs of this DPR.
602 
605  continue;
606  MachineInstr *Def = MRI->getVRegDef(*I);
607  if (!Def)
608  continue;
609 
610  elideCopiesAndPHIs(Def, DefSrcs);
611 
612  for (MachineInstr *MI : DefSrcs) {
613  // If we've already analyzed and replaced this operand, don't do
614  // anything.
615  if (Replacements.find(MI) != Replacements.end())
616  continue;
617 
618  // Now, work out if the instruction causes a SPR->DPR dependency.
619  if (!hasPartialWrite(MI))
620  continue;
621 
622  // Collect all the uses of this MI's DPR def for updating later.
624  Register DPRDefReg = MI->getOperand(0).getReg();
625  for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg),
626  E = MRI->use_end(); I != E; ++I)
627  Uses.push_back(&*I);
628 
629  // We can optimize this.
630  unsigned NewReg = optimizeSDPattern(MI);
631 
632  if (NewReg != 0) {
633  Modified = true;
635  E = Uses.end(); I != E; ++I) {
636  // Make sure to constrain the register class of the new register to
637  // match what we're replacing. Otherwise we can optimize a DPR_VFP2
638  // reference into a plain DPR, and that will end poorly. NewReg is
639  // always virtual here, so there will always be a matching subclass
640  // to find.
641  MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
642 
643  LLVM_DEBUG(dbgs() << "Replacing operand " << **I << " with "
644  << printReg(NewReg) << "\n");
645  (*I)->substVirtReg(NewReg, 0, *TRI);
646  }
647  }
648  Replacements[MI] = NewReg;
649  }
650  }
651  return Modified;
652 }
653 
654 bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
655  if (skipFunction(Fn.getFunction()))
656  return false;
657 
658  const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
659  // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
660  // enabled when NEON is available.
661  if (!(STI.useSplatVFPToNeon() && STI.hasNEON()))
662  return false;
663 
664  TII = STI.getInstrInfo();
665  TRI = STI.getRegisterInfo();
666  MRI = &Fn.getRegInfo();
667  bool Modified = false;
668 
669  LLVM_DEBUG(dbgs() << "Running on function " << Fn.getName() << "\n");
670 
671  DeadInstr.clear();
672  Replacements.clear();
673 
674  for (MachineBasicBlock &MBB : Fn) {
675  for (MachineInstr &MI : MBB) {
676  Modified |= runOnInstruction(&MI);
677  }
678  }
679 
680  for (MachineInstr *MI : DeadInstr) {
681  MI->eraseFromParent();
682  }
683 
684  return Modified;
685 }
686 
688  return new A15SDOptimizer();
689 }
const MachineInstrBuilder & add(const MachineOperand &MO) const
FunctionPass * createA15SDOptimizerPass()
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
bool IsDead
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:366
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:409
unsigned Reg
unsigned getSubReg() const
bool isRegSequence() const
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:559
bool isCopyLike() const
Return true if the instruction behaves like a copy.
bool isPHI() const
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineBasicBlock & MBB
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:539
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:459
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
bool isFullCopy() const
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
bool isCopy() const
bool isImplicitDef() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
MachineOperand class - Representation of each machine instruction operand.
bool isInsertSubreg() const
bool hasNEON() const
Definition: ARMSubtarget.h:628
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
typename SuperClass::iterator iterator
Definition: SmallVector.h:365
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:513
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:280
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:62
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:59
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:551
bool useSplatVFPToNeon() const
Definition: ARMSubtarget.h:680
bool isKill() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:466
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL