LLVM 19.0.0git
SystemZAsmParser.cpp
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1//===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
14#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/MC/MCAsmInfo.h"
19#include "llvm/MC/MCContext.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
29#include "llvm/MC/MCStreamer.h"
34#include "llvm/Support/SMLoc.h"
35#include <algorithm>
36#include <cassert>
37#include <cstddef>
38#include <cstdint>
39#include <iterator>
40#include <memory>
41#include <string>
42
43using namespace llvm;
44
45// Return true if Expr is in the range [MinValue, MaxValue]. If AllowSymbol
46// is true any MCExpr is accepted (address displacement).
47static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue,
48 bool AllowSymbol = false) {
49 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
50 int64_t Value = CE->getValue();
51 return Value >= MinValue && Value <= MaxValue;
52 }
53 return AllowSymbol;
54}
55
56namespace {
57
58enum RegisterKind {
59 GR32Reg,
60 GRH32Reg,
61 GR64Reg,
62 GR128Reg,
63 FP32Reg,
64 FP64Reg,
65 FP128Reg,
66 VR32Reg,
67 VR64Reg,
68 VR128Reg,
69 AR32Reg,
70 CR64Reg,
71};
72
73enum MemoryKind {
74 BDMem,
75 BDXMem,
76 BDLMem,
77 BDRMem,
78 BDVMem
79};
80
81class SystemZOperand : public MCParsedAsmOperand {
82private:
83 enum OperandKind {
84 KindInvalid,
85 KindToken,
86 KindReg,
87 KindImm,
88 KindImmTLS,
89 KindMem
90 };
91
92 OperandKind Kind;
93 SMLoc StartLoc, EndLoc;
94
95 // A string of length Length, starting at Data.
96 struct TokenOp {
97 const char *Data;
98 unsigned Length;
99 };
100
101 // LLVM register Num, which has kind Kind. In some ways it might be
102 // easier for this class to have a register bank (general, floating-point
103 // or access) and a raw register number (0-15). This would postpone the
104 // interpretation of the operand to the add*() methods and avoid the need
105 // for context-dependent parsing. However, we do things the current way
106 // because of the virtual getReg() method, which needs to distinguish
107 // between (say) %r0 used as a single register and %r0 used as a pair.
108 // Context-dependent parsing can also give us slightly better error
109 // messages when invalid pairs like %r1 are used.
110 struct RegOp {
111 RegisterKind Kind;
112 unsigned Num;
113 };
114
115 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
116 // MemKind says what type of memory this is and RegKind says what type
117 // the base register has (GR32Reg or GR64Reg). Length is the operand
118 // length for D(L,B)-style operands, otherwise it is null.
119 struct MemOp {
120 unsigned Base : 12;
121 unsigned Index : 12;
122 unsigned MemKind : 4;
123 unsigned RegKind : 4;
124 const MCExpr *Disp;
125 union {
126 const MCExpr *Imm;
127 unsigned Reg;
128 } Length;
129 };
130
131 // Imm is an immediate operand, and Sym is an optional TLS symbol
132 // for use with a __tls_get_offset marker relocation.
133 struct ImmTLSOp {
134 const MCExpr *Imm;
135 const MCExpr *Sym;
136 };
137
138 union {
139 TokenOp Token;
140 RegOp Reg;
141 const MCExpr *Imm;
142 ImmTLSOp ImmTLS;
143 MemOp Mem;
144 };
145
146 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
147 // Add as immediates when possible. Null MCExpr = 0.
148 if (!Expr)
150 else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
151 Inst.addOperand(MCOperand::createImm(CE->getValue()));
152 else
154 }
155
156public:
157 SystemZOperand(OperandKind Kind, SMLoc StartLoc, SMLoc EndLoc)
158 : Kind(Kind), StartLoc(StartLoc), EndLoc(EndLoc) {}
159
160 // Create particular kinds of operand.
161 static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
162 SMLoc EndLoc) {
163 return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
164 }
165
166 static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
167 auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc);
168 Op->Token.Data = Str.data();
169 Op->Token.Length = Str.size();
170 return Op;
171 }
172
173 static std::unique_ptr<SystemZOperand>
174 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
175 auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
176 Op->Reg.Kind = Kind;
177 Op->Reg.Num = Num;
178 return Op;
179 }
180
181 static std::unique_ptr<SystemZOperand>
182 createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
183 auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
184 Op->Imm = Expr;
185 return Op;
186 }
187
188 static std::unique_ptr<SystemZOperand>
189 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
190 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
191 unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
192 auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
193 Op->Mem.MemKind = MemKind;
194 Op->Mem.RegKind = RegKind;
195 Op->Mem.Base = Base;
196 Op->Mem.Index = Index;
197 Op->Mem.Disp = Disp;
198 if (MemKind == BDLMem)
199 Op->Mem.Length.Imm = LengthImm;
200 if (MemKind == BDRMem)
201 Op->Mem.Length.Reg = LengthReg;
202 return Op;
203 }
204
205 static std::unique_ptr<SystemZOperand>
206 createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
207 SMLoc StartLoc, SMLoc EndLoc) {
208 auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
209 Op->ImmTLS.Imm = Imm;
210 Op->ImmTLS.Sym = Sym;
211 return Op;
212 }
213
214 // Token operands
215 bool isToken() const override {
216 return Kind == KindToken;
217 }
218 StringRef getToken() const {
219 assert(Kind == KindToken && "Not a token");
220 return StringRef(Token.Data, Token.Length);
221 }
222
223 // Register operands.
224 bool isReg() const override {
225 return Kind == KindReg;
226 }
227 bool isReg(RegisterKind RegKind) const {
228 return Kind == KindReg && Reg.Kind == RegKind;
229 }
230 MCRegister getReg() const override {
231 assert(Kind == KindReg && "Not a register");
232 return Reg.Num;
233 }
234
235 // Immediate operands.
236 bool isImm() const override {
237 return Kind == KindImm;
238 }
239 bool isImm(int64_t MinValue, int64_t MaxValue) const {
240 return Kind == KindImm && inRange(Imm, MinValue, MaxValue, true);
241 }
242 const MCExpr *getImm() const {
243 assert(Kind == KindImm && "Not an immediate");
244 return Imm;
245 }
246
247 // Immediate operands with optional TLS symbol.
248 bool isImmTLS() const {
249 return Kind == KindImmTLS;
250 }
251
252 const ImmTLSOp getImmTLS() const {
253 assert(Kind == KindImmTLS && "Not a TLS immediate");
254 return ImmTLS;
255 }
256
257 // Memory operands.
258 bool isMem() const override {
259 return Kind == KindMem;
260 }
261 bool isMem(MemoryKind MemKind) const {
262 return (Kind == KindMem &&
263 (Mem.MemKind == MemKind ||
264 // A BDMem can be treated as a BDXMem in which the index
265 // register field is 0.
266 (Mem.MemKind == BDMem && MemKind == BDXMem)));
267 }
268 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
269 return isMem(MemKind) && Mem.RegKind == RegKind;
270 }
271 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
272 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff, true);
273 }
274 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
275 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287, true);
276 }
277 bool isMemDisp12Len4(RegisterKind RegKind) const {
278 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
279 }
280 bool isMemDisp12Len8(RegisterKind RegKind) const {
281 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
282 }
283
284 const MemOp& getMem() const {
285 assert(Kind == KindMem && "Not a Mem operand");
286 return Mem;
287 }
288
289 // Override MCParsedAsmOperand.
290 SMLoc getStartLoc() const override { return StartLoc; }
291 SMLoc getEndLoc() const override { return EndLoc; }
292 void print(raw_ostream &OS) const override;
293
294 /// getLocRange - Get the range between the first and last token of this
295 /// operand.
296 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
297
298 // Used by the TableGen code to add particular types of operand
299 // to an instruction.
300 void addRegOperands(MCInst &Inst, unsigned N) const {
301 assert(N == 1 && "Invalid number of operands");
303 }
304 void addImmOperands(MCInst &Inst, unsigned N) const {
305 assert(N == 1 && "Invalid number of operands");
306 addExpr(Inst, getImm());
307 }
308 void addBDAddrOperands(MCInst &Inst, unsigned N) const {
309 assert(N == 2 && "Invalid number of operands");
310 assert(isMem(BDMem) && "Invalid operand type");
311 Inst.addOperand(MCOperand::createReg(Mem.Base));
312 addExpr(Inst, Mem.Disp);
313 }
314 void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
315 assert(N == 3 && "Invalid number of operands");
316 assert(isMem(BDXMem) && "Invalid operand type");
317 Inst.addOperand(MCOperand::createReg(Mem.Base));
318 addExpr(Inst, Mem.Disp);
319 Inst.addOperand(MCOperand::createReg(Mem.Index));
320 }
321 void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
322 assert(N == 3 && "Invalid number of operands");
323 assert(isMem(BDLMem) && "Invalid operand type");
324 Inst.addOperand(MCOperand::createReg(Mem.Base));
325 addExpr(Inst, Mem.Disp);
326 addExpr(Inst, Mem.Length.Imm);
327 }
328 void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
329 assert(N == 3 && "Invalid number of operands");
330 assert(isMem(BDRMem) && "Invalid operand type");
331 Inst.addOperand(MCOperand::createReg(Mem.Base));
332 addExpr(Inst, Mem.Disp);
333 Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
334 }
335 void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
336 assert(N == 3 && "Invalid number of operands");
337 assert(isMem(BDVMem) && "Invalid operand type");
338 Inst.addOperand(MCOperand::createReg(Mem.Base));
339 addExpr(Inst, Mem.Disp);
340 Inst.addOperand(MCOperand::createReg(Mem.Index));
341 }
342 void addImmTLSOperands(MCInst &Inst, unsigned N) const {
343 assert(N == 2 && "Invalid number of operands");
344 assert(Kind == KindImmTLS && "Invalid operand type");
345 addExpr(Inst, ImmTLS.Imm);
346 if (ImmTLS.Sym)
347 addExpr(Inst, ImmTLS.Sym);
348 }
349
350 // Used by the TableGen code to check for particular operand types.
351 bool isGR32() const { return isReg(GR32Reg); }
352 bool isGRH32() const { return isReg(GRH32Reg); }
353 bool isGRX32() const { return false; }
354 bool isGR64() const { return isReg(GR64Reg); }
355 bool isGR128() const { return isReg(GR128Reg); }
356 bool isADDR32() const { return isReg(GR32Reg); }
357 bool isADDR64() const { return isReg(GR64Reg); }
358 bool isADDR128() const { return false; }
359 bool isFP32() const { return isReg(FP32Reg); }
360 bool isFP64() const { return isReg(FP64Reg); }
361 bool isFP128() const { return isReg(FP128Reg); }
362 bool isVR32() const { return isReg(VR32Reg); }
363 bool isVR64() const { return isReg(VR64Reg); }
364 bool isVF128() const { return false; }
365 bool isVR128() const { return isReg(VR128Reg); }
366 bool isAR32() const { return isReg(AR32Reg); }
367 bool isCR64() const { return isReg(CR64Reg); }
368 bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
369 bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, GR32Reg); }
370 bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, GR32Reg); }
371 bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, GR64Reg); }
372 bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, GR64Reg); }
373 bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, GR64Reg); }
374 bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, GR64Reg); }
375 bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(GR64Reg); }
376 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(GR64Reg); }
377 bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, GR64Reg); }
378 bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, GR64Reg); }
379 bool isU1Imm() const { return isImm(0, 1); }
380 bool isU2Imm() const { return isImm(0, 3); }
381 bool isU3Imm() const { return isImm(0, 7); }
382 bool isU4Imm() const { return isImm(0, 15); }
383 bool isU8Imm() const { return isImm(0, 255); }
384 bool isS8Imm() const { return isImm(-128, 127); }
385 bool isU12Imm() const { return isImm(0, 4095); }
386 bool isU16Imm() const { return isImm(0, 65535); }
387 bool isS16Imm() const { return isImm(-32768, 32767); }
388 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
389 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
390 bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
391};
392
393class SystemZAsmParser : public MCTargetAsmParser {
394#define GET_ASSEMBLER_HEADER
395#include "SystemZGenAsmMatcher.inc"
396
397private:
398 MCAsmParser &Parser;
399 enum RegisterGroup {
400 RegGR,
401 RegFP,
402 RegV,
403 RegAR,
404 RegCR
405 };
406 struct Register {
407 RegisterGroup Group;
408 unsigned Num;
409 SMLoc StartLoc, EndLoc;
410 };
411
412 SystemZTargetStreamer &getTargetStreamer() {
413 assert(getParser().getStreamer().getTargetStreamer() &&
414 "do not have a target streamer");
416 return static_cast<SystemZTargetStreamer &>(TS);
417 }
418
419 bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
420
421 bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
422
423 ParseStatus parseRegister(OperandVector &Operands, RegisterKind Kind);
424
425 ParseStatus parseAnyRegister(OperandVector &Operands);
426
427 bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
428 Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
429 bool HasLength = false, bool HasVectorIndex = false);
430 bool parseAddressRegister(Register &Reg);
431
432 bool ParseDirectiveInsn(SMLoc L);
433 bool ParseDirectiveMachine(SMLoc L);
434 bool ParseGNUAttribute(SMLoc L);
435
436 ParseStatus parseAddress(OperandVector &Operands, MemoryKind MemKind,
437 RegisterKind RegKind);
438
439 ParseStatus parsePCRel(OperandVector &Operands, int64_t MinVal,
440 int64_t MaxVal, bool AllowTLS);
441
442 bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
443
444 // Both the hlasm and att variants still rely on the basic gnu asm
445 // format with respect to inputs, clobbers, outputs etc.
446 //
447 // However, calling the overriden getAssemblerDialect() method in
448 // AsmParser is problematic. It either returns the AssemblerDialect field
449 // in the MCAsmInfo instance if the AssemblerDialect field in AsmParser is
450 // unset, otherwise it returns the private AssemblerDialect field in
451 // AsmParser.
452 //
453 // The problematic part is because, we forcibly set the inline asm dialect
454 // in the AsmParser instance in AsmPrinterInlineAsm.cpp. Soo any query
455 // to the overriden getAssemblerDialect function in AsmParser.cpp, will
456 // not return the assembler dialect set in the respective MCAsmInfo instance.
457 //
458 // For this purpose, we explicitly query the SystemZMCAsmInfo instance
459 // here, to get the "correct" assembler dialect, and use it in various
460 // functions.
461 unsigned getMAIAssemblerDialect() {
462 return Parser.getContext().getAsmInfo()->getAssemblerDialect();
463 }
464
465 // An alphabetic character in HLASM is a letter from 'A' through 'Z',
466 // or from 'a' through 'z', or '$', '_','#', or '@'.
467 inline bool isHLASMAlpha(char C) {
468 return isAlpha(C) || llvm::is_contained("_@#$", C);
469 }
470
471 // A digit in HLASM is a number from 0 to 9.
472 inline bool isHLASMAlnum(char C) { return isHLASMAlpha(C) || isDigit(C); }
473
474 // Are we parsing using the AD_HLASM dialect?
475 inline bool isParsingHLASM() { return getMAIAssemblerDialect() == AD_HLASM; }
476
477 // Are we parsing using the AD_ATT dialect?
478 inline bool isParsingATT() { return getMAIAssemblerDialect() == AD_ATT; }
479
480public:
481 SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
482 const MCInstrInfo &MII,
484 : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
486
487 // Alias the .word directive to .short.
488 parser.addAliasForDirective(".word", ".short");
489
490 // Initialize the set of available features.
491 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
492 }
493
494 // Override MCTargetAsmParser.
495 ParseStatus parseDirective(AsmToken DirectiveID) override;
496 bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
497 bool ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
498 bool RestoreOnFailure);
500 SMLoc &EndLoc) override;
502 SMLoc NameLoc, OperandVector &Operands) override;
503 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
506 bool MatchingInlineAsm) override;
507 bool isLabel(AsmToken &Token) override;
508
509 // Used by the TableGen code to parse particular operand types.
511 return parseRegister(Operands, GR32Reg);
512 }
513 ParseStatus parseGRH32(OperandVector &Operands) {
514 return parseRegister(Operands, GRH32Reg);
515 }
516 ParseStatus parseGRX32(OperandVector &Operands) {
517 llvm_unreachable("GRX32 should only be used for pseudo instructions");
518 }
520 return parseRegister(Operands, GR64Reg);
521 }
522 ParseStatus parseGR128(OperandVector &Operands) {
523 return parseRegister(Operands, GR128Reg);
524 }
525 ParseStatus parseADDR32(OperandVector &Operands) {
526 // For the AsmParser, we will accept %r0 for ADDR32 as well.
527 return parseRegister(Operands, GR32Reg);
528 }
529 ParseStatus parseADDR64(OperandVector &Operands) {
530 // For the AsmParser, we will accept %r0 for ADDR64 as well.
531 return parseRegister(Operands, GR64Reg);
532 }
533 ParseStatus parseADDR128(OperandVector &Operands) {
534 llvm_unreachable("Shouldn't be used as an operand");
535 }
537 return parseRegister(Operands, FP32Reg);
538 }
540 return parseRegister(Operands, FP64Reg);
541 }
542 ParseStatus parseFP128(OperandVector &Operands) {
543 return parseRegister(Operands, FP128Reg);
544 }
546 return parseRegister(Operands, VR32Reg);
547 }
549 return parseRegister(Operands, VR64Reg);
550 }
551 ParseStatus parseVF128(OperandVector &Operands) {
552 llvm_unreachable("Shouldn't be used as an operand");
553 }
554 ParseStatus parseVR128(OperandVector &Operands) {
555 return parseRegister(Operands, VR128Reg);
556 }
558 return parseRegister(Operands, AR32Reg);
559 }
561 return parseRegister(Operands, CR64Reg);
562 }
563 ParseStatus parseAnyReg(OperandVector &Operands) {
564 return parseAnyRegister(Operands);
565 }
566 ParseStatus parseBDAddr32(OperandVector &Operands) {
567 return parseAddress(Operands, BDMem, GR32Reg);
568 }
569 ParseStatus parseBDAddr64(OperandVector &Operands) {
570 return parseAddress(Operands, BDMem, GR64Reg);
571 }
572 ParseStatus parseBDXAddr64(OperandVector &Operands) {
573 return parseAddress(Operands, BDXMem, GR64Reg);
574 }
575 ParseStatus parseBDLAddr64(OperandVector &Operands) {
576 return parseAddress(Operands, BDLMem, GR64Reg);
577 }
578 ParseStatus parseBDRAddr64(OperandVector &Operands) {
579 return parseAddress(Operands, BDRMem, GR64Reg);
580 }
581 ParseStatus parseBDVAddr64(OperandVector &Operands) {
582 return parseAddress(Operands, BDVMem, GR64Reg);
583 }
584 ParseStatus parsePCRel12(OperandVector &Operands) {
585 return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
586 }
587 ParseStatus parsePCRel16(OperandVector &Operands) {
588 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
589 }
590 ParseStatus parsePCRel24(OperandVector &Operands) {
591 return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
592 }
593 ParseStatus parsePCRel32(OperandVector &Operands) {
594 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
595 }
596 ParseStatus parsePCRelTLS16(OperandVector &Operands) {
597 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
598 }
599 ParseStatus parsePCRelTLS32(OperandVector &Operands) {
600 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
601 }
602};
603
604} // end anonymous namespace
605
606#define GET_REGISTER_MATCHER
607#define GET_SUBTARGET_FEATURE_NAME
608#define GET_MATCHER_IMPLEMENTATION
609#define GET_MNEMONIC_SPELL_CHECKER
610#include "SystemZGenAsmMatcher.inc"
611
612// Used for the .insn directives; contains information needed to parse the
613// operands in the directive.
617 int32_t NumOperands;
618 MatchClassKind OperandKinds[7];
619};
620
621// For equal_range comparison.
623 bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
624 return LHS.Format < RHS;
625 }
626 bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
627 return LHS < RHS.Format;
628 }
629 bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
630 return LHS.Format < RHS.Format;
631 }
632};
633
634// Table initializing information for parsing the .insn directive.
636 /* Format, Opcode, NumOperands, OperandKinds */
637 { "e", SystemZ::InsnE, 1,
638 { MCK_U16Imm } },
639 { "ri", SystemZ::InsnRI, 3,
640 { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
641 { "rie", SystemZ::InsnRIE, 4,
642 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
643 { "ril", SystemZ::InsnRIL, 3,
644 { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
645 { "rilu", SystemZ::InsnRILU, 3,
646 { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
647 { "ris", SystemZ::InsnRIS, 5,
648 { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
649 { "rr", SystemZ::InsnRR, 3,
650 { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
651 { "rre", SystemZ::InsnRRE, 3,
652 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
653 { "rrf", SystemZ::InsnRRF, 5,
654 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
655 { "rrs", SystemZ::InsnRRS, 5,
656 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
657 { "rs", SystemZ::InsnRS, 4,
658 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
659 { "rse", SystemZ::InsnRSE, 4,
660 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
661 { "rsi", SystemZ::InsnRSI, 4,
662 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
663 { "rsy", SystemZ::InsnRSY, 4,
664 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
665 { "rx", SystemZ::InsnRX, 3,
666 { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
667 { "rxe", SystemZ::InsnRXE, 3,
668 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
669 { "rxf", SystemZ::InsnRXF, 4,
670 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
671 { "rxy", SystemZ::InsnRXY, 3,
672 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
673 { "s", SystemZ::InsnS, 2,
674 { MCK_U32Imm, MCK_BDAddr64Disp12 } },
675 { "si", SystemZ::InsnSI, 3,
676 { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
677 { "sil", SystemZ::InsnSIL, 3,
678 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
679 { "siy", SystemZ::InsnSIY, 3,
680 { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
681 { "ss", SystemZ::InsnSS, 4,
682 { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
683 { "sse", SystemZ::InsnSSE, 3,
684 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
685 { "ssf", SystemZ::InsnSSF, 4,
686 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
687 { "vri", SystemZ::InsnVRI, 6,
688 { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } },
689 { "vrr", SystemZ::InsnVRR, 7,
690 { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm,
691 MCK_U4Imm } },
692 { "vrs", SystemZ::InsnVRS, 5,
693 { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } },
694 { "vrv", SystemZ::InsnVRV, 4,
695 { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } },
696 { "vrx", SystemZ::InsnVRX, 4,
697 { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } },
698 { "vsi", SystemZ::InsnVSI, 4,
699 { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } }
700};
701
702static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
703 if (!E)
704 return;
705 if (auto *CE = dyn_cast<MCConstantExpr>(E))
706 OS << *CE;
707 else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
708 OS << *UE;
709 else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
710 OS << *BE;
711 else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
712 OS << *SRE;
713 else
714 OS << *E;
715}
716
717void SystemZOperand::print(raw_ostream &OS) const {
718 switch (Kind) {
719 case KindToken:
720 OS << "Token:" << getToken();
721 break;
722 case KindReg:
724 break;
725 case KindImm:
726 OS << "Imm:";
727 printMCExpr(getImm(), OS);
728 break;
729 case KindImmTLS:
730 OS << "ImmTLS:";
731 printMCExpr(getImmTLS().Imm, OS);
732 if (getImmTLS().Sym) {
733 OS << ", ";
734 printMCExpr(getImmTLS().Sym, OS);
735 }
736 break;
737 case KindMem: {
738 const MemOp &Op = getMem();
739 OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
740 if (Op.Base) {
741 OS << "(";
742 if (Op.MemKind == BDLMem)
743 OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
744 else if (Op.MemKind == BDRMem)
745 OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
746 if (Op.Index)
749 OS << ")";
750 }
751 break;
752 }
753 case KindInvalid:
754 break;
755 }
756}
757
758// Parse one register of the form %<prefix><number>.
759bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
760 Reg.StartLoc = Parser.getTok().getLoc();
761
762 // Eat the % prefix.
763 if (Parser.getTok().isNot(AsmToken::Percent))
764 return Error(Parser.getTok().getLoc(), "register expected");
765 const AsmToken &PercentTok = Parser.getTok();
766 Parser.Lex();
767
768 // Expect a register name.
769 if (Parser.getTok().isNot(AsmToken::Identifier)) {
770 if (RestoreOnFailure)
771 getLexer().UnLex(PercentTok);
772 return Error(Reg.StartLoc, "invalid register");
773 }
774
775 // Check that there's a prefix.
776 StringRef Name = Parser.getTok().getString();
777 if (Name.size() < 2) {
778 if (RestoreOnFailure)
779 getLexer().UnLex(PercentTok);
780 return Error(Reg.StartLoc, "invalid register");
781 }
782 char Prefix = Name[0];
783
784 // Treat the rest of the register name as a register number.
785 if (Name.substr(1).getAsInteger(10, Reg.Num)) {
786 if (RestoreOnFailure)
787 getLexer().UnLex(PercentTok);
788 return Error(Reg.StartLoc, "invalid register");
789 }
790
791 // Look for valid combinations of prefix and number.
792 if (Prefix == 'r' && Reg.Num < 16)
793 Reg.Group = RegGR;
794 else if (Prefix == 'f' && Reg.Num < 16)
795 Reg.Group = RegFP;
796 else if (Prefix == 'v' && Reg.Num < 32)
797 Reg.Group = RegV;
798 else if (Prefix == 'a' && Reg.Num < 16)
799 Reg.Group = RegAR;
800 else if (Prefix == 'c' && Reg.Num < 16)
801 Reg.Group = RegCR;
802 else {
803 if (RestoreOnFailure)
804 getLexer().UnLex(PercentTok);
805 return Error(Reg.StartLoc, "invalid register");
806 }
807
808 Reg.EndLoc = Parser.getTok().getLoc();
809 Parser.Lex();
810 return false;
811}
812
813// Parse a register of kind Kind and add it to Operands.
814ParseStatus SystemZAsmParser::parseRegister(OperandVector &Operands,
815 RegisterKind Kind) {
817 RegisterGroup Group;
818 switch (Kind) {
819 case GR32Reg:
820 case GRH32Reg:
821 case GR64Reg:
822 case GR128Reg:
823 Group = RegGR;
824 break;
825 case FP32Reg:
826 case FP64Reg:
827 case FP128Reg:
828 Group = RegFP;
829 break;
830 case VR32Reg:
831 case VR64Reg:
832 case VR128Reg:
833 Group = RegV;
834 break;
835 case AR32Reg:
836 Group = RegAR;
837 break;
838 case CR64Reg:
839 Group = RegCR;
840 break;
841 }
842
843 // Handle register names of the form %<prefix><number>
844 if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
845 if (parseRegister(Reg))
847
848 // Check the parsed register group "Reg.Group" with the expected "Group"
849 // Have to error out if user specified wrong prefix.
850 switch (Group) {
851 case RegGR:
852 case RegFP:
853 case RegAR:
854 case RegCR:
855 if (Group != Reg.Group)
856 return Error(Reg.StartLoc, "invalid operand for instruction");
857 break;
858 case RegV:
859 if (Reg.Group != RegV && Reg.Group != RegFP)
860 return Error(Reg.StartLoc, "invalid operand for instruction");
861 break;
862 }
863 } else if (Parser.getTok().is(AsmToken::Integer)) {
864 if (parseIntegerRegister(Reg, Group))
866 }
867 // Otherwise we didn't match a register operand.
868 else
870
871 // Determine the LLVM register number according to Kind.
872 const unsigned *Regs;
873 switch (Kind) {
874 case GR32Reg: Regs = SystemZMC::GR32Regs; break;
875 case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
876 case GR64Reg: Regs = SystemZMC::GR64Regs; break;
877 case GR128Reg: Regs = SystemZMC::GR128Regs; break;
878 case FP32Reg: Regs = SystemZMC::FP32Regs; break;
879 case FP64Reg: Regs = SystemZMC::FP64Regs; break;
880 case FP128Reg: Regs = SystemZMC::FP128Regs; break;
881 case VR32Reg: Regs = SystemZMC::VR32Regs; break;
882 case VR64Reg: Regs = SystemZMC::VR64Regs; break;
883 case VR128Reg: Regs = SystemZMC::VR128Regs; break;
884 case AR32Reg: Regs = SystemZMC::AR32Regs; break;
885 case CR64Reg: Regs = SystemZMC::CR64Regs; break;
886 }
887 if (Regs[Reg.Num] == 0)
888 return Error(Reg.StartLoc, "invalid register pair");
889
890 Operands.push_back(
891 SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
893}
894
895// Parse any type of register (including integers) and add it to Operands.
896ParseStatus SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
897 SMLoc StartLoc = Parser.getTok().getLoc();
898
899 // Handle integer values.
900 if (Parser.getTok().is(AsmToken::Integer)) {
901 const MCExpr *Register;
902 if (Parser.parseExpression(Register))
904
905 if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
906 int64_t Value = CE->getValue();
907 if (Value < 0 || Value > 15)
908 return Error(StartLoc, "invalid register");
909 }
910
911 SMLoc EndLoc =
913
914 Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
915 }
916 else {
917 if (isParsingHLASM())
919
921 if (parseRegister(Reg))
923
924 if (Reg.Num > 15)
925 return Error(StartLoc, "invalid register");
926
927 // Map to the correct register kind.
928 RegisterKind Kind;
929 unsigned RegNo;
930 if (Reg.Group == RegGR) {
931 Kind = GR64Reg;
932 RegNo = SystemZMC::GR64Regs[Reg.Num];
933 }
934 else if (Reg.Group == RegFP) {
935 Kind = FP64Reg;
936 RegNo = SystemZMC::FP64Regs[Reg.Num];
937 }
938 else if (Reg.Group == RegV) {
939 Kind = VR128Reg;
940 RegNo = SystemZMC::VR128Regs[Reg.Num];
941 }
942 else if (Reg.Group == RegAR) {
943 Kind = AR32Reg;
944 RegNo = SystemZMC::AR32Regs[Reg.Num];
945 }
946 else if (Reg.Group == RegCR) {
947 Kind = CR64Reg;
948 RegNo = SystemZMC::CR64Regs[Reg.Num];
949 }
950 else {
952 }
953
954 Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
955 Reg.StartLoc, Reg.EndLoc));
956 }
958}
959
960bool SystemZAsmParser::parseIntegerRegister(Register &Reg,
961 RegisterGroup Group) {
962 Reg.StartLoc = Parser.getTok().getLoc();
963 // We have an integer token
964 const MCExpr *Register;
965 if (Parser.parseExpression(Register))
966 return true;
967
968 const auto *CE = dyn_cast<MCConstantExpr>(Register);
969 if (!CE)
970 return true;
971
972 int64_t MaxRegNum = (Group == RegV) ? 31 : 15;
973 int64_t Value = CE->getValue();
974 if (Value < 0 || Value > MaxRegNum) {
975 Error(Parser.getTok().getLoc(), "invalid register");
976 return true;
977 }
978
979 // Assign the Register Number
980 Reg.Num = (unsigned)Value;
981 Reg.Group = Group;
982 Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
983
984 // At this point, successfully parsed an integer register.
985 return false;
986}
987
988// Parse a memory operand into Reg1, Reg2, Disp, and Length.
989bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
990 bool &HaveReg2, Register &Reg2,
991 const MCExpr *&Disp, const MCExpr *&Length,
992 bool HasLength, bool HasVectorIndex) {
993 // Parse the displacement, which must always be present.
994 if (getParser().parseExpression(Disp))
995 return true;
996
997 // Parse the optional base and index.
998 HaveReg1 = false;
999 HaveReg2 = false;
1000 Length = nullptr;
1001
1002 // If we have a scenario as below:
1003 // vgef %v0, 0(0), 0
1004 // This is an example of a "BDVMem" instruction type.
1005 //
1006 // So when we parse this as an integer register, the register group
1007 // needs to be tied to "RegV". Usually when the prefix is passed in
1008 // as %<prefix><reg-number> its easy to check which group it should belong to
1009 // However, if we're passing in just the integer there's no real way to
1010 // "check" what register group it should belong to.
1011 //
1012 // When the user passes in the register as an integer, the user assumes that
1013 // the compiler is responsible for substituting it as the right kind of
1014 // register. Whereas, when the user specifies a "prefix", the onus is on
1015 // the user to make sure they pass in the right kind of register.
1016 //
1017 // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
1018 // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
1019 // (i.e. insn is of type BDVMem) is true.
1020 RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR;
1021
1022 if (getLexer().is(AsmToken::LParen)) {
1023 Parser.Lex();
1024
1025 if (isParsingATT() && getLexer().is(AsmToken::Percent)) {
1026 // Parse the first register.
1027 HaveReg1 = true;
1028 if (parseRegister(Reg1))
1029 return true;
1030 }
1031 // So if we have an integer as the first token in ([tok1], ..), it could:
1032 // 1. Refer to a "Register" (i.e X,R,V fields in BD[X|R|V]Mem type of
1033 // instructions)
1034 // 2. Refer to a "Length" field (i.e L field in BDLMem type of instructions)
1035 else if (getLexer().is(AsmToken::Integer)) {
1036 if (HasLength) {
1037 // Instruction has a "Length" field, safe to parse the first token as
1038 // the "Length" field
1039 if (getParser().parseExpression(Length))
1040 return true;
1041 } else {
1042 // Otherwise, if the instruction has no "Length" field, parse the
1043 // token as a "Register". We don't have to worry about whether the
1044 // instruction is invalid here, because the caller will take care of
1045 // error reporting.
1046 HaveReg1 = true;
1047 if (parseIntegerRegister(Reg1, RegGroup))
1048 return true;
1049 }
1050 } else {
1051 // If its not an integer or a percent token, then if the instruction
1052 // is reported to have a "Length" then, parse it as "Length".
1053 if (HasLength) {
1054 if (getParser().parseExpression(Length))
1055 return true;
1056 }
1057 }
1058
1059 // Check whether there's a second register.
1060 if (getLexer().is(AsmToken::Comma)) {
1061 Parser.Lex();
1062 HaveReg2 = true;
1063
1064 if (getLexer().is(AsmToken::Integer)) {
1065 if (parseIntegerRegister(Reg2, RegGR))
1066 return true;
1067 } else {
1068 if (isParsingATT() && parseRegister(Reg2))
1069 return true;
1070 }
1071 }
1072
1073 // Consume the closing bracket.
1074 if (getLexer().isNot(AsmToken::RParen))
1075 return Error(Parser.getTok().getLoc(), "unexpected token in address");
1076 Parser.Lex();
1077 }
1078 return false;
1079}
1080
1081// Verify that Reg is a valid address register (base or index).
1082bool
1083SystemZAsmParser::parseAddressRegister(Register &Reg) {
1084 if (Reg.Group == RegV) {
1085 Error(Reg.StartLoc, "invalid use of vector addressing");
1086 return true;
1087 }
1088 if (Reg.Group != RegGR) {
1089 Error(Reg.StartLoc, "invalid address register");
1090 return true;
1091 }
1092 return false;
1093}
1094
1095// Parse a memory operand and add it to Operands. The other arguments
1096// are as above.
1097ParseStatus SystemZAsmParser::parseAddress(OperandVector &Operands,
1098 MemoryKind MemKind,
1099 RegisterKind RegKind) {
1100 SMLoc StartLoc = Parser.getTok().getLoc();
1101 unsigned Base = 0, Index = 0, LengthReg = 0;
1102 Register Reg1, Reg2;
1103 bool HaveReg1, HaveReg2;
1104 const MCExpr *Disp;
1105 const MCExpr *Length;
1106
1107 bool HasLength = (MemKind == BDLMem) ? true : false;
1108 bool HasVectorIndex = (MemKind == BDVMem) ? true : false;
1109 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
1110 HasVectorIndex))
1111 return ParseStatus::Failure;
1112
1113 const unsigned *Regs;
1114 switch (RegKind) {
1115 case GR32Reg: Regs = SystemZMC::GR32Regs; break;
1116 case GR64Reg: Regs = SystemZMC::GR64Regs; break;
1117 default: llvm_unreachable("invalid RegKind");
1118 }
1119
1120 switch (MemKind) {
1121 case BDMem:
1122 // If we have Reg1, it must be an address register.
1123 if (HaveReg1) {
1124 if (parseAddressRegister(Reg1))
1125 return ParseStatus::Failure;
1126 Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];
1127 }
1128 // There must be no Reg2.
1129 if (HaveReg2)
1130 return Error(StartLoc, "invalid use of indexed addressing");
1131 break;
1132 case BDXMem:
1133 // If we have Reg1, it must be an address register.
1134 if (HaveReg1) {
1135 if (parseAddressRegister(Reg1))
1136 return ParseStatus::Failure;
1137 // If the are two registers, the first one is the index and the
1138 // second is the base.
1139 if (HaveReg2)
1140 Index = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];
1141 else
1142 Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];
1143 }
1144 // If we have Reg2, it must be an address register.
1145 if (HaveReg2) {
1146 if (parseAddressRegister(Reg2))
1147 return ParseStatus::Failure;
1148 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
1149 }
1150 break;
1151 case BDLMem:
1152 // If we have Reg2, it must be an address register.
1153 if (HaveReg2) {
1154 if (parseAddressRegister(Reg2))
1155 return ParseStatus::Failure;
1156 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
1157 }
1158 // We cannot support base+index addressing.
1159 if (HaveReg1 && HaveReg2)
1160 return Error(StartLoc, "invalid use of indexed addressing");
1161 // We must have a length.
1162 if (!Length)
1163 return Error(StartLoc, "missing length in address");
1164 break;
1165 case BDRMem:
1166 // We must have Reg1, and it must be a GPR.
1167 if (!HaveReg1 || Reg1.Group != RegGR)
1168 return Error(StartLoc, "invalid operand for instruction");
1169 LengthReg = SystemZMC::GR64Regs[Reg1.Num];
1170 // If we have Reg2, it must be an address register.
1171 if (HaveReg2) {
1172 if (parseAddressRegister(Reg2))
1173 return ParseStatus::Failure;
1174 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
1175 }
1176 break;
1177 case BDVMem:
1178 // We must have Reg1, and it must be a vector register.
1179 if (!HaveReg1 || Reg1.Group != RegV)
1180 return Error(StartLoc, "vector index required in address");
1181 Index = SystemZMC::VR128Regs[Reg1.Num];
1182 // If we have Reg2, it must be an address register.
1183 if (HaveReg2) {
1184 if (parseAddressRegister(Reg2))
1185 return ParseStatus::Failure;
1186 Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
1187 }
1188 break;
1189 }
1190
1191 SMLoc EndLoc =
1193 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1194 Index, Length, LengthReg,
1195 StartLoc, EndLoc));
1196 return ParseStatus::Success;
1197}
1198
1199ParseStatus SystemZAsmParser::parseDirective(AsmToken DirectiveID) {
1200 StringRef IDVal = DirectiveID.getIdentifier();
1201
1202 if (IDVal == ".insn")
1203 return ParseDirectiveInsn(DirectiveID.getLoc());
1204 if (IDVal == ".machine")
1205 return ParseDirectiveMachine(DirectiveID.getLoc());
1206 if (IDVal.starts_with(".gnu_attribute"))
1207 return ParseGNUAttribute(DirectiveID.getLoc());
1208
1209 return ParseStatus::NoMatch;
1210}
1211
1212/// ParseDirectiveInsn
1213/// ::= .insn [ format, encoding, (operands (, operands)*) ]
1214bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1215 MCAsmParser &Parser = getParser();
1216
1217 // Expect instruction format as identifier.
1219 SMLoc ErrorLoc = Parser.getTok().getLoc();
1220 if (Parser.parseIdentifier(Format))
1221 return Error(ErrorLoc, "expected instruction format");
1222
1224
1225 // Find entry for this format in InsnMatchTable.
1226 auto EntryRange =
1227 std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1228 Format, CompareInsn());
1229
1230 // If first == second, couldn't find a match in the table.
1231 if (EntryRange.first == EntryRange.second)
1232 return Error(ErrorLoc, "unrecognized format");
1233
1234 struct InsnMatchEntry *Entry = EntryRange.first;
1235
1236 // Format should match from equal_range.
1237 assert(Entry->Format == Format);
1238
1239 // Parse the following operands using the table's information.
1240 for (int I = 0; I < Entry->NumOperands; I++) {
1241 MatchClassKind Kind = Entry->OperandKinds[I];
1242
1243 SMLoc StartLoc = Parser.getTok().getLoc();
1244
1245 // Always expect commas as separators for operands.
1246 if (getLexer().isNot(AsmToken::Comma))
1247 return Error(StartLoc, "unexpected token in directive");
1248 Lex();
1249
1250 // Parse operands.
1251 ParseStatus ResTy;
1252 if (Kind == MCK_AnyReg)
1253 ResTy = parseAnyReg(Operands);
1254 else if (Kind == MCK_VR128)
1255 ResTy = parseVR128(Operands);
1256 else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1257 ResTy = parseBDXAddr64(Operands);
1258 else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1259 ResTy = parseBDAddr64(Operands);
1260 else if (Kind == MCK_BDVAddr64Disp12)
1261 ResTy = parseBDVAddr64(Operands);
1262 else if (Kind == MCK_PCRel32)
1263 ResTy = parsePCRel32(Operands);
1264 else if (Kind == MCK_PCRel16)
1265 ResTy = parsePCRel16(Operands);
1266 else {
1267 // Only remaining operand kind is an immediate.
1268 const MCExpr *Expr;
1269 SMLoc StartLoc = Parser.getTok().getLoc();
1270
1271 // Expect immediate expression.
1272 if (Parser.parseExpression(Expr))
1273 return Error(StartLoc, "unexpected token in directive");
1274
1275 SMLoc EndLoc =
1277
1278 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1279 ResTy = ParseStatus::Success;
1280 }
1281
1282 if (!ResTy.isSuccess())
1283 return true;
1284 }
1285
1286 // Build the instruction with the parsed operands.
1287 MCInst Inst = MCInstBuilder(Entry->Opcode);
1288
1289 for (size_t I = 0; I < Operands.size(); I++) {
1290 MCParsedAsmOperand &Operand = *Operands[I];
1291 MatchClassKind Kind = Entry->OperandKinds[I];
1292
1293 // Verify operand.
1294 unsigned Res = validateOperandClass(Operand, Kind);
1295 if (Res != Match_Success)
1296 return Error(Operand.getStartLoc(), "unexpected operand type");
1297
1298 // Add operands to instruction.
1299 SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1300 if (ZOperand.isReg())
1301 ZOperand.addRegOperands(Inst, 1);
1302 else if (ZOperand.isMem(BDMem))
1303 ZOperand.addBDAddrOperands(Inst, 2);
1304 else if (ZOperand.isMem(BDXMem))
1305 ZOperand.addBDXAddrOperands(Inst, 3);
1306 else if (ZOperand.isMem(BDVMem))
1307 ZOperand.addBDVAddrOperands(Inst, 3);
1308 else if (ZOperand.isImm())
1309 ZOperand.addImmOperands(Inst, 1);
1310 else
1311 llvm_unreachable("unexpected operand type");
1312 }
1313
1314 // Emit as a regular instruction.
1315 Parser.getStreamer().emitInstruction(Inst, getSTI());
1316
1317 return false;
1318}
1319
1320/// ParseDirectiveMachine
1321/// ::= .machine [ mcpu ]
1322bool SystemZAsmParser::ParseDirectiveMachine(SMLoc L) {
1323 MCAsmParser &Parser = getParser();
1324 if (Parser.getTok().isNot(AsmToken::Identifier) &&
1325 Parser.getTok().isNot(AsmToken::String))
1326 return TokError("unexpected token in '.machine' directive");
1327
1328 StringRef CPU = Parser.getTok().getIdentifier();
1329 Parser.Lex();
1330 if (parseEOL())
1331 return true;
1332
1333 MCSubtargetInfo &STI = copySTI();
1334 STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, "");
1335 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
1336
1337 getTargetStreamer().emitMachine(CPU);
1338
1339 return false;
1340}
1341
1342bool SystemZAsmParser::ParseGNUAttribute(SMLoc L) {
1343 int64_t Tag;
1344 int64_t IntegerValue;
1345 if (!Parser.parseGNUAttribute(L, Tag, IntegerValue))
1346 return Error(L, "malformed .gnu_attribute directive");
1347
1348 // Tag_GNU_S390_ABI_Vector tag is '8' and can be 0, 1, or 2.
1349 if (Tag != 8 || (IntegerValue < 0 || IntegerValue > 2))
1350 return Error(L, "unrecognized .gnu_attribute tag/value pair.");
1351
1352 Parser.getStreamer().emitGNUAttribute(Tag, IntegerValue);
1353
1354 return parseEOL();
1355}
1356
1357bool SystemZAsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
1358 SMLoc &EndLoc, bool RestoreOnFailure) {
1359 Register Reg;
1360 if (parseRegister(Reg, RestoreOnFailure))
1361 return true;
1362 if (Reg.Group == RegGR)
1363 RegNo = SystemZMC::GR64Regs[Reg.Num];
1364 else if (Reg.Group == RegFP)
1365 RegNo = SystemZMC::FP64Regs[Reg.Num];
1366 else if (Reg.Group == RegV)
1367 RegNo = SystemZMC::VR128Regs[Reg.Num];
1368 else if (Reg.Group == RegAR)
1369 RegNo = SystemZMC::AR32Regs[Reg.Num];
1370 else if (Reg.Group == RegCR)
1371 RegNo = SystemZMC::CR64Regs[Reg.Num];
1372 StartLoc = Reg.StartLoc;
1373 EndLoc = Reg.EndLoc;
1374 return false;
1375}
1376
1377bool SystemZAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
1378 SMLoc &EndLoc) {
1379 return ParseRegister(Reg, StartLoc, EndLoc, /*RestoreOnFailure=*/false);
1380}
1381
1382ParseStatus SystemZAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
1383 SMLoc &EndLoc) {
1384 bool Result = ParseRegister(Reg, StartLoc, EndLoc, /*RestoreOnFailure=*/true);
1385 bool PendingErrors = getParser().hasPendingError();
1386 getParser().clearPendingErrors();
1387 if (PendingErrors)
1388 return ParseStatus::Failure;
1389 if (Result)
1390 return ParseStatus::NoMatch;
1391 return ParseStatus::Success;
1392}
1393
1394bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1395 StringRef Name, SMLoc NameLoc,
1397
1398 // Apply mnemonic aliases first, before doing anything else, in
1399 // case the target uses it.
1400 applyMnemonicAliases(Name, getAvailableFeatures(), getMAIAssemblerDialect());
1401
1402 Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1403
1404 // Read the remaining operands.
1405 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1406 // Read the first operand.
1407 if (parseOperand(Operands, Name)) {
1408 return true;
1409 }
1410
1411 // Read any subsequent operands.
1412 while (getLexer().is(AsmToken::Comma)) {
1413 Parser.Lex();
1414
1415 if (isParsingHLASM() && getLexer().is(AsmToken::Space))
1416 return Error(
1417 Parser.getTok().getLoc(),
1418 "No space allowed between comma that separates operand entries");
1419
1420 if (parseOperand(Operands, Name)) {
1421 return true;
1422 }
1423 }
1424
1425 // Under the HLASM variant, we could have the remark field
1426 // The remark field occurs after the operation entries
1427 // There is a space that separates the operation entries and the
1428 // remark field.
1429 if (isParsingHLASM() && getTok().is(AsmToken::Space)) {
1430 // We've confirmed that there is a Remark field.
1431 StringRef Remark(getLexer().LexUntilEndOfStatement());
1432 Parser.Lex();
1433
1434 // If there is nothing after the space, then there is nothing to emit
1435 // We could have a situation as this:
1436 // " \n"
1437 // After lexing above, we will have
1438 // "\n"
1439 // This isn't an explicit remark field, so we don't have to output
1440 // this as a comment.
1441 if (Remark.size())
1442 // Output the entire Remarks Field as a comment
1443 getStreamer().AddComment(Remark);
1444 }
1445
1446 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1447 SMLoc Loc = getLexer().getLoc();
1448 return Error(Loc, "unexpected token in argument list");
1449 }
1450 }
1451
1452 // Consume the EndOfStatement.
1453 Parser.Lex();
1454 return false;
1455}
1456
1457bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1458 StringRef Mnemonic) {
1459 // Check if the current operand has a custom associated parser, if so, try to
1460 // custom parse the operand, or fallback to the general approach. Force all
1461 // features to be available during the operand check, or else we will fail to
1462 // find the custom parser, and then we will later get an InvalidOperand error
1463 // instead of a MissingFeature errror.
1464 FeatureBitset AvailableFeatures = getAvailableFeatures();
1466 All.set();
1467 setAvailableFeatures(All);
1468 ParseStatus Res = MatchOperandParserImpl(Operands, Mnemonic);
1469 setAvailableFeatures(AvailableFeatures);
1470 if (Res.isSuccess())
1471 return false;
1472
1473 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1474 // there was a match, but an error occurred, in which case, just return that
1475 // the operand parsing failed.
1476 if (Res.isFailure())
1477 return true;
1478
1479 // Check for a register. All real register operands should have used
1480 // a context-dependent parse routine, which gives the required register
1481 // class. The code is here to mop up other cases, like those where
1482 // the instruction isn't recognized.
1483 if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
1484 Register Reg;
1485 if (parseRegister(Reg))
1486 return true;
1487 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1488 return false;
1489 }
1490
1491 // The only other type of operand is an immediate or address. As above,
1492 // real address operands should have used a context-dependent parse routine,
1493 // so we treat any plain expression as an immediate.
1494 SMLoc StartLoc = Parser.getTok().getLoc();
1495 Register Reg1, Reg2;
1496 bool HaveReg1, HaveReg2;
1497 const MCExpr *Expr;
1498 const MCExpr *Length;
1499 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
1500 /*HasLength*/ true, /*HasVectorIndex*/ true))
1501 return true;
1502 // If the register combination is not valid for any instruction, reject it.
1503 // Otherwise, fall back to reporting an unrecognized instruction.
1504 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1505 && parseAddressRegister(Reg1))
1506 return true;
1507 if (HaveReg2 && parseAddressRegister(Reg2))
1508 return true;
1509
1510 SMLoc EndLoc =
1512 if (HaveReg1 || HaveReg2 || Length)
1513 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1514 else
1515 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1516 return false;
1517}
1518
1519bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1521 MCStreamer &Out,
1523 bool MatchingInlineAsm) {
1524 MCInst Inst;
1525 unsigned MatchResult;
1526
1527 unsigned Dialect = getMAIAssemblerDialect();
1528
1529 FeatureBitset MissingFeatures;
1530 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
1531 MatchingInlineAsm, Dialect);
1532 switch (MatchResult) {
1533 case Match_Success:
1534 Inst.setLoc(IDLoc);
1535 Out.emitInstruction(Inst, getSTI());
1536 return false;
1537
1538 case Match_MissingFeature: {
1539 assert(MissingFeatures.any() && "Unknown missing feature!");
1540 // Special case the error message for the very common case where only
1541 // a single subtarget feature is missing
1542 std::string Msg = "instruction requires:";
1543 for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) {
1544 if (MissingFeatures[I]) {
1545 Msg += " ";
1546 Msg += getSubtargetFeatureName(I);
1547 }
1548 }
1549 return Error(IDLoc, Msg);
1550 }
1551
1552 case Match_InvalidOperand: {
1553 SMLoc ErrorLoc = IDLoc;
1554 if (ErrorInfo != ~0ULL) {
1555 if (ErrorInfo >= Operands.size())
1556 return Error(IDLoc, "too few operands for instruction");
1557
1558 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1559 if (ErrorLoc == SMLoc())
1560 ErrorLoc = IDLoc;
1561 }
1562 return Error(ErrorLoc, "invalid operand for instruction");
1563 }
1564
1565 case Match_MnemonicFail: {
1566 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1567 std::string Suggestion = SystemZMnemonicSpellCheck(
1568 ((SystemZOperand &)*Operands[0]).getToken(), FBS, Dialect);
1569 return Error(IDLoc, "invalid instruction" + Suggestion,
1570 ((SystemZOperand &)*Operands[0]).getLocRange());
1571 }
1572 }
1573
1574 llvm_unreachable("Unexpected match type");
1575}
1576
1577ParseStatus SystemZAsmParser::parsePCRel(OperandVector &Operands,
1578 int64_t MinVal, int64_t MaxVal,
1579 bool AllowTLS) {
1580 MCContext &Ctx = getContext();
1581 MCStreamer &Out = getStreamer();
1582 const MCExpr *Expr;
1583 SMLoc StartLoc = Parser.getTok().getLoc();
1584 if (getParser().parseExpression(Expr))
1585 return ParseStatus::NoMatch;
1586
1587 auto IsOutOfRangeConstant = [&](const MCExpr *E, bool Negate) -> bool {
1588 if (auto *CE = dyn_cast<MCConstantExpr>(E)) {
1589 int64_t Value = CE->getValue();
1590 if (Negate)
1591 Value = -Value;
1592 if ((Value & 1) || Value < MinVal || Value > MaxVal)
1593 return true;
1594 }
1595 return false;
1596 };
1597
1598 // For consistency with the GNU assembler, treat immediates as offsets
1599 // from ".".
1600 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1601 if (isParsingHLASM())
1602 return Error(StartLoc, "Expected PC-relative expression");
1603 if (IsOutOfRangeConstant(CE, false))
1604 return Error(StartLoc, "offset out of range");
1605 int64_t Value = CE->getValue();
1606 MCSymbol *Sym = Ctx.createTempSymbol();
1607 Out.emitLabel(Sym);
1609 Ctx);
1610 Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1611 }
1612
1613 // For consistency with the GNU assembler, conservatively assume that a
1614 // constant offset must by itself be within the given size range.
1615 if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr))
1616 if (IsOutOfRangeConstant(BE->getLHS(), false) ||
1617 IsOutOfRangeConstant(BE->getRHS(),
1618 BE->getOpcode() == MCBinaryExpr::Sub))
1619 return Error(StartLoc, "offset out of range");
1620
1621 // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1622 const MCExpr *Sym = nullptr;
1623 if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1624 Parser.Lex();
1625
1626 if (Parser.getTok().isNot(AsmToken::Identifier))
1627 return Error(Parser.getTok().getLoc(), "unexpected token");
1628
1630 StringRef Name = Parser.getTok().getString();
1631 if (Name == "tls_gdcall")
1633 else if (Name == "tls_ldcall")
1635 else
1636 return Error(Parser.getTok().getLoc(), "unknown TLS tag");
1637 Parser.Lex();
1638
1639 if (Parser.getTok().isNot(AsmToken::Colon))
1640 return Error(Parser.getTok().getLoc(), "unexpected token");
1641 Parser.Lex();
1642
1643 if (Parser.getTok().isNot(AsmToken::Identifier))
1644 return Error(Parser.getTok().getLoc(), "unexpected token");
1645
1646 StringRef Identifier = Parser.getTok().getString();
1648 Kind, Ctx);
1649 Parser.Lex();
1650 }
1651
1652 SMLoc EndLoc =
1654
1655 if (AllowTLS)
1656 Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1657 StartLoc, EndLoc));
1658 else
1659 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1660
1661 return ParseStatus::Success;
1662}
1663
1664bool SystemZAsmParser::isLabel(AsmToken &Token) {
1665 if (isParsingATT())
1666 return true;
1667
1668 // HLASM labels are ordinary symbols.
1669 // An HLASM label always starts at column 1.
1670 // An ordinary symbol syntax is laid out as follows:
1671 // Rules:
1672 // 1. Has to start with an "alphabetic character". Can be followed by up to
1673 // 62 alphanumeric characters. An "alphabetic character", in this scenario,
1674 // is a letter from 'A' through 'Z', or from 'a' through 'z',
1675 // or '$', '_', '#', or '@'
1676 // 2. Labels are case-insensitive. E.g. "lab123", "LAB123", "lAb123", etc.
1677 // are all treated as the same symbol. However, the processing for the case
1678 // folding will not be done in this function.
1679 StringRef RawLabel = Token.getString();
1680 SMLoc Loc = Token.getLoc();
1681
1682 // An HLASM label cannot be empty.
1683 if (!RawLabel.size())
1684 return !Error(Loc, "HLASM Label cannot be empty");
1685
1686 // An HLASM label cannot exceed greater than 63 characters.
1687 if (RawLabel.size() > 63)
1688 return !Error(Loc, "Maximum length for HLASM Label is 63 characters");
1689
1690 // A label must start with an "alphabetic character".
1691 if (!isHLASMAlpha(RawLabel[0]))
1692 return !Error(Loc, "HLASM Label has to start with an alphabetic "
1693 "character or the underscore character");
1694
1695 // Now, we've established that the length is valid
1696 // and the first character is alphabetic.
1697 // Check whether remaining string is alphanumeric.
1698 for (unsigned I = 1; I < RawLabel.size(); ++I)
1699 if (!isHLASMAlnum(RawLabel[I]))
1700 return !Error(Loc, "HLASM Label has to be alphanumeric");
1701
1702 return true;
1703}
1704
1705// Force static initialization.
1706// NOLINTNEXTLINE(readability-identifier-naming)
1709}
static const char * getSubtargetFeatureName(uint64_t Val)
static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID)
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
std::string Name
Symbol * Sym
Definition: ELF_riscv.cpp:479
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static LVOptions Options
Definition: LVOptions.cpp:25
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isDigit(const char C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
raw_pwrite_stream & OS
This file defines the SmallVector class.
This file contains some functions that are useful when dealing with strings.
static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue, bool AllowSymbol=false)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmParser()
static struct InsnMatchEntry InsnMatchTable[]
static void printMCExpr(const MCExpr *E, raw_ostream &OS)
Value * RHS
Value * LHS
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:26
bool isNot(TokenKind K) const
Definition: MCAsmMacro.h:83
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmMacro.h:110
bool is(TokenKind K) const
Definition: MCAsmMacro.h:82
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string.
Definition: MCAsmMacro.h:99
This class represents an Operation in the Expression.
Base class for user error types.
Definition: Error.h:355
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
Container class for subtarget features.
constexpr size_t size() const
unsigned getAssemblerDialect() const
Definition: MCAsmInfo.h:682
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:123
virtual MCStreamer & getStreamer()=0
Return the output streamer for the assembler.
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:40
virtual bool parseIdentifier(StringRef &Res)=0
Parse an identifier or string (as a quoted identifier) and set Res to the identifier contents.
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
virtual void addAliasForDirective(StringRef Directive, StringRef Alias)=0
bool parseGNUAttribute(SMLoc L, int64_t &Tag, int64_t &IntegerValue)
Parse a .gnu_attribute.
virtual MCContext & getContext()=0
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:536
@ Sub
Subtraction.
Definition: MCExpr.h:517
Context object for machine code objects.
Definition: MCContext.h:82
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:331
const MCAsmInfo * getAsmInfo() const
Definition: MCContext.h:415
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:211
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void setLoc(SMLoc loc)
Definition: MCInst.h:203
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
virtual SMLoc getStartLoc() const =0
getStartLoc - Get the location of the first token of this operand.
virtual bool isReg() const =0
isReg - Is this a register operand?
virtual bool isMem() const =0
isMem - Is this a memory operand?
virtual MCRegister getReg() const =0
virtual void print(raw_ostream &OS) const =0
print - Print a debug representation of the operand to the given stream.
virtual bool isToken() const =0
isToken - Is this a token operand?
virtual bool isImm() const =0
isImm - Is this an immediate operand?
virtual SMLoc getEndLoc() const =0
getEndLoc - Get the location of the last token of this operand.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Streaming machine code generation interface.
Definition: MCStreamer.h:212
virtual void emitGNUAttribute(unsigned Tag, unsigned Value)
Emit a .gnu_attribute directive.
Definition: MCStreamer.h:676
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:424
MCTargetStreamer * getTargetStreamer()
Definition: MCStreamer.h:306
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
void setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:397
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
MCTargetAsmParser - Generic interface to target specific assembly parsers.
virtual ParseStatus parseDirective(AsmToken DirectiveID)
Parses a target-specific assembler directive.
virtual bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
virtual ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
tryParseRegister - parse one register if possible
virtual bool isLabel(AsmToken &Token)
void setAvailableFeatures(const FeatureBitset &Value)
const MCSubtargetInfo & getSTI() const
virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands)=0
ParseInstruction - Parse one assembly instruction.
virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm)=0
MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst ...
Target specific streamer interface.
Definition: MCStreamer.h:93
Ternary parse status returned by various parse* methods.
constexpr bool isFailure() const
static constexpr StatusTy Failure
constexpr bool isSuccess() const
static constexpr StatusTy Success
static constexpr StatusTy NoMatch
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents a location in source code.
Definition: SMLoc.h:23
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
constexpr const char * getPointer() const
Definition: SMLoc.h:34
Represents a range in source code.
Definition: SMLoc.h:48
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:258
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
static const char * getRegisterName(MCRegister Reg)
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Entry
Definition: COFF.h:811
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
const unsigned GR64Regs[16]
const unsigned VR128Regs[32]
const unsigned GR128Regs[16]
const unsigned GRH32Regs[16]
const unsigned FP32Regs[16]
const unsigned GR32Regs[16]
const unsigned FP64Regs[16]
const unsigned VR64Regs[32]
const unsigned FP128Regs[16]
const unsigned AR32Regs[16]
const unsigned VR32Regs[32]
const unsigned CR64Regs[16]
@ CE
Windows NT (Windows on ARM)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheSystemZTarget()
@ Length
Definition: DWP.cpp:456
DWARFExpression::Operation Op
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1879
#define N
bool operator()(const InsnMatchEntry &LHS, StringRef RHS)
MatchClassKind OperandKinds[7]
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...