LLVM  10.0.0svn
SystemZAsmParser.cpp
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1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/ADT/StringRef.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstBuilder.h"
24 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/Support/Casting.h"
28 #include "llvm/Support/SMLoc.h"
30 #include <algorithm>
31 #include <cassert>
32 #include <cstddef>
33 #include <cstdint>
34 #include <iterator>
35 #include <memory>
36 #include <string>
37 
38 using namespace llvm;
39 
40 // Return true if Expr is in the range [MinValue, MaxValue].
41 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
42  if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
43  int64_t Value = CE->getValue();
44  return Value >= MinValue && Value <= MaxValue;
45  }
46  return false;
47 }
48 
49 namespace {
50 
52  GR32Reg,
53  GRH32Reg,
54  GR64Reg,
55  GR128Reg,
56  ADDR32Reg,
57  ADDR64Reg,
58  FP32Reg,
59  FP64Reg,
60  FP128Reg,
61  VR32Reg,
62  VR64Reg,
63  VR128Reg,
64  AR32Reg,
65  CR64Reg,
66 };
67 
68 enum MemoryKind {
69  BDMem,
70  BDXMem,
71  BDLMem,
72  BDRMem,
73  BDVMem
74 };
75 
76 class SystemZOperand : public MCParsedAsmOperand {
77 private:
78  enum OperandKind {
79  KindInvalid,
80  KindToken,
81  KindReg,
82  KindImm,
83  KindImmTLS,
84  KindMem
85  };
86 
87  OperandKind Kind;
88  SMLoc StartLoc, EndLoc;
89 
90  // A string of length Length, starting at Data.
91  struct TokenOp {
92  const char *Data;
93  unsigned Length;
94  };
95 
96  // LLVM register Num, which has kind Kind. In some ways it might be
97  // easier for this class to have a register bank (general, floating-point
98  // or access) and a raw register number (0-15). This would postpone the
99  // interpretation of the operand to the add*() methods and avoid the need
100  // for context-dependent parsing. However, we do things the current way
101  // because of the virtual getReg() method, which needs to distinguish
102  // between (say) %r0 used as a single register and %r0 used as a pair.
103  // Context-dependent parsing can also give us slightly better error
104  // messages when invalid pairs like %r1 are used.
105  struct RegOp {
107  unsigned Num;
108  };
109 
110  // Base + Disp + Index, where Base and Index are LLVM registers or 0.
111  // MemKind says what type of memory this is and RegKind says what type
112  // the base register has (ADDR32Reg or ADDR64Reg). Length is the operand
113  // length for D(L,B)-style operands, otherwise it is null.
114  struct MemOp {
115  unsigned Base : 12;
116  unsigned Index : 12;
117  unsigned MemKind : 4;
118  unsigned RegKind : 4;
119  const MCExpr *Disp;
120  union {
121  const MCExpr *Imm;
122  unsigned Reg;
123  } Length;
124  };
125 
126  // Imm is an immediate operand, and Sym is an optional TLS symbol
127  // for use with a __tls_get_offset marker relocation.
128  struct ImmTLSOp {
129  const MCExpr *Imm;
130  const MCExpr *Sym;
131  };
132 
133  union {
134  TokenOp Token;
135  RegOp Reg;
136  const MCExpr *Imm;
137  ImmTLSOp ImmTLS;
138  MemOp Mem;
139  };
140 
141  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
142  // Add as immediates when possible. Null MCExpr = 0.
143  if (!Expr)
145  else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
146  Inst.addOperand(MCOperand::createImm(CE->getValue()));
147  else
148  Inst.addOperand(MCOperand::createExpr(Expr));
149  }
150 
151 public:
152  SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
153  : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
154 
155  // Create particular kinds of operand.
156  static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
157  SMLoc EndLoc) {
158  return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
159  }
160 
161  static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
162  auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc);
163  Op->Token.Data = Str.data();
164  Op->Token.Length = Str.size();
165  return Op;
166  }
167 
168  static std::unique_ptr<SystemZOperand>
169  createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
170  auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
171  Op->Reg.Kind = Kind;
172  Op->Reg.Num = Num;
173  return Op;
174  }
175 
176  static std::unique_ptr<SystemZOperand>
177  createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
178  auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
179  Op->Imm = Expr;
180  return Op;
181  }
182 
183  static std::unique_ptr<SystemZOperand>
184  createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
185  const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm,
186  unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) {
187  auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
188  Op->Mem.MemKind = MemKind;
189  Op->Mem.RegKind = RegKind;
190  Op->Mem.Base = Base;
191  Op->Mem.Index = Index;
192  Op->Mem.Disp = Disp;
193  if (MemKind == BDLMem)
194  Op->Mem.Length.Imm = LengthImm;
195  if (MemKind == BDRMem)
196  Op->Mem.Length.Reg = LengthReg;
197  return Op;
198  }
199 
200  static std::unique_ptr<SystemZOperand>
201  createImmTLS(const MCExpr *Imm, const MCExpr *Sym,
202  SMLoc StartLoc, SMLoc EndLoc) {
203  auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
204  Op->ImmTLS.Imm = Imm;
205  Op->ImmTLS.Sym = Sym;
206  return Op;
207  }
208 
209  // Token operands
210  bool isToken() const override {
211  return Kind == KindToken;
212  }
213  StringRef getToken() const {
214  assert(Kind == KindToken && "Not a token");
215  return StringRef(Token.Data, Token.Length);
216  }
217 
218  // Register operands.
219  bool isReg() const override {
220  return Kind == KindReg;
221  }
222  bool isReg(RegisterKind RegKind) const {
223  return Kind == KindReg && Reg.Kind == RegKind;
224  }
225  unsigned getReg() const override {
226  assert(Kind == KindReg && "Not a register");
227  return Reg.Num;
228  }
229 
230  // Immediate operands.
231  bool isImm() const override {
232  return Kind == KindImm;
233  }
234  bool isImm(int64_t MinValue, int64_t MaxValue) const {
235  return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
236  }
237  const MCExpr *getImm() const {
238  assert(Kind == KindImm && "Not an immediate");
239  return Imm;
240  }
241 
242  // Immediate operands with optional TLS symbol.
243  bool isImmTLS() const {
244  return Kind == KindImmTLS;
245  }
246 
247  const ImmTLSOp getImmTLS() const {
248  assert(Kind == KindImmTLS && "Not a TLS immediate");
249  return ImmTLS;
250  }
251 
252  // Memory operands.
253  bool isMem() const override {
254  return Kind == KindMem;
255  }
256  bool isMem(MemoryKind MemKind) const {
257  return (Kind == KindMem &&
258  (Mem.MemKind == MemKind ||
259  // A BDMem can be treated as a BDXMem in which the index
260  // register field is 0.
261  (Mem.MemKind == BDMem && MemKind == BDXMem)));
262  }
263  bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
264  return isMem(MemKind) && Mem.RegKind == RegKind;
265  }
266  bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
267  return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
268  }
269  bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
270  return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
271  }
272  bool isMemDisp12Len4(RegisterKind RegKind) const {
273  return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
274  }
275  bool isMemDisp12Len8(RegisterKind RegKind) const {
276  return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
277  }
278 
279  const MemOp& getMem() const {
280  assert(Kind == KindMem && "Not a Mem operand");
281  return Mem;
282  }
283 
284  // Override MCParsedAsmOperand.
285  SMLoc getStartLoc() const override { return StartLoc; }
286  SMLoc getEndLoc() const override { return EndLoc; }
287  void print(raw_ostream &OS) const override;
288 
289  /// getLocRange - Get the range between the first and last token of this
290  /// operand.
291  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
292 
293  // Used by the TableGen code to add particular types of operand
294  // to an instruction.
295  void addRegOperands(MCInst &Inst, unsigned N) const {
296  assert(N == 1 && "Invalid number of operands");
298  }
299  void addImmOperands(MCInst &Inst, unsigned N) const {
300  assert(N == 1 && "Invalid number of operands");
301  addExpr(Inst, getImm());
302  }
303  void addBDAddrOperands(MCInst &Inst, unsigned N) const {
304  assert(N == 2 && "Invalid number of operands");
305  assert(isMem(BDMem) && "Invalid operand type");
306  Inst.addOperand(MCOperand::createReg(Mem.Base));
307  addExpr(Inst, Mem.Disp);
308  }
309  void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
310  assert(N == 3 && "Invalid number of operands");
311  assert(isMem(BDXMem) && "Invalid operand type");
312  Inst.addOperand(MCOperand::createReg(Mem.Base));
313  addExpr(Inst, Mem.Disp);
314  Inst.addOperand(MCOperand::createReg(Mem.Index));
315  }
316  void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
317  assert(N == 3 && "Invalid number of operands");
318  assert(isMem(BDLMem) && "Invalid operand type");
319  Inst.addOperand(MCOperand::createReg(Mem.Base));
320  addExpr(Inst, Mem.Disp);
321  addExpr(Inst, Mem.Length.Imm);
322  }
323  void addBDRAddrOperands(MCInst &Inst, unsigned N) const {
324  assert(N == 3 && "Invalid number of operands");
325  assert(isMem(BDRMem) && "Invalid operand type");
326  Inst.addOperand(MCOperand::createReg(Mem.Base));
327  addExpr(Inst, Mem.Disp);
328  Inst.addOperand(MCOperand::createReg(Mem.Length.Reg));
329  }
330  void addBDVAddrOperands(MCInst &Inst, unsigned N) const {
331  assert(N == 3 && "Invalid number of operands");
332  assert(isMem(BDVMem) && "Invalid operand type");
333  Inst.addOperand(MCOperand::createReg(Mem.Base));
334  addExpr(Inst, Mem.Disp);
335  Inst.addOperand(MCOperand::createReg(Mem.Index));
336  }
337  void addImmTLSOperands(MCInst &Inst, unsigned N) const {
338  assert(N == 2 && "Invalid number of operands");
339  assert(Kind == KindImmTLS && "Invalid operand type");
340  addExpr(Inst, ImmTLS.Imm);
341  if (ImmTLS.Sym)
342  addExpr(Inst, ImmTLS.Sym);
343  }
344 
345  // Used by the TableGen code to check for particular operand types.
346  bool isGR32() const { return isReg(GR32Reg); }
347  bool isGRH32() const { return isReg(GRH32Reg); }
348  bool isGRX32() const { return false; }
349  bool isGR64() const { return isReg(GR64Reg); }
350  bool isGR128() const { return isReg(GR128Reg); }
351  bool isADDR32() const { return isReg(ADDR32Reg); }
352  bool isADDR64() const { return isReg(ADDR64Reg); }
353  bool isADDR128() const { return false; }
354  bool isFP32() const { return isReg(FP32Reg); }
355  bool isFP64() const { return isReg(FP64Reg); }
356  bool isFP128() const { return isReg(FP128Reg); }
357  bool isVR32() const { return isReg(VR32Reg); }
358  bool isVR64() const { return isReg(VR64Reg); }
359  bool isVF128() const { return false; }
360  bool isVR128() const { return isReg(VR128Reg); }
361  bool isAR32() const { return isReg(AR32Reg); }
362  bool isCR64() const { return isReg(CR64Reg); }
363  bool isAnyReg() const { return (isReg() || isImm(0, 15)); }
364  bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); }
365  bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); }
366  bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); }
367  bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); }
368  bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); }
369  bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); }
370  bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(ADDR64Reg); }
371  bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
372  bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, ADDR64Reg); }
373  bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); }
374  bool isU1Imm() const { return isImm(0, 1); }
375  bool isU2Imm() const { return isImm(0, 3); }
376  bool isU3Imm() const { return isImm(0, 7); }
377  bool isU4Imm() const { return isImm(0, 15); }
378  bool isU6Imm() const { return isImm(0, 63); }
379  bool isU8Imm() const { return isImm(0, 255); }
380  bool isS8Imm() const { return isImm(-128, 127); }
381  bool isU12Imm() const { return isImm(0, 4095); }
382  bool isU16Imm() const { return isImm(0, 65535); }
383  bool isS16Imm() const { return isImm(-32768, 32767); }
384  bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
385  bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
386  bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); }
387 };
388 
389 class SystemZAsmParser : public MCTargetAsmParser {
390 #define GET_ASSEMBLER_HEADER
391 #include "SystemZGenAsmMatcher.inc"
392 
393 private:
394  MCAsmParser &Parser;
395  enum RegisterGroup {
396  RegGR,
397  RegFP,
398  RegV,
399  RegAR,
400  RegCR
401  };
402  struct Register {
403  RegisterGroup Group;
404  unsigned Num;
405  SMLoc StartLoc, EndLoc;
406  };
407 
408  bool parseRegister(Register &Reg);
409 
410  bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
411  bool IsAddress = false);
412 
413  OperandMatchResultTy parseRegister(OperandVector &Operands,
414  RegisterGroup Group, const unsigned *Regs,
416 
417  OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
418 
419  bool parseAddress(bool &HaveReg1, Register &Reg1,
420  bool &HaveReg2, Register &Reg2,
421  const MCExpr *&Disp, const MCExpr *&Length);
422  bool parseAddressRegister(Register &Reg);
423 
424  bool ParseDirectiveInsn(SMLoc L);
425 
426  OperandMatchResultTy parseAddress(OperandVector &Operands,
427  MemoryKind MemKind, const unsigned *Regs,
429 
430  OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
431  int64_t MaxVal, bool AllowTLS);
432 
433  bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
434 
435 public:
436  SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
437  const MCInstrInfo &MII,
438  const MCTargetOptions &Options)
439  : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
441 
442  // Alias the .word directive to .short.
443  parser.addAliasForDirective(".word", ".short");
444 
445  // Initialize the set of available features.
446  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
447  }
448 
449  // Override MCTargetAsmParser.
450  bool ParseDirective(AsmToken DirectiveID) override;
451  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
452  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
453  SMLoc NameLoc, OperandVector &Operands) override;
454  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
455  OperandVector &Operands, MCStreamer &Out,
456  uint64_t &ErrorInfo,
457  bool MatchingInlineAsm) override;
458 
459  // Used by the TableGen code to parse particular operand types.
460  OperandMatchResultTy parseGR32(OperandVector &Operands) {
461  return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
462  }
463  OperandMatchResultTy parseGRH32(OperandVector &Operands) {
464  return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
465  }
466  OperandMatchResultTy parseGRX32(OperandVector &Operands) {
467  llvm_unreachable("GRX32 should only be used for pseudo instructions");
468  }
469  OperandMatchResultTy parseGR64(OperandVector &Operands) {
470  return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
471  }
472  OperandMatchResultTy parseGR128(OperandVector &Operands) {
473  return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
474  }
475  OperandMatchResultTy parseADDR32(OperandVector &Operands) {
476  return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
477  }
478  OperandMatchResultTy parseADDR64(OperandVector &Operands) {
479  return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
480  }
481  OperandMatchResultTy parseADDR128(OperandVector &Operands) {
482  llvm_unreachable("Shouldn't be used as an operand");
483  }
484  OperandMatchResultTy parseFP32(OperandVector &Operands) {
485  return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
486  }
487  OperandMatchResultTy parseFP64(OperandVector &Operands) {
488  return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
489  }
490  OperandMatchResultTy parseFP128(OperandVector &Operands) {
491  return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
492  }
493  OperandMatchResultTy parseVR32(OperandVector &Operands) {
494  return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
495  }
496  OperandMatchResultTy parseVR64(OperandVector &Operands) {
497  return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
498  }
499  OperandMatchResultTy parseVF128(OperandVector &Operands) {
500  llvm_unreachable("Shouldn't be used as an operand");
501  }
502  OperandMatchResultTy parseVR128(OperandVector &Operands) {
503  return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
504  }
505  OperandMatchResultTy parseAR32(OperandVector &Operands) {
506  return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg);
507  }
508  OperandMatchResultTy parseCR64(OperandVector &Operands) {
509  return parseRegister(Operands, RegCR, SystemZMC::CR64Regs, CR64Reg);
510  }
511  OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
512  return parseAnyRegister(Operands);
513  }
514  OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
515  return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
516  }
517  OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
518  return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
519  }
520  OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
521  return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
522  }
523  OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
524  return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
525  }
526  OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
527  return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, ADDR64Reg);
528  }
529  OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
530  return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
531  }
532  OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
533  return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
534  }
535  OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
536  return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
537  }
538  OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
539  return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
540  }
541  OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
542  return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
543  }
544  OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
545  return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
546  }
547  OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
548  return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
549  }
550 };
551 
552 } // end anonymous namespace
553 
554 #define GET_REGISTER_MATCHER
555 #define GET_SUBTARGET_FEATURE_NAME
556 #define GET_MATCHER_IMPLEMENTATION
557 #define GET_MNEMONIC_SPELL_CHECKER
558 #include "SystemZGenAsmMatcher.inc"
559 
560 // Used for the .insn directives; contains information needed to parse the
561 // operands in the directive.
564  uint64_t Opcode;
565  int32_t NumOperands;
566  MatchClassKind OperandKinds[5];
567 };
568 
569 // For equal_range comparison.
570 struct CompareInsn {
571  bool operator() (const InsnMatchEntry &LHS, StringRef RHS) {
572  return LHS.Format < RHS;
573  }
574  bool operator() (StringRef LHS, const InsnMatchEntry &RHS) {
575  return LHS < RHS.Format;
576  }
577  bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) {
578  return LHS.Format < RHS.Format;
579  }
580 };
581 
582 // Table initializing information for parsing the .insn directive.
583 static struct InsnMatchEntry InsnMatchTable[] = {
584  /* Format, Opcode, NumOperands, OperandKinds */
585  { "e", SystemZ::InsnE, 1,
586  { MCK_U16Imm } },
587  { "ri", SystemZ::InsnRI, 3,
588  { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
589  { "rie", SystemZ::InsnRIE, 4,
590  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
591  { "ril", SystemZ::InsnRIL, 3,
592  { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
593  { "rilu", SystemZ::InsnRILU, 3,
594  { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
595  { "ris", SystemZ::InsnRIS, 5,
596  { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
597  { "rr", SystemZ::InsnRR, 3,
598  { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
599  { "rre", SystemZ::InsnRRE, 3,
600  { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
601  { "rrf", SystemZ::InsnRRF, 5,
602  { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
603  { "rrs", SystemZ::InsnRRS, 5,
604  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
605  { "rs", SystemZ::InsnRS, 4,
606  { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
607  { "rse", SystemZ::InsnRSE, 4,
608  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
609  { "rsi", SystemZ::InsnRSI, 4,
610  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
611  { "rsy", SystemZ::InsnRSY, 4,
612  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
613  { "rx", SystemZ::InsnRX, 3,
614  { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
615  { "rxe", SystemZ::InsnRXE, 3,
616  { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
617  { "rxf", SystemZ::InsnRXF, 4,
618  { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
619  { "rxy", SystemZ::InsnRXY, 3,
620  { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
621  { "s", SystemZ::InsnS, 2,
622  { MCK_U32Imm, MCK_BDAddr64Disp12 } },
623  { "si", SystemZ::InsnSI, 3,
624  { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
625  { "sil", SystemZ::InsnSIL, 3,
626  { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
627  { "siy", SystemZ::InsnSIY, 3,
628  { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
629  { "ss", SystemZ::InsnSS, 4,
630  { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
631  { "sse", SystemZ::InsnSSE, 3,
632  { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
633  { "ssf", SystemZ::InsnSSF, 4,
634  { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
635 };
636 
637 static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
638  if (!E)
639  return;
640  if (auto *CE = dyn_cast<MCConstantExpr>(E))
641  OS << *CE;
642  else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
643  OS << *UE;
644  else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
645  OS << *BE;
646  else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
647  OS << *SRE;
648  else
649  OS << *E;
650 }
651 
652 void SystemZOperand::print(raw_ostream &OS) const {
653  switch (Kind) {
654  case KindToken:
655  OS << "Token:" << getToken();
656  break;
657  case KindReg:
658  OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
659  break;
660  case KindImm:
661  OS << "Imm:";
662  printMCExpr(getImm(), OS);
663  break;
664  case KindImmTLS:
665  OS << "ImmTLS:";
666  printMCExpr(getImmTLS().Imm, OS);
667  if (getImmTLS().Sym) {
668  OS << ", ";
669  printMCExpr(getImmTLS().Sym, OS);
670  }
671  break;
672  case KindMem: {
673  const MemOp &Op = getMem();
674  OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
675  if (Op.Base) {
676  OS << "(";
677  if (Op.MemKind == BDLMem)
678  OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
679  else if (Op.MemKind == BDRMem)
680  OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
681  if (Op.Index)
682  OS << SystemZInstPrinter::getRegisterName(Op.Index) << ",";
684  OS << ")";
685  }
686  break;
687  }
688  case KindInvalid:
689  break;
690  }
691 }
692 
693 // Parse one register of the form %<prefix><number>.
694 bool SystemZAsmParser::parseRegister(Register &Reg) {
695  Reg.StartLoc = Parser.getTok().getLoc();
696 
697  // Eat the % prefix.
698  if (Parser.getTok().isNot(AsmToken::Percent))
699  return Error(Parser.getTok().getLoc(), "register expected");
700  Parser.Lex();
701 
702  // Expect a register name.
703  if (Parser.getTok().isNot(AsmToken::Identifier))
704  return Error(Reg.StartLoc, "invalid register");
705 
706  // Check that there's a prefix.
707  StringRef Name = Parser.getTok().getString();
708  if (Name.size() < 2)
709  return Error(Reg.StartLoc, "invalid register");
710  char Prefix = Name[0];
711 
712  // Treat the rest of the register name as a register number.
713  if (Name.substr(1).getAsInteger(10, Reg.Num))
714  return Error(Reg.StartLoc, "invalid register");
715 
716  // Look for valid combinations of prefix and number.
717  if (Prefix == 'r' && Reg.Num < 16)
718  Reg.Group = RegGR;
719  else if (Prefix == 'f' && Reg.Num < 16)
720  Reg.Group = RegFP;
721  else if (Prefix == 'v' && Reg.Num < 32)
722  Reg.Group = RegV;
723  else if (Prefix == 'a' && Reg.Num < 16)
724  Reg.Group = RegAR;
725  else if (Prefix == 'c' && Reg.Num < 16)
726  Reg.Group = RegCR;
727  else
728  return Error(Reg.StartLoc, "invalid register");
729 
730  Reg.EndLoc = Parser.getTok().getLoc();
731  Parser.Lex();
732  return false;
733 }
734 
735 // Parse a register of group Group. If Regs is nonnull, use it to map
736 // the raw register number to LLVM numbering, with zero entries
737 // indicating an invalid register. IsAddress says whether the
738 // register appears in an address context. Allow FP Group if expecting
739 // RegV Group, since the f-prefix yields the FP group even while used
740 // with vector instructions.
741 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
742  const unsigned *Regs, bool IsAddress) {
743  if (parseRegister(Reg))
744  return true;
745  if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
746  return Error(Reg.StartLoc, "invalid operand for instruction");
747  if (Regs && Regs[Reg.Num] == 0)
748  return Error(Reg.StartLoc, "invalid register pair");
749  if (Reg.Num == 0 && IsAddress)
750  return Error(Reg.StartLoc, "%r0 used in an address");
751  if (Regs)
752  Reg.Num = Regs[Reg.Num];
753  return false;
754 }
755 
756 // Parse a register and add it to Operands. The other arguments are as above.
758 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
759  const unsigned *Regs, RegisterKind Kind) {
760  if (Parser.getTok().isNot(AsmToken::Percent))
761  return MatchOperand_NoMatch;
762 
763  Register Reg;
764  bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
765  if (parseRegister(Reg, Group, Regs, IsAddress))
766  return MatchOperand_ParseFail;
767 
768  Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
769  Reg.StartLoc, Reg.EndLoc));
770  return MatchOperand_Success;
771 }
772 
773 // Parse any type of register (including integers) and add it to Operands.
775 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
776  // Handle integer values.
777  if (Parser.getTok().is(AsmToken::Integer)) {
778  const MCExpr *Register;
779  SMLoc StartLoc = Parser.getTok().getLoc();
780  if (Parser.parseExpression(Register))
781  return MatchOperand_ParseFail;
782 
783  if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
784  int64_t Value = CE->getValue();
785  if (Value < 0 || Value > 15) {
786  Error(StartLoc, "invalid register");
787  return MatchOperand_ParseFail;
788  }
789  }
790 
791  SMLoc EndLoc =
792  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
793 
794  Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
795  }
796  else {
797  Register Reg;
798  if (parseRegister(Reg))
799  return MatchOperand_ParseFail;
800 
801  // Map to the correct register kind.
803  unsigned RegNo;
804  if (Reg.Group == RegGR) {
805  Kind = GR64Reg;
806  RegNo = SystemZMC::GR64Regs[Reg.Num];
807  }
808  else if (Reg.Group == RegFP) {
809  Kind = FP64Reg;
810  RegNo = SystemZMC::FP64Regs[Reg.Num];
811  }
812  else if (Reg.Group == RegV) {
813  Kind = VR128Reg;
814  RegNo = SystemZMC::VR128Regs[Reg.Num];
815  }
816  else if (Reg.Group == RegAR) {
817  Kind = AR32Reg;
818  RegNo = SystemZMC::AR32Regs[Reg.Num];
819  }
820  else if (Reg.Group == RegCR) {
821  Kind = CR64Reg;
822  RegNo = SystemZMC::CR64Regs[Reg.Num];
823  }
824  else {
825  return MatchOperand_ParseFail;
826  }
827 
828  Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
829  Reg.StartLoc, Reg.EndLoc));
830  }
831  return MatchOperand_Success;
832 }
833 
834 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
835 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
836  bool &HaveReg2, Register &Reg2,
837  const MCExpr *&Disp,
838  const MCExpr *&Length) {
839  // Parse the displacement, which must always be present.
840  if (getParser().parseExpression(Disp))
841  return true;
842 
843  // Parse the optional base and index.
844  HaveReg1 = false;
845  HaveReg2 = false;
846  Length = nullptr;
847  if (getLexer().is(AsmToken::LParen)) {
848  Parser.Lex();
849 
850  if (getLexer().is(AsmToken::Percent)) {
851  // Parse the first register.
852  HaveReg1 = true;
853  if (parseRegister(Reg1))
854  return true;
855  } else {
856  // Parse the length.
857  if (getParser().parseExpression(Length))
858  return true;
859  }
860 
861  // Check whether there's a second register.
862  if (getLexer().is(AsmToken::Comma)) {
863  Parser.Lex();
864  HaveReg2 = true;
865  if (parseRegister(Reg2))
866  return true;
867  }
868 
869  // Consume the closing bracket.
870  if (getLexer().isNot(AsmToken::RParen))
871  return Error(Parser.getTok().getLoc(), "unexpected token in address");
872  Parser.Lex();
873  }
874  return false;
875 }
876 
877 // Verify that Reg is a valid address register (base or index).
878 bool
879 SystemZAsmParser::parseAddressRegister(Register &Reg) {
880  if (Reg.Group == RegV) {
881  Error(Reg.StartLoc, "invalid use of vector addressing");
882  return true;
883  } else if (Reg.Group != RegGR) {
884  Error(Reg.StartLoc, "invalid address register");
885  return true;
886  } else if (Reg.Num == 0) {
887  Error(Reg.StartLoc, "%r0 used in an address");
888  return true;
889  }
890  return false;
891 }
892 
893 // Parse a memory operand and add it to Operands. The other arguments
894 // are as above.
896 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
897  const unsigned *Regs, RegisterKind RegKind) {
898  SMLoc StartLoc = Parser.getTok().getLoc();
899  unsigned Base = 0, Index = 0, LengthReg = 0;
900  Register Reg1, Reg2;
901  bool HaveReg1, HaveReg2;
902  const MCExpr *Disp;
903  const MCExpr *Length;
904  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
905  return MatchOperand_ParseFail;
906 
907  switch (MemKind) {
908  case BDMem:
909  // If we have Reg1, it must be an address register.
910  if (HaveReg1) {
911  if (parseAddressRegister(Reg1))
912  return MatchOperand_ParseFail;
913  Base = Regs[Reg1.Num];
914  }
915  // There must be no Reg2 or length.
916  if (Length) {
917  Error(StartLoc, "invalid use of length addressing");
918  return MatchOperand_ParseFail;
919  }
920  if (HaveReg2) {
921  Error(StartLoc, "invalid use of indexed addressing");
922  return MatchOperand_ParseFail;
923  }
924  break;
925  case BDXMem:
926  // If we have Reg1, it must be an address register.
927  if (HaveReg1) {
928  if (parseAddressRegister(Reg1))
929  return MatchOperand_ParseFail;
930  // If the are two registers, the first one is the index and the
931  // second is the base.
932  if (HaveReg2)
933  Index = Regs[Reg1.Num];
934  else
935  Base = Regs[Reg1.Num];
936  }
937  // If we have Reg2, it must be an address register.
938  if (HaveReg2) {
939  if (parseAddressRegister(Reg2))
940  return MatchOperand_ParseFail;
941  Base = Regs[Reg2.Num];
942  }
943  // There must be no length.
944  if (Length) {
945  Error(StartLoc, "invalid use of length addressing");
946  return MatchOperand_ParseFail;
947  }
948  break;
949  case BDLMem:
950  // If we have Reg2, it must be an address register.
951  if (HaveReg2) {
952  if (parseAddressRegister(Reg2))
953  return MatchOperand_ParseFail;
954  Base = Regs[Reg2.Num];
955  }
956  // We cannot support base+index addressing.
957  if (HaveReg1 && HaveReg2) {
958  Error(StartLoc, "invalid use of indexed addressing");
959  return MatchOperand_ParseFail;
960  }
961  // We must have a length.
962  if (!Length) {
963  Error(StartLoc, "missing length in address");
964  return MatchOperand_ParseFail;
965  }
966  break;
967  case BDRMem:
968  // We must have Reg1, and it must be a GPR.
969  if (!HaveReg1 || Reg1.Group != RegGR) {
970  Error(StartLoc, "invalid operand for instruction");
971  return MatchOperand_ParseFail;
972  }
973  LengthReg = SystemZMC::GR64Regs[Reg1.Num];
974  // If we have Reg2, it must be an address register.
975  if (HaveReg2) {
976  if (parseAddressRegister(Reg2))
977  return MatchOperand_ParseFail;
978  Base = Regs[Reg2.Num];
979  }
980  // There must be no length.
981  if (Length) {
982  Error(StartLoc, "invalid use of length addressing");
983  return MatchOperand_ParseFail;
984  }
985  break;
986  case BDVMem:
987  // We must have Reg1, and it must be a vector register.
988  if (!HaveReg1 || Reg1.Group != RegV) {
989  Error(StartLoc, "vector index required in address");
990  return MatchOperand_ParseFail;
991  }
992  Index = SystemZMC::VR128Regs[Reg1.Num];
993  // If we have Reg2, it must be an address register.
994  if (HaveReg2) {
995  if (parseAddressRegister(Reg2))
996  return MatchOperand_ParseFail;
997  Base = Regs[Reg2.Num];
998  }
999  // There must be no length.
1000  if (Length) {
1001  Error(StartLoc, "invalid use of length addressing");
1002  return MatchOperand_ParseFail;
1003  }
1004  break;
1005  }
1006 
1007  SMLoc EndLoc =
1008  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1009  Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
1010  Index, Length, LengthReg,
1011  StartLoc, EndLoc));
1012  return MatchOperand_Success;
1013 }
1014 
1015 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
1016  StringRef IDVal = DirectiveID.getIdentifier();
1017 
1018  if (IDVal == ".insn")
1019  return ParseDirectiveInsn(DirectiveID.getLoc());
1020 
1021  return true;
1022 }
1023 
1024 /// ParseDirectiveInsn
1025 /// ::= .insn [ format, encoding, (operands (, operands)*) ]
1026 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) {
1027  MCAsmParser &Parser = getParser();
1028 
1029  // Expect instruction format as identifier.
1030  StringRef Format;
1031  SMLoc ErrorLoc = Parser.getTok().getLoc();
1032  if (Parser.parseIdentifier(Format))
1033  return Error(ErrorLoc, "expected instruction format");
1034 
1036 
1037  // Find entry for this format in InsnMatchTable.
1038  auto EntryRange =
1039  std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable),
1040  Format, CompareInsn());
1041 
1042  // If first == second, couldn't find a match in the table.
1043  if (EntryRange.first == EntryRange.second)
1044  return Error(ErrorLoc, "unrecognized format");
1045 
1046  struct InsnMatchEntry *Entry = EntryRange.first;
1047 
1048  // Format should match from equal_range.
1049  assert(Entry->Format == Format);
1050 
1051  // Parse the following operands using the table's information.
1052  for (int i = 0; i < Entry->NumOperands; i++) {
1053  MatchClassKind Kind = Entry->OperandKinds[i];
1054 
1055  SMLoc StartLoc = Parser.getTok().getLoc();
1056 
1057  // Always expect commas as separators for operands.
1058  if (getLexer().isNot(AsmToken::Comma))
1059  return Error(StartLoc, "unexpected token in directive");
1060  Lex();
1061 
1062  // Parse operands.
1063  OperandMatchResultTy ResTy;
1064  if (Kind == MCK_AnyReg)
1065  ResTy = parseAnyReg(Operands);
1066  else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
1067  ResTy = parseBDXAddr64(Operands);
1068  else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
1069  ResTy = parseBDAddr64(Operands);
1070  else if (Kind == MCK_PCRel32)
1071  ResTy = parsePCRel32(Operands);
1072  else if (Kind == MCK_PCRel16)
1073  ResTy = parsePCRel16(Operands);
1074  else {
1075  // Only remaining operand kind is an immediate.
1076  const MCExpr *Expr;
1077  SMLoc StartLoc = Parser.getTok().getLoc();
1078 
1079  // Expect immediate expression.
1080  if (Parser.parseExpression(Expr))
1081  return Error(StartLoc, "unexpected token in directive");
1082 
1083  SMLoc EndLoc =
1084  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1085 
1086  Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1087  ResTy = MatchOperand_Success;
1088  }
1089 
1090  if (ResTy != MatchOperand_Success)
1091  return true;
1092  }
1093 
1094  // Build the instruction with the parsed operands.
1095  MCInst Inst = MCInstBuilder(Entry->Opcode);
1096 
1097  for (size_t i = 0; i < Operands.size(); i++) {
1098  MCParsedAsmOperand &Operand = *Operands[i];
1099  MatchClassKind Kind = Entry->OperandKinds[i];
1100 
1101  // Verify operand.
1102  unsigned Res = validateOperandClass(Operand, Kind);
1103  if (Res != Match_Success)
1104  return Error(Operand.getStartLoc(), "unexpected operand type");
1105 
1106  // Add operands to instruction.
1107  SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand);
1108  if (ZOperand.isReg())
1109  ZOperand.addRegOperands(Inst, 1);
1110  else if (ZOperand.isMem(BDMem))
1111  ZOperand.addBDAddrOperands(Inst, 2);
1112  else if (ZOperand.isMem(BDXMem))
1113  ZOperand.addBDXAddrOperands(Inst, 3);
1114  else if (ZOperand.isImm())
1115  ZOperand.addImmOperands(Inst, 1);
1116  else
1117  llvm_unreachable("unexpected operand type");
1118  }
1119 
1120  // Emit as a regular instruction.
1121  Parser.getStreamer().EmitInstruction(Inst, getSTI());
1122 
1123  return false;
1124 }
1125 
1126 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1127  SMLoc &EndLoc) {
1128  Register Reg;
1129  if (parseRegister(Reg))
1130  return true;
1131  if (Reg.Group == RegGR)
1132  RegNo = SystemZMC::GR64Regs[Reg.Num];
1133  else if (Reg.Group == RegFP)
1134  RegNo = SystemZMC::FP64Regs[Reg.Num];
1135  else if (Reg.Group == RegV)
1136  RegNo = SystemZMC::VR128Regs[Reg.Num];
1137  else if (Reg.Group == RegAR)
1138  RegNo = SystemZMC::AR32Regs[Reg.Num];
1139  else if (Reg.Group == RegCR)
1140  RegNo = SystemZMC::CR64Regs[Reg.Num];
1141  StartLoc = Reg.StartLoc;
1142  EndLoc = Reg.EndLoc;
1143  return false;
1144 }
1145 
1146 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1147  StringRef Name, SMLoc NameLoc,
1148  OperandVector &Operands) {
1149  Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
1150 
1151  // Read the remaining operands.
1152  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1153  // Read the first operand.
1154  if (parseOperand(Operands, Name)) {
1155  return true;
1156  }
1157 
1158  // Read any subsequent operands.
1159  while (getLexer().is(AsmToken::Comma)) {
1160  Parser.Lex();
1161  if (parseOperand(Operands, Name)) {
1162  return true;
1163  }
1164  }
1165  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1166  SMLoc Loc = getLexer().getLoc();
1167  return Error(Loc, "unexpected token in argument list");
1168  }
1169  }
1170 
1171  // Consume the EndOfStatement.
1172  Parser.Lex();
1173  return false;
1174 }
1175 
1176 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
1177  StringRef Mnemonic) {
1178  // Check if the current operand has a custom associated parser, if so, try to
1179  // custom parse the operand, or fallback to the general approach. Force all
1180  // features to be available during the operand check, or else we will fail to
1181  // find the custom parser, and then we will later get an InvalidOperand error
1182  // instead of a MissingFeature errror.
1183  FeatureBitset AvailableFeatures = getAvailableFeatures();
1185  All.set();
1186  setAvailableFeatures(All);
1187  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1188  setAvailableFeatures(AvailableFeatures);
1189  if (ResTy == MatchOperand_Success)
1190  return false;
1191 
1192  // If there wasn't a custom match, try the generic matcher below. Otherwise,
1193  // there was a match, but an error occurred, in which case, just return that
1194  // the operand parsing failed.
1195  if (ResTy == MatchOperand_ParseFail)
1196  return true;
1197 
1198  // Check for a register. All real register operands should have used
1199  // a context-dependent parse routine, which gives the required register
1200  // class. The code is here to mop up other cases, like those where
1201  // the instruction isn't recognized.
1202  if (Parser.getTok().is(AsmToken::Percent)) {
1203  Register Reg;
1204  if (parseRegister(Reg))
1205  return true;
1206  Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1207  return false;
1208  }
1209 
1210  // The only other type of operand is an immediate or address. As above,
1211  // real address operands should have used a context-dependent parse routine,
1212  // so we treat any plain expression as an immediate.
1213  SMLoc StartLoc = Parser.getTok().getLoc();
1214  Register Reg1, Reg2;
1215  bool HaveReg1, HaveReg2;
1216  const MCExpr *Expr;
1217  const MCExpr *Length;
1218  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1219  return true;
1220  // If the register combination is not valid for any instruction, reject it.
1221  // Otherwise, fall back to reporting an unrecognized instruction.
1222  if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1223  && parseAddressRegister(Reg1))
1224  return true;
1225  if (HaveReg2 && parseAddressRegister(Reg2))
1226  return true;
1227 
1228  SMLoc EndLoc =
1229  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1230  if (HaveReg1 || HaveReg2 || Length)
1231  Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1232  else
1233  Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1234  return false;
1235 }
1236 
1237 static std::string SystemZMnemonicSpellCheck(StringRef S,
1238  const FeatureBitset &FBS,
1239  unsigned VariantID = 0);
1240 
1241 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1242  OperandVector &Operands,
1243  MCStreamer &Out,
1244  uint64_t &ErrorInfo,
1245  bool MatchingInlineAsm) {
1246  MCInst Inst;
1247  unsigned MatchResult;
1248 
1249  FeatureBitset MissingFeatures;
1250  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1251  MissingFeatures, MatchingInlineAsm);
1252  switch (MatchResult) {
1253  case Match_Success:
1254  Inst.setLoc(IDLoc);
1255  Out.EmitInstruction(Inst, getSTI());
1256  return false;
1257 
1258  case Match_MissingFeature: {
1259  assert(MissingFeatures.any() && "Unknown missing feature!");
1260  // Special case the error message for the very common case where only
1261  // a single subtarget feature is missing
1262  std::string Msg = "instruction requires:";
1263  for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) {
1264  if (MissingFeatures[I]) {
1265  Msg += " ";
1266  Msg += getSubtargetFeatureName(I);
1267  }
1268  }
1269  return Error(IDLoc, Msg);
1270  }
1271 
1272  case Match_InvalidOperand: {
1273  SMLoc ErrorLoc = IDLoc;
1274  if (ErrorInfo != ~0ULL) {
1275  if (ErrorInfo >= Operands.size())
1276  return Error(IDLoc, "too few operands for instruction");
1277 
1278  ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1279  if (ErrorLoc == SMLoc())
1280  ErrorLoc = IDLoc;
1281  }
1282  return Error(ErrorLoc, "invalid operand for instruction");
1283  }
1284 
1285  case Match_MnemonicFail: {
1286  FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1287  std::string Suggestion = SystemZMnemonicSpellCheck(
1288  ((SystemZOperand &)*Operands[0]).getToken(), FBS);
1289  return Error(IDLoc, "invalid instruction" + Suggestion,
1290  ((SystemZOperand &)*Operands[0]).getLocRange());
1291  }
1292  }
1293 
1294  llvm_unreachable("Unexpected match type");
1295 }
1296 
1298 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
1299  int64_t MaxVal, bool AllowTLS) {
1300  MCContext &Ctx = getContext();
1301  MCStreamer &Out = getStreamer();
1302  const MCExpr *Expr;
1303  SMLoc StartLoc = Parser.getTok().getLoc();
1304  if (getParser().parseExpression(Expr))
1305  return MatchOperand_NoMatch;
1306 
1307  // For consistency with the GNU assembler, treat immediates as offsets
1308  // from ".".
1309  if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1310  int64_t Value = CE->getValue();
1311  if ((Value & 1) || Value < MinVal || Value > MaxVal) {
1312  Error(StartLoc, "offset out of range");
1313  return MatchOperand_ParseFail;
1314  }
1315  MCSymbol *Sym = Ctx.createTempSymbol();
1316  Out.EmitLabel(Sym);
1318  Ctx);
1319  Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
1320  }
1321 
1322  // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
1323  const MCExpr *Sym = nullptr;
1324  if (AllowTLS && getLexer().is(AsmToken::Colon)) {
1325  Parser.Lex();
1326 
1327  if (Parser.getTok().isNot(AsmToken::Identifier)) {
1328  Error(Parser.getTok().getLoc(), "unexpected token");
1329  return MatchOperand_ParseFail;
1330  }
1331 
1333  StringRef Name = Parser.getTok().getString();
1334  if (Name == "tls_gdcall")
1336  else if (Name == "tls_ldcall")
1338  else {
1339  Error(Parser.getTok().getLoc(), "unknown TLS tag");
1340  return MatchOperand_ParseFail;
1341  }
1342  Parser.Lex();
1343 
1344  if (Parser.getTok().isNot(AsmToken::Colon)) {
1345  Error(Parser.getTok().getLoc(), "unexpected token");
1346  return MatchOperand_ParseFail;
1347  }
1348  Parser.Lex();
1349 
1350  if (Parser.getTok().isNot(AsmToken::Identifier)) {
1351  Error(Parser.getTok().getLoc(), "unexpected token");
1352  return MatchOperand_ParseFail;
1353  }
1354 
1355  StringRef Identifier = Parser.getTok().getString();
1356  Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
1357  Kind, Ctx);
1358  Parser.Lex();
1359  }
1360 
1361  SMLoc EndLoc =
1362  SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1363 
1364  if (AllowTLS)
1365  Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
1366  StartLoc, EndLoc));
1367  else
1368  Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1369 
1370  return MatchOperand_Success;
1371 }
1372 
1373 // Force static initialization.
1376 }
static bool isReg(const MCInst &MI, unsigned OpNo)
Represents a range in source code.
Definition: SMLoc.h:48
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const unsigned GR32Regs[16]
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:327
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const unsigned FP128Regs[16]
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:109
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
MCTargetAsmParser - Generic interface to target specific assembly parsers.
void push_back(const T &Elt)
Definition: SmallVector.h:211
MatchClassKind OperandKinds[5]
unsigned Reg
const unsigned FP32Regs[16]
static struct InsnMatchEntry InsnMatchTable[]
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:33
MemoryKind
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
const unsigned VR64Regs[32]
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
Definition: MCAsmMacro.h:99
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
RegisterKind
const unsigned AR32Regs[16]
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
const unsigned GRH32Regs[16]
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:578
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:122
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
Context object for machine code objects.
Definition: MCContext.h:65
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \\\)
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:27
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:465
const unsigned CR64Regs[16]
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
virtual void addAliasForDirective(StringRef Directive, StringRef Alias)=0
const char * getPointer() const
Definition: SMLoc.h:34
Streaming machine code generation interface.
Definition: MCStreamer.h:189
static const char * getRegisterName(unsigned RegNo)
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:225
Container class for subtarget features.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
static std::string SystemZMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID=0)
size_t size() const
Definition: SmallVector.h:52
void setLoc(SMLoc loc)
Definition: MCInst.h:176
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
virtual MCStreamer & getStreamer()=0
Return the output streamer for the assembler.
static void printMCExpr(const MCExpr *E, raw_ostream &OS)
void LLVMInitializeSystemZAsmParser()
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
const unsigned FP64Regs[16]
virtual SMLoc getStartLoc() const =0
getStartLoc - Get the location of the first token of this operand.
Promote Memory to Register
Definition: Mem2Reg.cpp:109
const unsigned GR128Regs[16]
const unsigned GR64Regs[16]
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Base class for user error types.
Definition: Error.h:344
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
Target & getTheSystemZTarget()
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:129
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
Generic base class for all target subtargets.
const unsigned VR32Regs[32]
LLVM_NODISCARD const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:122
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
virtual void EmitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:397
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual bool parseIdentifier(StringRef &Res)=0
Parse an identifier or string (as a quoted identifier) and set Res to the identifier contents...
Represents a location in source code.
Definition: SMLoc.h:23
static const char * getSubtargetFeatureName(uint64_t Val)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
const unsigned VR128Regs[32]
Wrapper class representing virtual and physical registers.
Definition: Register.h:19