32#define DEBUG_TYPE "mccodeemitter"
40 mutable unsigned MemOpsEmitted;
44 : MCII(mcii), Ctx(ctx) {
47 ~SystemZMCCodeEmitter()
override =
default;
108 unsigned Kind, int64_t
Offset,
109 bool AllowTLS)
const;
114 return getPCRelEncoding(
MI, OpNum, Fixups,
120 return getPCRelEncoding(
MI, OpNum, Fixups,
126 return getPCRelEncoding(
MI, OpNum, Fixups,
132 return getPCRelEncoding(
MI, OpNum, Fixups,
138 return getPCRelEncoding(
MI, OpNum, Fixups,
144 return getPCRelEncoding(
MI, OpNum, Fixups,
150 return getPCRelEncoding(
MI, OpNum, Fixups,
162 unsigned Size = MCII.get(
MI.getOpcode()).getSize();
164 unsigned ShiftValue = (
Size * 8) - 8;
165 for (
unsigned I = 0;
I !=
Size; ++
I) {
166 OS << uint8_t(Bits >> ShiftValue);
176 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg());
183getDispOpValue(
const MCInst &
MI,
unsigned OpNum,
194 unsigned ByteOffs = MemOpsEmitted++ == 0 ? 2 : 4;
197 assert(
Fixups.size() <= 2 &&
"More than two memory operands in MI?");
204getBDAddr12Encoding(
const MCInst &
MI,
unsigned OpNum,
210 return (
Base << 12) | Disp;
214getBDAddr20Encoding(
const MCInst &
MI,
unsigned OpNum,
220 return (
Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
224getBDXAddr12Encoding(
const MCInst &
MI,
unsigned OpNum,
231 return (
Index << 16) | (
Base << 12) | Disp;
235getBDXAddr20Encoding(
const MCInst &
MI,
unsigned OpNum,
242 return (
Index << 24) | (
Base << 20) | ((Disp & 0xfff) << 8)
243 | ((Disp & 0xff000) >> 12);
247getBDLAddr12Len4Encoding(
const MCInst &
MI,
unsigned OpNum,
252 uint64_t Len = getMachineOpValue(
MI,
MI.getOperand(OpNum + 2), Fixups, STI) - 1;
253 assert(isUInt<4>(
Base) && isUInt<12>(Disp) && isUInt<4>(Len));
254 return (Len << 16) | (
Base << 12) | Disp;
258getBDLAddr12Len8Encoding(
const MCInst &
MI,
unsigned OpNum,
263 uint64_t Len = getMachineOpValue(
MI,
MI.getOperand(OpNum + 2), Fixups, STI) - 1;
264 assert(isUInt<4>(
Base) && isUInt<12>(Disp) && isUInt<8>(Len));
265 return (Len << 16) | (
Base << 12) | Disp;
269getBDRAddr12Encoding(
const MCInst &
MI,
unsigned OpNum,
274 uint64_t Len = getMachineOpValue(
MI,
MI.getOperand(OpNum + 2), Fixups, STI);
275 assert(isUInt<4>(
Base) && isUInt<12>(Disp) && isUInt<4>(Len));
276 return (Len << 16) | (
Base << 12) | Disp;
280getBDVAddr12Encoding(
const MCInst &
MI,
unsigned OpNum,
287 return (
Index << 16) | (
Base << 12) | Disp;
291SystemZMCCodeEmitter::getPCRelEncoding(
const MCInst &
MI,
unsigned OpNum,
293 unsigned Kind, int64_t
Offset,
294 bool AllowTLS)
const {
314 if (AllowTLS && OpNum + 1 <
MI.getNumOperands()) {
322#include "SystemZGenMCCodeEmitter.inc"
326 return new SystemZMCCodeEmitter(MCII, Ctx);
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Instances of this class represent a single low-level machine instruction.
Interface to description of machine instruction set.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
Generic base class for all target subtargets.
Represents a location in source code.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
MCCodeEmitter * createSystemZMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)