LLVM  15.0.0git
VEMCCodeEmitter.cpp
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1 //===-- VEMCCodeEmitter.cpp - Convert VE code to machine code -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the VEMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "VE.h"
15 #include "VEMCExpr.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCFixup.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSymbol.h"
30 #include <cassert>
31 #include <cstdint>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "mccodeemitter"
36 
37 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
38 
39 namespace {
40 
41 class VEMCCodeEmitter : public MCCodeEmitter {
42  MCContext &Ctx;
43 
44 public:
45  VEMCCodeEmitter(const MCInstrInfo &, MCContext &ctx)
46  : Ctx(ctx) {}
47  VEMCCodeEmitter(const VEMCCodeEmitter &) = delete;
48  VEMCCodeEmitter &operator=(const VEMCCodeEmitter &) = delete;
49  ~VEMCCodeEmitter() override = default;
50 
51  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
53  const MCSubtargetInfo &STI) const override;
54 
55  // getBinaryCodeForInstr - TableGen'erated function for getting the
56  // binary encoding for an instruction.
57  uint64_t getBinaryCodeForInstr(const MCInst &MI,
59  const MCSubtargetInfo &STI) const;
60 
61  /// getMachineOpValue - Return binary encoding of operand. If the machine
62  /// operand requires relocation, record the relocation and return zero.
63  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
65  const MCSubtargetInfo &STI) const;
66 
67  uint64_t getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
69  const MCSubtargetInfo &STI) const;
70  uint64_t getCCOpValue(const MCInst &MI, unsigned OpNo,
72  const MCSubtargetInfo &STI) const;
73  uint64_t getRDOpValue(const MCInst &MI, unsigned OpNo,
75  const MCSubtargetInfo &STI) const;
76 };
77 
78 } // end anonymous namespace
79 
80 void VEMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
82  const MCSubtargetInfo &STI) const {
83  uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
84  support::endian::write<uint64_t>(OS, Bits, support::little);
85 
86  ++MCNumEmitted; // Keep track of the # of mi's emitted.
87 }
88 
89 unsigned VEMCCodeEmitter::getMachineOpValue(const MCInst &MI,
90  const MCOperand &MO,
92  const MCSubtargetInfo &STI) const {
93  if (MO.isReg())
94  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
95  if (MO.isImm())
96  return static_cast<unsigned>(MO.getImm());
97 
98  assert(MO.isExpr());
99 
100  const MCExpr *Expr = MO.getExpr();
101  if (const VEMCExpr *SExpr = dyn_cast<VEMCExpr>(Expr)) {
102  MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
103  Fixups.push_back(MCFixup::create(0, Expr, Kind));
104  return 0;
105  }
106 
107  int64_t Res;
108  if (Expr->evaluateAsAbsolute(Res))
109  return Res;
110 
111  llvm_unreachable("Unhandled expression!");
112  return 0;
113 }
114 
115 uint64_t
118  const MCSubtargetInfo &STI) const {
119  const MCOperand &MO = MI.getOperand(OpNo);
120  if (MO.isReg() || MO.isImm())
121  return getMachineOpValue(MI, MO, Fixups, STI);
122 
123  Fixups.push_back(
125  return 0;
126 }
127 
128 uint64_t VEMCCodeEmitter::getCCOpValue(const MCInst &MI, unsigned OpNo,
130  const MCSubtargetInfo &STI) const {
131  const MCOperand &MO = MI.getOperand(OpNo);
132  if (MO.isImm())
133  return VECondCodeToVal(
134  static_cast<VECC::CondCode>(getMachineOpValue(MI, MO, Fixups, STI)));
135  return 0;
136 }
137 
138 uint64_t VEMCCodeEmitter::getRDOpValue(const MCInst &MI, unsigned OpNo,
140  const MCSubtargetInfo &STI) const {
141  const MCOperand &MO = MI.getOperand(OpNo);
142  if (MO.isImm())
143  return VERDToVal(static_cast<VERD::RoundingMode>(
144  getMachineOpValue(MI, MO, Fixups, STI)));
145  return 0;
146 }
147 
148 #include "VEGenMCCodeEmitter.inc"
149 
151  MCContext &Ctx) {
152  return new VEMCCodeEmitter(MCII, Ctx);
153 }
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::VECC::CondCode
CondCode
Definition: VE.h:40
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
MCCodeEmitter.h
Statistic.h
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
ErrorHandling.h
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
VEFixupKinds.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::VECondCodeToVal
static unsigned VECondCodeToVal(VECC::CondCode CC)
Definition: VE.h:148
llvm::support::little
@ little
Definition: Endian.h:27
MCContext.h
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
MCSymbol.h
MCInst.h
llvm::VEMCExpr
Definition: VEMCExpr.h:23
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
MCSubtargetInfo.h
getBranchTargetOpValue
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
Definition: ARMMCCodeEmitter.cpp:620
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
uint64_t
MCRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::createVEMCCodeEmitter
MCCodeEmitter * createVEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: VEMCCodeEmitter.cpp:150
llvm::VERDToVal
static unsigned VERDToVal(VERD::RoundingMode R)
Definition: VE.h:288
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
MCFixup.h
VEMCExpr.h
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
EndianStream.h
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
VE.h
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
SmallVector.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
raw_ostream.h
llvm::VE::fixup_ve_srel32
@ fixup_ve_srel32
fixup_ve_srel32 - 32-bit fixup corresponding to foo for relative branch
Definition: VEFixupKinds.h:21
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::VERD::RoundingMode
RoundingMode
Definition: VE.h:72
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69