35 #define DEBUG_TYPE "mccodeemitter" 37 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
47 : MCII(mcii), Ctx(ctx) {}
48 VEMCCodeEmitter(
const VEMCCodeEmitter &) =
delete;
49 VEMCCodeEmitter &
operator=(
const VEMCCodeEmitter &) =
delete;
50 ~VEMCCodeEmitter()
override =
default;
58 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
71 uint64_t getCCOpValue(
const MCInst &
MI,
unsigned OpNo,
74 uint64_t getRDOpValue(
const MCInst &
MI,
unsigned OpNo,
81 verifyInstructionPredicates(
const MCInst &
MI,
90 verifyInstructionPredicates(
MI,
99 unsigned VEMCCodeEmitter::getMachineOpValue(
const MCInst &
MI,
104 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg());
111 if (
const VEMCExpr *SExpr = dyn_cast<VEMCExpr>(Expr)) {
118 if (Expr->evaluateAsAbsolute(Res))
131 return getMachineOpValue(
MI, MO,
Fixups, STI);
138 uint64_t VEMCCodeEmitter::getCCOpValue(
const MCInst &
MI,
unsigned OpNo,
144 static_cast<VECC::CondCode>(getMachineOpValue(
MI, MO,
Fixups, STI)));
148 uint64_t VEMCCodeEmitter::getRDOpValue(
const MCInst &
MI,
unsigned OpNo,
153 return VERDToVal(static_cast<VERD::RoundingMode>(
154 getMachineOpValue(
MI, MO,
Fixups, STI)));
158 #define ENABLE_INSTR_PREDICATE_VERIFIER 159 #include "VEGenMCCodeEmitter.inc" 164 return new VEMCCodeEmitter(MCII, Ctx);
This class represents lattice values for constants.
STATISTIC(NumFunctions, "Total number of functions")
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
unsigned getReg() const
Returns the register number.
Context object for machine code objects.
const MCExpr * getExpr() const
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Generic base class for all target subtargets.
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
Root & operator=(Root &&)=delete
fixup_ve_pc_lo32 - 32-bit fixup corresponding to foo@pc_lo
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static unsigned VERDToVal(VERD::RoundingMode R)
MCCodeEmitter * createVEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
This class implements an extremely fast bulk output stream that can only output to a stream.
Instances of this class represent operands of the MCInst class.
static unsigned VECondCodeToVal(VECC::CondCode CC)