LLVM  12.0.0git
VEMCCodeEmitter.cpp
Go to the documentation of this file.
1 //===-- VEMCCodeEmitter.cpp - Convert VE code to machine code -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the VEMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "VE.h"
15 #include "VEMCExpr.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCFixup.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSymbol.h"
30 #include <cassert>
31 #include <cstdint>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "mccodeemitter"
36 
37 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
38 
39 namespace {
40 
41 class VEMCCodeEmitter : public MCCodeEmitter {
42  const MCInstrInfo &MCII;
43  MCContext &Ctx;
44 
45 public:
46  VEMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
47  : MCII(mcii), Ctx(ctx) {}
48  VEMCCodeEmitter(const VEMCCodeEmitter &) = delete;
49  VEMCCodeEmitter &operator=(const VEMCCodeEmitter &) = delete;
50  ~VEMCCodeEmitter() override = default;
51 
52  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
54  const MCSubtargetInfo &STI) const override;
55 
56  // getBinaryCodeForInstr - TableGen'erated function for getting the
57  // binary encoding for an instruction.
58  uint64_t getBinaryCodeForInstr(const MCInst &MI,
60  const MCSubtargetInfo &STI) const;
61 
62  /// getMachineOpValue - Return binary encoding of operand. If the machine
63  /// operand requires relocation, record the relocation and return zero.
64  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
66  const MCSubtargetInfo &STI) const;
67 
68  uint64_t getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
70  const MCSubtargetInfo &STI) const;
71  uint64_t getCCOpValue(const MCInst &MI, unsigned OpNo,
73  const MCSubtargetInfo &STI) const;
74  uint64_t getRDOpValue(const MCInst &MI, unsigned OpNo,
76  const MCSubtargetInfo &STI) const;
77 
78 private:
79  FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
80  void
81  verifyInstructionPredicates(const MCInst &MI,
82  const FeatureBitset &AvailableFeatures) const;
83 };
84 
85 } // end anonymous namespace
86 
87 void VEMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
89  const MCSubtargetInfo &STI) const {
90  verifyInstructionPredicates(MI,
91  computeAvailableFeatures(STI.getFeatureBits()));
92 
93  uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
94  support::endian::write<uint64_t>(OS, Bits, support::little);
95 
96  ++MCNumEmitted; // Keep track of the # of mi's emitted.
97 }
98 
99 unsigned VEMCCodeEmitter::getMachineOpValue(const MCInst &MI,
100  const MCOperand &MO,
102  const MCSubtargetInfo &STI) const {
103  if (MO.isReg())
104  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
105 
106  if (MO.isImm())
107  return MO.getImm();
108 
109  assert(MO.isExpr());
110  const MCExpr *Expr = MO.getExpr();
111  if (const VEMCExpr *SExpr = dyn_cast<VEMCExpr>(Expr)) {
112  MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
113  Fixups.push_back(MCFixup::create(0, Expr, Kind));
114  return 0;
115  }
116 
117  int64_t Res;
118  if (Expr->evaluateAsAbsolute(Res))
119  return Res;
120 
121  llvm_unreachable("Unhandled expression!");
122  return 0;
123 }
124 
125 uint64_t
128  const MCSubtargetInfo &STI) const {
129  const MCOperand &MO = MI.getOperand(OpNo);
130  if (MO.isReg() || MO.isImm())
131  return getMachineOpValue(MI, MO, Fixups, STI);
132 
133  Fixups.push_back(
135  return 0;
136 }
137 
138 uint64_t VEMCCodeEmitter::getCCOpValue(const MCInst &MI, unsigned OpNo,
140  const MCSubtargetInfo &STI) const {
141  const MCOperand &MO = MI.getOperand(OpNo);
142  if (MO.isImm())
143  return VECondCodeToVal(
144  static_cast<VECC::CondCode>(getMachineOpValue(MI, MO, Fixups, STI)));
145  return 0;
146 }
147 
148 uint64_t VEMCCodeEmitter::getRDOpValue(const MCInst &MI, unsigned OpNo,
150  const MCSubtargetInfo &STI) const {
151  const MCOperand &MO = MI.getOperand(OpNo);
152  if (MO.isImm())
153  return VERDToVal(static_cast<VERD::RoundingMode>(
154  getMachineOpValue(MI, MO, Fixups, STI)));
155  return 0;
156 }
157 
158 #define ENABLE_INSTR_PREDICATE_VERIFIER
159 #include "VEGenMCCodeEmitter.inc"
160 
162  const MCRegisterInfo &MRI,
163  MCContext &Ctx) {
164  return new VEMCCodeEmitter(MCII, Ctx);
165 }
bool isImm() const
Definition: MCInst.h:58
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isReg() const
Definition: MCInst.h:57
STATISTIC(NumFunctions, "Total number of functions")
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
Context object for machine code objects.
Definition: MCContext.h:68
const MCExpr * getExpr() const
Definition: MCInst.h:95
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
int64_t getImm() const
Definition: MCInst.h:75
unsigned const MachineRegisterInfo * MRI
Container class for subtarget features.
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
bool isExpr() const
Definition: MCInst.h:60
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:97
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Generic base class for all target subtargets.
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
Root & operator=(Root &&)=delete
fixup_ve_pc_lo32 - 32-bit fixup corresponding to foo@pc_lo
Definition: VEFixupKinds.h:30
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static unsigned VERDToVal(VERD::RoundingMode R)
Definition: VE.h:290
MCCodeEmitter * createVEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
IRTranslator LLVM IR MI
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
static unsigned VECondCodeToVal(VECC::CondCode CC)
Definition: VE.h:150