LLVM 17.0.0git
X86PreTileConfig.cpp
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1//===-- X86PreTileConfig.cpp - Tile Register Pre-configure-----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file Pass to pre-config the shapes of AMX registers
10/// AMX register needs to be configured before use. The shapes of AMX register
11/// are encoded in the 1st and 2nd machine operand of AMX pseudo instructions.
12///
13/// The instruction ldtilecfg is used to config the shapes. It must be reachable
14/// for all variable shapes. ldtilecfg will be inserted more than once if we
15/// cannot find a dominating point for all AMX instructions.
16///
17/// The configure register is caller saved according to ABI. We need to insert
18/// ldtilecfg again after the call instruction if callee clobbers any AMX
19/// registers.
20///
21/// This pass calculates all points that ldtilecfg need to be inserted to and
22/// insert them. It reports error if the reachability conditions aren't met.
23//
24//===----------------------------------------------------------------------===//
25
26#include "X86.h"
27#include "X86InstrBuilder.h"
29#include "X86RegisterInfo.h"
30#include "X86Subtarget.h"
36#include "llvm/CodeGen/Passes.h"
40
41using namespace llvm;
42
43#define DEBUG_TYPE "tile-pre-config"
44
45static void emitErrorMsg(MachineFunction &MF) {
47 Twine ErrorMsg =
48 MF.getName() +
49 ": Failed to config tile register, please define the shape earlier";
51 Context.emitError(ErrorMsg);
52}
53
54namespace {
55
56struct MIRef {
57 MachineInstr *MI = nullptr;
58 MachineBasicBlock *MBB = nullptr;
59 // A virtual position for instruction that will be inserted after MI.
60 size_t Pos = 0;
61 MIRef() = default;
62 MIRef(MachineBasicBlock *MBB) : MBB(MBB) {
63 for (auto I = MBB->begin(), E = MBB->end(); I != E && I->isPHI();
64 ++I, ++Pos)
65 MI = &*I;
66 }
67 MIRef(MachineInstr *MI)
68 : MI(MI), MBB(MI->getParent()),
69 Pos(std::distance(MBB->instr_begin(), ++MI->getIterator())) {}
70 MIRef(MachineInstr *MI, MachineBasicBlock *MBB)
71 : MI(MI), MBB(MBB),
72 Pos(std::distance(MBB->instr_begin(), ++MI->getIterator())) {}
73 MIRef(MachineInstr *MI, MachineBasicBlock *MBB, size_t Pos)
74 : MI(MI), MBB(MBB), Pos(Pos) {}
75 operator bool() const { return MBB != nullptr; }
76 bool operator==(const MIRef &RHS) const {
77 return MI == RHS.MI && MBB == RHS.MBB;
78 }
79 bool operator!=(const MIRef &RHS) const { return !(*this == RHS); }
80 bool operator<(const MIRef &RHS) const {
81 // Comparison between different BBs happens when inserting a MIRef into set.
82 // So we compare MBB first to make the insertion happy.
83 return MBB < RHS.MBB || (MBB == RHS.MBB && Pos < RHS.Pos);
84 }
85 bool operator>(const MIRef &RHS) const {
86 // Comparison between different BBs happens when inserting a MIRef into set.
87 // So we compare MBB first to make the insertion happy.
88 return MBB > RHS.MBB || (MBB == RHS.MBB && Pos > RHS.Pos);
89 }
90};
91
92struct BBInfo {
93 MIRef FirstAMX;
94 MIRef LastCall;
95 bool HasAMXRegLiveIn = false;
96 bool TileCfgForbidden = false;
97 bool NeedTileCfgLiveIn = false;
98};
99
100class X86PreTileConfig : public MachineFunctionPass {
102 const MachineLoopInfo *MLI;
106
107 /// Check if the callee will clobber AMX registers.
108 bool isDestructiveCall(MachineInstr &MI, BitVector UsableRegs) {
109 auto Iter = llvm::find_if(
110 MI.operands(), [](MachineOperand &MO) { return MO.isRegMask(); });
111 if (Iter == MI.operands_end())
112 return false;
113 UsableRegs.clearBitsInMask(Iter->getRegMask());
114 return !UsableRegs.none();
115 }
116
117 /// Check if MI is AMX pseudo instruction.
118 bool isAMXInstruction(MachineInstr &MI) {
119 if (MI.isPHI() || MI.isDebugInstr() || MI.getNumOperands() < 3)
120 return false;
121 MachineOperand &MO = MI.getOperand(0);
122 // We can simply check if it is AMX instruction by its def.
123 // But we should exclude old API which uses physical registers.
124 if (MO.isReg() && MO.getReg().isVirtual() &&
125 MRI->getRegClass(MO.getReg())->getID() == X86::TILERegClassID) {
126 collectShapeInfo(MI);
127 return true;
128 }
129 // PTILESTOREDV is the only exception that doesn't def a AMX register.
130 return MI.getOpcode() == X86::PTILESTOREDV;
131 }
132
133 /// Check if it is an edge from loop bottom to loop head.
134 bool isLoopBackEdge(MachineBasicBlock *Header, MachineBasicBlock *Bottom) {
135 if (!MLI->isLoopHeader(Header))
136 return false;
137 auto *ML = MLI->getLoopFor(Header);
138 if (ML->contains(Bottom) && ML->isLoopLatch(Bottom))
139 return true;
140
141 return false;
142 }
143
144 /// Collect the shape def information for later use.
145 void collectShapeInfo(MachineInstr &MI);
146
147 /// Try to hoist shapes definded below AMX instructions.
148 bool hoistShapesInBB(MachineBasicBlock *MBB, SmallVectorImpl<MIRef> &Shapes) {
149 MIRef &FirstAMX = BBVisitedInfo[MBB].FirstAMX;
150 auto FirstShapeBelowAMX = llvm::lower_bound(Shapes, FirstAMX);
151 auto InsertPoint = FirstAMX.MI->getIterator();
152 for (auto I = FirstShapeBelowAMX, E = Shapes.end(); I != E; ++I) {
153 // Do not hoist instructions that access memory.
154 if (I->MI->mayLoadOrStore())
155 return false;
156 for (auto &MO : I->MI->operands()) {
157 if (MO.isDef())
158 continue;
159 // Do not hoist instructions if the sources' def under AMX instruction.
160 // TODO: We can handle isMoveImmediate MI here.
161 if (MO.isReg() && MIRef(MRI->getVRegDef(MO.getReg())) > FirstAMX)
162 return false;
163 // TODO: Maybe need more checks here.
164 }
165 MBB->insert(InsertPoint, I->MI->removeFromParent());
166 }
167 // We only need to mark the last shape in the BB now.
168 Shapes.clear();
169 Shapes.push_back(MIRef(&*--InsertPoint, MBB));
170 return true;
171 }
172
173public:
174 X86PreTileConfig() : MachineFunctionPass(ID) {}
175
176 /// Return the pass name.
177 StringRef getPassName() const override {
178 return "Tile Register Pre-configure";
179 }
180
181 /// X86PreTileConfig analysis usage.
182 void getAnalysisUsage(AnalysisUsage &AU) const override {
183 AU.setPreservesAll();
186 }
187
188 /// Clear MF related structures.
189 void releaseMemory() override {
190 ShapeBBs.clear();
191 DefVisited.clear();
192 BBVisitedInfo.clear();
193 }
194
195 /// Perform ldtilecfg instructions inserting.
196 bool runOnMachineFunction(MachineFunction &MF) override;
197
198 static char ID;
199};
200
201} // end anonymous namespace
202
203char X86PreTileConfig::ID = 0;
204
205INITIALIZE_PASS_BEGIN(X86PreTileConfig, "tilepreconfig",
206 "Tile Register Pre-configure", false, false)
210
211void X86PreTileConfig::collectShapeInfo(MachineInstr &MI) {
212 auto RecordShape = [&](MachineInstr *MI, MachineBasicBlock *MBB) {
213 MIRef MIR(MI, MBB);
214 auto I = llvm::lower_bound(ShapeBBs[MBB], MIR);
215 if (I == ShapeBBs[MBB].end() || *I != MIR)
216 ShapeBBs[MBB].insert(I, MIR);
217 };
218
220 {MI.getOperand(1).getReg(), MI.getOperand(2).getReg()});
221 while (!WorkList.empty()) {
222 Register R = WorkList.pop_back_val();
223 MachineInstr *DefMI = MRI->getVRegDef(R);
224 assert(DefMI && "R must has one define instruction");
225 MachineBasicBlock *DefMBB = DefMI->getParent();
226 if (DefMI->isMoveImmediate() || !DefVisited.insert(DefMI).second)
227 continue;
228 if (DefMI->isPHI()) {
229 for (unsigned I = 1; I < DefMI->getNumOperands(); I += 2)
230 if (isLoopBackEdge(DefMBB, DefMI->getOperand(I + 1).getMBB()))
231 RecordShape(DefMI, DefMBB); // In this case, PHI is also a shape def.
232 else
233 WorkList.push_back(DefMI->getOperand(I).getReg());
234 } else {
235 RecordShape(DefMI, DefMBB);
236 }
237 }
238}
239
240bool X86PreTileConfig::runOnMachineFunction(MachineFunction &MF) {
242 const TargetInstrInfo *TII = ST.getInstrInfo();
243 const TargetRegisterInfo *TRI = ST.getRegisterInfo();
244 const TargetRegisterClass *RC = TRI->getRegClass(X86::TILERegClassID);
246
247 BitVector AMXRegs(TRI->getNumRegs());
248 for (unsigned I = 0; I < RC->getNumRegs(); I++)
249 AMXRegs.set(X86::TMM0 + I);
250
251 // Iterate MF to collect information.
252 MRI = &MF.getRegInfo();
253 MLI = &getAnalysis<MachineLoopInfo>();
254 SmallSet<MIRef, 8> CfgNeedInsert;
256 for (auto &MBB : MF) {
257 size_t Pos = 0;
258 for (auto &MI : MBB) {
259 ++Pos;
260 if (isAMXInstruction(MI)) {
261 // If there's call before the AMX, we need to reload tile config.
262 if (BBVisitedInfo[&MBB].LastCall)
263 CfgNeedInsert.insert(BBVisitedInfo[&MBB].LastCall);
264 else // Otherwise, we need tile config to live in this BB.
265 BBVisitedInfo[&MBB].NeedTileCfgLiveIn = true;
266 // Always record the first AMX in case there's shape def after it.
267 if (!BBVisitedInfo[&MBB].FirstAMX)
268 BBVisitedInfo[&MBB].FirstAMX = MIRef(&MI, &MBB, Pos);
269 } else if (MI.isCall() && isDestructiveCall(MI, AMXRegs)) {
270 // Record the call only if the callee clobbers all AMX registers.
271 BBVisitedInfo[&MBB].LastCall = MIRef(&MI, &MBB, Pos);
272 }
273 }
274 if (BBVisitedInfo[&MBB].NeedTileCfgLiveIn) {
275 if (&MBB == &MF.front())
276 CfgNeedInsert.insert(MIRef(&MBB));
277 else
278 CfgLiveInBBs.push_back(&MBB);
279 }
280 if (BBVisitedInfo[&MBB].FirstAMX || BBVisitedInfo[&MBB].HasAMXRegLiveIn)
281 for (auto *Succ : MBB.successors())
282 if (!isLoopBackEdge(Succ, &MBB))
283 BBVisitedInfo[Succ].HasAMXRegLiveIn = true;
284 }
285
286 // Update NeedTileCfgLiveIn for predecessors.
287 while (!CfgLiveInBBs.empty()) {
288 MachineBasicBlock *MBB = CfgLiveInBBs.pop_back_val();
289 for (auto *Pred : MBB->predecessors()) {
290 if (BBVisitedInfo[Pred].LastCall) {
291 CfgNeedInsert.insert(BBVisitedInfo[Pred].LastCall);
292 } else if (!BBVisitedInfo[Pred].NeedTileCfgLiveIn) {
293 BBVisitedInfo[Pred].NeedTileCfgLiveIn = true;
294 if (Pred == &MF.front())
295 CfgNeedInsert.insert(MIRef(Pred));
296 else
297 CfgLiveInBBs.push_back(Pred);
298 }
299 }
300 }
301
302 // There's no AMX instruction if we didn't find a tile config live in point.
303 if (CfgNeedInsert.empty())
304 return false;
305 X86FI->setHasVirtualTileReg(true);
306
307 // Avoid to insert ldtilecfg before any shape defs.
309 for (auto &I : ShapeBBs) {
310 // TODO: We can hoist shapes across BBs here.
311 if (BBVisitedInfo[I.first].HasAMXRegLiveIn) {
312 // We are not able to config tile registers since the shape to config
313 // is not defined yet. Emit error message and continue. The function
314 // would not config tile registers.
315 emitErrorMsg(MF);
316 return false;
317 }
318 if (BBVisitedInfo[I.first].FirstAMX &&
319 BBVisitedInfo[I.first].FirstAMX < I.second.back() &&
320 !hoistShapesInBB(I.first, I.second)) {
321 emitErrorMsg(MF);
322 return false;
323 }
324 WorkList.push_back(I.first);
325 }
326 while (!WorkList.empty()) {
327 MachineBasicBlock *MBB = WorkList.pop_back_val();
328 for (auto *Pred : MBB->predecessors()) {
329 if (!BBVisitedInfo[Pred].TileCfgForbidden && !isLoopBackEdge(MBB, Pred)) {
330 BBVisitedInfo[Pred].TileCfgForbidden = true;
331 WorkList.push_back(Pred);
332 }
333 }
334 }
335
336 DebugLoc DL;
337 SmallSet<MIRef, 8> VisitedOrInserted;
338 int SS = MF.getFrameInfo().CreateStackObject(
339 ST.getTileConfigSize(), ST.getTileConfigAlignment(), false);
340
341 // Try to insert for the tile config live in points.
342 for (const auto &I : CfgNeedInsert) {
343 SmallSet<MIRef, 8> InsertPoints;
344 SmallVector<MIRef, 8> WorkList({I});
345 while (!WorkList.empty()) {
346 MIRef I = WorkList.pop_back_val();
347 if (!VisitedOrInserted.count(I)) {
348 if (!BBVisitedInfo[I.MBB].TileCfgForbidden) {
349 // If the BB is all shapes reachable, stop sink and try to insert.
350 InsertPoints.insert(I);
351 } else {
352 // Avoid the BB to be multi visited.
353 VisitedOrInserted.insert(I);
354 // Sink the inserting point along the chain with NeedTileCfgLiveIn =
355 // true when MBB isn't all shapes reachable.
356 for (auto *Succ : I.MBB->successors())
357 if (BBVisitedInfo[Succ].NeedTileCfgLiveIn)
358 WorkList.push_back(MIRef(Succ));
359 }
360 }
361 }
362
363 // A given point might be forked due to shape conditions are not met.
364 for (MIRef I : InsertPoints) {
365 // Make sure we insert ldtilecfg after the last shape def in MBB.
366 if (ShapeBBs.count(I.MBB) && I < ShapeBBs[I.MBB].back())
367 I = ShapeBBs[I.MBB].back();
368 // There're chances the MBB is sunk more than once. Record it to avoid
369 // multi insert.
370 if (VisitedOrInserted.insert(I).second) {
371 auto II = I.MI ? I.MI->getIterator() : I.MBB->instr_begin();
372 addFrameReference(BuildMI(*I.MBB, ++II, DL, TII->get(X86::PLDTILECFGV)),
373 SS);
374 }
375 }
376 }
377
378 // Zero stack slot.
380 MachineInstr *MI = &*MBB.begin();
381 if (ST.hasAVX512()) {
382 Register Zmm = MRI->createVirtualRegister(&X86::VR512RegClass);
383 BuildMI(MBB, MI, DL, TII->get(X86::AVX512_512_SET0), Zmm);
384 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::VMOVUPSZmr)), SS)
385 .addReg(Zmm);
386 } else if (ST.hasAVX2()) {
387 Register Ymm = MRI->createVirtualRegister(&X86::VR256RegClass);
388 BuildMI(MBB, MI, DL, TII->get(X86::AVX_SET0), Ymm);
389 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::VMOVUPSYmr)), SS)
390 .addReg(Ymm);
391 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::VMOVUPSYmr)), SS, 32)
392 .addReg(Ymm);
393 } else {
394 assert(ST.hasSSE2() && "AMX should assume SSE2 enabled");
395 unsigned StoreOpc = ST.hasAVX() ? X86::VMOVUPSmr : X86::MOVUPSmr;
396 Register Xmm = MRI->createVirtualRegister(&X86::VR128RegClass);
397 BuildMI(MBB, MI, DL, TII->get(X86::V_SET0), Xmm);
398 addFrameReference(BuildMI(MBB, MI, DL, TII->get(StoreOpc)), SS).addReg(Xmm);
399 addFrameReference(BuildMI(MBB, MI, DL, TII->get(StoreOpc)), SS, 16)
400 .addReg(Xmm);
401 addFrameReference(BuildMI(MBB, MI, DL, TII->get(StoreOpc)), SS, 32)
402 .addReg(Xmm);
403 addFrameReference(BuildMI(MBB, MI, DL, TII->get(StoreOpc)), SS, 48)
404 .addReg(Xmm);
405 }
406 // Fill in the palette first.
407 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV8mi)), SS).addImm(1);
408
409 return true;
410}
411
413 return new X86PreTileConfig();
414}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static const Function * getParent(const Value *V)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
LLVMContext & Context
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Value * RHS
Tile Register Pre configure
tilepreconfig
static void emitErrorMsg(MachineFunction &MF)
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
void setPreservesAll()
Set by analyses that do not transform their input at all.
void clearBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
clearBitsInMask - Clear any bits in this vector that are set in Mask.
Definition: BitVector.h:706
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:181
A debug info location.
Definition: DebugLoc.h:33
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:207
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
iterator_range< succ_iterator > successors()
iterator_range< pred_iterator > predecessors()
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineModuleInfo & getMMI() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:313
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:519
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition: MachineInstr.h:947
bool isPHI() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
bool isLoopHeader(const MachineBasicBlock *BB) const
True if the block is a loop header node.
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
const Module * getModule() const
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:262
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
virtual void releaseMemory()
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
Definition: Pass.cpp:102
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
bool empty() const
Definition: SmallSet.h:157
void clear()
Definition: SmallSet.h:216
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:177
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
bool empty() const
Definition: SmallVector.h:94
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getNumRegs() const
Return the number of registers in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ SS
Definition: X86.h:202
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:361
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool operator!=(uint64_t V1, const APInt &V2)
Definition: APInt.h:2040
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
bool operator==(const AddressRangeValuePair &LHS, const AddressRangeValuePair &RHS)
bool operator>(int64_t V1, const APSInt &V2)
Definition: APSInt.h:362
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1923
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1762
FunctionPass * createX86PreTileConfigPass()
Return a pass that insert pseudo tile config instruction.
Definition: BitVector.h:851