LLVM  9.0.0svn
X86AsmParser.cpp
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1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "MCTargetDesc/X86MCExpr.h"
13 #include "X86AsmParserCommon.h"
14 #include "X86Operand.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/SmallString.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/MC/MCSection.h"
30 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSymbol.h"
33 #include "llvm/Support/SourceMgr.h"
36 #include <algorithm>
37 #include <memory>
38 
39 using namespace llvm;
40 
41 static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
42  if (Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
43  ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
44  return true;
45  }
46  return false;
47 }
48 
49 namespace {
50 
51 static const char OpPrecedence[] = {
52  0, // IC_OR
53  1, // IC_XOR
54  2, // IC_AND
55  3, // IC_LSHIFT
56  3, // IC_RSHIFT
57  4, // IC_PLUS
58  4, // IC_MINUS
59  5, // IC_MULTIPLY
60  5, // IC_DIVIDE
61  5, // IC_MOD
62  6, // IC_NOT
63  7, // IC_NEG
64  8, // IC_RPAREN
65  9, // IC_LPAREN
66  0, // IC_IMM
67  0 // IC_REGISTER
68 };
69 
70 class X86AsmParser : public MCTargetAsmParser {
71  ParseInstructionInfo *InstInfo;
72  bool Code16GCC;
73 
74  enum VEXEncoding {
75  VEXEncoding_Default,
76  VEXEncoding_VEX2,
77  VEXEncoding_VEX3,
78  VEXEncoding_EVEX,
79  };
80 
81  VEXEncoding ForcedVEXEncoding = VEXEncoding_Default;
82 
83 private:
84  SMLoc consumeToken() {
85  MCAsmParser &Parser = getParser();
86  SMLoc Result = Parser.getTok().getLoc();
87  Parser.Lex();
88  return Result;
89  }
90 
91  X86TargetStreamer &getTargetStreamer() {
92  assert(getParser().getStreamer().getTargetStreamer() &&
93  "do not have a target streamer");
94  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
95  return static_cast<X86TargetStreamer &>(TS);
96  }
97 
98  unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst,
99  uint64_t &ErrorInfo, FeatureBitset &MissingFeatures,
100  bool matchingInlineAsm, unsigned VariantID = 0) {
101  // In Code16GCC mode, match as 32-bit.
102  if (Code16GCC)
103  SwitchMode(X86::Mode32Bit);
104  unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo,
105  MissingFeatures, matchingInlineAsm,
106  VariantID);
107  if (Code16GCC)
108  SwitchMode(X86::Mode16Bit);
109  return rv;
110  }
111 
112  enum InfixCalculatorTok {
113  IC_OR = 0,
114  IC_XOR,
115  IC_AND,
116  IC_LSHIFT,
117  IC_RSHIFT,
118  IC_PLUS,
119  IC_MINUS,
120  IC_MULTIPLY,
121  IC_DIVIDE,
122  IC_MOD,
123  IC_NOT,
124  IC_NEG,
125  IC_RPAREN,
126  IC_LPAREN,
127  IC_IMM,
128  IC_REGISTER
129  };
130 
131  enum IntelOperatorKind {
132  IOK_INVALID = 0,
133  IOK_LENGTH,
134  IOK_SIZE,
135  IOK_TYPE,
136  IOK_OFFSET
137  };
138 
139  class InfixCalculator {
140  typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
141  SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
142  SmallVector<ICToken, 4> PostfixStack;
143 
144  bool isUnaryOperator(const InfixCalculatorTok Op) {
145  return Op == IC_NEG || Op == IC_NOT;
146  }
147 
148  public:
149  int64_t popOperand() {
150  assert (!PostfixStack.empty() && "Poped an empty stack!");
151  ICToken Op = PostfixStack.pop_back_val();
152  if (!(Op.first == IC_IMM || Op.first == IC_REGISTER))
153  return -1; // The invalid Scale value will be caught later by checkScale
154  return Op.second;
155  }
156  void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
157  assert ((Op == IC_IMM || Op == IC_REGISTER) &&
158  "Unexpected operand!");
159  PostfixStack.push_back(std::make_pair(Op, Val));
160  }
161 
162  void popOperator() { InfixOperatorStack.pop_back(); }
163  void pushOperator(InfixCalculatorTok Op) {
164  // Push the new operator if the stack is empty.
165  if (InfixOperatorStack.empty()) {
166  InfixOperatorStack.push_back(Op);
167  return;
168  }
169 
170  // Push the new operator if it has a higher precedence than the operator
171  // on the top of the stack or the operator on the top of the stack is a
172  // left parentheses.
173  unsigned Idx = InfixOperatorStack.size() - 1;
174  InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
175  if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
176  InfixOperatorStack.push_back(Op);
177  return;
178  }
179 
180  // The operator on the top of the stack has higher precedence than the
181  // new operator.
182  unsigned ParenCount = 0;
183  while (1) {
184  // Nothing to process.
185  if (InfixOperatorStack.empty())
186  break;
187 
188  Idx = InfixOperatorStack.size() - 1;
189  StackOp = InfixOperatorStack[Idx];
190  if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
191  break;
192 
193  // If we have an even parentheses count and we see a left parentheses,
194  // then stop processing.
195  if (!ParenCount && StackOp == IC_LPAREN)
196  break;
197 
198  if (StackOp == IC_RPAREN) {
199  ++ParenCount;
200  InfixOperatorStack.pop_back();
201  } else if (StackOp == IC_LPAREN) {
202  --ParenCount;
203  InfixOperatorStack.pop_back();
204  } else {
205  InfixOperatorStack.pop_back();
206  PostfixStack.push_back(std::make_pair(StackOp, 0));
207  }
208  }
209  // Push the new operator.
210  InfixOperatorStack.push_back(Op);
211  }
212 
213  int64_t execute() {
214  // Push any remaining operators onto the postfix stack.
215  while (!InfixOperatorStack.empty()) {
216  InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
217  if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
218  PostfixStack.push_back(std::make_pair(StackOp, 0));
219  }
220 
221  if (PostfixStack.empty())
222  return 0;
223 
224  SmallVector<ICToken, 16> OperandStack;
225  for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
226  ICToken Op = PostfixStack[i];
227  if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
228  OperandStack.push_back(Op);
229  } else if (isUnaryOperator(Op.first)) {
230  assert (OperandStack.size() > 0 && "Too few operands.");
231  ICToken Operand = OperandStack.pop_back_val();
232  assert (Operand.first == IC_IMM &&
233  "Unary operation with a register!");
234  switch (Op.first) {
235  default:
236  report_fatal_error("Unexpected operator!");
237  break;
238  case IC_NEG:
239  OperandStack.push_back(std::make_pair(IC_IMM, -Operand.second));
240  break;
241  case IC_NOT:
242  OperandStack.push_back(std::make_pair(IC_IMM, ~Operand.second));
243  break;
244  }
245  } else {
246  assert (OperandStack.size() > 1 && "Too few operands.");
247  int64_t Val;
248  ICToken Op2 = OperandStack.pop_back_val();
249  ICToken Op1 = OperandStack.pop_back_val();
250  switch (Op.first) {
251  default:
252  report_fatal_error("Unexpected operator!");
253  break;
254  case IC_PLUS:
255  Val = Op1.second + Op2.second;
256  OperandStack.push_back(std::make_pair(IC_IMM, Val));
257  break;
258  case IC_MINUS:
259  Val = Op1.second - Op2.second;
260  OperandStack.push_back(std::make_pair(IC_IMM, Val));
261  break;
262  case IC_MULTIPLY:
263  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
264  "Multiply operation with an immediate and a register!");
265  Val = Op1.second * Op2.second;
266  OperandStack.push_back(std::make_pair(IC_IMM, Val));
267  break;
268  case IC_DIVIDE:
269  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
270  "Divide operation with an immediate and a register!");
271  assert (Op2.second != 0 && "Division by zero!");
272  Val = Op1.second / Op2.second;
273  OperandStack.push_back(std::make_pair(IC_IMM, Val));
274  break;
275  case IC_MOD:
276  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
277  "Modulo operation with an immediate and a register!");
278  Val = Op1.second % Op2.second;
279  OperandStack.push_back(std::make_pair(IC_IMM, Val));
280  break;
281  case IC_OR:
282  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
283  "Or operation with an immediate and a register!");
284  Val = Op1.second | Op2.second;
285  OperandStack.push_back(std::make_pair(IC_IMM, Val));
286  break;
287  case IC_XOR:
288  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
289  "Xor operation with an immediate and a register!");
290  Val = Op1.second ^ Op2.second;
291  OperandStack.push_back(std::make_pair(IC_IMM, Val));
292  break;
293  case IC_AND:
294  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
295  "And operation with an immediate and a register!");
296  Val = Op1.second & Op2.second;
297  OperandStack.push_back(std::make_pair(IC_IMM, Val));
298  break;
299  case IC_LSHIFT:
300  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
301  "Left shift operation with an immediate and a register!");
302  Val = Op1.second << Op2.second;
303  OperandStack.push_back(std::make_pair(IC_IMM, Val));
304  break;
305  case IC_RSHIFT:
306  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
307  "Right shift operation with an immediate and a register!");
308  Val = Op1.second >> Op2.second;
309  OperandStack.push_back(std::make_pair(IC_IMM, Val));
310  break;
311  }
312  }
313  }
314  assert (OperandStack.size() == 1 && "Expected a single result.");
315  return OperandStack.pop_back_val().second;
316  }
317  };
318 
319  enum IntelExprState {
320  IES_INIT,
321  IES_OR,
322  IES_XOR,
323  IES_AND,
324  IES_LSHIFT,
325  IES_RSHIFT,
326  IES_PLUS,
327  IES_MINUS,
328  IES_NOT,
329  IES_MULTIPLY,
330  IES_DIVIDE,
331  IES_MOD,
332  IES_LBRAC,
333  IES_RBRAC,
334  IES_LPAREN,
335  IES_RPAREN,
336  IES_REGISTER,
337  IES_INTEGER,
338  IES_IDENTIFIER,
339  IES_ERROR
340  };
341 
342  class IntelExprStateMachine {
343  IntelExprState State, PrevState;
344  unsigned BaseReg, IndexReg, TmpReg, Scale;
345  int64_t Imm;
346  const MCExpr *Sym;
347  StringRef SymName;
348  InfixCalculator IC;
350  short BracCount;
351  bool MemExpr;
352 
353  public:
354  IntelExprStateMachine()
355  : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),
356  TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0),
357  MemExpr(false) {}
358 
359  void addImm(int64_t imm) { Imm += imm; }
360  short getBracCount() { return BracCount; }
361  bool isMemExpr() { return MemExpr; }
362  unsigned getBaseReg() { return BaseReg; }
363  unsigned getIndexReg() { return IndexReg; }
364  unsigned getScale() { return Scale; }
365  const MCExpr *getSym() { return Sym; }
366  StringRef getSymName() { return SymName; }
367  int64_t getImm() { return Imm + IC.execute(); }
368  bool isValidEndState() {
369  return State == IES_RBRAC || State == IES_INTEGER;
370  }
371  bool hadError() { return State == IES_ERROR; }
372  InlineAsmIdentifierInfo &getIdentifierInfo() { return Info; }
373 
374  void onOr() {
375  IntelExprState CurrState = State;
376  switch (State) {
377  default:
378  State = IES_ERROR;
379  break;
380  case IES_INTEGER:
381  case IES_RPAREN:
382  case IES_REGISTER:
383  State = IES_OR;
384  IC.pushOperator(IC_OR);
385  break;
386  }
387  PrevState = CurrState;
388  }
389  void onXor() {
390  IntelExprState CurrState = State;
391  switch (State) {
392  default:
393  State = IES_ERROR;
394  break;
395  case IES_INTEGER:
396  case IES_RPAREN:
397  case IES_REGISTER:
398  State = IES_XOR;
399  IC.pushOperator(IC_XOR);
400  break;
401  }
402  PrevState = CurrState;
403  }
404  void onAnd() {
405  IntelExprState CurrState = State;
406  switch (State) {
407  default:
408  State = IES_ERROR;
409  break;
410  case IES_INTEGER:
411  case IES_RPAREN:
412  case IES_REGISTER:
413  State = IES_AND;
414  IC.pushOperator(IC_AND);
415  break;
416  }
417  PrevState = CurrState;
418  }
419  void onLShift() {
420  IntelExprState CurrState = State;
421  switch (State) {
422  default:
423  State = IES_ERROR;
424  break;
425  case IES_INTEGER:
426  case IES_RPAREN:
427  case IES_REGISTER:
428  State = IES_LSHIFT;
429  IC.pushOperator(IC_LSHIFT);
430  break;
431  }
432  PrevState = CurrState;
433  }
434  void onRShift() {
435  IntelExprState CurrState = State;
436  switch (State) {
437  default:
438  State = IES_ERROR;
439  break;
440  case IES_INTEGER:
441  case IES_RPAREN:
442  case IES_REGISTER:
443  State = IES_RSHIFT;
444  IC.pushOperator(IC_RSHIFT);
445  break;
446  }
447  PrevState = CurrState;
448  }
449  bool onPlus(StringRef &ErrMsg) {
450  IntelExprState CurrState = State;
451  switch (State) {
452  default:
453  State = IES_ERROR;
454  break;
455  case IES_INTEGER:
456  case IES_RPAREN:
457  case IES_REGISTER:
458  State = IES_PLUS;
459  IC.pushOperator(IC_PLUS);
460  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
461  // If we already have a BaseReg, then assume this is the IndexReg with
462  // no explicit scale.
463  if (!BaseReg) {
464  BaseReg = TmpReg;
465  } else {
466  if (IndexReg) {
467  ErrMsg = "BaseReg/IndexReg already set!";
468  return true;
469  }
470  IndexReg = TmpReg;
471  Scale = 0;
472  }
473  }
474  break;
475  }
476  PrevState = CurrState;
477  return false;
478  }
479  bool onMinus(StringRef &ErrMsg) {
480  IntelExprState CurrState = State;
481  switch (State) {
482  default:
483  State = IES_ERROR;
484  break;
485  case IES_OR:
486  case IES_XOR:
487  case IES_AND:
488  case IES_LSHIFT:
489  case IES_RSHIFT:
490  case IES_PLUS:
491  case IES_NOT:
492  case IES_MULTIPLY:
493  case IES_DIVIDE:
494  case IES_MOD:
495  case IES_LPAREN:
496  case IES_RPAREN:
497  case IES_LBRAC:
498  case IES_RBRAC:
499  case IES_INTEGER:
500  case IES_REGISTER:
501  case IES_INIT:
502  State = IES_MINUS;
503  // push minus operator if it is not a negate operator
504  if (CurrState == IES_REGISTER || CurrState == IES_RPAREN ||
505  CurrState == IES_INTEGER || CurrState == IES_RBRAC)
506  IC.pushOperator(IC_MINUS);
507  else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
508  // We have negate operator for Scale: it's illegal
509  ErrMsg = "Scale can't be negative";
510  return true;
511  } else
512  IC.pushOperator(IC_NEG);
513  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
514  // If we already have a BaseReg, then assume this is the IndexReg with
515  // no explicit scale.
516  if (!BaseReg) {
517  BaseReg = TmpReg;
518  } else {
519  if (IndexReg) {
520  ErrMsg = "BaseReg/IndexReg already set!";
521  return true;
522  }
523  IndexReg = TmpReg;
524  Scale = 0;
525  }
526  }
527  break;
528  }
529  PrevState = CurrState;
530  return false;
531  }
532  void onNot() {
533  IntelExprState CurrState = State;
534  switch (State) {
535  default:
536  State = IES_ERROR;
537  break;
538  case IES_OR:
539  case IES_XOR:
540  case IES_AND:
541  case IES_LSHIFT:
542  case IES_RSHIFT:
543  case IES_PLUS:
544  case IES_MINUS:
545  case IES_NOT:
546  case IES_MULTIPLY:
547  case IES_DIVIDE:
548  case IES_MOD:
549  case IES_LPAREN:
550  case IES_LBRAC:
551  case IES_INIT:
552  State = IES_NOT;
553  IC.pushOperator(IC_NOT);
554  break;
555  }
556  PrevState = CurrState;
557  }
558 
559  bool onRegister(unsigned Reg, StringRef &ErrMsg) {
560  IntelExprState CurrState = State;
561  switch (State) {
562  default:
563  State = IES_ERROR;
564  break;
565  case IES_PLUS:
566  case IES_LPAREN:
567  case IES_LBRAC:
568  State = IES_REGISTER;
569  TmpReg = Reg;
570  IC.pushOperand(IC_REGISTER);
571  break;
572  case IES_MULTIPLY:
573  // Index Register - Scale * Register
574  if (PrevState == IES_INTEGER) {
575  if (IndexReg) {
576  ErrMsg = "BaseReg/IndexReg already set!";
577  return true;
578  }
579  State = IES_REGISTER;
580  IndexReg = Reg;
581  // Get the scale and replace the 'Scale * Register' with '0'.
582  Scale = IC.popOperand();
583  if (checkScale(Scale, ErrMsg))
584  return true;
585  IC.pushOperand(IC_IMM);
586  IC.popOperator();
587  } else {
588  State = IES_ERROR;
589  }
590  break;
591  }
592  PrevState = CurrState;
593  return false;
594  }
595  bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName,
596  const InlineAsmIdentifierInfo &IDInfo,
597  bool ParsingInlineAsm, StringRef &ErrMsg) {
598  // InlineAsm: Treat an enum value as an integer
599  if (ParsingInlineAsm)
601  return onInteger(IDInfo.Enum.EnumVal, ErrMsg);
602  // Treat a symbolic constant like an integer
603  if (auto *CE = dyn_cast<MCConstantExpr>(SymRef))
604  return onInteger(CE->getValue(), ErrMsg);
605  PrevState = State;
606  bool HasSymbol = Sym != nullptr;
607  switch (State) {
608  default:
609  State = IES_ERROR;
610  break;
611  case IES_PLUS:
612  case IES_MINUS:
613  case IES_NOT:
614  case IES_INIT:
615  case IES_LBRAC:
616  MemExpr = true;
617  State = IES_INTEGER;
618  Sym = SymRef;
619  SymName = SymRefName;
620  IC.pushOperand(IC_IMM);
621  if (ParsingInlineAsm)
622  Info = IDInfo;
623  break;
624  }
625  if (HasSymbol)
626  ErrMsg = "cannot use more than one symbol in memory operand";
627  return HasSymbol;
628  }
629  bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
630  IntelExprState CurrState = State;
631  switch (State) {
632  default:
633  State = IES_ERROR;
634  break;
635  case IES_PLUS:
636  case IES_MINUS:
637  case IES_NOT:
638  case IES_OR:
639  case IES_XOR:
640  case IES_AND:
641  case IES_LSHIFT:
642  case IES_RSHIFT:
643  case IES_DIVIDE:
644  case IES_MOD:
645  case IES_MULTIPLY:
646  case IES_LPAREN:
647  case IES_INIT:
648  case IES_LBRAC:
649  State = IES_INTEGER;
650  if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
651  // Index Register - Register * Scale
652  if (IndexReg) {
653  ErrMsg = "BaseReg/IndexReg already set!";
654  return true;
655  }
656  IndexReg = TmpReg;
657  Scale = TmpInt;
658  if (checkScale(Scale, ErrMsg))
659  return true;
660  // Get the scale and replace the 'Register * Scale' with '0'.
661  IC.popOperator();
662  } else {
663  IC.pushOperand(IC_IMM, TmpInt);
664  }
665  break;
666  }
667  PrevState = CurrState;
668  return false;
669  }
670  void onStar() {
671  PrevState = State;
672  switch (State) {
673  default:
674  State = IES_ERROR;
675  break;
676  case IES_INTEGER:
677  case IES_REGISTER:
678  case IES_RPAREN:
679  State = IES_MULTIPLY;
680  IC.pushOperator(IC_MULTIPLY);
681  break;
682  }
683  }
684  void onDivide() {
685  PrevState = State;
686  switch (State) {
687  default:
688  State = IES_ERROR;
689  break;
690  case IES_INTEGER:
691  case IES_RPAREN:
692  State = IES_DIVIDE;
693  IC.pushOperator(IC_DIVIDE);
694  break;
695  }
696  }
697  void onMod() {
698  PrevState = State;
699  switch (State) {
700  default:
701  State = IES_ERROR;
702  break;
703  case IES_INTEGER:
704  case IES_RPAREN:
705  State = IES_MOD;
706  IC.pushOperator(IC_MOD);
707  break;
708  }
709  }
710  bool onLBrac() {
711  if (BracCount)
712  return true;
713  PrevState = State;
714  switch (State) {
715  default:
716  State = IES_ERROR;
717  break;
718  case IES_RBRAC:
719  case IES_INTEGER:
720  case IES_RPAREN:
721  State = IES_PLUS;
722  IC.pushOperator(IC_PLUS);
723  break;
724  case IES_INIT:
725  assert(!BracCount && "BracCount should be zero on parsing's start");
726  State = IES_LBRAC;
727  break;
728  }
729  MemExpr = true;
730  BracCount++;
731  return false;
732  }
733  bool onRBrac() {
734  IntelExprState CurrState = State;
735  switch (State) {
736  default:
737  State = IES_ERROR;
738  break;
739  case IES_INTEGER:
740  case IES_REGISTER:
741  case IES_RPAREN:
742  if (BracCount-- != 1)
743  return true;
744  State = IES_RBRAC;
745  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
746  // If we already have a BaseReg, then assume this is the IndexReg with
747  // no explicit scale.
748  if (!BaseReg) {
749  BaseReg = TmpReg;
750  } else {
751  assert (!IndexReg && "BaseReg/IndexReg already set!");
752  IndexReg = TmpReg;
753  Scale = 0;
754  }
755  }
756  break;
757  }
758  PrevState = CurrState;
759  return false;
760  }
761  void onLParen() {
762  IntelExprState CurrState = State;
763  switch (State) {
764  default:
765  State = IES_ERROR;
766  break;
767  case IES_PLUS:
768  case IES_MINUS:
769  case IES_NOT:
770  case IES_OR:
771  case IES_XOR:
772  case IES_AND:
773  case IES_LSHIFT:
774  case IES_RSHIFT:
775  case IES_MULTIPLY:
776  case IES_DIVIDE:
777  case IES_MOD:
778  case IES_LPAREN:
779  case IES_INIT:
780  case IES_LBRAC:
781  State = IES_LPAREN;
782  IC.pushOperator(IC_LPAREN);
783  break;
784  }
785  PrevState = CurrState;
786  }
787  void onRParen() {
788  PrevState = State;
789  switch (State) {
790  default:
791  State = IES_ERROR;
792  break;
793  case IES_INTEGER:
794  case IES_REGISTER:
795  case IES_RPAREN:
796  State = IES_RPAREN;
797  IC.pushOperator(IC_RPAREN);
798  break;
799  }
800  }
801  };
802 
803  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
804  bool MatchingInlineAsm = false) {
805  MCAsmParser &Parser = getParser();
806  if (MatchingInlineAsm) {
807  if (!getLexer().isAtStartOfStatement())
808  Parser.eatToEndOfStatement();
809  return false;
810  }
811  return Parser.Error(L, Msg, Range);
812  }
813 
814  std::nullptr_t ErrorOperand(SMLoc Loc, StringRef Msg, SMRange R = SMRange()) {
815  Error(Loc, Msg, R);
816  return nullptr;
817  }
818 
819  std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
820  std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc);
821  bool IsSIReg(unsigned Reg);
822  unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
823  void
824  AddDefaultSrcDestOperands(OperandVector &Operands,
825  std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
826  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
827  bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
828  OperandVector &FinalOperands);
829  std::unique_ptr<X86Operand> ParseOperand();
830  std::unique_ptr<X86Operand> ParseATTOperand();
831  std::unique_ptr<X86Operand> ParseIntelOperand();
832  std::unique_ptr<X86Operand> ParseIntelOffsetOfOperator();
833  bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End);
834  unsigned IdentifyIntelInlineAsmOperator(StringRef Name);
835  unsigned ParseIntelInlineAsmOperator(unsigned OpKind);
836  std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start);
837  bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM);
838  void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start,
839  SMLoc End);
840  bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
841  bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier,
843  bool IsUnevaluatedOperand, SMLoc &End);
844 
845  std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg,
846  const MCExpr *&Disp,
847  const SMLoc &StartLoc,
848  SMLoc &EndLoc);
849 
850  bool ParseIntelMemoryOperandSize(unsigned &Size);
851  std::unique_ptr<X86Operand>
852  CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
853  unsigned IndexReg, unsigned Scale, SMLoc Start,
854  SMLoc End, unsigned Size, StringRef Identifier,
855  const InlineAsmIdentifierInfo &Info);
856 
857  bool parseDirectiveEven(SMLoc L);
858  bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
859 
860  /// CodeView FPO data directives.
861  bool parseDirectiveFPOProc(SMLoc L);
862  bool parseDirectiveFPOSetFrame(SMLoc L);
863  bool parseDirectiveFPOPushReg(SMLoc L);
864  bool parseDirectiveFPOStackAlloc(SMLoc L);
865  bool parseDirectiveFPOStackAlign(SMLoc L);
866  bool parseDirectiveFPOEndPrologue(SMLoc L);
867  bool parseDirectiveFPOEndProc(SMLoc L);
868  bool parseDirectiveFPOData(SMLoc L);
869 
870  unsigned checkTargetMatchPredicate(MCInst &Inst) override;
871 
872  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
873  bool processInstruction(MCInst &Inst, const OperandVector &Ops);
874 
875  /// Wrapper around MCStreamer::EmitInstruction(). Possibly adds
876  /// instrumentation around Inst.
877  void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
878 
879  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
880  OperandVector &Operands, MCStreamer &Out,
881  uint64_t &ErrorInfo,
882  bool MatchingInlineAsm) override;
883 
884  void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
885  MCStreamer &Out, bool MatchingInlineAsm);
886 
887  bool ErrorMissingFeature(SMLoc IDLoc, const FeatureBitset &MissingFeatures,
888  bool MatchingInlineAsm);
889 
890  bool MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
891  OperandVector &Operands, MCStreamer &Out,
892  uint64_t &ErrorInfo,
893  bool MatchingInlineAsm);
894 
895  bool MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
896  OperandVector &Operands, MCStreamer &Out,
897  uint64_t &ErrorInfo,
898  bool MatchingInlineAsm);
899 
900  bool OmitRegisterFromClobberLists(unsigned RegNo) override;
901 
902  /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
903  /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
904  /// return false if no parsing errors occurred, true otherwise.
905  bool HandleAVX512Operand(OperandVector &Operands,
906  const MCParsedAsmOperand &Op);
907 
908  bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
909 
910  bool is64BitMode() const {
911  // FIXME: Can tablegen auto-generate this?
912  return getSTI().getFeatureBits()[X86::Mode64Bit];
913  }
914  bool is32BitMode() const {
915  // FIXME: Can tablegen auto-generate this?
916  return getSTI().getFeatureBits()[X86::Mode32Bit];
917  }
918  bool is16BitMode() const {
919  // FIXME: Can tablegen auto-generate this?
920  return getSTI().getFeatureBits()[X86::Mode16Bit];
921  }
922  void SwitchMode(unsigned mode) {
923  MCSubtargetInfo &STI = copySTI();
924  FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
925  FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
926  FeatureBitset FB = ComputeAvailableFeatures(
927  STI.ToggleFeature(OldMode.flip(mode)));
928  setAvailableFeatures(FB);
929 
930  assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
931  }
932 
933  unsigned getPointerWidth() {
934  if (is16BitMode()) return 16;
935  if (is32BitMode()) return 32;
936  if (is64BitMode()) return 64;
937  llvm_unreachable("invalid mode");
938  }
939 
940  bool isParsingIntelSyntax() {
941  return getParser().getAssemblerDialect();
942  }
943 
944  /// @name Auto-generated Matcher Functions
945  /// {
946 
947 #define GET_ASSEMBLER_HEADER
948 #include "X86GenAsmMatcher.inc"
949 
950  /// }
951 
952 public:
953  enum X86MatchResultTy {
954  Match_Unsupported = FIRST_TARGET_MATCH_RESULT_TY,
955  };
956 
957  X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
958  const MCInstrInfo &mii, const MCTargetOptions &Options)
959  : MCTargetAsmParser(Options, sti, mii), InstInfo(nullptr),
960  Code16GCC(false) {
961 
962  Parser.addAliasForDirective(".word", ".2byte");
963 
964  // Initialize the set of available features.
965  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
966  }
967 
968  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
969 
970  bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) override;
971 
972  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
973  SMLoc NameLoc, OperandVector &Operands) override;
974 
975  bool ParseDirective(AsmToken DirectiveID) override;
976 };
977 } // end anonymous namespace
978 
979 /// @name Auto-generated Match Functions
980 /// {
981 
982 static unsigned MatchRegisterName(StringRef Name);
983 
984 /// }
985 
986 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,
987  unsigned Scale, bool Is64BitMode,
988  StringRef &ErrMsg) {
989  // If we have both a base register and an index register make sure they are
990  // both 64-bit or 32-bit registers.
991  // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
992 
993  if (BaseReg != 0 &&
994  !(BaseReg == X86::RIP || BaseReg == X86::EIP ||
995  X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) ||
996  X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) ||
997  X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg))) {
998  ErrMsg = "invalid base+index expression";
999  return true;
1000  }
1001 
1002  if (IndexReg != 0 &&
1003  !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||
1004  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1005  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1006  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1007  X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
1008  X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
1009  X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg))) {
1010  ErrMsg = "invalid base+index expression";
1011  return true;
1012  }
1013 
1014  if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||
1015  IndexReg == X86::EIP || IndexReg == X86::RIP ||
1016  IndexReg == X86::ESP || IndexReg == X86::RSP) {
1017  ErrMsg = "invalid base+index expression";
1018  return true;
1019  }
1020 
1021  // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
1022  // and then only in non-64-bit modes.
1023  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
1024  (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&
1025  BaseReg != X86::SI && BaseReg != X86::DI))) {
1026  ErrMsg = "invalid 16-bit base register";
1027  return true;
1028  }
1029 
1030  if (BaseReg == 0 &&
1031  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
1032  ErrMsg = "16-bit memory operand may not include only index register";
1033  return true;
1034  }
1035 
1036  if (BaseReg != 0 && IndexReg != 0) {
1037  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
1038  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1039  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1040  IndexReg == X86::EIZ)) {
1041  ErrMsg = "base register is 64-bit, but index register is not";
1042  return true;
1043  }
1044  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
1045  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1046  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1047  IndexReg == X86::RIZ)) {
1048  ErrMsg = "base register is 32-bit, but index register is not";
1049  return true;
1050  }
1051  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
1052  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1053  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
1054  ErrMsg = "base register is 16-bit, but index register is not";
1055  return true;
1056  }
1057  if ((BaseReg != X86::BX && BaseReg != X86::BP) ||
1058  (IndexReg != X86::SI && IndexReg != X86::DI)) {
1059  ErrMsg = "invalid 16-bit base/index register combination";
1060  return true;
1061  }
1062  }
1063  }
1064 
1065  // RIP/EIP-relative addressing is only supported in 64-bit mode.
1066  if (!Is64BitMode && BaseReg != 0 &&
1067  (BaseReg == X86::RIP || BaseReg == X86::EIP)) {
1068  ErrMsg = "IP-relative addressing requires 64-bit mode";
1069  return true;
1070  }
1071 
1072  return checkScale(Scale, ErrMsg);
1073 }
1074 
1075 bool X86AsmParser::ParseRegister(unsigned &RegNo,
1076  SMLoc &StartLoc, SMLoc &EndLoc) {
1077  MCAsmParser &Parser = getParser();
1078  RegNo = 0;
1079  const AsmToken &PercentTok = Parser.getTok();
1080  StartLoc = PercentTok.getLoc();
1081 
1082  // If we encounter a %, ignore it. This code handles registers with and
1083  // without the prefix, unprefixed registers can occur in cfi directives.
1084  if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
1085  Parser.Lex(); // Eat percent token.
1086 
1087  const AsmToken &Tok = Parser.getTok();
1088  EndLoc = Tok.getEndLoc();
1089 
1090  if (Tok.isNot(AsmToken::Identifier)) {
1091  if (isParsingIntelSyntax()) return true;
1092  return Error(StartLoc, "invalid register name",
1093  SMRange(StartLoc, EndLoc));
1094  }
1095 
1096  RegNo = MatchRegisterName(Tok.getString());
1097 
1098  // If the match failed, try the register name as lowercase.
1099  if (RegNo == 0)
1100  RegNo = MatchRegisterName(Tok.getString().lower());
1101 
1102  // The "flags" register cannot be referenced directly.
1103  // Treat it as an identifier instead.
1104  if (isParsingInlineAsm() && isParsingIntelSyntax() && RegNo == X86::EFLAGS)
1105  RegNo = 0;
1106 
1107  if (!is64BitMode()) {
1108  // FIXME: This should be done using Requires<Not64BitMode> and
1109  // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1110  // checked.
1111  // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
1112  // REX prefix.
1113  if (RegNo == X86::RIZ || RegNo == X86::RIP ||
1114  X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
1116  X86II::isX86_64ExtendedReg(RegNo)) {
1117  StringRef RegName = Tok.getString();
1118  Parser.Lex(); // Eat register name.
1119  return Error(StartLoc,
1120  "register %" + RegName + " is only available in 64-bit mode",
1121  SMRange(StartLoc, EndLoc));
1122  }
1123  }
1124 
1125  // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1126  if (RegNo == X86::ST0) {
1127  Parser.Lex(); // Eat 'st'
1128 
1129  // Check to see if we have '(4)' after %st.
1130  if (getLexer().isNot(AsmToken::LParen))
1131  return false;
1132  // Lex the paren.
1133  getParser().Lex();
1134 
1135  const AsmToken &IntTok = Parser.getTok();
1136  if (IntTok.isNot(AsmToken::Integer))
1137  return Error(IntTok.getLoc(), "expected stack index");
1138  switch (IntTok.getIntVal()) {
1139  case 0: RegNo = X86::ST0; break;
1140  case 1: RegNo = X86::ST1; break;
1141  case 2: RegNo = X86::ST2; break;
1142  case 3: RegNo = X86::ST3; break;
1143  case 4: RegNo = X86::ST4; break;
1144  case 5: RegNo = X86::ST5; break;
1145  case 6: RegNo = X86::ST6; break;
1146  case 7: RegNo = X86::ST7; break;
1147  default: return Error(IntTok.getLoc(), "invalid stack index");
1148  }
1149 
1150  if (getParser().Lex().isNot(AsmToken::RParen))
1151  return Error(Parser.getTok().getLoc(), "expected ')'");
1152 
1153  EndLoc = Parser.getTok().getEndLoc();
1154  Parser.Lex(); // Eat ')'
1155  return false;
1156  }
1157 
1158  EndLoc = Parser.getTok().getEndLoc();
1159 
1160  // If this is "db[0-15]", match it as an alias
1161  // for dr[0-15].
1162  if (RegNo == 0 && Tok.getString().startswith("db")) {
1163  if (Tok.getString().size() == 3) {
1164  switch (Tok.getString()[2]) {
1165  case '0': RegNo = X86::DR0; break;
1166  case '1': RegNo = X86::DR1; break;
1167  case '2': RegNo = X86::DR2; break;
1168  case '3': RegNo = X86::DR3; break;
1169  case '4': RegNo = X86::DR4; break;
1170  case '5': RegNo = X86::DR5; break;
1171  case '6': RegNo = X86::DR6; break;
1172  case '7': RegNo = X86::DR7; break;
1173  case '8': RegNo = X86::DR8; break;
1174  case '9': RegNo = X86::DR9; break;
1175  }
1176  } else if (Tok.getString().size() == 4 && Tok.getString()[2] == '1') {
1177  switch (Tok.getString()[3]) {
1178  case '0': RegNo = X86::DR10; break;
1179  case '1': RegNo = X86::DR11; break;
1180  case '2': RegNo = X86::DR12; break;
1181  case '3': RegNo = X86::DR13; break;
1182  case '4': RegNo = X86::DR14; break;
1183  case '5': RegNo = X86::DR15; break;
1184  }
1185  }
1186 
1187  if (RegNo != 0) {
1188  EndLoc = Parser.getTok().getEndLoc();
1189  Parser.Lex(); // Eat it.
1190  return false;
1191  }
1192  }
1193 
1194  if (RegNo == 0) {
1195  if (isParsingIntelSyntax()) return true;
1196  return Error(StartLoc, "invalid register name",
1197  SMRange(StartLoc, EndLoc));
1198  }
1199 
1200  Parser.Lex(); // Eat identifier token.
1201  return false;
1202 }
1203 
1204 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1205  bool Parse32 = is32BitMode() || Code16GCC;
1206  unsigned Basereg = is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI);
1207  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1208  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1209  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1210  Loc, Loc, 0);
1211 }
1212 
1213 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1214  bool Parse32 = is32BitMode() || Code16GCC;
1215  unsigned Basereg = is64BitMode() ? X86::RDI : (Parse32 ? X86::EDI : X86::DI);
1216  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1217  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1218  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1219  Loc, Loc, 0);
1220 }
1221 
1222 bool X86AsmParser::IsSIReg(unsigned Reg) {
1223  switch (Reg) {
1224  default: llvm_unreachable("Only (R|E)SI and (R|E)DI are expected!");
1225  case X86::RSI:
1226  case X86::ESI:
1227  case X86::SI:
1228  return true;
1229  case X86::RDI:
1230  case X86::EDI:
1231  case X86::DI:
1232  return false;
1233  }
1234 }
1235 
1236 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg,
1237  bool IsSIReg) {
1238  switch (RegClassID) {
1239  default: llvm_unreachable("Unexpected register class");
1240  case X86::GR64RegClassID:
1241  return IsSIReg ? X86::RSI : X86::RDI;
1242  case X86::GR32RegClassID:
1243  return IsSIReg ? X86::ESI : X86::EDI;
1244  case X86::GR16RegClassID:
1245  return IsSIReg ? X86::SI : X86::DI;
1246  }
1247 }
1248 
1249 void X86AsmParser::AddDefaultSrcDestOperands(
1250  OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1251  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) {
1252  if (isParsingIntelSyntax()) {
1253  Operands.push_back(std::move(Dst));
1254  Operands.push_back(std::move(Src));
1255  }
1256  else {
1257  Operands.push_back(std::move(Src));
1258  Operands.push_back(std::move(Dst));
1259  }
1260 }
1261 
1262 bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
1263  OperandVector &FinalOperands) {
1264 
1265  if (OrigOperands.size() > 1) {
1266  // Check if sizes match, OrigOperands also contains the instruction name
1267  assert(OrigOperands.size() == FinalOperands.size() + 1 &&
1268  "Operand size mismatch");
1269 
1271  // Verify types match
1272  int RegClassID = -1;
1273  for (unsigned int i = 0; i < FinalOperands.size(); ++i) {
1274  X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]);
1275  X86Operand &FinalOp = static_cast<X86Operand &>(*FinalOperands[i]);
1276 
1277  if (FinalOp.isReg() &&
1278  (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg()))
1279  // Return false and let a normal complaint about bogus operands happen
1280  return false;
1281 
1282  if (FinalOp.isMem()) {
1283 
1284  if (!OrigOp.isMem())
1285  // Return false and let a normal complaint about bogus operands happen
1286  return false;
1287 
1288  unsigned OrigReg = OrigOp.Mem.BaseReg;
1289  unsigned FinalReg = FinalOp.Mem.BaseReg;
1290 
1291  // If we've already encounterd a register class, make sure all register
1292  // bases are of the same register class
1293  if (RegClassID != -1 &&
1294  !X86MCRegisterClasses[RegClassID].contains(OrigReg)) {
1295  return Error(OrigOp.getStartLoc(),
1296  "mismatching source and destination index registers");
1297  }
1298 
1299  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg))
1300  RegClassID = X86::GR64RegClassID;
1301  else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg))
1302  RegClassID = X86::GR32RegClassID;
1303  else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg))
1304  RegClassID = X86::GR16RegClassID;
1305  else
1306  // Unexpected register class type
1307  // Return false and let a normal complaint about bogus operands happen
1308  return false;
1309 
1310  bool IsSI = IsSIReg(FinalReg);
1311  FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI);
1312 
1313  if (FinalReg != OrigReg) {
1314  std::string RegName = IsSI ? "ES:(R|E)SI" : "ES:(R|E)DI";
1315  Warnings.push_back(std::make_pair(
1316  OrigOp.getStartLoc(),
1317  "memory operand is only for determining the size, " + RegName +
1318  " will be used for the location"));
1319  }
1320 
1321  FinalOp.Mem.Size = OrigOp.Mem.Size;
1322  FinalOp.Mem.SegReg = OrigOp.Mem.SegReg;
1323  FinalOp.Mem.BaseReg = FinalReg;
1324  }
1325  }
1326 
1327  // Produce warnings only if all the operands passed the adjustment - prevent
1328  // legal cases like "movsd (%rax), %xmm0" mistakenly produce warnings
1329  for (auto &WarningMsg : Warnings) {
1330  Warning(WarningMsg.first, WarningMsg.second);
1331  }
1332 
1333  // Remove old operands
1334  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1335  OrigOperands.pop_back();
1336  }
1337  // OrigOperands.append(FinalOperands.begin(), FinalOperands.end());
1338  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1339  OrigOperands.push_back(std::move(FinalOperands[i]));
1340 
1341  return false;
1342 }
1343 
1344 std::unique_ptr<X86Operand> X86AsmParser::ParseOperand() {
1345  if (isParsingIntelSyntax())
1346  return ParseIntelOperand();
1347  return ParseATTOperand();
1348 }
1349 
1350 std::unique_ptr<X86Operand> X86AsmParser::CreateMemForInlineAsm(
1351  unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1352  unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier,
1353  const InlineAsmIdentifierInfo &Info) {
1354  // If we found a decl other than a VarDecl, then assume it is a FuncDecl or
1355  // some other label reference.
1357  // Insert an explicit size if the user didn't have one.
1358  if (!Size) {
1359  Size = getPointerWidth();
1360  InstInfo->AsmRewrites->emplace_back(AOK_SizeDirective, Start,
1361  /*Len=*/0, Size);
1362  }
1363  // Create an absolute memory reference in order to match against
1364  // instructions taking a PC relative operand.
1365  return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size,
1366  Identifier, Info.Label.Decl);
1367  }
1368  // We either have a direct symbol reference, or an offset from a symbol. The
1369  // parser always puts the symbol on the LHS, so look there for size
1370  // calculation purposes.
1371  unsigned FrontendSize = 0;
1372  void *Decl = nullptr;
1373  bool IsGlobalLV = false;
1375  // Size is in terms of bits in this context.
1376  FrontendSize = Info.Var.Type * 8;
1377  Decl = Info.Var.Decl;
1378  IsGlobalLV = Info.Var.IsGlobalLV;
1379  }
1380  // It is widely common for MS InlineAsm to use a global variable and one/two
1381  // registers in a mmory expression, and though unaccessible via rip/eip.
1382  if (IsGlobalLV && (BaseReg || IndexReg)) {
1383  return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End);
1384  // Otherwise, we set the base register to a non-zero value
1385  // if we don't know the actual value at this time. This is necessary to
1386  // get the matching correct in some cases.
1387  } else {
1388  BaseReg = BaseReg ? BaseReg : 1;
1389  return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
1390  IndexReg, Scale, Start, End, Size, Identifier,
1391  Decl, FrontendSize);
1392  }
1393 }
1394 
1395 // Some binary bitwise operators have a named synonymous
1396 // Query a candidate string for being such a named operator
1397 // and if so - invoke the appropriate handler
1398 bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM) {
1399  // A named operator should be either lower or upper case, but not a mix
1400  if (Name.compare(Name.lower()) && Name.compare(Name.upper()))
1401  return false;
1402  if (Name.equals_lower("not"))
1403  SM.onNot();
1404  else if (Name.equals_lower("or"))
1405  SM.onOr();
1406  else if (Name.equals_lower("shl"))
1407  SM.onLShift();
1408  else if (Name.equals_lower("shr"))
1409  SM.onRShift();
1410  else if (Name.equals_lower("xor"))
1411  SM.onXor();
1412  else if (Name.equals_lower("and"))
1413  SM.onAnd();
1414  else if (Name.equals_lower("mod"))
1415  SM.onMod();
1416  else
1417  return false;
1418  return true;
1419 }
1420 
1421 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1422  MCAsmParser &Parser = getParser();
1423  const AsmToken &Tok = Parser.getTok();
1424  StringRef ErrMsg;
1425 
1427  bool Done = false;
1428  while (!Done) {
1429  bool UpdateLocLex = true;
1430  AsmToken::TokenKind TK = getLexer().getKind();
1431 
1432  switch (TK) {
1433  default:
1434  if ((Done = SM.isValidEndState()))
1435  break;
1436  return Error(Tok.getLoc(), "unknown token in expression");
1438  Done = true;
1439  break;
1440  case AsmToken::Real:
1441  // DotOperator: [ebx].0
1442  UpdateLocLex = false;
1443  if (ParseIntelDotOperator(SM, End))
1444  return true;
1445  break;
1446  case AsmToken::At:
1447  case AsmToken::String:
1448  case AsmToken::Identifier: {
1449  SMLoc IdentLoc = Tok.getLoc();
1450  StringRef Identifier = Tok.getString();
1451  UpdateLocLex = false;
1452  // Register
1453  unsigned Reg;
1454  if (Tok.is(AsmToken::Identifier) && !ParseRegister(Reg, IdentLoc, End)) {
1455  if (SM.onRegister(Reg, ErrMsg))
1456  return Error(Tok.getLoc(), ErrMsg);
1457  break;
1458  }
1459  // Operator synonymous ("not", "or" etc.)
1460  if ((UpdateLocLex = ParseIntelNamedOperator(Identifier, SM)))
1461  break;
1462  // Symbol reference, when parsing assembly content
1464  const MCExpr *Val;
1465  if (!isParsingInlineAsm()) {
1466  if (getParser().parsePrimaryExpr(Val, End)) {
1467  return Error(Tok.getLoc(), "Unexpected identifier!");
1468  } else if (SM.onIdentifierExpr(Val, Identifier, Info, false, ErrMsg)) {
1469  return Error(IdentLoc, ErrMsg);
1470  } else
1471  break;
1472  }
1473  // MS InlineAsm operators (TYPE/LENGTH/SIZE)
1474  if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Identifier)) {
1475  if (OpKind == IOK_OFFSET)
1476  return Error(IdentLoc, "Dealing OFFSET operator as part of"
1477  "a compound immediate expression is yet to be supported");
1478  if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) {
1479  if (SM.onInteger(Val, ErrMsg))
1480  return Error(IdentLoc, ErrMsg);
1481  } else
1482  return true;
1483  break;
1484  }
1485  // MS Dot Operator expression
1486  if (Identifier.count('.') && PrevTK == AsmToken::RBrac) {
1487  if (ParseIntelDotOperator(SM, End))
1488  return true;
1489  break;
1490  }
1491  // MS InlineAsm identifier
1492  // Call parseIdentifier() to combine @ with the identifier behind it.
1493  if (TK == AsmToken::At && Parser.parseIdentifier(Identifier))
1494  return Error(IdentLoc, "expected identifier");
1495  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, false, End))
1496  return true;
1497  else if (SM.onIdentifierExpr(Val, Identifier, Info, true, ErrMsg))
1498  return Error(IdentLoc, ErrMsg);
1499  break;
1500  }
1501  case AsmToken::Integer: {
1502  // Look for 'b' or 'f' following an Integer as a directional label
1503  SMLoc Loc = getTok().getLoc();
1504  int64_t IntVal = getTok().getIntVal();
1505  End = consumeToken();
1506  UpdateLocLex = false;
1507  if (getLexer().getKind() == AsmToken::Identifier) {
1508  StringRef IDVal = getTok().getString();
1509  if (IDVal == "f" || IDVal == "b") {
1510  MCSymbol *Sym =
1511  getContext().getDirectionalLocalSymbol(IntVal, IDVal == "b");
1513  const MCExpr *Val =
1514  MCSymbolRefExpr::create(Sym, Variant, getContext());
1515  if (IDVal == "b" && Sym->isUndefined())
1516  return Error(Loc, "invalid reference to undefined symbol");
1517  StringRef Identifier = Sym->getName();
1519  if (SM.onIdentifierExpr(Val, Identifier, Info,
1520  isParsingInlineAsm(), ErrMsg))
1521  return Error(Loc, ErrMsg);
1522  End = consumeToken();
1523  } else {
1524  if (SM.onInteger(IntVal, ErrMsg))
1525  return Error(Loc, ErrMsg);
1526  }
1527  } else {
1528  if (SM.onInteger(IntVal, ErrMsg))
1529  return Error(Loc, ErrMsg);
1530  }
1531  break;
1532  }
1533  case AsmToken::Plus:
1534  if (SM.onPlus(ErrMsg))
1535  return Error(getTok().getLoc(), ErrMsg);
1536  break;
1537  case AsmToken::Minus:
1538  if (SM.onMinus(ErrMsg))
1539  return Error(getTok().getLoc(), ErrMsg);
1540  break;
1541  case AsmToken::Tilde: SM.onNot(); break;
1542  case AsmToken::Star: SM.onStar(); break;
1543  case AsmToken::Slash: SM.onDivide(); break;
1544  case AsmToken::Percent: SM.onMod(); break;
1545  case AsmToken::Pipe: SM.onOr(); break;
1546  case AsmToken::Caret: SM.onXor(); break;
1547  case AsmToken::Amp: SM.onAnd(); break;
1548  case AsmToken::LessLess:
1549  SM.onLShift(); break;
1551  SM.onRShift(); break;
1552  case AsmToken::LBrac:
1553  if (SM.onLBrac())
1554  return Error(Tok.getLoc(), "unexpected bracket encountered");
1555  break;
1556  case AsmToken::RBrac:
1557  if (SM.onRBrac())
1558  return Error(Tok.getLoc(), "unexpected bracket encountered");
1559  break;
1560  case AsmToken::LParen: SM.onLParen(); break;
1561  case AsmToken::RParen: SM.onRParen(); break;
1562  }
1563  if (SM.hadError())
1564  return Error(Tok.getLoc(), "unknown token in expression");
1565 
1566  if (!Done && UpdateLocLex)
1567  End = consumeToken();
1568 
1569  PrevTK = TK;
1570  }
1571  return false;
1572 }
1573 
1574 void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM,
1575  SMLoc Start, SMLoc End) {
1576  SMLoc Loc = Start;
1577  unsigned ExprLen = End.getPointer() - Start.getPointer();
1578  // Skip everything before a symbol displacement (if we have one)
1579  if (SM.getSym()) {
1580  StringRef SymName = SM.getSymName();
1581  if (unsigned Len = SymName.data() - Start.getPointer())
1582  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Start, Len);
1583  Loc = SMLoc::getFromPointer(SymName.data() + SymName.size());
1584  ExprLen = End.getPointer() - (SymName.data() + SymName.size());
1585  // If we have only a symbol than there's no need for complex rewrite,
1586  // simply skip everything after it
1587  if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) {
1588  if (ExprLen)
1589  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Loc, ExprLen);
1590  return;
1591  }
1592  }
1593  // Build an Intel Expression rewrite
1594  StringRef BaseRegStr;
1595  StringRef IndexRegStr;
1596  if (SM.getBaseReg())
1597  BaseRegStr = X86IntelInstPrinter::getRegisterName(SM.getBaseReg());
1598  if (SM.getIndexReg())
1599  IndexRegStr = X86IntelInstPrinter::getRegisterName(SM.getIndexReg());
1600  // Emit it
1601  IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), SM.getImm(), SM.isMemExpr());
1602  InstInfo->AsmRewrites->emplace_back(Loc, ExprLen, Expr);
1603 }
1604 
1605 // Inline assembly may use variable names with namespace alias qualifiers.
1606 bool X86AsmParser::ParseIntelInlineAsmIdentifier(const MCExpr *&Val,
1607  StringRef &Identifier,
1609  bool IsUnevaluatedOperand,
1610  SMLoc &End) {
1611  MCAsmParser &Parser = getParser();
1612  assert(isParsingInlineAsm() && "Expected to be parsing inline assembly.");
1613  Val = nullptr;
1614 
1615  StringRef LineBuf(Identifier.data());
1616  SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
1617 
1618  const AsmToken &Tok = Parser.getTok();
1619  SMLoc Loc = Tok.getLoc();
1620 
1621  // Advance the token stream until the end of the current token is
1622  // after the end of what the frontend claimed.
1623  const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
1624  do {
1625  End = Tok.getEndLoc();
1626  getLexer().Lex();
1627  } while (End.getPointer() < EndPtr);
1628  Identifier = LineBuf;
1629 
1630  // The frontend should end parsing on an assembler token boundary, unless it
1631  // failed parsing.
1632  assert((End.getPointer() == EndPtr ||
1634  "frontend claimed part of a token?");
1635 
1636  // If the identifier lookup was unsuccessful, assume that we are dealing with
1637  // a label.
1639  StringRef InternalName =
1640  SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(),
1641  Loc, false);
1642  assert(InternalName.size() && "We should have an internal name here.");
1643  // Push a rewrite for replacing the identifier name with the internal name.
1644  InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(),
1645  InternalName);
1647  return false;
1648  // Create the symbol reference.
1649  MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
1651  Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext());
1652  return false;
1653 }
1654 
1655 //ParseRoundingModeOp - Parse AVX-512 rounding mode operand
1656 std::unique_ptr<X86Operand>
1657 X86AsmParser::ParseRoundingModeOp(SMLoc Start) {
1658  MCAsmParser &Parser = getParser();
1659  const AsmToken &Tok = Parser.getTok();
1660  // Eat "{" and mark the current place.
1661  const SMLoc consumedToken = consumeToken();
1662  if (Tok.isNot(AsmToken::Identifier))
1663  return ErrorOperand(Tok.getLoc(), "Expected an identifier after {");
1664  if (Tok.getIdentifier().startswith("r")){
1665  int rndMode = StringSwitch<int>(Tok.getIdentifier())
1670  .Default(-1);
1671  if (-1 == rndMode)
1672  return ErrorOperand(Tok.getLoc(), "Invalid rounding mode.");
1673  Parser.Lex(); // Eat "r*" of r*-sae
1674  if (!getLexer().is(AsmToken::Minus))
1675  return ErrorOperand(Tok.getLoc(), "Expected - at this point");
1676  Parser.Lex(); // Eat "-"
1677  Parser.Lex(); // Eat the sae
1678  if (!getLexer().is(AsmToken::RCurly))
1679  return ErrorOperand(Tok.getLoc(), "Expected } at this point");
1680  SMLoc End = Tok.getEndLoc();
1681  Parser.Lex(); // Eat "}"
1682  const MCExpr *RndModeOp =
1683  MCConstantExpr::create(rndMode, Parser.getContext());
1684  return X86Operand::CreateImm(RndModeOp, Start, End);
1685  }
1686  if(Tok.getIdentifier().equals("sae")){
1687  Parser.Lex(); // Eat the sae
1688  if (!getLexer().is(AsmToken::RCurly))
1689  return ErrorOperand(Tok.getLoc(), "Expected } at this point");
1690  Parser.Lex(); // Eat "}"
1691  return X86Operand::CreateToken("{sae}", consumedToken);
1692  }
1693  return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1694 }
1695 
1696 /// Parse the '.' operator.
1697 bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End) {
1698  const AsmToken &Tok = getTok();
1699  unsigned Offset;
1700 
1701  // Drop the optional '.'.
1702  StringRef DotDispStr = Tok.getString();
1703  if (DotDispStr.startswith("."))
1704  DotDispStr = DotDispStr.drop_front(1);
1705 
1706  // .Imm gets lexed as a real.
1707  if (Tok.is(AsmToken::Real)) {
1708  APInt DotDisp;
1709  DotDispStr.getAsInteger(10, DotDisp);
1710  Offset = DotDisp.getZExtValue();
1711  } else if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1712  std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1713  if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
1714  Offset))
1715  return Error(Tok.getLoc(), "Unable to lookup field reference!");
1716  } else
1717  return Error(Tok.getLoc(), "Unexpected token type!");
1718 
1719  // Eat the DotExpression and update End
1720  End = SMLoc::getFromPointer(DotDispStr.data());
1721  const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size();
1722  while (Tok.getLoc().getPointer() < DotExprEndLoc)
1723  Lex();
1724  SM.addImm(Offset);
1725  return false;
1726 }
1727 
1728 /// Parse the 'offset' operator. This operator is used to specify the
1729 /// location rather then the content of a variable.
1730 std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOffsetOfOperator() {
1731  MCAsmParser &Parser = getParser();
1732  const AsmToken &Tok = Parser.getTok();
1733  SMLoc OffsetOfLoc = Tok.getLoc();
1734  Parser.Lex(); // Eat offset.
1735 
1736  const MCExpr *Val;
1738  SMLoc Start = Tok.getLoc(), End;
1739  StringRef Identifier = Tok.getString();
1740  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
1741  /*Unevaluated=*/false, End))
1742  return nullptr;
1743 
1744  void *Decl = nullptr;
1745  // FIXME: MS evaluates "offset <Constant>" to the underlying integral
1747  return ErrorOperand(Start, "offset operator cannot yet handle constants");
1748  else if (Info.isKind(InlineAsmIdentifierInfo::IK_Var))
1749  Decl = Info.Var.Decl;
1750  // Don't emit the offset operator.
1751  InstInfo->AsmRewrites->emplace_back(AOK_Skip, OffsetOfLoc, 7);
1752 
1753  // The offset operator will have an 'r' constraint, thus we need to create
1754  // register operand to ensure proper matching. Just pick a GPR based on
1755  // the size of a pointer.
1756  bool Parse32 = is32BitMode() || Code16GCC;
1757  unsigned RegNo = is64BitMode() ? X86::RBX : (Parse32 ? X86::EBX : X86::BX);
1758 
1759  return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
1760  OffsetOfLoc, Identifier, Decl);
1761 }
1762 
1763 // Query a candidate string for being an Intel assembly operator
1764 // Report back its kind, or IOK_INVALID if does not evaluated as a known one
1765 unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
1767  .Cases("TYPE","type",IOK_TYPE)
1768  .Cases("SIZE","size",IOK_SIZE)
1769  .Cases("LENGTH","length",IOK_LENGTH)
1770  .Cases("OFFSET","offset",IOK_OFFSET)
1771  .Default(IOK_INVALID);
1772 }
1773 
1774 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
1775 /// returns the number of elements in an array. It returns the value 1 for
1776 /// non-array variables. The SIZE operator returns the size of a C or C++
1777 /// variable. A variable's size is the product of its LENGTH and TYPE. The
1778 /// TYPE operator returns the size of a C or C++ type or variable. If the
1779 /// variable is an array, TYPE returns the size of a single element.
1780 unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) {
1781  MCAsmParser &Parser = getParser();
1782  const AsmToken &Tok = Parser.getTok();
1783  Parser.Lex(); // Eat operator.
1784 
1785  const MCExpr *Val = nullptr;
1787  SMLoc Start = Tok.getLoc(), End;
1788  StringRef Identifier = Tok.getString();
1789  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
1790  /*Unevaluated=*/true, End))
1791  return 0;
1792 
1794  Error(Start, "unable to lookup expression");
1795  return 0;
1796  }
1797 
1798  unsigned CVal = 0;
1799  switch(OpKind) {
1800  default: llvm_unreachable("Unexpected operand kind!");
1801  case IOK_LENGTH: CVal = Info.Var.Length; break;
1802  case IOK_SIZE: CVal = Info.Var.Size; break;
1803  case IOK_TYPE: CVal = Info.Var.Type; break;
1804  }
1805 
1806  return CVal;
1807 }
1808 
1809 bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
1810  Size = StringSwitch<unsigned>(getTok().getString())
1811  .Cases("BYTE", "byte", 8)
1812  .Cases("WORD", "word", 16)
1813  .Cases("DWORD", "dword", 32)
1814  .Cases("FLOAT", "float", 32)
1815  .Cases("LONG", "long", 32)
1816  .Cases("FWORD", "fword", 48)
1817  .Cases("DOUBLE", "double", 64)
1818  .Cases("QWORD", "qword", 64)
1819  .Cases("MMWORD","mmword", 64)
1820  .Cases("XWORD", "xword", 80)
1821  .Cases("TBYTE", "tbyte", 80)
1822  .Cases("XMMWORD", "xmmword", 128)
1823  .Cases("YMMWORD", "ymmword", 256)
1824  .Cases("ZMMWORD", "zmmword", 512)
1825  .Default(0);
1826  if (Size) {
1827  const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word).
1828  if (!(Tok.getString().equals("PTR") || Tok.getString().equals("ptr")))
1829  return Error(Tok.getLoc(), "Expected 'PTR' or 'ptr' token!");
1830  Lex(); // Eat ptr.
1831  }
1832  return false;
1833 }
1834 
1835 std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
1836  MCAsmParser &Parser = getParser();
1837  const AsmToken &Tok = Parser.getTok();
1838  SMLoc Start, End;
1839 
1840  // FIXME: Offset operator
1841  // Should be handled as part of immediate expression, as other operators
1842  // Currently, only supported as a stand-alone operand
1843  if (isParsingInlineAsm())
1844  if (IdentifyIntelInlineAsmOperator(Tok.getString()) == IOK_OFFSET)
1845  return ParseIntelOffsetOfOperator();
1846 
1847  // Parse optional Size directive.
1848  unsigned Size;
1849  if (ParseIntelMemoryOperandSize(Size))
1850  return nullptr;
1851  bool PtrInOperand = bool(Size);
1852 
1853  Start = Tok.getLoc();
1854 
1855  // Rounding mode operand.
1856  if (getLexer().is(AsmToken::LCurly))
1857  return ParseRoundingModeOp(Start);
1858 
1859  // Register operand.
1860  unsigned RegNo = 0;
1861  if (Tok.is(AsmToken::Identifier) && !ParseRegister(RegNo, Start, End)) {
1862  if (RegNo == X86::RIP)
1863  return ErrorOperand(Start, "rip can only be used as a base register");
1864  // A Register followed by ':' is considered a segment override
1865  if (Tok.isNot(AsmToken::Colon))
1866  return !PtrInOperand ? X86Operand::CreateReg(RegNo, Start, End) :
1867  ErrorOperand(Start, "expected memory operand after 'ptr', "
1868  "found register operand instead");
1869  // An alleged segment override. check if we have a valid segment register
1870  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
1871  return ErrorOperand(Start, "invalid segment register");
1872  // Eat ':' and update Start location
1873  Start = Lex().getLoc();
1874  }
1875 
1876  // Immediates and Memory
1877  IntelExprStateMachine SM;
1878  if (ParseIntelExpression(SM, End))
1879  return nullptr;
1880 
1881  if (isParsingInlineAsm())
1882  RewriteIntelExpression(SM, Start, Tok.getLoc());
1883 
1884  int64_t Imm = SM.getImm();
1885  const MCExpr *Disp = SM.getSym();
1886  const MCExpr *ImmDisp = MCConstantExpr::create(Imm, getContext());
1887  if (Disp && Imm)
1888  Disp = MCBinaryExpr::createAdd(Disp, ImmDisp, getContext());
1889  if (!Disp)
1890  Disp = ImmDisp;
1891 
1892  // RegNo != 0 specifies a valid segment register,
1893  // and we are parsing a segment override
1894  if (!SM.isMemExpr() && !RegNo)
1895  return X86Operand::CreateImm(Disp, Start, End);
1896 
1897  StringRef ErrMsg;
1898  unsigned BaseReg = SM.getBaseReg();
1899  unsigned IndexReg = SM.getIndexReg();
1900  unsigned Scale = SM.getScale();
1901 
1902  if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&
1903  (IndexReg == X86::ESP || IndexReg == X86::RSP))
1904  std::swap(BaseReg, IndexReg);
1905 
1906  // If BaseReg is a vector register and IndexReg is not, swap them unless
1907  // Scale was specified in which case it would be an error.
1908  if (Scale == 0 &&
1909  !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
1910  X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
1911  X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&
1912  (X86MCRegisterClasses[X86::VR128XRegClassID].contains(BaseReg) ||
1913  X86MCRegisterClasses[X86::VR256XRegClassID].contains(BaseReg) ||
1914  X86MCRegisterClasses[X86::VR512RegClassID].contains(BaseReg)))
1915  std::swap(BaseReg, IndexReg);
1916 
1917  if (Scale != 0 &&
1918  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))
1919  return ErrorOperand(Start, "16-bit addresses cannot have a scale");
1920 
1921  // If there was no explicit scale specified, change it to 1.
1922  if (Scale == 0)
1923  Scale = 1;
1924 
1925  // If this is a 16-bit addressing mode with the base and index in the wrong
1926  // order, swap them so CheckBaseRegAndIndexRegAndScale doesn't fail. It is
1927  // shared with att syntax where order matters.
1928  if ((BaseReg == X86::SI || BaseReg == X86::DI) &&
1929  (IndexReg == X86::BX || IndexReg == X86::BP))
1930  std::swap(BaseReg, IndexReg);
1931 
1932  if ((BaseReg || IndexReg) &&
1933  CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
1934  ErrMsg))
1935  return ErrorOperand(Start, ErrMsg);
1936  if (isParsingInlineAsm())
1937  return CreateMemForInlineAsm(RegNo, Disp, BaseReg, IndexReg,
1938  Scale, Start, End, Size, SM.getSymName(),
1939  SM.getIdentifierInfo());
1940  if (!(BaseReg || IndexReg || RegNo))
1941  return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size);
1942  return X86Operand::CreateMem(getPointerWidth(), RegNo, Disp,
1943  BaseReg, IndexReg, Scale, Start, End, Size);
1944 }
1945 
1946 std::unique_ptr<X86Operand> X86AsmParser::ParseATTOperand() {
1947  MCAsmParser &Parser = getParser();
1948  switch (getLexer().getKind()) {
1949  case AsmToken::Dollar: {
1950  // $42 or $ID -> immediate.
1951  SMLoc Start = Parser.getTok().getLoc(), End;
1952  Parser.Lex();
1953  const MCExpr *Val;
1954  // This is an immediate, so we should not parse a register. Do a precheck
1955  // for '%' to supercede intra-register parse errors.
1956  SMLoc L = Parser.getTok().getLoc();
1957  if (check(getLexer().is(AsmToken::Percent), L,
1958  "expected immediate expression") ||
1959  getParser().parseExpression(Val, End) ||
1960  check(isa<X86MCExpr>(Val), L, "expected immediate expression"))
1961  return nullptr;
1962  return X86Operand::CreateImm(Val, Start, End);
1963  }
1964  case AsmToken::LCurly: {
1965  SMLoc Start = Parser.getTok().getLoc();
1966  return ParseRoundingModeOp(Start);
1967  }
1968  default: {
1969  // This a memory operand or a register. We have some parsing complications
1970  // as a '(' may be part of an immediate expression or the addressing mode
1971  // block. This is complicated by the fact that an assembler-level variable
1972  // may refer either to a register or an immediate expression.
1973 
1974  SMLoc Loc = Parser.getTok().getLoc(), EndLoc;
1975  const MCExpr *Expr = nullptr;
1976  unsigned Reg = 0;
1977  if (getLexer().isNot(AsmToken::LParen)) {
1978  // No '(' so this is either a displacement expression or a register.
1979  if (Parser.parseExpression(Expr, EndLoc))
1980  return nullptr;
1981  if (auto *RE = dyn_cast<X86MCExpr>(Expr)) {
1982  // Segment Register. Reset Expr and copy value to register.
1983  Expr = nullptr;
1984  Reg = RE->getRegNo();
1985 
1986  // Sanity check register.
1987  if (Reg == X86::EIZ || Reg == X86::RIZ)
1988  return ErrorOperand(
1989  Loc, "%eiz and %riz can only be used as index registers",
1990  SMRange(Loc, EndLoc));
1991  if (Reg == X86::RIP)
1992  return ErrorOperand(Loc, "%rip can only be used as a base register",
1993  SMRange(Loc, EndLoc));
1994  // Return register that are not segment prefixes immediately.
1995  if (!Parser.parseOptionalToken(AsmToken::Colon))
1996  return X86Operand::CreateReg(Reg, Loc, EndLoc);
1997  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(Reg))
1998  return ErrorOperand(Loc, "invalid segment register");
1999  }
2000  }
2001  // This is a Memory operand.
2002  return ParseMemOperand(Reg, Expr, Loc, EndLoc);
2003  }
2004  }
2005 }
2006 
2007 // true on failure, false otherwise
2008 // If no {z} mark was found - Parser doesn't advance
2009 bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
2010  const SMLoc &StartLoc) {
2011  MCAsmParser &Parser = getParser();
2012  // Assuming we are just pass the '{' mark, quering the next token
2013  // Searched for {z}, but none was found. Return false, as no parsing error was
2014  // encountered
2015  if (!(getLexer().is(AsmToken::Identifier) &&
2016  (getLexer().getTok().getIdentifier() == "z")))
2017  return false;
2018  Parser.Lex(); // Eat z
2019  // Query and eat the '}' mark
2020  if (!getLexer().is(AsmToken::RCurly))
2021  return Error(getLexer().getLoc(), "Expected } at this point");
2022  Parser.Lex(); // Eat '}'
2023  // Assign Z with the {z} mark opernad
2024  Z = X86Operand::CreateToken("{z}", StartLoc);
2025  return false;
2026 }
2027 
2028 // true on failure, false otherwise
2029 bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
2030  const MCParsedAsmOperand &Op) {
2031  MCAsmParser &Parser = getParser();
2032  if (getLexer().is(AsmToken::LCurly)) {
2033  // Eat "{" and mark the current place.
2034  const SMLoc consumedToken = consumeToken();
2035  // Distinguish {1to<NUM>} from {%k<NUM>}.
2036  if(getLexer().is(AsmToken::Integer)) {
2037  // Parse memory broadcasting ({1to<NUM>}).
2038  if (getLexer().getTok().getIntVal() != 1)
2039  return TokError("Expected 1to<NUM> at this point");
2040  Parser.Lex(); // Eat "1" of 1to8
2041  if (!getLexer().is(AsmToken::Identifier) ||
2042  !getLexer().getTok().getIdentifier().startswith("to"))
2043  return TokError("Expected 1to<NUM> at this point");
2044  // Recognize only reasonable suffixes.
2045  const char *BroadcastPrimitive =
2046  StringSwitch<const char*>(getLexer().getTok().getIdentifier())
2047  .Case("to2", "{1to2}")
2048  .Case("to4", "{1to4}")
2049  .Case("to8", "{1to8}")
2050  .Case("to16", "{1to16}")
2051  .Default(nullptr);
2052  if (!BroadcastPrimitive)
2053  return TokError("Invalid memory broadcast primitive.");
2054  Parser.Lex(); // Eat "toN" of 1toN
2055  if (!getLexer().is(AsmToken::RCurly))
2056  return TokError("Expected } at this point");
2057  Parser.Lex(); // Eat "}"
2058  Operands.push_back(X86Operand::CreateToken(BroadcastPrimitive,
2059  consumedToken));
2060  // No AVX512 specific primitives can pass
2061  // after memory broadcasting, so return.
2062  return false;
2063  } else {
2064  // Parse either {k}{z}, {z}{k}, {k} or {z}
2065  // last one have no meaning, but GCC accepts it
2066  // Currently, we're just pass a '{' mark
2067  std::unique_ptr<X86Operand> Z;
2068  if (ParseZ(Z, consumedToken))
2069  return true;
2070  // Reaching here means that parsing of the allegadly '{z}' mark yielded
2071  // no errors.
2072  // Query for the need of further parsing for a {%k<NUM>} mark
2073  if (!Z || getLexer().is(AsmToken::LCurly)) {
2074  SMLoc StartLoc = Z ? consumeToken() : consumedToken;
2075  // Parse an op-mask register mark ({%k<NUM>}), which is now to be
2076  // expected
2077  unsigned RegNo;
2078  SMLoc RegLoc;
2079  if (!ParseRegister(RegNo, RegLoc, StartLoc) &&
2080  X86MCRegisterClasses[X86::VK1RegClassID].contains(RegNo)) {
2081  if (RegNo == X86::K0)
2082  return Error(RegLoc, "Register k0 can't be used as write mask");
2083  if (!getLexer().is(AsmToken::RCurly))
2084  return Error(getLexer().getLoc(), "Expected } at this point");
2085  Operands.push_back(X86Operand::CreateToken("{", StartLoc));
2086  Operands.push_back(
2087  X86Operand::CreateReg(RegNo, StartLoc, StartLoc));
2088  Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
2089  } else
2090  return Error(getLexer().getLoc(),
2091  "Expected an op-mask register at this point");
2092  // {%k<NUM>} mark is found, inquire for {z}
2093  if (getLexer().is(AsmToken::LCurly) && !Z) {
2094  // Have we've found a parsing error, or found no (expected) {z} mark
2095  // - report an error
2096  if (ParseZ(Z, consumeToken()) || !Z)
2097  return Error(getLexer().getLoc(),
2098  "Expected a {z} mark at this point");
2099 
2100  }
2101  // '{z}' on its own is meaningless, hence should be ignored.
2102  // on the contrary - have it been accompanied by a K register,
2103  // allow it.
2104  if (Z)
2105  Operands.push_back(std::move(Z));
2106  }
2107  }
2108  }
2109  return false;
2110 }
2111 
2112 /// ParseMemOperand: 'seg : disp(basereg, indexreg, scale)'. The '%ds:' prefix
2113 /// has already been parsed if present. disp may be provided as well.
2114 std::unique_ptr<X86Operand> X86AsmParser::ParseMemOperand(unsigned SegReg,
2115  const MCExpr *&Disp,
2116  const SMLoc &StartLoc,
2117  SMLoc &EndLoc) {
2118  MCAsmParser &Parser = getParser();
2119  SMLoc Loc;
2120  // Based on the initial passed values, we may be in any of these cases, we are
2121  // in one of these cases (with current position (*)):
2122 
2123  // 1. seg : * disp (base-index-scale-expr)
2124  // 2. seg : *(disp) (base-index-scale-expr)
2125  // 3. seg : *(base-index-scale-expr)
2126  // 4. disp *(base-index-scale-expr)
2127  // 5. *(disp) (base-index-scale-expr)
2128  // 6. *(base-index-scale-expr)
2129  // 7. disp *
2130  // 8. *(disp)
2131 
2132  // If we do not have an displacement yet, check if we're in cases 4 or 6 by
2133  // checking if the first object after the parenthesis is a register (or an
2134  // identifier referring to a register) and parse the displacement or default
2135  // to 0 as appropriate.
2136  auto isAtMemOperand = [this]() {
2137  if (this->getLexer().isNot(AsmToken::LParen))
2138  return false;
2139  AsmToken Buf[2];
2140  StringRef Id;
2141  auto TokCount = this->getLexer().peekTokens(Buf, true);
2142  if (TokCount == 0)
2143  return false;
2144  switch (Buf[0].getKind()) {
2145  case AsmToken::Percent:
2146  case AsmToken::Comma:
2147  return true;
2148  // These lower cases are doing a peekIdentifier.
2149  case AsmToken::At:
2150  case AsmToken::Dollar:
2151  if ((TokCount > 1) &&
2152  (Buf[1].is(AsmToken::Identifier) || Buf[1].is(AsmToken::String)) &&
2153  (Buf[0].getLoc().getPointer() + 1 == Buf[1].getLoc().getPointer()))
2154  Id = StringRef(Buf[0].getLoc().getPointer(),
2155  Buf[1].getIdentifier().size() + 1);
2156  break;
2157  case AsmToken::Identifier:
2158  case AsmToken::String:
2159  Id = Buf[0].getIdentifier();
2160  break;
2161  default:
2162  return false;
2163  }
2164  // We have an ID. Check if it is bound to a register.
2165  if (!Id.empty()) {
2166  MCSymbol *Sym = this->getContext().getOrCreateSymbol(Id);
2167  if (Sym->isVariable()) {
2168  auto V = Sym->getVariableValue(/*SetUsed*/ false);
2169  return isa<X86MCExpr>(V);
2170  }
2171  }
2172  return false;
2173  };
2174 
2175  if (!Disp) {
2176  // Parse immediate if we're not at a mem operand yet.
2177  if (!isAtMemOperand()) {
2178  if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(Disp, EndLoc))
2179  return nullptr;
2180  assert(!isa<X86MCExpr>(Disp) && "Expected non-register here.");
2181  } else {
2182  // Disp is implicitly zero if we haven't parsed it yet.
2183  Disp = MCConstantExpr::create(0, Parser.getContext());
2184  }
2185  }
2186 
2187  // We are now either at the end of the operand or at the '(' at the start of a
2188  // base-index-scale-expr.
2189 
2190  if (!parseOptionalToken(AsmToken::LParen)) {
2191  if (SegReg == 0)
2192  return X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc);
2193  return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
2194  StartLoc, EndLoc);
2195  }
2196 
2197  // If we reached here, then eat the '(' and Process
2198  // the rest of the memory operand.
2199  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
2200  SMLoc BaseLoc = getLexer().getLoc();
2201  const MCExpr *E;
2202  StringRef ErrMsg;
2203 
2204  // Parse BaseReg if one is provided.
2205  if (getLexer().isNot(AsmToken::Comma) && getLexer().isNot(AsmToken::RParen)) {
2206  if (Parser.parseExpression(E, EndLoc) ||
2207  check(!isa<X86MCExpr>(E), BaseLoc, "expected register here"))
2208  return nullptr;
2209 
2210  // Sanity check register.
2211  BaseReg = cast<X86MCExpr>(E)->getRegNo();
2212  if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)
2213  return ErrorOperand(BaseLoc,
2214  "eiz and riz can only be used as index registers",
2215  SMRange(BaseLoc, EndLoc));
2216  }
2217 
2218  if (parseOptionalToken(AsmToken::Comma)) {
2219  // Following the comma we should have either an index register, or a scale
2220  // value. We don't support the later form, but we want to parse it
2221  // correctly.
2222  //
2223  // Even though it would be completely consistent to support syntax like
2224  // "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
2225  if (getLexer().isNot(AsmToken::RParen)) {
2226  if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(E, EndLoc))
2227  return nullptr;
2228 
2229  if (!isa<X86MCExpr>(E)) {
2230  // We've parsed an unexpected Scale Value instead of an index
2231  // register. Interpret it as an absolute.
2232  int64_t ScaleVal;
2233  if (!E->evaluateAsAbsolute(ScaleVal, getStreamer().getAssemblerPtr()))
2234  return ErrorOperand(Loc, "expected absolute expression");
2235  if (ScaleVal != 1)
2236  Warning(Loc, "scale factor without index register is ignored");
2237  Scale = 1;
2238  } else { // IndexReg Found.
2239  IndexReg = cast<X86MCExpr>(E)->getRegNo();
2240 
2241  if (BaseReg == X86::RIP)
2242  return ErrorOperand(
2243  Loc, "%rip as base register can not have an index register");
2244  if (IndexReg == X86::RIP)
2245  return ErrorOperand(Loc, "%rip is not allowed as an index register");
2246 
2247  if (parseOptionalToken(AsmToken::Comma)) {
2248  // Parse the scale amount:
2249  // ::= ',' [scale-expression]
2250 
2251  // A scale amount without an index is ignored.
2252  if (getLexer().isNot(AsmToken::RParen)) {
2253  int64_t ScaleVal;
2254  if (Parser.parseTokenLoc(Loc) ||
2255  Parser.parseAbsoluteExpression(ScaleVal))
2256  return ErrorOperand(Loc, "expected scale expression");
2257  Scale = (unsigned)ScaleVal;
2258  // Validate the scale amount.
2259  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2260  Scale != 1)
2261  return ErrorOperand(Loc,
2262  "scale factor in 16-bit address must be 1");
2263  if (checkScale(Scale, ErrMsg))
2264  return ErrorOperand(Loc, ErrMsg);
2265  }
2266  }
2267  }
2268  }
2269  }
2270 
2271  // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
2272  if (parseToken(AsmToken::RParen, "unexpected token in memory operand"))
2273  return nullptr;
2274 
2275  // This is to support otherwise illegal operand (%dx) found in various
2276  // unofficial manuals examples (e.g. "out[s]?[bwl]? %al, (%dx)") and must now
2277  // be supported. Mark such DX variants separately fix only in special cases.
2278  if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&
2279  isa<MCConstantExpr>(Disp) && cast<MCConstantExpr>(Disp)->getValue() == 0)
2280  return X86Operand::CreateDXReg(BaseLoc, BaseLoc);
2281 
2282  if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
2283  ErrMsg))
2284  return ErrorOperand(BaseLoc, ErrMsg);
2285 
2286  if (SegReg || BaseReg || IndexReg)
2287  return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
2288  IndexReg, Scale, StartLoc, EndLoc);
2289  return X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc);
2290 }
2291 
2292 // Parse either a standard primary expression or a register.
2293 bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
2294  MCAsmParser &Parser = getParser();
2295  // See if this is a register first.
2296  if (getTok().is(AsmToken::Percent) ||
2297  (isParsingIntelSyntax() && getTok().is(AsmToken::Identifier) &&
2298  MatchRegisterName(Parser.getTok().getString()))) {
2299  SMLoc StartLoc = Parser.getTok().getLoc();
2300  unsigned RegNo;
2301  if (ParseRegister(RegNo, StartLoc, EndLoc))
2302  return true;
2303  Res = X86MCExpr::create(RegNo, Parser.getContext());
2304  return false;
2305  }
2306  return Parser.parsePrimaryExpr(Res, EndLoc);
2307 }
2308 
2309 bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
2310  SMLoc NameLoc, OperandVector &Operands) {
2311  MCAsmParser &Parser = getParser();
2312  InstInfo = &Info;
2313 
2314  // Reset the forced VEX encoding.
2315  ForcedVEXEncoding = VEXEncoding_Default;
2316 
2317  // Parse pseudo prefixes.
2318  while (1) {
2319  if (Name == "{") {
2320  if (getLexer().isNot(AsmToken::Identifier))
2321  return Error(Parser.getTok().getLoc(), "Unexpected token after '{'");
2322  std::string Prefix = Parser.getTok().getString().lower();
2323  Parser.Lex(); // Eat identifier.
2324  if (getLexer().isNot(AsmToken::RCurly))
2325  return Error(Parser.getTok().getLoc(), "Expected '}'");
2326  Parser.Lex(); // Eat curly.
2327 
2328  if (Prefix == "vex2")
2329  ForcedVEXEncoding = VEXEncoding_VEX2;
2330  else if (Prefix == "vex3")
2331  ForcedVEXEncoding = VEXEncoding_VEX3;
2332  else if (Prefix == "evex")
2333  ForcedVEXEncoding = VEXEncoding_EVEX;
2334  else
2335  return Error(NameLoc, "unknown prefix");
2336 
2337  NameLoc = Parser.getTok().getLoc();
2338  if (getLexer().is(AsmToken::LCurly)) {
2339  Parser.Lex();
2340  Name = "{";
2341  } else {
2342  if (getLexer().isNot(AsmToken::Identifier))
2343  return Error(Parser.getTok().getLoc(), "Expected identifier");
2344  // FIXME: The mnemonic won't match correctly if its not in lower case.
2345  Name = Parser.getTok().getString();
2346  Parser.Lex();
2347  }
2348  continue;
2349  }
2350 
2351  break;
2352  }
2353 
2354  StringRef PatchedName = Name;
2355 
2356  if ((Name.equals("jmp") || Name.equals("jc") || Name.equals("jz")) &&
2357  isParsingIntelSyntax() && isParsingInlineAsm()) {
2358  StringRef NextTok = Parser.getTok().getString();
2359  if (NextTok == "short") {
2360  SMLoc NameEndLoc =
2361  NameLoc.getFromPointer(NameLoc.getPointer() + Name.size());
2362  // Eat the short keyword
2363  Parser.Lex();
2364  // MS ignores the short keyword, it determines the jmp type based
2365  // on the distance of the label
2366  InstInfo->AsmRewrites->emplace_back(AOK_Skip, NameEndLoc,
2367  NextTok.size() + 1);
2368  }
2369  }
2370 
2371  // FIXME: Hack to recognize setneb as setne.
2372  if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
2373  PatchedName != "setb" && PatchedName != "setnb")
2374  PatchedName = PatchedName.substr(0, Name.size()-1);
2375 
2376  unsigned ComparisonCode = ~0U;
2377 
2378  // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
2379  if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
2380  (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
2381  PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
2382  bool IsVCMP = PatchedName[0] == 'v';
2383  unsigned CCIdx = IsVCMP ? 4 : 3;
2384  unsigned CC = StringSwitch<unsigned>(
2385  PatchedName.slice(CCIdx, PatchedName.size() - 2))
2386  .Case("eq", 0x00)
2387  .Case("eq_oq", 0x00)
2388  .Case("lt", 0x01)
2389  .Case("lt_os", 0x01)
2390  .Case("le", 0x02)
2391  .Case("le_os", 0x02)
2392  .Case("unord", 0x03)
2393  .Case("unord_q", 0x03)
2394  .Case("neq", 0x04)
2395  .Case("neq_uq", 0x04)
2396  .Case("nlt", 0x05)
2397  .Case("nlt_us", 0x05)
2398  .Case("nle", 0x06)
2399  .Case("nle_us", 0x06)
2400  .Case("ord", 0x07)
2401  .Case("ord_q", 0x07)
2402  /* AVX only from here */
2403  .Case("eq_uq", 0x08)
2404  .Case("nge", 0x09)
2405  .Case("nge_us", 0x09)
2406  .Case("ngt", 0x0A)
2407  .Case("ngt_us", 0x0A)
2408  .Case("false", 0x0B)
2409  .Case("false_oq", 0x0B)
2410  .Case("neq_oq", 0x0C)
2411  .Case("ge", 0x0D)
2412  .Case("ge_os", 0x0D)
2413  .Case("gt", 0x0E)
2414  .Case("gt_os", 0x0E)
2415  .Case("true", 0x0F)
2416  .Case("true_uq", 0x0F)
2417  .Case("eq_os", 0x10)
2418  .Case("lt_oq", 0x11)
2419  .Case("le_oq", 0x12)
2420  .Case("unord_s", 0x13)
2421  .Case("neq_us", 0x14)
2422  .Case("nlt_uq", 0x15)
2423  .Case("nle_uq", 0x16)
2424  .Case("ord_s", 0x17)
2425  .Case("eq_us", 0x18)
2426  .Case("nge_uq", 0x19)
2427  .Case("ngt_uq", 0x1A)
2428  .Case("false_os", 0x1B)
2429  .Case("neq_os", 0x1C)
2430  .Case("ge_oq", 0x1D)
2431  .Case("gt_oq", 0x1E)
2432  .Case("true_us", 0x1F)
2433  .Default(~0U);
2434  if (CC != ~0U && (IsVCMP || CC < 8)) {
2435  if (PatchedName.endswith("ss"))
2436  PatchedName = IsVCMP ? "vcmpss" : "cmpss";
2437  else if (PatchedName.endswith("sd"))
2438  PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
2439  else if (PatchedName.endswith("ps"))
2440  PatchedName = IsVCMP ? "vcmpps" : "cmpps";
2441  else if (PatchedName.endswith("pd"))
2442  PatchedName = IsVCMP ? "vcmppd" : "cmppd";
2443  else
2444  llvm_unreachable("Unexpecte suffix!");
2445 
2446  ComparisonCode = CC;
2447  }
2448  }
2449 
2450  // FIXME: Hack to recognize vpcmp<comparison code>{ub,uw,ud,uq,b,w,d,q}.
2451  if (PatchedName.startswith("vpcmp") &&
2452  (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
2453  PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
2454  unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
2455  unsigned CC = StringSwitch<unsigned>(
2456  PatchedName.slice(5, PatchedName.size() - SuffixSize))
2457  .Case("eq", 0x0) // Only allowed on unsigned. Checked below.
2458  .Case("lt", 0x1)
2459  .Case("le", 0x2)
2460  //.Case("false", 0x3) // Not a documented alias.
2461  .Case("neq", 0x4)
2462  .Case("nlt", 0x5)
2463  .Case("nle", 0x6)
2464  //.Case("true", 0x7) // Not a documented alias.
2465  .Default(~0U);
2466  if (CC != ~0U && (CC != 0 || SuffixSize == 2)) {
2467  switch (PatchedName.back()) {
2468  default: llvm_unreachable("Unexpected character!");
2469  case 'b': PatchedName = SuffixSize == 2 ? "vpcmpub" : "vpcmpb"; break;
2470  case 'w': PatchedName = SuffixSize == 2 ? "vpcmpuw" : "vpcmpw"; break;
2471  case 'd': PatchedName = SuffixSize == 2 ? "vpcmpud" : "vpcmpd"; break;
2472  case 'q': PatchedName = SuffixSize == 2 ? "vpcmpuq" : "vpcmpq"; break;
2473  }
2474  // Set up the immediate to push into the operands later.
2475  ComparisonCode = CC;
2476  }
2477  }
2478 
2479  // FIXME: Hack to recognize vpcom<comparison code>{ub,uw,ud,uq,b,w,d,q}.
2480  if (PatchedName.startswith("vpcom") &&
2481  (PatchedName.back() == 'b' || PatchedName.back() == 'w' ||
2482  PatchedName.back() == 'd' || PatchedName.back() == 'q')) {
2483  unsigned SuffixSize = PatchedName.drop_back().back() == 'u' ? 2 : 1;
2484  unsigned CC = StringSwitch<unsigned>(
2485  PatchedName.slice(5, PatchedName.size() - SuffixSize))
2486  .Case("lt", 0x0)
2487  .Case("le", 0x1)
2488  .Case("gt", 0x2)
2489  .Case("ge", 0x3)
2490  .Case("eq", 0x4)
2491  .Case("neq", 0x5)
2492  .Case("false", 0x6)
2493  .Case("true", 0x7)
2494  .Default(~0U);
2495  if (CC != ~0U) {
2496  switch (PatchedName.back()) {
2497  default: llvm_unreachable("Unexpected character!");
2498  case 'b': PatchedName = SuffixSize == 2 ? "vpcomub" : "vpcomb"; break;
2499  case 'w': PatchedName = SuffixSize == 2 ? "vpcomuw" : "vpcomw"; break;
2500  case 'd': PatchedName = SuffixSize == 2 ? "vpcomud" : "vpcomd"; break;
2501  case 'q': PatchedName = SuffixSize == 2 ? "vpcomuq" : "vpcomq"; break;
2502  }
2503  // Set up the immediate to push into the operands later.
2504  ComparisonCode = CC;
2505  }
2506  }
2507 
2508 
2509  // Determine whether this is an instruction prefix.
2510  // FIXME:
2511  // Enhance prefixes integrity robustness. for example, following forms
2512  // are currently tolerated:
2513  // repz repnz <insn> ; GAS errors for the use of two similar prefixes
2514  // lock addq %rax, %rbx ; Destination operand must be of memory type
2515  // xacquire <insn> ; xacquire must be accompanied by 'lock'
2517  .Cases("rex64", "data32", "data16", true)
2518  .Cases("xacquire", "xrelease", true)
2519  .Cases("acquire", "release", isParsingIntelSyntax())
2520  .Default(false);
2521 
2522  auto isLockRepeatNtPrefix = [](StringRef N) {
2523  return StringSwitch<bool>(N)
2524  .Cases("lock", "rep", "repe", "repz", "repne", "repnz", "notrack", true)
2525  .Default(false);
2526  };
2527 
2528  bool CurlyAsEndOfStatement = false;
2529 
2530  unsigned Flags = X86::IP_NO_PREFIX;
2531  while (isLockRepeatNtPrefix(Name.lower())) {
2532  unsigned Prefix =
2534  .Cases("lock", "lock", X86::IP_HAS_LOCK)
2535  .Cases("rep", "repe", "repz", X86::IP_HAS_REPEAT)
2536  .Cases("repne", "repnz", X86::IP_HAS_REPEAT_NE)
2537  .Cases("notrack", "notrack", X86::IP_HAS_NOTRACK)
2538  .Default(X86::IP_NO_PREFIX); // Invalid prefix (impossible)
2539  Flags |= Prefix;
2540  if (getLexer().is(AsmToken::EndOfStatement)) {
2541  // We don't have real instr with the given prefix
2542  // let's use the prefix as the instr.
2543  // TODO: there could be several prefixes one after another
2544  Flags = X86::IP_NO_PREFIX;
2545  break;
2546  }
2547  // FIXME: The mnemonic won't match correctly if its not in lower case.
2548  Name = Parser.getTok().getString();
2549  Parser.Lex(); // eat the prefix
2550  // Hack: we could have something like "rep # some comment" or
2551  // "lock; cmpxchg16b $1" or "lock\0A\09incl" or "lock/incl"
2552  while (Name.startswith(";") || Name.startswith("\n") ||
2553  Name.startswith("#") || Name.startswith("\t") ||
2554  Name.startswith("/")) {
2555  // FIXME: The mnemonic won't match correctly if its not in lower case.
2556  Name = Parser.getTok().getString();
2557  Parser.Lex(); // go to next prefix or instr
2558  }
2559  }
2560 
2561  if (Flags)
2562  PatchedName = Name;
2563 
2564  // Hacks to handle 'data16' and 'data32'
2565  if (PatchedName == "data16" && is16BitMode()) {
2566  return Error(NameLoc, "redundant data16 prefix");
2567  }
2568  if (PatchedName == "data32") {
2569  if (is32BitMode())
2570  return Error(NameLoc, "redundant data32 prefix");
2571  if (is64BitMode())
2572  return Error(NameLoc, "'data32' is not supported in 64-bit mode");
2573  // Hack to 'data16' for the table lookup.
2574  PatchedName = "data16";
2575  }
2576 
2577  Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
2578 
2579  // Push the immediate if we extracted one from the mnemonic.
2580  if (ComparisonCode != ~0U && !isParsingIntelSyntax()) {
2581  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
2582  getParser().getContext());
2583  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2584  }
2585 
2586  // This does the actual operand parsing. Don't parse any more if we have a
2587  // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
2588  // just want to parse the "lock" as the first instruction and the "incl" as
2589  // the next one.
2590  if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
2591  // Parse '*' modifier.
2592  if (getLexer().is(AsmToken::Star))
2593  Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
2594 
2595  // Read the operands.
2596  while(1) {
2597  if (std::unique_ptr<X86Operand> Op = ParseOperand()) {
2598  Operands.push_back(std::move(Op));
2599  if (HandleAVX512Operand(Operands, *Operands.back()))
2600  return true;
2601  } else {
2602  return true;
2603  }
2604  // check for comma and eat it
2605  if (getLexer().is(AsmToken::Comma))
2606  Parser.Lex();
2607  else
2608  break;
2609  }
2610 
2611  // In MS inline asm curly braces mark the beginning/end of a block,
2612  // therefore they should be interepreted as end of statement
2613  CurlyAsEndOfStatement =
2614  isParsingIntelSyntax() && isParsingInlineAsm() &&
2615  (getLexer().is(AsmToken::LCurly) || getLexer().is(AsmToken::RCurly));
2616  if (getLexer().isNot(AsmToken::EndOfStatement) && !CurlyAsEndOfStatement)
2617  return TokError("unexpected token in argument list");
2618  }
2619 
2620  // Push the immediate if we extracted one from the mnemonic.
2621  if (ComparisonCode != ~0U && isParsingIntelSyntax()) {
2622  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
2623  getParser().getContext());
2624  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2625  }
2626 
2627  // Consume the EndOfStatement or the prefix separator Slash
2628  if (getLexer().is(AsmToken::EndOfStatement) ||
2629  (isPrefix && getLexer().is(AsmToken::Slash)))
2630  Parser.Lex();
2631  else if (CurlyAsEndOfStatement)
2632  // Add an actual EndOfStatement before the curly brace
2633  Info.AsmRewrites->emplace_back(AOK_EndOfStatement,
2634  getLexer().getTok().getLoc(), 0);
2635 
2636  // This is for gas compatibility and cannot be done in td.
2637  // Adding "p" for some floating point with no argument.
2638  // For example: fsub --> fsubp
2639  bool IsFp =
2640  Name == "fsub" || Name == "fdiv" || Name == "fsubr" || Name == "fdivr";
2641  if (IsFp && Operands.size() == 1) {
2642  const char *Repl = StringSwitch<const char *>(Name)
2643  .Case("fsub", "fsubp")
2644  .Case("fdiv", "fdivp")
2645  .Case("fsubr", "fsubrp")
2646  .Case("fdivr", "fdivrp");
2647  static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl);
2648  }
2649 
2650  // Moving a 32 or 16 bit value into a segment register has the same
2651  // behavior. Modify such instructions to always take shorter form.
2652  if ((Name == "mov" || Name == "movw" || Name == "movl") &&
2653  (Operands.size() == 3)) {
2654  X86Operand &Op1 = (X86Operand &)*Operands[1];
2655  X86Operand &Op2 = (X86Operand &)*Operands[2];
2656  SMLoc Loc = Op1.getEndLoc();
2657  if (Op1.isReg() && Op2.isReg() &&
2658  X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(
2659  Op2.getReg()) &&
2660  (X86MCRegisterClasses[X86::GR16RegClassID].contains(Op1.getReg()) ||
2661  X86MCRegisterClasses[X86::GR32RegClassID].contains(Op1.getReg()))) {
2662  // Change instruction name to match new instruction.
2663  if (Name != "mov" && Name[3] == (is16BitMode() ? 'l' : 'w')) {
2664  Name = is16BitMode() ? "movw" : "movl";
2665  Operands[0] = X86Operand::CreateToken(Name, NameLoc);
2666  }
2667  // Select the correct equivalent 16-/32-bit source register.
2668  unsigned Reg =
2669  getX86SubSuperRegisterOrZero(Op1.getReg(), is16BitMode() ? 16 : 32);
2670  Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc);
2671  }
2672  }
2673 
2674  // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
2675  // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
2676  // documented form in various unofficial manuals, so a lot of code uses it.
2677  if ((Name == "outb" || Name == "outsb" || Name == "outw" || Name == "outsw" ||
2678  Name == "outl" || Name == "outsl" || Name == "out" || Name == "outs") &&
2679  Operands.size() == 3) {
2680  X86Operand &Op = (X86Operand &)*Operands.back();
2681  if (Op.isDXReg())
2682  Operands.back() = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
2683  Op.getEndLoc());
2684  }
2685  // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al".
2686  if ((Name == "inb" || Name == "insb" || Name == "inw" || Name == "insw" ||
2687  Name == "inl" || Name == "insl" || Name == "in" || Name == "ins") &&
2688  Operands.size() == 3) {
2689  X86Operand &Op = (X86Operand &)*Operands[1];
2690  if (Op.isDXReg())
2691  Operands[1] = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
2692  Op.getEndLoc());
2693  }
2694 
2696  bool HadVerifyError = false;
2697 
2698  // Append default arguments to "ins[bwld]"
2699  if (Name.startswith("ins") &&
2700  (Operands.size() == 1 || Operands.size() == 3) &&
2701  (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
2702  Name == "ins")) {
2703 
2704  AddDefaultSrcDestOperands(TmpOperands,
2705  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),
2706  DefaultMemDIOperand(NameLoc));
2707  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2708  }
2709 
2710  // Append default arguments to "outs[bwld]"
2711  if (Name.startswith("outs") &&
2712  (Operands.size() == 1 || Operands.size() == 3) &&
2713  (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
2714  Name == "outsd" || Name == "outs")) {
2715  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
2716  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2717  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2718  }
2719 
2720  // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
2721  // values of $SIREG according to the mode. It would be nice if this
2722  // could be achieved with InstAlias in the tables.
2723  if (Name.startswith("lods") &&
2724  (Operands.size() == 1 || Operands.size() == 2) &&
2725  (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
2726  Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) {
2727  TmpOperands.push_back(DefaultMemSIOperand(NameLoc));
2728  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2729  }
2730 
2731  // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
2732  // values of $DIREG according to the mode. It would be nice if this
2733  // could be achieved with InstAlias in the tables.
2734  if (Name.startswith("stos") &&
2735  (Operands.size() == 1 || Operands.size() == 2) &&
2736  (Name == "stos" || Name == "stosb" || Name == "stosw" ||
2737  Name == "stosl" || Name == "stosd" || Name == "stosq")) {
2738  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
2739  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2740  }
2741 
2742  // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
2743  // values of $DIREG according to the mode. It would be nice if this
2744  // could be achieved with InstAlias in the tables.
2745  if (Name.startswith("scas") &&
2746  (Operands.size() == 1 || Operands.size() == 2) &&
2747  (Name == "scas" || Name == "scasb" || Name == "scasw" ||
2748  Name == "scasl" || Name == "scasd" || Name == "scasq")) {
2749  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
2750  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2751  }
2752 
2753  // Add default SI and DI operands to "cmps[bwlq]".
2754  if (Name.startswith("cmps") &&
2755  (Operands.size() == 1 || Operands.size() == 3) &&
2756  (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
2757  Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
2758  AddDefaultSrcDestOperands(TmpOperands, DefaultMemDIOperand(NameLoc),
2759  DefaultMemSIOperand(NameLoc));
2760  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2761  }
2762 
2763  // Add default SI and DI operands to "movs[bwlq]".
2764  if (((Name.startswith("movs") &&
2765  (Name == "movs" || Name == "movsb" || Name == "movsw" ||
2766  Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
2767  (Name.startswith("smov") &&
2768  (Name == "smov" || Name == "smovb" || Name == "smovw" ||
2769  Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
2770  (Operands.size() == 1 || Operands.size() == 3)) {
2771  if (Name == "movsd" && Operands.size() == 1 && !isParsingIntelSyntax())
2772  Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
2773  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
2774  DefaultMemDIOperand(NameLoc));
2775  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2776  }
2777 
2778  // Check if we encountered an error for one the string insturctions
2779  if (HadVerifyError) {
2780  return HadVerifyError;
2781  }
2782 
2783  // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
2784  // "shift <op>".
2785  if ((Name.startswith("shr") || Name.startswith("sar") ||
2786  Name.startswith("shl") || Name.startswith("sal") ||
2787  Name.startswith("rcl") || Name.startswith("rcr") ||
2788  Name.startswith("rol") || Name.startswith("ror")) &&
2789  Operands.size() == 3) {
2790  if (isParsingIntelSyntax()) {
2791  // Intel syntax
2792  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[2]);
2793  if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) &&
2794  cast<MCConstantExpr>(Op1.getImm())->getValue() == 1)
2795  Operands.pop_back();
2796  } else {
2797  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2798  if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) &&
2799  cast<MCConstantExpr>(Op1.getImm())->getValue() == 1)
2800  Operands.erase(Operands.begin() + 1);
2801  }
2802  }
2803 
2804  // Transforms "int $3" into "int3" as a size optimization. We can't write an
2805  // instalias with an immediate operand yet.
2806  if (Name == "int" && Operands.size() == 2) {
2807  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2808  if (Op1.isImm())
2809  if (auto *CE = dyn_cast<MCConstantExpr>(Op1.getImm()))
2810  if (CE->getValue() == 3) {
2811  Operands.erase(Operands.begin() + 1);
2812  static_cast<X86Operand &>(*Operands[0]).setTokenValue("int3");
2813  }
2814  }
2815 
2816  // Transforms "xlat mem8" into "xlatb"
2817  if ((Name == "xlat" || Name == "xlatb") && Operands.size() == 2) {
2818  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2819  if (Op1.isMem8()) {
2820  Warning(Op1.getStartLoc(), "memory operand is only for determining the "
2821  "size, (R|E)BX will be used for the location");
2822  Operands.pop_back();
2823  static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb");
2824  }
2825  }
2826 
2827  if (Flags)
2828  Operands.push_back(X86Operand::CreatePrefix(Flags, NameLoc, NameLoc));
2829  return false;
2830 }
2831 
2832 bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
2833  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
2834 
2835  switch (Inst.getOpcode()) {
2836  default: return false;
2837  case X86::VMOVZPQILo2PQIrr:
2838  case X86::VMOVAPDrr:
2839  case X86::VMOVAPDYrr:
2840  case X86::VMOVAPSrr:
2841  case X86::VMOVAPSYrr:
2842  case X86::VMOVDQArr:
2843  case X86::VMOVDQAYrr:
2844  case X86::VMOVDQUrr:
2845  case X86::VMOVDQUYrr:
2846  case X86::VMOVUPDrr:
2847  case X86::VMOVUPDYrr:
2848  case X86::VMOVUPSrr:
2849  case X86::VMOVUPSYrr: {
2850  // We can get a smaller encoding by using VEX.R instead of VEX.B if one of
2851  // the registers is extended, but other isn't.
2852  if (ForcedVEXEncoding == VEXEncoding_VEX3 ||
2853  MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 ||
2854  MRI->getEncodingValue(Inst.getOperand(1).getReg()) < 8)
2855  return false;
2856 
2857  unsigned NewOpc;
2858  switch (Inst.getOpcode()) {
2859  default: llvm_unreachable("Invalid opcode");
2860  case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
2861  case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
2862  case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
2863  case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
2864  case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
2865  case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
2866  case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
2867  case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
2868  case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
2869  case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
2870  case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
2871  case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
2872  case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
2873  }
2874  Inst.setOpcode(NewOpc);
2875  return true;
2876  }
2877  case X86::VMOVSDrr:
2878  case X86::VMOVSSrr: {
2879  // We can get a smaller encoding by using VEX.R instead of VEX.B if one of
2880  // the registers is extended, but other isn't.
2881  if (ForcedVEXEncoding == VEXEncoding_VEX3 ||
2882  MRI->getEncodingValue(Inst.getOperand(0).getReg()) >= 8 ||
2883  MRI->getEncodingValue(Inst.getOperand(2).getReg()) < 8)
2884  return false;
2885 
2886  unsigned NewOpc;
2887  switch (Inst.getOpcode()) {
2888  default: llvm_unreachable("Invalid opcode");
2889  case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
2890  case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
2891  }
2892  Inst.setOpcode(NewOpc);
2893  return true;
2894  }
2895  }
2896 }
2897 
2898 bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
2899  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
2900 
2901  switch (Inst.getOpcode()) {
2902  case X86::VGATHERDPDYrm:
2903  case X86::VGATHERDPDrm:
2904  case X86::VGATHERDPSYrm:
2905  case X86::VGATHERDPSrm:
2906  case X86::VGATHERQPDYrm:
2907  case X86::VGATHERQPDrm:
2908  case X86::VGATHERQPSYrm:
2909  case X86::VGATHERQPSrm:
2910  case X86::VPGATHERDDYrm:
2911  case X86::VPGATHERDDrm:
2912  case X86::VPGATHERDQYrm:
2913  case X86::VPGATHERDQrm:
2914  case X86::VPGATHERQDYrm:
2915  case X86::VPGATHERQDrm:
2916  case X86::VPGATHERQQYrm:
2917  case X86::VPGATHERQQrm: {
2918  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
2919  unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg());
2920  unsigned Index =
2922  if (Dest == Mask || Dest == Index || Mask == Index)
2923  return Warning(Ops[0]->getStartLoc(), "mask, index, and destination "
2924  "registers should be distinct");
2925  break;
2926  }
2927  case X86::VGATHERDPDZ128rm:
2928  case X86::VGATHERDPDZ256rm:
2929  case X86::VGATHERDPDZrm:
2930  case X86::VGATHERDPSZ128rm:
2931  case X86::VGATHERDPSZ256rm:
2932  case X86::VGATHERDPSZrm:
2933  case X86::VGATHERQPDZ128rm:
2934  case X86::VGATHERQPDZ256rm:
2935  case X86::VGATHERQPDZrm:
2936  case X86::VGATHERQPSZ128rm:
2937  case X86::VGATHERQPSZ256rm:
2938  case X86::VGATHERQPSZrm:
2939  case X86::VPGATHERDDZ128rm:
2940  case X86::VPGATHERDDZ256rm:
2941  case X86::VPGATHERDDZrm:
2942  case X86::VPGATHERDQZ128rm:
2943  case X86::VPGATHERDQZ256rm:
2944  case X86::VPGATHERDQZrm:
2945  case X86::VPGATHERQDZ128rm:
2946  case X86::VPGATHERQDZ256rm:
2947  case X86::VPGATHERQDZrm:
2948  case X86::VPGATHERQQZ128rm:
2949  case X86::VPGATHERQQZ256rm:
2950  case X86::VPGATHERQQZrm: {
2951  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
2952  unsigned Index =
2954  if (Dest == Index)
2955  return Warning(Ops[0]->getStartLoc(), "index and destination registers "
2956  "should be distinct");
2957  break;
2958  }
2959  case X86::V4FMADDPSrm:
2960  case X86::V4FMADDPSrmk:
2961  case X86::V4FMADDPSrmkz:
2962  case X86::V4FMADDSSrm:
2963  case X86::V4FMADDSSrmk:
2964  case X86::V4FMADDSSrmkz:
2965  case X86::V4FNMADDPSrm:
2966  case X86::V4FNMADDPSrmk:
2967  case X86::V4FNMADDPSrmkz:
2968  case X86::V4FNMADDSSrm:
2969  case X86::V4FNMADDSSrmk:
2970  case X86::V4FNMADDSSrmkz:
2971  case X86::VP4DPWSSDSrm:
2972  case X86::VP4DPWSSDSrmk:
2973  case X86::VP4DPWSSDSrmkz:
2974  case X86::VP4DPWSSDrm:
2975  case X86::VP4DPWSSDrmk:
2976  case X86::VP4DPWSSDrmkz: {
2977  unsigned Src2 = Inst.getOperand(Inst.getNumOperands() -
2979  unsigned Src2Enc = MRI->getEncodingValue(Src2);
2980  if (Src2Enc % 4 != 0) {
2982  unsigned GroupStart = (Src2Enc / 4) * 4;
2983  unsigned GroupEnd = GroupStart + 3;
2984  return Warning(Ops[0]->getStartLoc(),
2985  "source register '" + RegName + "' implicitly denotes '" +
2986  RegName.take_front(3) + Twine(GroupStart) + "' to '" +
2987  RegName.take_front(3) + Twine(GroupEnd) +
2988  "' source group");
2989  }
2990  break;
2991  }
2992  }
2993 
2994  return false;
2995 }
2996 
2997 static const char *getSubtargetFeatureName(uint64_t Val);
2998 
2999 void X86AsmParser::EmitInstruction(MCInst &Inst, OperandVector &Operands,
3000  MCStreamer &Out) {
3001  Out.EmitInstruction(Inst, getSTI());
3002 }
3003 
3004 bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
3005  OperandVector &Operands,
3006  MCStreamer &Out, uint64_t &ErrorInfo,
3007  bool MatchingInlineAsm) {
3008  if (isParsingIntelSyntax())
3009  return MatchAndEmitIntelInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
3010  MatchingInlineAsm);
3011  return MatchAndEmitATTInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
3012  MatchingInlineAsm);
3013 }
3014 
3015 void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op,
3016  OperandVector &Operands, MCStreamer &Out,
3017  bool MatchingInlineAsm) {
3018  // FIXME: This should be replaced with a real .td file alias mechanism.
3019  // Also, MatchInstructionImpl should actually *do* the EmitInstruction
3020  // call.
3021  const char *Repl = StringSwitch<const char *>(Op.getToken())
3022  .Case("finit", "fninit")
3023  .Case("fsave", "fnsave")
3024  .Case("fstcw", "fnstcw")
3025  .Case("fstcww", "fnstcw")
3026  .Case("fstenv", "fnstenv")
3027  .Case("fstsw", "fnstsw")
3028  .Case("fstsww", "fnstsw")
3029  .Case("fclex", "fnclex")
3030  .Default(nullptr);
3031  if (Repl) {
3032  MCInst Inst;
3033  Inst.setOpcode(X86::WAIT);
3034  Inst.setLoc(IDLoc);
3035  if (!MatchingInlineAsm)
3036  EmitInstruction(Inst, Operands, Out);
3037  Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
3038  }
3039 }
3040 
3041 bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc,
3042  const FeatureBitset &MissingFeatures,
3043  bool MatchingInlineAsm) {
3044  assert(MissingFeatures.any() && "Unknown missing feature!");
3045  SmallString<126> Msg;
3046  raw_svector_ostream OS(Msg);
3047  OS << "instruction requires:";
3048  for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) {
3049  if (MissingFeatures[i])
3050  OS << ' ' << getSubtargetFeatureName(i);
3051  }
3052  return Error(IDLoc, OS.str(), SMRange(), MatchingInlineAsm);
3053 }
3054 
3055 static unsigned getPrefixes(OperandVector &Operands) {
3056  unsigned Result = 0;
3057  X86Operand &Prefix = static_cast<X86Operand &>(*Operands.back());
3058  if (Prefix.isPrefix()) {
3059  Result = Prefix.getPrefix();
3060  Operands.pop_back();
3061  }
3062  return Result;
3063 }
3064 
3065 unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3066  unsigned Opc = Inst.getOpcode();
3067  const MCInstrDesc &MCID = MII.get(Opc);
3068 
3069  if (ForcedVEXEncoding == VEXEncoding_EVEX &&
3071  return Match_Unsupported;
3072 
3073  if ((ForcedVEXEncoding == VEXEncoding_VEX2 ||
3074  ForcedVEXEncoding == VEXEncoding_VEX3) &&
3076  return Match_Unsupported;
3077 
3078  // These instructions match ambiguously with their VEX encoded counterparts
3079  // and appear first in the matching table. Reject them unless we're forcing
3080  // EVEX encoding.
3081  // FIXME: We really need a way to break the ambiguity.
3082  switch (Opc) {
3083  case X86::VCVTSD2SIZrm_Int:
3084  case X86::VCVTSD2SI64Zrm_Int:
3085  case X86::VCVTSS2SIZrm_Int:
3086  case X86::VCVTSS2SI64Zrm_Int:
3087  case X86::VCVTTSD2SIZrm: case X86::VCVTTSD2SIZrm_Int:
3088  case X86::VCVTTSD2SI64Zrm: case X86::VCVTTSD2SI64Zrm_Int:
3089  case X86::VCVTTSS2SIZrm: case X86::VCVTTSS2SIZrm_Int:
3090  case X86::VCVTTSS2SI64Zrm: case X86::VCVTTSS2SI64Zrm_Int:
3091  if (ForcedVEXEncoding != VEXEncoding_EVEX)
3092  return Match_Unsupported;
3093  }
3094 
3095  return Match_Success;
3096 }
3097 
3098 bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
3099  OperandVector &Operands,
3100  MCStreamer &Out,
3101  uint64_t &ErrorInfo,
3102  bool MatchingInlineAsm) {
3103  assert(!Operands.empty() && "Unexpect empty operand list!");
3104  assert((*Operands[0]).isToken() && "Leading operand should always be a mnemonic!");
3105  SMRange EmptyRange = None;
3106 
3107  // First, handle aliases that expand to multiple instructions.
3108  MatchFPUWaitAlias(IDLoc, static_cast<X86Operand &>(*Operands[0]), Operands,
3109  Out, MatchingInlineAsm);
3110  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
3111  unsigned Prefixes = getPrefixes(Operands);
3112 
3113  MCInst Inst;
3114 
3115  // If VEX3 encoding is forced, we need to pass the USE_VEX3 flag to the
3116  // encoder.
3117  if (ForcedVEXEncoding == VEXEncoding_VEX3)
3118  Prefixes |= X86::IP_USE_VEX3;
3119 
3120  if (Prefixes)
3121  Inst.setFlags(Prefixes);
3122 
3123  // First, try a direct match.
3124  FeatureBitset MissingFeatures;
3125  unsigned OriginalError = MatchInstruction(Operands, Inst, ErrorInfo,
3126  MissingFeatures, MatchingInlineAsm,
3127  isParsingIntelSyntax());
3128  switch (OriginalError) {
3129  default: llvm_unreachable("Unexpected match result!");
3130  case Match_Success:
3131  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
3132  return true;
3133  // Some instructions need post-processing to, for example, tweak which
3134  // encoding is selected. Loop on it while changes happen so the
3135  // individual transformations can chain off each other.
3136  if (!MatchingInlineAsm)
3137  while (processInstruction(Inst, Operands))
3138  ;
3139 
3140  Inst.setLoc(IDLoc);
3141  if (!MatchingInlineAsm)
3142  EmitInstruction(Inst, Operands, Out);
3143  Opcode = Inst.getOpcode();
3144  return false;
3145  case Match_MissingFeature:
3146  return ErrorMissingFeature(IDLoc, MissingFeatures, MatchingInlineAsm);
3147  case Match_InvalidOperand:
3148  case Match_MnemonicFail:
3149  case Match_Unsupported:
3150  break;
3151  }
3152  if (Op.getToken().empty()) {
3153  Error(IDLoc, "instruction must have size higher than 0", EmptyRange,
3154  MatchingInlineAsm);
3155  return true;
3156  }
3157 
3158  // FIXME: Ideally, we would only attempt suffix matches for things which are
3159  // valid prefixes, and we could just infer the right unambiguous
3160  // type. However, that requires substantially more matcher support than the
3161  // following hack.
3162 
3163  // Change the operand to point to a temporary token.
3164  StringRef Base = Op.getToken();
3165  SmallString<16> Tmp;
3166  Tmp += Base;
3167  Tmp += ' ';
3168  Op.setTokenValue(Tmp);
3169 
3170  // If this instruction starts with an 'f', then it is a floating point stack
3171  // instruction. These come in up to three forms for 32-bit, 64-bit, and
3172  // 80-bit floating point, which use the suffixes s,l,t respectively.
3173  //
3174  // Otherwise, we assume that this may be an integer instruction, which comes
3175  // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
3176  const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
3177 
3178  // Check for the various suffix matches.
3179  uint64_t ErrorInfoIgnore;
3180  FeatureBitset ErrorInfoMissingFeatures; // Init suppresses compiler warnings.
3181  unsigned Match[4];
3182 
3183  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) {
3184  Tmp.back() = Suffixes[I];
3185  Match[I] = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
3186  MissingFeatures, MatchingInlineAsm,
3187  isParsingIntelSyntax());
3188  // If this returned as a missing feature failure, remember that.
3189  if (Match[I] == Match_MissingFeature)
3190  ErrorInfoMissingFeatures = MissingFeatures;
3191  }
3192 
3193  // Restore the old token.
3194  Op.setTokenValue(Base);
3195 
3196  // If exactly one matched, then we treat that as a successful match (and the
3197  // instruction will already have been filled in correctly, since the failing
3198  // matches won't have modified it).
3199  unsigned NumSuccessfulMatches =
3200  std::count(std::begin(Match), std::end(Match), Match_Success);
3201  if (NumSuccessfulMatches == 1) {
3202  Inst.setLoc(IDLoc);
3203  if (!MatchingInlineAsm)
3204  EmitInstruction(Inst, Operands, Out);
3205  Opcode = Inst.getOpcode();
3206  return false;
3207  }
3208 
3209  // Otherwise, the match failed, try to produce a decent error message.
3210 
3211  // If we had multiple suffix matches, then identify this as an ambiguous
3212  // match.
3213  if (NumSuccessfulMatches > 1) {
3214  char MatchChars[4];
3215  unsigned NumMatches = 0;
3216  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I)
3217  if (Match[I] == Match_Success)
3218  MatchChars[NumMatches++] = Suffixes[I];
3219 
3220  SmallString<126> Msg;
3221  raw_svector_ostream OS(Msg);
3222  OS << "ambiguous instructions require an explicit suffix (could be ";
3223  for (unsigned i = 0; i != NumMatches; ++i) {
3224  if (i != 0)
3225  OS << ", ";
3226  if (i + 1 == NumMatches)
3227  OS << "or ";
3228  OS << "'" << Base << MatchChars[i] << "'";
3229  }
3230  OS << ")";
3231  Error(IDLoc, OS.str(), EmptyRange, MatchingInlineAsm);
3232  return true;
3233  }
3234 
3235  // Okay, we know that none of the variants matched successfully.
3236 
3237  // If all of the instructions reported an invalid mnemonic, then the original
3238  // mnemonic was invalid.
3239  if (std::count(std::begin(Match), std::end(Match), Match_MnemonicFail) == 4) {
3240  if (OriginalError == Match_MnemonicFail)
3241  return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
3242  Op.getLocRange(), MatchingInlineAsm);
3243 
3244  if (OriginalError == Match_Unsupported)
3245  return Error(IDLoc, "unsupported instruction", EmptyRange,
3246  MatchingInlineAsm);
3247 
3248  assert(OriginalError == Match_InvalidOperand && "Unexpected error");
3249  // Recover location info for the operand if we know which was the problem.
3250  if (ErrorInfo != ~0ULL) {
3251  if (ErrorInfo >= Operands.size())
3252  return Error(IDLoc, "too few operands for instruction", EmptyRange,
3253  MatchingInlineAsm);
3254 
3255  X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo];
3256  if (Operand.getStartLoc().isValid()) {
3257  SMRange OperandRange = Operand.getLocRange();
3258  return Error(Operand.getStartLoc(), "invalid operand for instruction",
3259  OperandRange, MatchingInlineAsm);
3260  }
3261  }
3262 
3263  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
3264  MatchingInlineAsm);
3265  }
3266 
3267  // If one instruction matched as unsupported, report this as unsupported.
3268  if (std::count(std::begin(Match), std::end(Match),
3269  Match_Unsupported) == 1) {
3270  return Error(IDLoc, "unsupported instruction", EmptyRange,
3271  MatchingInlineAsm);
3272  }
3273 
3274  // If one instruction matched with a missing feature, report this as a
3275  // missing feature.
3276  if (std::count(std::begin(Match), std::end(Match),
3277  Match_MissingFeature) == 1) {
3278  ErrorInfo = Match_MissingFeature;
3279  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeatures,
3280  MatchingInlineAsm);
3281  }
3282 
3283  // If one instruction matched with an invalid operand, report this as an
3284  // operand failure.
3285  if (std::count(std::begin(Match), std::end(Match),
3286  Match_InvalidOperand) == 1) {
3287  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
3288  MatchingInlineAsm);
3289  }
3290 
3291  // If all of these were an outright failure, report it in a useless way.
3292  Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
3293  EmptyRange, MatchingInlineAsm);
3294  return true;
3295 }
3296 
3297 bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
3298  OperandVector &Operands,
3299  MCStreamer &Out,
3300  uint64_t &ErrorInfo,
3301  bool MatchingInlineAsm) {
3302  assert(!Operands.empty() && "Unexpect empty operand list!");
3303  assert((*Operands[0]).isToken() && "Leading operand should always be a mnemonic!");
3304  StringRef Mnemonic = (static_cast<X86Operand &>(*Operands[0])).getToken();
3305  SMRange EmptyRange = None;
3306  StringRef Base = (static_cast<X86Operand &>(*Operands[0])).getToken();
3307  unsigned Prefixes = getPrefixes(Operands);
3308 
3309  // First, handle aliases that expand to multiple instructions.
3310  MatchFPUWaitAlias(IDLoc, static_cast<X86Operand &>(*Operands[0]), Operands, Out, MatchingInlineAsm);
3311  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
3312 
3313  MCInst Inst;
3314 
3315  // If VEX3 encoding is forced, we need to pass the USE_VEX3 flag to the
3316  // encoder.
3317  if (ForcedVEXEncoding == VEXEncoding_VEX3)
3318  Prefixes |= X86::IP_USE_VEX3;
3319 
3320  if (Prefixes)
3321  Inst.setFlags(Prefixes);
3322 
3323  // Find one unsized memory operand, if present.
3324  X86Operand *UnsizedMemOp = nullptr;
3325  for (const auto &Op : Operands) {
3326  X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
3327  if (X86Op->isMemUnsized()) {
3328  UnsizedMemOp = X86Op;
3329  // Have we found an unqualified memory operand,
3330  // break. IA allows only one memory operand.
3331  break;
3332  }
3333  }
3334 
3335  // Allow some instructions to have implicitly pointer-sized operands. This is
3336  // compatible with gas.
3337  if (UnsizedMemOp) {
3338  static const char *const PtrSizedInstrs[] = {"call", "jmp", "push"};
3339  for (const char *Instr : PtrSizedInstrs) {
3340  if (Mnemonic == Instr) {
3341  UnsizedMemOp->Mem.Size = getPointerWidth();
3342  break;
3343  }
3344  }
3345  }
3346 
3348  FeatureBitset ErrorInfoMissingFeatures;
3349  FeatureBitset MissingFeatures;
3350 
3351  // If unsized push has immediate operand we should default the default pointer
3352  // size for the size.
3353  if (Mnemonic == "push" && Operands.size() == 2) {
3354  auto *X86Op = static_cast<X86Operand *>(Operands[1].get());
3355  if (X86Op->isImm()) {
3356  // If it's not a constant fall through and let remainder take care of it.
3357  const auto *CE = dyn_cast<MCConstantExpr>(X86Op->getImm());
3358  unsigned Size = getPointerWidth();
3359  if (CE &&
3360  (isIntN(Size, CE->getValue()) || isUIntN(Size, CE->getValue()))) {
3361  SmallString<16> Tmp;
3362  Tmp += Base;
3363  Tmp += (is64BitMode())
3364  ? "q"
3365  : (is32BitMode()) ? "l" : (is16BitMode()) ? "w" : " ";
3366  Op.setTokenValue(Tmp);
3367  // Do match in ATT mode to allow explicit suffix usage.
3368  Match.push_back(MatchInstruction(Operands, Inst, ErrorInfo,
3369  MissingFeatures, MatchingInlineAsm,
3370  false /*isParsingIntelSyntax()*/));
3371  Op.setTokenValue(Base);
3372  }
3373  }
3374  }
3375 
3376  // If an unsized memory operand is present, try to match with each memory
3377  // operand size. In Intel assembly, the size is not part of the instruction
3378  // mnemonic.
3379  if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
3380  static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
3381  for (unsigned Size : MopSizes) {
3382  UnsizedMemOp->Mem.Size = Size;
3383  uint64_t ErrorInfoIgnore;
3384  unsigned LastOpcode = Inst.getOpcode();
3385  unsigned M = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
3386  MissingFeatures, MatchingInlineAsm,
3387  isParsingIntelSyntax());
3388  if (Match.empty() || LastOpcode != Inst.getOpcode())
3389  Match.push_back(M);
3390 
3391  // If this returned as a missing feature failure, remember that.
3392  if (Match.back() == Match_MissingFeature)
3393  ErrorInfoMissingFeatures = MissingFeatures;
3394  }
3395 
3396  // Restore the size of the unsized memory operand if we modified it.
3397  UnsizedMemOp->Mem.Size = 0;
3398  }
3399 
3400  // If we haven't matched anything yet, this is not a basic integer or FPU
3401  // operation. There shouldn't be any ambiguity in our mnemonic table, so try
3402  // matching with the unsized operand.
3403  if (Match.empty()) {
3404  Match.push_back(MatchInstruction(
3405  Operands, Inst, ErrorInfo, MissingFeatures, MatchingInlineAsm,
3406  isParsingIntelSyntax()));
3407  // If this returned as a missing feature failure, remember that.
3408  if (Match.back() == Match_MissingFeature)
3409  ErrorInfoMissingFeatures = MissingFeatures;
3410  }
3411 
3412  // Restore the size of the unsized memory operand if we modified it.
3413  if (UnsizedMemOp)
3414  UnsizedMemOp->Mem.Size = 0;
3415 
3416  // If it's a bad mnemonic, all results will be the same.
3417  if (Match.back() == Match_MnemonicFail) {
3418  return Error(IDLoc, "invalid instruction mnemonic '" + Mnemonic + "'",
3419  Op.getLocRange(), MatchingInlineAsm);
3420  }
3421 
3422  unsigned NumSuccessfulMatches =
3423  std::count(std::begin(Match), std::end(Match), Match_Success);
3424 
3425  // If matching was ambiguous and we had size information from the frontend,
3426  // try again with that. This handles cases like "movxz eax, m8/m16".
3427  if (UnsizedMemOp && NumSuccessfulMatches > 1 &&
3428  UnsizedMemOp->getMemFrontendSize()) {
3429  UnsizedMemOp->Mem.Size = UnsizedMemOp->getMemFrontendSize();
3430  unsigned M = MatchInstruction(
3431  Operands, Inst, ErrorInfo, MissingFeatures, MatchingInlineAsm,
3432  isParsingIntelSyntax());
3433  if (M == Match_Success)
3434  NumSuccessfulMatches = 1;
3435 
3436  // Add a rewrite that encodes the size information we used from the
3437  // frontend.
3438  InstInfo->AsmRewrites->emplace_back(
3439  AOK_SizeDirective, UnsizedMemOp->getStartLoc(),
3440  /*Len=*/0, UnsizedMemOp->getMemFrontendSize());
3441  }
3442 
3443  // If exactly one matched, then we treat that as a successful match (and the
3444  // instruction will already have been filled in correctly, since the failing
3445  // matches won't have modified it).
3446  if (NumSuccessfulMatches == 1) {
3447  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
3448  return true;
3449  // Some instructions need post-processing to, for example, tweak which
3450  // encoding is selected. Loop on it while changes happen so the individual
3451  // transformations can chain off each other.
3452  if (!MatchingInlineAsm)
3453  while (processInstruction(Inst, Operands))
3454  ;
3455  Inst.setLoc(IDLoc);
3456  if (!MatchingInlineAsm)
3457  EmitInstruction(Inst, Operands, Out);
3458  Opcode = Inst.getOpcode();
3459  return false;
3460  } else if (NumSuccessfulMatches > 1) {
3461  assert(UnsizedMemOp &&
3462  "multiple matches only possible with unsized memory operands");
3463  return Error(UnsizedMemOp->getStartLoc(),
3464  "ambiguous operand size for instruction '" + Mnemonic + "\'",
3465  UnsizedMemOp->getLocRange());
3466  }
3467 
3468  // If one instruction matched as unsupported, report this as unsupported.
3469  if (std::count(std::begin(Match), std::end(Match),
3470  Match_Unsupported) == 1) {
3471  return Error(IDLoc, "unsupported instruction", EmptyRange,
3472  MatchingInlineAsm);
3473  }
3474 
3475  // If one instruction matched with a missing feature, report this as a
3476  // missing feature.
3477  if (std::count(std::begin(Match), std::end(Match),
3478  Match_MissingFeature) == 1) {
3479  ErrorInfo = Match_MissingFeature;
3480  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeatures,
3481  MatchingInlineAsm);
3482  }
3483 
3484  // If one instruction matched with an invalid operand, report this as an
3485  // operand failure.
3486  if (std::count(std::begin(Match), std::end(Match),
3487  Match_InvalidOperand) == 1) {
3488  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
3489  MatchingInlineAsm);
3490  }
3491 
3492  // If all of these were an outright failure, report it in a useless way.
3493  return Error(IDLoc, "unknown instruction mnemonic", EmptyRange,
3494  MatchingInlineAsm);
3495 }
3496 
3497 bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
3498  return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
3499 }
3500 
3501 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
3502  MCAsmParser &Parser = getParser();
3503  StringRef IDVal = DirectiveID.getIdentifier();
3504  if (IDVal.startswith(".code"))
3505  return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
3506  else if (IDVal.startswith(".att_syntax")) {
3507  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3508  if (Parser.getTok().getString() == "prefix")
3509  Parser.Lex();
3510  else if (Parser.getTok().getString() == "noprefix")
3511  return Error(DirectiveID.getLoc(), "'.att_syntax noprefix' is not "
3512  "supported: registers must have a "
3513  "'%' prefix in .att_syntax");
3514  }
3515  getParser().setAssemblerDialect(0);
3516  return false;
3517  } else if (IDVal.startswith(".intel_syntax")) {
3518  getParser().setAssemblerDialect(1);
3519  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3520  if (Parser.getTok().getString() == "noprefix")
3521  Parser.Lex();
3522  else if (Parser.getTok().getString() == "prefix")
3523  return Error(DirectiveID.getLoc(), "'.intel_syntax prefix' is not "
3524  "supported: registers must not have "
3525  "a '%' prefix in .intel_syntax");
3526  }
3527  return false;
3528  } else if (IDVal == ".even")
3529  return parseDirectiveEven(DirectiveID.getLoc());
3530  else if (IDVal == ".cv_fpo_proc")
3531  return parseDirectiveFPOProc(DirectiveID.getLoc());
3532  else if (IDVal == ".cv_fpo_setframe")
3533  return parseDirectiveFPOSetFrame(DirectiveID.getLoc());
3534  else if (IDVal == ".cv_fpo_pushreg")
3535  return parseDirectiveFPOPushReg(DirectiveID.getLoc());
3536  else if (IDVal == ".cv_fpo_stackalloc")
3537  return parseDirectiveFPOStackAlloc(DirectiveID.getLoc());
3538  else if (IDVal == ".cv_fpo_stackalign")
3539  return parseDirectiveFPOStackAlign(DirectiveID.getLoc());
3540  else if (IDVal == ".cv_fpo_endprologue")
3541  return parseDirectiveFPOEndPrologue(DirectiveID.getLoc());
3542  else if (IDVal == ".cv_fpo_endproc")
3543  return parseDirectiveFPOEndProc(DirectiveID.getLoc());
3544 
3545  return true;
3546 }
3547 
3548 /// parseDirectiveEven
3549 /// ::= .even
3550 bool X86AsmParser::parseDirectiveEven(SMLoc L) {
3551  if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
3552  return false;
3553 
3554  const MCSection *Section = getStreamer().getCurrentSectionOnly();
3555  if (!Section) {
3556  getStreamer().InitSections(false);
3557  Section = getStreamer().getCurrentSectionOnly();
3558  }
3559  if (Section->UseCodeAlign())
3560  getStreamer().EmitCodeAlignment(2, 0);
3561  else
3562  getStreamer().EmitValueToAlignment(2, 0, 1, 0);
3563  return false;
3564 }
3565 
3566 /// ParseDirectiveCode
3567 /// ::= .code16 | .code32 | .code64
3568 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
3569  MCAsmParser &Parser = getParser();
3570  Code16GCC = false;
3571  if (IDVal == ".code16") {
3572  Parser.Lex();
3573  if (!is16BitMode()) {
3574  SwitchMode(X86::Mode16Bit);
3575  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3576  }
3577  } else if (IDVal == ".code16gcc") {
3578  // .code16gcc parses as if in 32-bit mode, but emits code in 16-bit mode.
3579  Parser.Lex();
3580  Code16GCC = true;
3581  if (!is16BitMode()) {
3582  SwitchMode(X86::Mode16Bit);
3583  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3584  }
3585  } else if (IDVal == ".code32") {
3586  Parser.Lex();
3587  if (!is32BitMode()) {
3588  SwitchMode(X86::Mode32Bit);
3589  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3590  }
3591  } else if (IDVal == ".code64") {
3592  Parser.Lex();
3593  if (!is64BitMode()) {
3594  SwitchMode(X86::Mode64Bit);
3595  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
3596  }
3597  } else {
3598  Error(L, "unknown directive " + IDVal);
3599  return false;
3600  }
3601 
3602  return false;
3603 }
3604 
3605 // .cv_fpo_proc foo
3606 bool X86AsmParser::parseDirectiveFPOProc(SMLoc L) {
3607  MCAsmParser &Parser = getParser();
3608  StringRef ProcName;
3609  int64_t ParamsSize;
3610  if (Parser.parseIdentifier(ProcName))
3611  return Parser.TokError("expected symbol name");
3612  if (Parser.parseIntToken(ParamsSize, "expected parameter byte count"))
3613  return true;
3614  if (!isUIntN(32, ParamsSize))
3615  return Parser.TokError("parameters size out of range");
3616  if (Parser.parseEOL("unexpected tokens"))
3617  return addErrorSuffix(" in '.cv_fpo_proc' directive");
3618  MCSymbol *ProcSym = getContext().getOrCreateSymbol(ProcName);
3619  return getTargetStreamer().emitFPOProc(ProcSym, ParamsSize, L);
3620 }
3621 
3622 // .cv_fpo_setframe ebp
3623 bool X86AsmParser::parseDirectiveFPOSetFrame(SMLoc L) {
3624  MCAsmParser &Parser = getParser();
3625  unsigned Reg;
3626  SMLoc DummyLoc;
3627  if (ParseRegister(Reg, DummyLoc, DummyLoc) ||
3628  Parser.parseEOL("unexpected tokens"))
3629  return addErrorSuffix(" in '.cv_fpo_setframe' directive");
3630  return getTargetStreamer().emitFPOSetFrame(Reg, L);
3631 }
3632 
3633 // .cv_fpo_pushreg ebx
3634 bool X86AsmParser::parseDirectiveFPOPushReg(SMLoc L) {
3635  MCAsmParser &Parser = getParser();
3636  unsigned Reg;
3637  SMLoc DummyLoc;
3638  if (ParseRegister(Reg, DummyLoc, DummyLoc) ||
3639  Parser.parseEOL("unexpected tokens"))
3640  return addErrorSuffix(" in '.cv_fpo_pushreg' directive");
3641  return getTargetStreamer().emitFPOPushReg(Reg, L);
3642 }
3643 
3644 // .cv_fpo_stackalloc 20
3645 bool X86AsmParser::parseDirectiveFPOStackAlloc(SMLoc L) {
3646  MCAsmParser &Parser = getParser();
3647  int64_t Offset;
3648  if (Parser.parseIntToken(Offset, "expected offset") ||
3649  Parser.parseEOL("unexpected tokens"))
3650  return addErrorSuffix(" in '.cv_fpo_stackalloc' directive");
3651  return getTargetStreamer().emitFPOStackAlloc(Offset, L);
3652 }
3653 
3654 // .cv_fpo_stackalign 8
3655 bool X86AsmParser::parseDirectiveFPOStackAlign(SMLoc L) {
3656  MCAsmParser &Parser = getParser();
3657  int64_t Offset;
3658  if (Parser.parseIntToken(Offset, "expected offset") ||
3659  Parser.parseEOL("unexpected tokens"))
3660  return addErrorSuffix(" in '.cv_fpo_stackalign' directive");
3661  return getTargetStreamer().emitFPOStackAlign(Offset, L);
3662 }
3663 
3664 // .cv_fpo_endprologue
3665 bool X86AsmParser::parseDirectiveFPOEndPrologue(SMLoc L) {
3666  MCAsmParser &Parser = getParser();
3667  if (Parser.parseEOL("unexpected tokens"))
3668  return addErrorSuffix(" in '.cv_fpo_endprologue' directive");
3669  return getTargetStreamer().emitFPOEndPrologue(L);
3670 }
3671 
3672 // .cv_fpo_endproc
3673 bool X86AsmParser::parseDirectiveFPOEndProc(SMLoc L) {
3674  MCAsmParser &Parser = getParser();
3675  if (Parser.parseEOL("unexpected tokens"))
3676  return addErrorSuffix(" in '.cv_fpo_endproc' directive");
3677  return getTargetStreamer().emitFPOEndProc(L);
3678 }
3679 
3680 // Force static initialization.
3681 extern "C" void LLVMInitializeX86AsmParser() {
3684 }
3685 
3686 #define GET_REGISTER_MATCHER
3687 #define GET_MATCHER_IMPLEMENTATION
3688 #define GET_SUBTARGET_FEATURE_NAME
3689 #include "X86GenAsmMatcher.inc"
static const char * getSubtargetFeatureName(uint64_t Val)
Represents a range in source code.
Definition: SMLoc.h:48
Instances of this class represent a uniqued identifier for a section in the current translation unit...
Definition: MCSection.h:38
static bool checkScale(unsigned Scale, StringRef &ErrMsg)
LLVM_NODISCARD StringRef take_front(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with only the first N elements remaining.
Definition: StringRef.h:587
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmMacro.h:110
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
unsigned getMemFrontendSize() const
Definition: X86Operand.h:197
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:877
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:267
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:321
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
SMRange getLocRange() const
getLocRange - Get the range between the first and last token of this operand.
Definition: X86Operand.h:93
bool isVariable() const
isVariable - Check if this is a variable symbol.
Definition: MCSymbol.h:293
SmallVectorImpl< AsmRewrite > * AsmRewrites
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
LLVM_NODISCARD bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Definition: StringRef.h:167
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:109
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
bool isKind(IdKind kind) const
Definition: MCAsmParser.h:65
MCTargetAsmParser - Generic interface to target specific assembly parsers.
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:256
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
LLVM_NODISCARD int compare(StringRef RHS) const
compare - Compare two strings; the result is -1, 0, or 1 if this string is lexicographically less tha...
Definition: StringRef.h:174
Target specific streamer interface.
Definition: MCStreamer.h:83
unsigned Reg
bool isNot(TokenKind K) const
Definition: MCAsmMacro.h:83
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:509
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:33
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, StringRef SymName=StringRef(), void *OpDecl=nullptr, unsigned FrontendSize=0)
Create an absolute memory operand.
Definition: X86Operand.h:566
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:960
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
bool parseIntToken(int64_t &V, const Twine &ErrMsg)
Definition: MCAsmParser.cpp:58
return AArch64::GPR64RegClass contains(Reg)
static ModuleSymbolTable::Symbol getSym(DataRefImpl &Symb)
StringRef getToken() const
Definition: X86Operand.h:148
amode Optimize addressing mode
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
Definition: MCAsmMacro.h:99
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
void LLVMInitializeX86AsmParser()
const FeatureBitset & getFeatureBits() const
unsigned getPrefix() const
Definition: X86Operand.h:163
bool isMemUnsized() const
Definition: X86Operand.h:281
SMLoc getEndLoc() const override
getEndLoc - Get the location of the last token of this operand.
Definition: X86Operand.h:89
LLVM_NODISCARD StringRef drop_front(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with the first N elements dropped.
Definition: StringRef.h:620
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:457
bool isImm() const override
isImm - Is this an immediate operand?
Definition: X86Operand.h:204
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
LLVM_NODISCARD StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: StringRef.h:679
static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg, unsigned Scale, bool Is64BitMode, StringRef &ErrMsg)
}
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:578
bool isMem8() const
Definition: X86Operand.h:284
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
zlib style complession
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
static std::unique_ptr< X86Operand > CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:557
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:29
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
unsigned getReg() const override
Definition: X86Operand.h:158
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:51
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:27
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:459
LLVM_NODISCARD std::string upper() const
Convert the given ASCII string to uppercase.
Definition: StringRef.cpp:115
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
virtual void eatToEndOfStatement()=0
Skip to the end of the current statement, for error recovery.
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(adl_begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1251
static const X86MCExpr * create(int64_t RegNo, MCContext &Ctx)
Definition: X86MCExpr.h:36
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isPrefix() const
Definition: X86Operand.h:444
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:843
virtual void addAliasForDirective(StringRef Directive, StringRef Alias)=0
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
const char * getPointer() const
Definition: SMLoc.h:34
virtual MCContext & getContext()=0
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
Streaming machine code generation interface.
Definition: MCStreamer.h:188
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
Definition: StringSwitch.h:88
unsigned const MachineRegisterInfo * MRI
X86Operand - Instances of this class represent a parsed X86 machine instruction.
Definition: X86Operand.h:31
MCTargetStreamer * getTargetStreamer()
Definition: MCStreamer.h:257
Container class for subtarget features.
SMLoc getEndLoc() const
Definition: MCAsmLexer.cpp:31
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse a primary expression.
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
const MCExpr * getImm() const
Definition: X86Operand.h:168
bool parseTokenLoc(SMLoc &Loc)
Definition: MCAsmParser.cpp:37
int64_t getIntVal() const
Definition: MCAsmMacro.h:115
unsigned getNumOperands() const
Definition: MCInst.h:181
static std::unique_ptr< X86Operand > CreateDXReg(SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:546
bool Error(SMLoc L, const Twine &Msg, SMRange Range=None)
Return an error at the location L, with the message Msg.
Definition: MCAsmParser.cpp:87
static const char * getRegisterName(unsigned RegNo)
void setTokenValue(StringRef Value)
Definition: X86Operand.h:152
virtual bool UseCodeAlign() const =0
Return true if a .align directive should use "optimized nops" to fill instead of 0s.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:397
iterator erase(const_iterator CI)
Definition: SmallVector.h:438
size_t size() const
Definition: SmallVector.h:52
LLVM_NODISCARD char back() const
back - Get the last character in the string.
Definition: StringRef.h:141
void setLoc(SMLoc loc)
Definition: MCInst.h:176
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SMLoc getStartLoc() const override
getStartLoc - Get the location of the first token of this operand.
Definition: X86Operand.h:86
unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
void setFlags(unsigned F)
Definition: MCInst.h:173
MCStreamer & getStreamer()
Definition: MCStreamer.h:91
void setOpcode(unsigned Op)
Definition: MCInst.h:170
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1166
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:256
static unsigned MatchRegisterName(StringRef Name)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
struct MemOp Mem
Definition: X86Operand.h:75
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:374
StringRef str()
Return a StringRef for the vector contents.
Definition: raw_ostream.h:534
X86 target streamer implementing x86-only assembly directives.
static bool isPrefix(const IndicesVector &Prefix, const IndicesVector &Longer)
Returns true if Prefix is a prefix of longer.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
bool is(TokenKind K) const
Definition: MCAsmMacro.h:82
Class for arbitrary precision integers.
Definition: APInt.h:69
bool isValid() const
Definition: SMLoc.h:29
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Base class for user error types.
Definition: Error.h:344
static std::unique_ptr< X86Operand > CreateToken(StringRef Str, SMLoc Loc)
Definition: X86Operand.h:524
VariableIdentifier Var
Definition: MCAsmParser.h:63
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:52
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
static std::unique_ptr< X86Operand > CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc, bool AddressOf=false, SMLoc OffsetOfLoc=SMLoc(), StringRef SymName=StringRef(), void *OpDecl=nullptr)
Definition: X86Operand.h:533
.code64 (X86)
Definition: MCDirectives.h:53
LLVM_NODISCARD bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:160
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
static unsigned getPrefixes(OperandVector &Operands)
Generic base class for all target subtargets.
virtual bool parseAbsoluteExpression(int64_t &Res)=0
Parse an expression which must evaluate to an absolute value.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
Target & getTheX86_32Target()
uint32_t Size
Definition: Profile.cpp:46
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:202
bool isDXReg() const
Definition: X86Operand.h:446
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:107
static std::unique_ptr< X86Operand > CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:551
LLVM_NODISCARD const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:122
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool TokError(const Twine &Msg, SMRange Range=None)
Report an error at the current lexer location.
Definition: MCAsmParser.cpp:83
const MCExpr * getVariableValue(bool SetUsed=true) const
getVariableValue - Get the value for variable symbols.
Definition: MCSymbol.h:298
LLVM_NODISCARD StringRef drop_back(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with the last N elements dropped.
Definition: StringRef.h:628
bool parseEOL(const Twine &ErrMsg)
Definition: MCAsmParser.cpp:42
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
bool parseOptionalToken(AsmToken::TokenKind T)
Attempt to parse and consume token, returning true on success.
Definition: MCAsmParser.cpp:66
bool isReg() const override
isReg - Is this a register operand?
Definition: X86Operand.h:445
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual bool parseIdentifier(StringRef &Res)=0
Parse an identifier or string (as a quoted identifier) and set Res to the identifier contents...
Represents a location in source code.
Definition: SMLoc.h:23
unsigned getOpcode() const
Definition: MCInst.h:171
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:392
Target & getTheX86_64Target()
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
bool isMem() const override
isMem - Is this a memory operand?
Definition: X86Operand.h:280
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41