LLVM  6.0.0svn
X86AsmParser.cpp
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1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
13 #include "X86AsmInstrumentation.h"
14 #include "X86AsmParserCommon.h"
15 #include "X86Operand.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallString.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCSection.h"
31 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/MC/MCSymbol.h"
34 #include "llvm/Support/SourceMgr.h"
37 #include <algorithm>
38 #include <memory>
39 
40 using namespace llvm;
41 
42 static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
43  if (Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
44  ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
45  return true;
46  }
47  return false;
48 }
49 
50 namespace {
51 
52 static const char OpPrecedence[] = {
53  0, // IC_OR
54  1, // IC_XOR
55  2, // IC_AND
56  3, // IC_LSHIFT
57  3, // IC_RSHIFT
58  4, // IC_PLUS
59  4, // IC_MINUS
60  5, // IC_MULTIPLY
61  5, // IC_DIVIDE
62  5, // IC_MOD
63  6, // IC_NOT
64  7, // IC_NEG
65  8, // IC_RPAREN
66  9, // IC_LPAREN
67  0, // IC_IMM
68  0 // IC_REGISTER
69 };
70 
71 class X86AsmParser : public MCTargetAsmParser {
72  ParseInstructionInfo *InstInfo;
73  std::unique_ptr<X86AsmInstrumentation> Instrumentation;
74  bool Code16GCC;
75 
76 private:
77  SMLoc consumeToken() {
78  MCAsmParser &Parser = getParser();
79  SMLoc Result = Parser.getTok().getLoc();
80  Parser.Lex();
81  return Result;
82  }
83 
84  X86TargetStreamer &getTargetStreamer() {
85  assert(getParser().getStreamer().getTargetStreamer() &&
86  "do not have a target streamer");
87  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
88  return static_cast<X86TargetStreamer &>(TS);
89  }
90 
91  unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst,
92  uint64_t &ErrorInfo, bool matchingInlineAsm,
93  unsigned VariantID = 0) {
94  // In Code16GCC mode, match as 32-bit.
95  if (Code16GCC)
96  SwitchMode(X86::Mode32Bit);
97  unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo,
98  matchingInlineAsm, VariantID);
99  if (Code16GCC)
100  SwitchMode(X86::Mode16Bit);
101  return rv;
102  }
103 
104  enum InfixCalculatorTok {
105  IC_OR = 0,
106  IC_XOR,
107  IC_AND,
108  IC_LSHIFT,
109  IC_RSHIFT,
110  IC_PLUS,
111  IC_MINUS,
112  IC_MULTIPLY,
113  IC_DIVIDE,
114  IC_MOD,
115  IC_NOT,
116  IC_NEG,
117  IC_RPAREN,
118  IC_LPAREN,
119  IC_IMM,
120  IC_REGISTER
121  };
122 
123  enum IntelOperatorKind {
124  IOK_INVALID = 0,
125  IOK_LENGTH,
126  IOK_SIZE,
127  IOK_TYPE,
128  IOK_OFFSET
129  };
130 
131  class InfixCalculator {
132  typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
133  SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
134  SmallVector<ICToken, 4> PostfixStack;
135 
136  bool isUnaryOperator(const InfixCalculatorTok Op) {
137  return Op == IC_NEG || Op == IC_NOT;
138  }
139 
140  public:
141  int64_t popOperand() {
142  assert (!PostfixStack.empty() && "Poped an empty stack!");
143  ICToken Op = PostfixStack.pop_back_val();
144  if (!(Op.first == IC_IMM || Op.first == IC_REGISTER))
145  return -1; // The invalid Scale value will be caught later by checkScale
146  return Op.second;
147  }
148  void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
149  assert ((Op == IC_IMM || Op == IC_REGISTER) &&
150  "Unexpected operand!");
151  PostfixStack.push_back(std::make_pair(Op, Val));
152  }
153 
154  void popOperator() { InfixOperatorStack.pop_back(); }
155  void pushOperator(InfixCalculatorTok Op) {
156  // Push the new operator if the stack is empty.
157  if (InfixOperatorStack.empty()) {
158  InfixOperatorStack.push_back(Op);
159  return;
160  }
161 
162  // Push the new operator if it has a higher precedence than the operator
163  // on the top of the stack or the operator on the top of the stack is a
164  // left parentheses.
165  unsigned Idx = InfixOperatorStack.size() - 1;
166  InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
167  if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
168  InfixOperatorStack.push_back(Op);
169  return;
170  }
171 
172  // The operator on the top of the stack has higher precedence than the
173  // new operator.
174  unsigned ParenCount = 0;
175  while (1) {
176  // Nothing to process.
177  if (InfixOperatorStack.empty())
178  break;
179 
180  Idx = InfixOperatorStack.size() - 1;
181  StackOp = InfixOperatorStack[Idx];
182  if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
183  break;
184 
185  // If we have an even parentheses count and we see a left parentheses,
186  // then stop processing.
187  if (!ParenCount && StackOp == IC_LPAREN)
188  break;
189 
190  if (StackOp == IC_RPAREN) {
191  ++ParenCount;
192  InfixOperatorStack.pop_back();
193  } else if (StackOp == IC_LPAREN) {
194  --ParenCount;
195  InfixOperatorStack.pop_back();
196  } else {
197  InfixOperatorStack.pop_back();
198  PostfixStack.push_back(std::make_pair(StackOp, 0));
199  }
200  }
201  // Push the new operator.
202  InfixOperatorStack.push_back(Op);
203  }
204 
205  int64_t execute() {
206  // Push any remaining operators onto the postfix stack.
207  while (!InfixOperatorStack.empty()) {
208  InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
209  if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
210  PostfixStack.push_back(std::make_pair(StackOp, 0));
211  }
212 
213  if (PostfixStack.empty())
214  return 0;
215 
216  SmallVector<ICToken, 16> OperandStack;
217  for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
218  ICToken Op = PostfixStack[i];
219  if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
220  OperandStack.push_back(Op);
221  } else if (isUnaryOperator(Op.first)) {
222  assert (OperandStack.size() > 0 && "Too few operands.");
223  ICToken Operand = OperandStack.pop_back_val();
224  assert (Operand.first == IC_IMM &&
225  "Unary operation with a register!");
226  switch (Op.first) {
227  default:
228  report_fatal_error("Unexpected operator!");
229  break;
230  case IC_NEG:
231  OperandStack.push_back(std::make_pair(IC_IMM, -Operand.second));
232  break;
233  case IC_NOT:
234  OperandStack.push_back(std::make_pair(IC_IMM, ~Operand.second));
235  break;
236  }
237  } else {
238  assert (OperandStack.size() > 1 && "Too few operands.");
239  int64_t Val;
240  ICToken Op2 = OperandStack.pop_back_val();
241  ICToken Op1 = OperandStack.pop_back_val();
242  switch (Op.first) {
243  default:
244  report_fatal_error("Unexpected operator!");
245  break;
246  case IC_PLUS:
247  Val = Op1.second + Op2.second;
248  OperandStack.push_back(std::make_pair(IC_IMM, Val));
249  break;
250  case IC_MINUS:
251  Val = Op1.second - Op2.second;
252  OperandStack.push_back(std::make_pair(IC_IMM, Val));
253  break;
254  case IC_MULTIPLY:
255  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
256  "Multiply operation with an immediate and a register!");
257  Val = Op1.second * Op2.second;
258  OperandStack.push_back(std::make_pair(IC_IMM, Val));
259  break;
260  case IC_DIVIDE:
261  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
262  "Divide operation with an immediate and a register!");
263  assert (Op2.second != 0 && "Division by zero!");
264  Val = Op1.second / Op2.second;
265  OperandStack.push_back(std::make_pair(IC_IMM, Val));
266  break;
267  case IC_MOD:
268  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
269  "Modulo operation with an immediate and a register!");
270  Val = Op1.second % Op2.second;
271  OperandStack.push_back(std::make_pair(IC_IMM, Val));
272  break;
273  case IC_OR:
274  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
275  "Or operation with an immediate and a register!");
276  Val = Op1.second | Op2.second;
277  OperandStack.push_back(std::make_pair(IC_IMM, Val));
278  break;
279  case IC_XOR:
280  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
281  "Xor operation with an immediate and a register!");
282  Val = Op1.second ^ Op2.second;
283  OperandStack.push_back(std::make_pair(IC_IMM, Val));
284  break;
285  case IC_AND:
286  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
287  "And operation with an immediate and a register!");
288  Val = Op1.second & Op2.second;
289  OperandStack.push_back(std::make_pair(IC_IMM, Val));
290  break;
291  case IC_LSHIFT:
292  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
293  "Left shift operation with an immediate and a register!");
294  Val = Op1.second << Op2.second;
295  OperandStack.push_back(std::make_pair(IC_IMM, Val));
296  break;
297  case IC_RSHIFT:
298  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
299  "Right shift operation with an immediate and a register!");
300  Val = Op1.second >> Op2.second;
301  OperandStack.push_back(std::make_pair(IC_IMM, Val));
302  break;
303  }
304  }
305  }
306  assert (OperandStack.size() == 1 && "Expected a single result.");
307  return OperandStack.pop_back_val().second;
308  }
309  };
310 
311  enum IntelExprState {
312  IES_INIT,
313  IES_OR,
314  IES_XOR,
315  IES_AND,
316  IES_LSHIFT,
317  IES_RSHIFT,
318  IES_PLUS,
319  IES_MINUS,
320  IES_NOT,
321  IES_MULTIPLY,
322  IES_DIVIDE,
323  IES_MOD,
324  IES_LBRAC,
325  IES_RBRAC,
326  IES_LPAREN,
327  IES_RPAREN,
328  IES_REGISTER,
329  IES_INTEGER,
330  IES_IDENTIFIER,
331  IES_ERROR
332  };
333 
334  class IntelExprStateMachine {
335  IntelExprState State, PrevState;
336  unsigned BaseReg, IndexReg, TmpReg, Scale;
337  int64_t Imm;
338  const MCExpr *Sym;
339  StringRef SymName;
340  InfixCalculator IC;
342  short BracCount;
343  bool MemExpr;
344 
345  public:
346  IntelExprStateMachine()
347  : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),
348  TmpReg(0), Scale(1), Imm(0), Sym(nullptr), BracCount(0),
349  MemExpr(false) {}
350 
351  void addImm(int64_t imm) { Imm += imm; }
352  short getBracCount() { return BracCount; }
353  bool isMemExpr() { return MemExpr; }
354  unsigned getBaseReg() { return BaseReg; }
355  unsigned getIndexReg() { return IndexReg; }
356  unsigned getScale() { return Scale; }
357  const MCExpr *getSym() { return Sym; }
358  StringRef getSymName() { return SymName; }
359  int64_t getImm() { return Imm + IC.execute(); }
360  bool isValidEndState() {
361  return State == IES_RBRAC || State == IES_INTEGER;
362  }
363  bool hadError() { return State == IES_ERROR; }
364  InlineAsmIdentifierInfo &getIdentifierInfo() { return Info; }
365 
366  void onOr() {
367  IntelExprState CurrState = State;
368  switch (State) {
369  default:
370  State = IES_ERROR;
371  break;
372  case IES_INTEGER:
373  case IES_RPAREN:
374  case IES_REGISTER:
375  State = IES_OR;
376  IC.pushOperator(IC_OR);
377  break;
378  }
379  PrevState = CurrState;
380  }
381  void onXor() {
382  IntelExprState CurrState = State;
383  switch (State) {
384  default:
385  State = IES_ERROR;
386  break;
387  case IES_INTEGER:
388  case IES_RPAREN:
389  case IES_REGISTER:
390  State = IES_XOR;
391  IC.pushOperator(IC_XOR);
392  break;
393  }
394  PrevState = CurrState;
395  }
396  void onAnd() {
397  IntelExprState CurrState = State;
398  switch (State) {
399  default:
400  State = IES_ERROR;
401  break;
402  case IES_INTEGER:
403  case IES_RPAREN:
404  case IES_REGISTER:
405  State = IES_AND;
406  IC.pushOperator(IC_AND);
407  break;
408  }
409  PrevState = CurrState;
410  }
411  void onLShift() {
412  IntelExprState CurrState = State;
413  switch (State) {
414  default:
415  State = IES_ERROR;
416  break;
417  case IES_INTEGER:
418  case IES_RPAREN:
419  case IES_REGISTER:
420  State = IES_LSHIFT;
421  IC.pushOperator(IC_LSHIFT);
422  break;
423  }
424  PrevState = CurrState;
425  }
426  void onRShift() {
427  IntelExprState CurrState = State;
428  switch (State) {
429  default:
430  State = IES_ERROR;
431  break;
432  case IES_INTEGER:
433  case IES_RPAREN:
434  case IES_REGISTER:
435  State = IES_RSHIFT;
436  IC.pushOperator(IC_RSHIFT);
437  break;
438  }
439  PrevState = CurrState;
440  }
441  bool onPlus(StringRef &ErrMsg) {
442  IntelExprState CurrState = State;
443  switch (State) {
444  default:
445  State = IES_ERROR;
446  break;
447  case IES_INTEGER:
448  case IES_RPAREN:
449  case IES_REGISTER:
450  State = IES_PLUS;
451  IC.pushOperator(IC_PLUS);
452  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
453  // If we already have a BaseReg, then assume this is the IndexReg with
454  // a scale of 1.
455  if (!BaseReg) {
456  BaseReg = TmpReg;
457  } else {
458  if (IndexReg) {
459  ErrMsg = "BaseReg/IndexReg already set!";
460  return true;
461  }
462  IndexReg = TmpReg;
463  Scale = 1;
464  }
465  }
466  break;
467  }
468  PrevState = CurrState;
469  return false;
470  }
471  bool onMinus(StringRef &ErrMsg) {
472  IntelExprState CurrState = State;
473  switch (State) {
474  default:
475  State = IES_ERROR;
476  break;
477  case IES_OR:
478  case IES_XOR:
479  case IES_AND:
480  case IES_LSHIFT:
481  case IES_RSHIFT:
482  case IES_PLUS:
483  case IES_NOT:
484  case IES_MULTIPLY:
485  case IES_DIVIDE:
486  case IES_MOD:
487  case IES_LPAREN:
488  case IES_RPAREN:
489  case IES_LBRAC:
490  case IES_RBRAC:
491  case IES_INTEGER:
492  case IES_REGISTER:
493  case IES_INIT:
494  State = IES_MINUS;
495  // push minus operator if it is not a negate operator
496  if (CurrState == IES_REGISTER || CurrState == IES_RPAREN ||
497  CurrState == IES_INTEGER || CurrState == IES_RBRAC)
498  IC.pushOperator(IC_MINUS);
499  else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
500  // We have negate operator for Scale: it's illegal
501  ErrMsg = "Scale can't be negative";
502  return true;
503  } else
504  IC.pushOperator(IC_NEG);
505  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
506  // If we already have a BaseReg, then assume this is the IndexReg with
507  // a scale of 1.
508  if (!BaseReg) {
509  BaseReg = TmpReg;
510  } else {
511  if (IndexReg) {
512  ErrMsg = "BaseReg/IndexReg already set!";
513  return true;
514  }
515  IndexReg = TmpReg;
516  Scale = 1;
517  }
518  }
519  break;
520  }
521  PrevState = CurrState;
522  return false;
523  }
524  void onNot() {
525  IntelExprState CurrState = State;
526  switch (State) {
527  default:
528  State = IES_ERROR;
529  break;
530  case IES_OR:
531  case IES_XOR:
532  case IES_AND:
533  case IES_LSHIFT:
534  case IES_RSHIFT:
535  case IES_PLUS:
536  case IES_MINUS:
537  case IES_NOT:
538  case IES_MULTIPLY:
539  case IES_DIVIDE:
540  case IES_MOD:
541  case IES_LPAREN:
542  case IES_LBRAC:
543  case IES_INIT:
544  State = IES_NOT;
545  IC.pushOperator(IC_NOT);
546  break;
547  }
548  PrevState = CurrState;
549  }
550 
551  bool onRegister(unsigned Reg, StringRef &ErrMsg) {
552  IntelExprState CurrState = State;
553  switch (State) {
554  default:
555  State = IES_ERROR;
556  break;
557  case IES_PLUS:
558  case IES_LPAREN:
559  case IES_LBRAC:
560  State = IES_REGISTER;
561  TmpReg = Reg;
562  IC.pushOperand(IC_REGISTER);
563  break;
564  case IES_MULTIPLY:
565  // Index Register - Scale * Register
566  if (PrevState == IES_INTEGER) {
567  if (IndexReg) {
568  ErrMsg = "BaseReg/IndexReg already set!";
569  return true;
570  }
571  State = IES_REGISTER;
572  IndexReg = Reg;
573  // Get the scale and replace the 'Scale * Register' with '0'.
574  Scale = IC.popOperand();
575  if (checkScale(Scale, ErrMsg))
576  return true;
577  IC.pushOperand(IC_IMM);
578  IC.popOperator();
579  } else {
580  State = IES_ERROR;
581  }
582  break;
583  }
584  PrevState = CurrState;
585  return false;
586  }
587  bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName,
588  const InlineAsmIdentifierInfo &IDInfo,
589  bool ParsingInlineAsm, StringRef &ErrMsg) {
590  // InlineAsm: Treat an enum value as an integer
591  if (ParsingInlineAsm)
593  return onInteger(IDInfo.Enum.EnumVal, ErrMsg);
594  // Treat a symbolic constant like an integer
595  if (auto *CE = dyn_cast<MCConstantExpr>(SymRef))
596  return onInteger(CE->getValue(), ErrMsg);
597  PrevState = State;
598  bool HasSymbol = Sym != nullptr;
599  switch (State) {
600  default:
601  State = IES_ERROR;
602  break;
603  case IES_PLUS:
604  case IES_MINUS:
605  case IES_NOT:
606  case IES_INIT:
607  case IES_LBRAC:
608  MemExpr = true;
609  State = IES_INTEGER;
610  Sym = SymRef;
611  SymName = SymRefName;
612  IC.pushOperand(IC_IMM);
613  if (ParsingInlineAsm)
614  Info = IDInfo;
615  break;
616  }
617  if (HasSymbol)
618  ErrMsg = "cannot use more than one symbol in memory operand";
619  return HasSymbol;
620  }
621  bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
622  IntelExprState CurrState = State;
623  switch (State) {
624  default:
625  State = IES_ERROR;
626  break;
627  case IES_PLUS:
628  case IES_MINUS:
629  case IES_NOT:
630  case IES_OR:
631  case IES_XOR:
632  case IES_AND:
633  case IES_LSHIFT:
634  case IES_RSHIFT:
635  case IES_DIVIDE:
636  case IES_MOD:
637  case IES_MULTIPLY:
638  case IES_LPAREN:
639  case IES_INIT:
640  case IES_LBRAC:
641  State = IES_INTEGER;
642  if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
643  // Index Register - Register * Scale
644  if (IndexReg) {
645  ErrMsg = "BaseReg/IndexReg already set!";
646  return true;
647  }
648  IndexReg = TmpReg;
649  Scale = TmpInt;
650  if (checkScale(Scale, ErrMsg))
651  return true;
652  // Get the scale and replace the 'Register * Scale' with '0'.
653  IC.popOperator();
654  } else {
655  IC.pushOperand(IC_IMM, TmpInt);
656  }
657  break;
658  }
659  PrevState = CurrState;
660  return false;
661  }
662  void onStar() {
663  PrevState = State;
664  switch (State) {
665  default:
666  State = IES_ERROR;
667  break;
668  case IES_INTEGER:
669  case IES_REGISTER:
670  case IES_RPAREN:
671  State = IES_MULTIPLY;
672  IC.pushOperator(IC_MULTIPLY);
673  break;
674  }
675  }
676  void onDivide() {
677  PrevState = State;
678  switch (State) {
679  default:
680  State = IES_ERROR;
681  break;
682  case IES_INTEGER:
683  case IES_RPAREN:
684  State = IES_DIVIDE;
685  IC.pushOperator(IC_DIVIDE);
686  break;
687  }
688  }
689  void onMod() {
690  PrevState = State;
691  switch (State) {
692  default:
693  State = IES_ERROR;
694  break;
695  case IES_INTEGER:
696  case IES_RPAREN:
697  State = IES_MOD;
698  IC.pushOperator(IC_MOD);
699  break;
700  }
701  }
702  bool onLBrac() {
703  if (BracCount)
704  return true;
705  PrevState = State;
706  switch (State) {
707  default:
708  State = IES_ERROR;
709  break;
710  case IES_RBRAC:
711  case IES_INTEGER:
712  case IES_RPAREN:
713  State = IES_PLUS;
714  IC.pushOperator(IC_PLUS);
715  break;
716  case IES_INIT:
717  assert(!BracCount && "BracCount should be zero on parsing's start");
718  State = IES_LBRAC;
719  break;
720  }
721  MemExpr = true;
722  BracCount++;
723  return false;
724  }
725  bool onRBrac() {
726  IntelExprState CurrState = State;
727  switch (State) {
728  default:
729  State = IES_ERROR;
730  break;
731  case IES_INTEGER:
732  case IES_REGISTER:
733  case IES_RPAREN:
734  if (BracCount-- != 1)
735  return true;
736  State = IES_RBRAC;
737  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
738  // If we already have a BaseReg, then assume this is the IndexReg with
739  // a scale of 1.
740  if (!BaseReg) {
741  BaseReg = TmpReg;
742  } else {
743  assert (!IndexReg && "BaseReg/IndexReg already set!");
744  IndexReg = TmpReg;
745  Scale = 1;
746  }
747  }
748  break;
749  }
750  PrevState = CurrState;
751  return false;
752  }
753  void onLParen() {
754  IntelExprState CurrState = State;
755  switch (State) {
756  default:
757  State = IES_ERROR;
758  break;
759  case IES_PLUS:
760  case IES_MINUS:
761  case IES_NOT:
762  case IES_OR:
763  case IES_XOR:
764  case IES_AND:
765  case IES_LSHIFT:
766  case IES_RSHIFT:
767  case IES_MULTIPLY:
768  case IES_DIVIDE:
769  case IES_MOD:
770  case IES_LPAREN:
771  case IES_INIT:
772  case IES_LBRAC:
773  State = IES_LPAREN;
774  IC.pushOperator(IC_LPAREN);
775  break;
776  }
777  PrevState = CurrState;
778  }
779  void onRParen() {
780  PrevState = State;
781  switch (State) {
782  default:
783  State = IES_ERROR;
784  break;
785  case IES_INTEGER:
786  case IES_REGISTER:
787  case IES_RPAREN:
788  State = IES_RPAREN;
789  IC.pushOperator(IC_RPAREN);
790  break;
791  }
792  }
793  };
794 
795  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
796  bool MatchingInlineAsm = false) {
797  MCAsmParser &Parser = getParser();
798  if (MatchingInlineAsm) {
799  if (!getLexer().isAtStartOfStatement())
800  Parser.eatToEndOfStatement();
801  return false;
802  }
803  return Parser.Error(L, Msg, Range);
804  }
805 
806  std::nullptr_t ErrorOperand(SMLoc Loc, StringRef Msg) {
807  Error(Loc, Msg);
808  return nullptr;
809  }
810 
811  std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
812  std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc);
813  bool IsSIReg(unsigned Reg);
814  unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
815  void
816  AddDefaultSrcDestOperands(OperandVector &Operands,
817  std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
818  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
819  bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
820  OperandVector &FinalOperands);
821  std::unique_ptr<X86Operand> ParseOperand();
822  std::unique_ptr<X86Operand> ParseATTOperand();
823  std::unique_ptr<X86Operand> ParseIntelOperand();
824  std::unique_ptr<X86Operand> ParseIntelOffsetOfOperator();
825  bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End);
826  unsigned IdentifyIntelInlineAsmOperator(StringRef Name);
827  unsigned ParseIntelInlineAsmOperator(unsigned OpKind);
828  std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start, SMLoc End);
829  bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM);
830  void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start,
831  SMLoc End);
832  bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
833  bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier,
835  bool IsUnevaluatedOperand, SMLoc &End);
836 
837  std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
838 
839  bool ParseIntelMemoryOperandSize(unsigned &Size);
840  std::unique_ptr<X86Operand>
841  CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
842  unsigned IndexReg, unsigned Scale, SMLoc Start,
843  SMLoc End, unsigned Size, StringRef Identifier,
844  const InlineAsmIdentifierInfo &Info);
845 
846  bool parseDirectiveEven(SMLoc L);
847  bool ParseDirectiveWord(unsigned Size, SMLoc L);
848  bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
849 
850  /// CodeView FPO data directives.
851  bool parseDirectiveFPOProc(SMLoc L);
852  bool parseDirectiveFPOSetFrame(SMLoc L);
853  bool parseDirectiveFPOPushReg(SMLoc L);
854  bool parseDirectiveFPOStackAlloc(SMLoc L);
855  bool parseDirectiveFPOEndPrologue(SMLoc L);
856  bool parseDirectiveFPOEndProc(SMLoc L);
857  bool parseDirectiveFPOData(SMLoc L);
858 
859  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
860  bool processInstruction(MCInst &Inst, const OperandVector &Ops);
861 
862  /// Wrapper around MCStreamer::EmitInstruction(). Possibly adds
863  /// instrumentation around Inst.
864  void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
865 
866  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
867  OperandVector &Operands, MCStreamer &Out,
868  uint64_t &ErrorInfo,
869  bool MatchingInlineAsm) override;
870 
871  void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
872  MCStreamer &Out, bool MatchingInlineAsm);
873 
874  bool ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo,
875  bool MatchingInlineAsm);
876 
877  bool MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
878  OperandVector &Operands, MCStreamer &Out,
879  uint64_t &ErrorInfo,
880  bool MatchingInlineAsm);
881 
882  bool MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
883  OperandVector &Operands, MCStreamer &Out,
884  uint64_t &ErrorInfo,
885  bool MatchingInlineAsm);
886 
887  bool OmitRegisterFromClobberLists(unsigned RegNo) override;
888 
889  /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
890  /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
891  /// return false if no parsing errors occurred, true otherwise.
892  bool HandleAVX512Operand(OperandVector &Operands,
893  const MCParsedAsmOperand &Op);
894 
895  bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
896 
897  bool is64BitMode() const {
898  // FIXME: Can tablegen auto-generate this?
899  return getSTI().getFeatureBits()[X86::Mode64Bit];
900  }
901  bool is32BitMode() const {
902  // FIXME: Can tablegen auto-generate this?
903  return getSTI().getFeatureBits()[X86::Mode32Bit];
904  }
905  bool is16BitMode() const {
906  // FIXME: Can tablegen auto-generate this?
907  return getSTI().getFeatureBits()[X86::Mode16Bit];
908  }
909  void SwitchMode(unsigned mode) {
910  MCSubtargetInfo &STI = copySTI();
911  FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
912  FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
913  uint64_t FB = ComputeAvailableFeatures(
914  STI.ToggleFeature(OldMode.flip(mode)));
915  setAvailableFeatures(FB);
916 
917  assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
918  }
919 
920  unsigned getPointerWidth() {
921  if (is16BitMode()) return 16;
922  if (is32BitMode()) return 32;
923  if (is64BitMode()) return 64;
924  llvm_unreachable("invalid mode");
925  }
926 
927  bool isParsingIntelSyntax() {
928  return getParser().getAssemblerDialect();
929  }
930 
931  /// @name Auto-generated Matcher Functions
932  /// {
933 
934 #define GET_ASSEMBLER_HEADER
935 #include "X86GenAsmMatcher.inc"
936 
937  /// }
938 
939 public:
940 
941  X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
942  const MCInstrInfo &mii, const MCTargetOptions &Options)
943  : MCTargetAsmParser(Options, sti, mii), InstInfo(nullptr),
944  Code16GCC(false) {
945 
946  // Initialize the set of available features.
947  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
948  Instrumentation.reset(
949  CreateX86AsmInstrumentation(Options, Parser.getContext(), STI));
950  }
951 
952  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
953 
954  void SetFrameRegister(unsigned RegNo) override;
955 
956  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
957  SMLoc NameLoc, OperandVector &Operands) override;
958 
959  bool ParseDirective(AsmToken DirectiveID) override;
960 };
961 } // end anonymous namespace
962 
963 /// @name Auto-generated Match Functions
964 /// {
965 
966 static unsigned MatchRegisterName(StringRef Name);
967 
968 /// }
969 
970 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,
971  unsigned Scale, StringRef &ErrMsg) {
972  // If we have both a base register and an index register make sure they are
973  // both 64-bit or 32-bit registers.
974  // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
975 
976  if ((BaseReg == X86::RIP && IndexReg != 0) || (IndexReg == X86::RIP)) {
977  ErrMsg = "invalid base+index expression";
978  return true;
979  }
980  if (BaseReg != 0 && IndexReg != 0) {
981  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
982  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
983  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
984  IndexReg != X86::RIZ) {
985  ErrMsg = "base register is 64-bit, but index register is not";
986  return true;
987  }
988  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
989  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
990  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
991  IndexReg != X86::EIZ){
992  ErrMsg = "base register is 32-bit, but index register is not";
993  return true;
994  }
995  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
996  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
997  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
998  ErrMsg = "base register is 16-bit, but index register is not";
999  return true;
1000  }
1001  if (((BaseReg == X86::BX || BaseReg == X86::BP) &&
1002  IndexReg != X86::SI && IndexReg != X86::DI) ||
1003  ((BaseReg == X86::SI || BaseReg == X86::DI) &&
1004  IndexReg != X86::BX && IndexReg != X86::BP)) {
1005  ErrMsg = "invalid 16-bit base/index register combination";
1006  return true;
1007  }
1008  }
1009  }
1010  return checkScale(Scale, ErrMsg);
1011 }
1012 
1013 bool X86AsmParser::ParseRegister(unsigned &RegNo,
1014  SMLoc &StartLoc, SMLoc &EndLoc) {
1015  MCAsmParser &Parser = getParser();
1016  RegNo = 0;
1017  const AsmToken &PercentTok = Parser.getTok();
1018  StartLoc = PercentTok.getLoc();
1019 
1020  // If we encounter a %, ignore it. This code handles registers with and
1021  // without the prefix, unprefixed registers can occur in cfi directives.
1022  if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
1023  Parser.Lex(); // Eat percent token.
1024 
1025  const AsmToken &Tok = Parser.getTok();
1026  EndLoc = Tok.getEndLoc();
1027 
1028  if (Tok.isNot(AsmToken::Identifier)) {
1029  if (isParsingIntelSyntax()) return true;
1030  return Error(StartLoc, "invalid register name",
1031  SMRange(StartLoc, EndLoc));
1032  }
1033 
1034  RegNo = MatchRegisterName(Tok.getString());
1035 
1036  // If the match failed, try the register name as lowercase.
1037  if (RegNo == 0)
1038  RegNo = MatchRegisterName(Tok.getString().lower());
1039 
1040  // The "flags" register cannot be referenced directly.
1041  // Treat it as an identifier instead.
1042  if (isParsingInlineAsm() && isParsingIntelSyntax() && RegNo == X86::EFLAGS)
1043  RegNo = 0;
1044 
1045  if (!is64BitMode()) {
1046  // FIXME: This should be done using Requires<Not64BitMode> and
1047  // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1048  // checked.
1049  // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
1050  // REX prefix.
1051  if (RegNo == X86::RIZ ||
1052  X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
1055  return Error(StartLoc, "register %"
1056  + Tok.getString() + " is only available in 64-bit mode",
1057  SMRange(StartLoc, EndLoc));
1058  } else if (!getSTI().getFeatureBits()[X86::FeatureAVX512]) {
1059  if (X86II::is32ExtendedReg(RegNo))
1060  return Error(StartLoc, "register %"
1061  + Tok.getString() + " is only available with AVX512",
1062  SMRange(StartLoc, EndLoc));
1063  }
1064 
1065  // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1066  if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
1067  RegNo = X86::ST0;
1068  Parser.Lex(); // Eat 'st'
1069 
1070  // Check to see if we have '(4)' after %st.
1071  if (getLexer().isNot(AsmToken::LParen))
1072  return false;
1073  // Lex the paren.
1074  getParser().Lex();
1075 
1076  const AsmToken &IntTok = Parser.getTok();
1077  if (IntTok.isNot(AsmToken::Integer))
1078  return Error(IntTok.getLoc(), "expected stack index");
1079  switch (IntTok.getIntVal()) {
1080  case 0: RegNo = X86::ST0; break;
1081  case 1: RegNo = X86::ST1; break;
1082  case 2: RegNo = X86::ST2; break;
1083  case 3: RegNo = X86::ST3; break;
1084  case 4: RegNo = X86::ST4; break;
1085  case 5: RegNo = X86::ST5; break;
1086  case 6: RegNo = X86::ST6; break;
1087  case 7: RegNo = X86::ST7; break;
1088  default: return Error(IntTok.getLoc(), "invalid stack index");
1089  }
1090 
1091  if (getParser().Lex().isNot(AsmToken::RParen))
1092  return Error(Parser.getTok().getLoc(), "expected ')'");
1093 
1094  EndLoc = Parser.getTok().getEndLoc();
1095  Parser.Lex(); // Eat ')'
1096  return false;
1097  }
1098 
1099  EndLoc = Parser.getTok().getEndLoc();
1100 
1101  // If this is "db[0-7]", match it as an alias
1102  // for dr[0-7].
1103  if (RegNo == 0 && Tok.getString().size() == 3 &&
1104  Tok.getString().startswith("db")) {
1105  switch (Tok.getString()[2]) {
1106  case '0': RegNo = X86::DR0; break;
1107  case '1': RegNo = X86::DR1; break;
1108  case '2': RegNo = X86::DR2; break;
1109  case '3': RegNo = X86::DR3; break;
1110  case '4': RegNo = X86::DR4; break;
1111  case '5': RegNo = X86::DR5; break;
1112  case '6': RegNo = X86::DR6; break;
1113  case '7': RegNo = X86::DR7; break;
1114  }
1115 
1116  if (RegNo != 0) {
1117  EndLoc = Parser.getTok().getEndLoc();
1118  Parser.Lex(); // Eat it.
1119  return false;
1120  }
1121  }
1122 
1123  if (RegNo == 0) {
1124  if (isParsingIntelSyntax()) return true;
1125  return Error(StartLoc, "invalid register name",
1126  SMRange(StartLoc, EndLoc));
1127  }
1128 
1129  Parser.Lex(); // Eat identifier token.
1130  return false;
1131 }
1132 
1133 void X86AsmParser::SetFrameRegister(unsigned RegNo) {
1134  Instrumentation->SetInitialFrameRegister(RegNo);
1135 }
1136 
1137 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1138  bool Parse32 = is32BitMode() || Code16GCC;
1139  unsigned Basereg = is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI);
1140  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1141  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1142  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1143  Loc, Loc, 0);
1144 }
1145 
1146 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1147  bool Parse32 = is32BitMode() || Code16GCC;
1148  unsigned Basereg = is64BitMode() ? X86::RDI : (Parse32 ? X86::EDI : X86::DI);
1149  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1150  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1151  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1152  Loc, Loc, 0);
1153 }
1154 
1155 bool X86AsmParser::IsSIReg(unsigned Reg) {
1156  switch (Reg) {
1157  default: llvm_unreachable("Only (R|E)SI and (R|E)DI are expected!");
1158  case X86::RSI:
1159  case X86::ESI:
1160  case X86::SI:
1161  return true;
1162  case X86::RDI:
1163  case X86::EDI:
1164  case X86::DI:
1165  return false;
1166  }
1167 }
1168 
1169 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg,
1170  bool IsSIReg) {
1171  switch (RegClassID) {
1172  default: llvm_unreachable("Unexpected register class");
1173  case X86::GR64RegClassID:
1174  return IsSIReg ? X86::RSI : X86::RDI;
1175  case X86::GR32RegClassID:
1176  return IsSIReg ? X86::ESI : X86::EDI;
1177  case X86::GR16RegClassID:
1178  return IsSIReg ? X86::SI : X86::DI;
1179  }
1180 }
1181 
1182 void X86AsmParser::AddDefaultSrcDestOperands(
1183  OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1184  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) {
1185  if (isParsingIntelSyntax()) {
1186  Operands.push_back(std::move(Dst));
1187  Operands.push_back(std::move(Src));
1188  }
1189  else {
1190  Operands.push_back(std::move(Src));
1191  Operands.push_back(std::move(Dst));
1192  }
1193 }
1194 
1195 bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
1196  OperandVector &FinalOperands) {
1197 
1198  if (OrigOperands.size() > 1) {
1199  // Check if sizes match, OrigOperands also contains the instruction name
1200  assert(OrigOperands.size() == FinalOperands.size() + 1 &&
1201  "Operand size mismatch");
1202 
1204  // Verify types match
1205  int RegClassID = -1;
1206  for (unsigned int i = 0; i < FinalOperands.size(); ++i) {
1207  X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]);
1208  X86Operand &FinalOp = static_cast<X86Operand &>(*FinalOperands[i]);
1209 
1210  if (FinalOp.isReg() &&
1211  (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg()))
1212  // Return false and let a normal complaint about bogus operands happen
1213  return false;
1214 
1215  if (FinalOp.isMem()) {
1216 
1217  if (!OrigOp.isMem())
1218  // Return false and let a normal complaint about bogus operands happen
1219  return false;
1220 
1221  unsigned OrigReg = OrigOp.Mem.BaseReg;
1222  unsigned FinalReg = FinalOp.Mem.BaseReg;
1223 
1224  // If we've already encounterd a register class, make sure all register
1225  // bases are of the same register class
1226  if (RegClassID != -1 &&
1227  !X86MCRegisterClasses[RegClassID].contains(OrigReg)) {
1228  return Error(OrigOp.getStartLoc(),
1229  "mismatching source and destination index registers");
1230  }
1231 
1232  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg))
1233  RegClassID = X86::GR64RegClassID;
1234  else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg))
1235  RegClassID = X86::GR32RegClassID;
1236  else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg))
1237  RegClassID = X86::GR16RegClassID;
1238  else
1239  // Unexpected register class type
1240  // Return false and let a normal complaint about bogus operands happen
1241  return false;
1242 
1243  bool IsSI = IsSIReg(FinalReg);
1244  FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI);
1245 
1246  if (FinalReg != OrigReg) {
1247  std::string RegName = IsSI ? "ES:(R|E)SI" : "ES:(R|E)DI";
1248  Warnings.push_back(std::make_pair(
1249  OrigOp.getStartLoc(),
1250  "memory operand is only for determining the size, " + RegName +
1251  " will be used for the location"));
1252  }
1253 
1254  FinalOp.Mem.Size = OrigOp.Mem.Size;
1255  FinalOp.Mem.SegReg = OrigOp.Mem.SegReg;
1256  FinalOp.Mem.BaseReg = FinalReg;
1257  }
1258  }
1259 
1260  // Produce warnings only if all the operands passed the adjustment - prevent
1261  // legal cases like "movsd (%rax), %xmm0" mistakenly produce warnings
1262  for (auto &WarningMsg : Warnings) {
1263  Warning(WarningMsg.first, WarningMsg.second);
1264  }
1265 
1266  // Remove old operands
1267  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1268  OrigOperands.pop_back();
1269  }
1270  // OrigOperands.append(FinalOperands.begin(), FinalOperands.end());
1271  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1272  OrigOperands.push_back(std::move(FinalOperands[i]));
1273 
1274  return false;
1275 }
1276 
1277 std::unique_ptr<X86Operand> X86AsmParser::ParseOperand() {
1278  if (isParsingIntelSyntax())
1279  return ParseIntelOperand();
1280  return ParseATTOperand();
1281 }
1282 
1283 std::unique_ptr<X86Operand> X86AsmParser::CreateMemForInlineAsm(
1284  unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1285  unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier,
1286  const InlineAsmIdentifierInfo &Info) {
1287  // If we found a decl other than a VarDecl, then assume it is a FuncDecl or
1288  // some other label reference.
1290  // Insert an explicit size if the user didn't have one.
1291  if (!Size) {
1292  Size = getPointerWidth();
1293  InstInfo->AsmRewrites->emplace_back(AOK_SizeDirective, Start,
1294  /*Len=*/0, Size);
1295  }
1296  // Create an absolute memory reference in order to match against
1297  // instructions taking a PC relative operand.
1298  return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size,
1299  Identifier, Info.Label.Decl);
1300  }
1301  // We either have a direct symbol reference, or an offset from a symbol. The
1302  // parser always puts the symbol on the LHS, so look there for size
1303  // calculation purposes.
1304  unsigned FrontendSize = 0;
1305  void *Decl = nullptr;
1306  bool IsGlobalLV = false;
1308  // Size is in terms of bits in this context.
1309  FrontendSize = Info.Var.Type * 8;
1310  Decl = Info.Var.Decl;
1311  IsGlobalLV = Info.Var.IsGlobalLV;
1312  }
1313  // It is widely common for MS InlineAsm to use a global variable and one/two
1314  // registers in a mmory expression, and though unaccessible via rip/eip.
1315  if (IsGlobalLV && (BaseReg || IndexReg)) {
1316  return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End);
1317  // Otherwise, we set the base register to a non-zero value
1318  // if we don't know the actual value at this time. This is necessary to
1319  // get the matching correct in some cases.
1320  } else {
1321  BaseReg = BaseReg ? BaseReg : 1;
1322  return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
1323  IndexReg, Scale, Start, End, Size, Identifier,
1324  Decl, FrontendSize);
1325  }
1326 }
1327 
1328 // Some binary bitwise operators have a named synonymous
1329 // Query a candidate string for being such a named operator
1330 // and if so - invoke the appropriate handler
1331 bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM) {
1332  // A named operator should be either lower or upper case, but not a mix
1333  if (Name.compare(Name.lower()) && Name.compare(Name.upper()))
1334  return false;
1335  if (Name.equals_lower("not"))
1336  SM.onNot();
1337  else if (Name.equals_lower("or"))
1338  SM.onOr();
1339  else if (Name.equals_lower("shl"))
1340  SM.onLShift();
1341  else if (Name.equals_lower("shr"))
1342  SM.onRShift();
1343  else if (Name.equals_lower("xor"))
1344  SM.onXor();
1345  else if (Name.equals_lower("and"))
1346  SM.onAnd();
1347  else if (Name.equals_lower("mod"))
1348  SM.onMod();
1349  else
1350  return false;
1351  return true;
1352 }
1353 
1354 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1355  MCAsmParser &Parser = getParser();
1356  const AsmToken &Tok = Parser.getTok();
1357  StringRef ErrMsg;
1358 
1360  bool Done = false;
1361  while (!Done) {
1362  bool UpdateLocLex = true;
1363  AsmToken::TokenKind TK = getLexer().getKind();
1364 
1365  switch (TK) {
1366  default:
1367  if ((Done = SM.isValidEndState()))
1368  break;
1369  return Error(Tok.getLoc(), "unknown token in expression");
1371  Done = true;
1372  break;
1373  case AsmToken::Real:
1374  // DotOperator: [ebx].0
1375  UpdateLocLex = false;
1376  if (ParseIntelDotOperator(SM, End))
1377  return true;
1378  break;
1379  case AsmToken::String:
1380  case AsmToken::Identifier: {
1381  SMLoc IdentLoc = Tok.getLoc();
1382  StringRef Identifier = Tok.getString();
1383  UpdateLocLex = false;
1384  // Register
1385  unsigned Reg;
1386  if (Tok.isNot(AsmToken::String) && !ParseRegister(Reg, IdentLoc, End)) {
1387  if (SM.onRegister(Reg, ErrMsg))
1388  return Error(Tok.getLoc(), ErrMsg);
1389  break;
1390  }
1391  // Operator synonymous ("not", "or" etc.)
1392  if ((UpdateLocLex = ParseIntelNamedOperator(Identifier, SM)))
1393  break;
1394  // Symbol reference, when parsing assembly content
1396  const MCExpr *Val;
1397  if (!isParsingInlineAsm()) {
1398  if (getParser().parsePrimaryExpr(Val, End)) {
1399  return Error(Tok.getLoc(), "Unexpected identifier!");
1400  } else if (SM.onIdentifierExpr(Val, Identifier, Info, false, ErrMsg)) {
1401  return Error(IdentLoc, ErrMsg);
1402  } else
1403  break;
1404  }
1405  // MS InlineAsm operators (TYPE/LENGTH/SIZE)
1406  if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Identifier)) {
1407  if (OpKind == IOK_OFFSET)
1408  return Error(IdentLoc, "Dealing OFFSET operator as part of"
1409  "a compound immediate expression is yet to be supported");
1410  if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) {
1411  if (SM.onInteger(Val, ErrMsg))
1412  return Error(IdentLoc, ErrMsg);
1413  } else
1414  return true;
1415  break;
1416  }
1417  // MS Dot Operator expression
1418  if (Identifier.count('.') && PrevTK == AsmToken::RBrac) {
1419  if (ParseIntelDotOperator(SM, End))
1420  return true;
1421  break;
1422  }
1423  // MS InlineAsm identifier
1424  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, false, End))
1425  return true;
1426  else if (SM.onIdentifierExpr(Val, Identifier, Info, true, ErrMsg))
1427  return Error(IdentLoc, ErrMsg);
1428  break;
1429  }
1430  case AsmToken::Integer: {
1431  // Look for 'b' or 'f' following an Integer as a directional label
1432  SMLoc Loc = getTok().getLoc();
1433  int64_t IntVal = getTok().getIntVal();
1434  End = consumeToken();
1435  UpdateLocLex = false;
1436  if (getLexer().getKind() == AsmToken::Identifier) {
1437  StringRef IDVal = getTok().getString();
1438  if (IDVal == "f" || IDVal == "b") {
1439  MCSymbol *Sym =
1440  getContext().getDirectionalLocalSymbol(IntVal, IDVal == "b");
1442  const MCExpr *Val =
1443  MCSymbolRefExpr::create(Sym, Variant, getContext());
1444  if (IDVal == "b" && Sym->isUndefined())
1445  return Error(Loc, "invalid reference to undefined symbol");
1446  StringRef Identifier = Sym->getName();
1448  if (SM.onIdentifierExpr(Val, Identifier, Info,
1449  isParsingInlineAsm(), ErrMsg))
1450  return Error(Loc, ErrMsg);
1451  End = consumeToken();
1452  } else {
1453  if (SM.onInteger(IntVal, ErrMsg))
1454  return Error(Loc, ErrMsg);
1455  }
1456  } else {
1457  if (SM.onInteger(IntVal, ErrMsg))
1458  return Error(Loc, ErrMsg);
1459  }
1460  break;
1461  }
1462  case AsmToken::Plus:
1463  if (SM.onPlus(ErrMsg))
1464  return Error(getTok().getLoc(), ErrMsg);
1465  break;
1466  case AsmToken::Minus:
1467  if (SM.onMinus(ErrMsg))
1468  return Error(getTok().getLoc(), ErrMsg);
1469  break;
1470  case AsmToken::Tilde: SM.onNot(); break;
1471  case AsmToken::Star: SM.onStar(); break;
1472  case AsmToken::Slash: SM.onDivide(); break;
1473  case AsmToken::Percent: SM.onMod(); break;
1474  case AsmToken::Pipe: SM.onOr(); break;
1475  case AsmToken::Caret: SM.onXor(); break;
1476  case AsmToken::Amp: SM.onAnd(); break;
1477  case AsmToken::LessLess:
1478  SM.onLShift(); break;
1480  SM.onRShift(); break;
1481  case AsmToken::LBrac:
1482  if (SM.onLBrac())
1483  return Error(Tok.getLoc(), "unexpected bracket encountered");
1484  break;
1485  case AsmToken::RBrac:
1486  if (SM.onRBrac())
1487  return Error(Tok.getLoc(), "unexpected bracket encountered");
1488  break;
1489  case AsmToken::LParen: SM.onLParen(); break;
1490  case AsmToken::RParen: SM.onRParen(); break;
1491  }
1492  if (SM.hadError())
1493  return Error(Tok.getLoc(), "unknown token in expression");
1494 
1495  if (!Done && UpdateLocLex)
1496  End = consumeToken();
1497 
1498  PrevTK = TK;
1499  }
1500  return false;
1501 }
1502 
1503 void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM,
1504  SMLoc Start, SMLoc End) {
1505  SMLoc Loc = Start;
1506  unsigned ExprLen = End.getPointer() - Start.getPointer();
1507  // Skip everything before a symbol displacement (if we have one)
1508  if (SM.getSym()) {
1509  StringRef SymName = SM.getSymName();
1510  if (unsigned Len = SymName.data() - Start.getPointer())
1511  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Start, Len);
1512  Loc = SMLoc::getFromPointer(SymName.data() + SymName.size());
1513  ExprLen = End.getPointer() - (SymName.data() + SymName.size());
1514  // If we have only a symbol than there's no need for complex rewrite,
1515  // simply skip everything after it
1516  if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) {
1517  if (ExprLen)
1518  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Loc, ExprLen);
1519  return;
1520  }
1521  }
1522  // Build an Intel Expression rewrite
1523  StringRef BaseRegStr;
1524  StringRef IndexRegStr;
1525  if (SM.getBaseReg())
1526  BaseRegStr = X86IntelInstPrinter::getRegisterName(SM.getBaseReg());
1527  if (SM.getIndexReg())
1528  IndexRegStr = X86IntelInstPrinter::getRegisterName(SM.getIndexReg());
1529  // Emit it
1530  IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), SM.getImm(), SM.isMemExpr());
1531  InstInfo->AsmRewrites->emplace_back(Loc, ExprLen, Expr);
1532 }
1533 
1534 // Inline assembly may use variable names with namespace alias qualifiers.
1535 bool X86AsmParser::ParseIntelInlineAsmIdentifier(const MCExpr *&Val,
1536  StringRef &Identifier,
1538  bool IsUnevaluatedOperand,
1539  SMLoc &End) {
1540  MCAsmParser &Parser = getParser();
1541  assert(isParsingInlineAsm() && "Expected to be parsing inline assembly.");
1542  Val = nullptr;
1543 
1544  StringRef LineBuf(Identifier.data());
1545  SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
1546 
1547  const AsmToken &Tok = Parser.getTok();
1548  SMLoc Loc = Tok.getLoc();
1549 
1550  // Advance the token stream until the end of the current token is
1551  // after the end of what the frontend claimed.
1552  const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
1553  do {
1554  End = Tok.getEndLoc();
1555  getLexer().Lex();
1556  } while (End.getPointer() < EndPtr);
1557  Identifier = LineBuf;
1558 
1559  // The frontend should end parsing on an assembler token boundary, unless it
1560  // failed parsing.
1561  assert((End.getPointer() == EndPtr ||
1563  "frontend claimed part of a token?");
1564 
1565  // If the identifier lookup was unsuccessful, assume that we are dealing with
1566  // a label.
1568  StringRef InternalName =
1569  SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(),
1570  Loc, false);
1571  assert(InternalName.size() && "We should have an internal name here.");
1572  // Push a rewrite for replacing the identifier name with the internal name.
1573  InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(),
1574  InternalName);
1576  return false;
1577  // Create the symbol reference.
1578  MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
1580  Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext());
1581  return false;
1582 }
1583 
1584 //ParseRoundingModeOp - Parse AVX-512 rounding mode operand
1585 std::unique_ptr<X86Operand>
1586 X86AsmParser::ParseRoundingModeOp(SMLoc Start, SMLoc End) {
1587  MCAsmParser &Parser = getParser();
1588  const AsmToken &Tok = Parser.getTok();
1589  // Eat "{" and mark the current place.
1590  const SMLoc consumedToken = consumeToken();
1591  if (Tok.getIdentifier().startswith("r")){
1592  int rndMode = StringSwitch<int>(Tok.getIdentifier())
1597  .Default(-1);
1598  if (-1 == rndMode)
1599  return ErrorOperand(Tok.getLoc(), "Invalid rounding mode.");
1600  Parser.Lex(); // Eat "r*" of r*-sae
1601  if (!getLexer().is(AsmToken::Minus))
1602  return ErrorOperand(Tok.getLoc(), "Expected - at this point");
1603  Parser.Lex(); // Eat "-"
1604  Parser.Lex(); // Eat the sae
1605  if (!getLexer().is(AsmToken::RCurly))
1606  return ErrorOperand(Tok.getLoc(), "Expected } at this point");
1607  Parser.Lex(); // Eat "}"
1608  const MCExpr *RndModeOp =
1609  MCConstantExpr::create(rndMode, Parser.getContext());
1610  return X86Operand::CreateImm(RndModeOp, Start, End);
1611  }
1612  if(Tok.getIdentifier().equals("sae")){
1613  Parser.Lex(); // Eat the sae
1614  if (!getLexer().is(AsmToken::RCurly))
1615  return ErrorOperand(Tok.getLoc(), "Expected } at this point");
1616  Parser.Lex(); // Eat "}"
1617  return X86Operand::CreateToken("{sae}", consumedToken);
1618  }
1619  return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1620 }
1621 
1622 /// Parse the '.' operator.
1623 bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End) {
1624  const AsmToken &Tok = getTok();
1625  unsigned Offset;
1626 
1627  // Drop the optional '.'.
1628  StringRef DotDispStr = Tok.getString();
1629  if (DotDispStr.startswith("."))
1630  DotDispStr = DotDispStr.drop_front(1);
1631 
1632  // .Imm gets lexed as a real.
1633  if (Tok.is(AsmToken::Real)) {
1634  APInt DotDisp;
1635  DotDispStr.getAsInteger(10, DotDisp);
1636  Offset = DotDisp.getZExtValue();
1637  } else if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1638  std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1639  if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
1640  Offset))
1641  return Error(Tok.getLoc(), "Unable to lookup field reference!");
1642  } else
1643  return Error(Tok.getLoc(), "Unexpected token type!");
1644 
1645  // Eat the DotExpression and update End
1646  End = SMLoc::getFromPointer(DotDispStr.data());
1647  const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size();
1648  while (Tok.getLoc().getPointer() < DotExprEndLoc)
1649  Lex();
1650  SM.addImm(Offset);
1651  return false;
1652 }
1653 
1654 /// Parse the 'offset' operator. This operator is used to specify the
1655 /// location rather then the content of a variable.
1656 std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOffsetOfOperator() {
1657  MCAsmParser &Parser = getParser();
1658  const AsmToken &Tok = Parser.getTok();
1659  SMLoc OffsetOfLoc = Tok.getLoc();
1660  Parser.Lex(); // Eat offset.
1661 
1662  const MCExpr *Val;
1664  SMLoc Start = Tok.getLoc(), End;
1665  StringRef Identifier = Tok.getString();
1666  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
1667  /*Unevaluated=*/false, End))
1668  return nullptr;
1669 
1670  void *Decl = nullptr;
1671  // FIXME: MS evaluates "offset <Constant>" to the underlying integral
1673  return ErrorOperand(Start, "offset operator cannot yet handle constants");
1674  else if (Info.isKind(InlineAsmIdentifierInfo::IK_Var))
1675  Decl = Info.Var.Decl;
1676  // Don't emit the offset operator.
1677  InstInfo->AsmRewrites->emplace_back(AOK_Skip, OffsetOfLoc, 7);
1678 
1679  // The offset operator will have an 'r' constraint, thus we need to create
1680  // register operand to ensure proper matching. Just pick a GPR based on
1681  // the size of a pointer.
1682  bool Parse32 = is32BitMode() || Code16GCC;
1683  unsigned RegNo = is64BitMode() ? X86::RBX : (Parse32 ? X86::EBX : X86::BX);
1684 
1685  return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
1686  OffsetOfLoc, Identifier, Decl);
1687 }
1688 
1689 // Query a candidate string for being an Intel assembly operator
1690 // Report back its kind, or IOK_INVALID if does not evaluated as a known one
1691 unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
1693  .Cases("TYPE","type",IOK_TYPE)
1694  .Cases("SIZE","size",IOK_SIZE)
1695  .Cases("LENGTH","length",IOK_LENGTH)
1696  .Cases("OFFSET","offset",IOK_OFFSET)
1697  .Default(IOK_INVALID);
1698 }
1699 
1700 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
1701 /// returns the number of elements in an array. It returns the value 1 for
1702 /// non-array variables. The SIZE operator returns the size of a C or C++
1703 /// variable. A variable's size is the product of its LENGTH and TYPE. The
1704 /// TYPE operator returns the size of a C or C++ type or variable. If the
1705 /// variable is an array, TYPE returns the size of a single element.
1706 unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) {
1707  MCAsmParser &Parser = getParser();
1708  const AsmToken &Tok = Parser.getTok();
1709  Parser.Lex(); // Eat operator.
1710 
1711  const MCExpr *Val = nullptr;
1713  SMLoc Start = Tok.getLoc(), End;
1714  StringRef Identifier = Tok.getString();
1715  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
1716  /*Unevaluated=*/true, End))
1717  return 0;
1718 
1720  Error(Start, "unable to lookup expression");
1721  return 0;
1722  }
1723 
1724  unsigned CVal = 0;
1725  switch(OpKind) {
1726  default: llvm_unreachable("Unexpected operand kind!");
1727  case IOK_LENGTH: CVal = Info.Var.Length; break;
1728  case IOK_SIZE: CVal = Info.Var.Size; break;
1729  case IOK_TYPE: CVal = Info.Var.Type; break;
1730  }
1731 
1732  return CVal;
1733 }
1734 
1735 bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
1736  Size = StringSwitch<unsigned>(getTok().getString())
1737  .Cases("BYTE", "byte", 8)
1738  .Cases("WORD", "word", 16)
1739  .Cases("DWORD", "dword", 32)
1740  .Cases("FLOAT", "float", 32)
1741  .Cases("LONG", "long", 32)
1742  .Cases("FWORD", "fword", 48)
1743  .Cases("DOUBLE", "double", 64)
1744  .Cases("QWORD", "qword", 64)
1745  .Cases("MMWORD","mmword", 64)
1746  .Cases("XWORD", "xword", 80)
1747  .Cases("TBYTE", "tbyte", 80)
1748  .Cases("XMMWORD", "xmmword", 128)
1749  .Cases("YMMWORD", "ymmword", 256)
1750  .Cases("ZMMWORD", "zmmword", 512)
1751  .Cases("OPAQUE", "opaque", -1U) // needs to be non-zero, but doesn't matter
1752  .Default(0);
1753  if (Size) {
1754  const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word).
1755  if (!(Tok.getString().equals("PTR") || Tok.getString().equals("ptr")))
1756  return Error(Tok.getLoc(), "Expected 'PTR' or 'ptr' token!");
1757  Lex(); // Eat ptr.
1758  }
1759  return false;
1760 }
1761 
1762 std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
1763  MCAsmParser &Parser = getParser();
1764  const AsmToken &Tok = Parser.getTok();
1765  SMLoc Start, End;
1766 
1767  // FIXME: Offset operator
1768  // Should be handled as part of immediate expression, as other operators
1769  // Currently, only supported as a stand-alone operand
1770  if (isParsingInlineAsm())
1771  if (IdentifyIntelInlineAsmOperator(Tok.getString()) == IOK_OFFSET)
1772  return ParseIntelOffsetOfOperator();
1773 
1774  // Parse optional Size directive.
1775  unsigned Size;
1776  if (ParseIntelMemoryOperandSize(Size))
1777  return nullptr;
1778  bool PtrInOperand = bool(Size);
1779 
1780  Start = Tok.getLoc();
1781 
1782  // Rounding mode operand.
1783  if (getSTI().getFeatureBits()[X86::FeatureAVX512] &&
1784  getLexer().is(AsmToken::LCurly))
1785  return ParseRoundingModeOp(Start, End);
1786 
1787  // Register operand.
1788  unsigned RegNo = 0;
1789  if (Tok.is(AsmToken::Identifier) && !ParseRegister(RegNo, Start, End)) {
1790  if (RegNo == X86::RIP)
1791  return ErrorOperand(Start, "rip can only be used as a base register");
1792  // A Register followed by ':' is considered a segment override
1793  if (Tok.isNot(AsmToken::Colon))
1794  return !PtrInOperand ? X86Operand::CreateReg(RegNo, Start, End) :
1795  ErrorOperand(Start, "expected memory operand after 'ptr', "
1796  "found register operand instead");
1797  // An alleged segment override. check if we have a valid segment register
1798  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
1799  return ErrorOperand(Start, "invalid segment register");
1800  // Eat ':' and update Start location
1801  Start = Lex().getLoc();
1802  }
1803 
1804  // Immediates and Memory
1805  IntelExprStateMachine SM;
1806  if (ParseIntelExpression(SM, End))
1807  return nullptr;
1808 
1809  if (isParsingInlineAsm())
1810  RewriteIntelExpression(SM, Start, Tok.getLoc());
1811 
1812  int64_t Imm = SM.getImm();
1813  const MCExpr *Disp = SM.getSym();
1814  const MCExpr *ImmDisp = MCConstantExpr::create(Imm, getContext());
1815  if (Disp && Imm)
1816  Disp = MCBinaryExpr::createAdd(Disp, ImmDisp, getContext());
1817  if (!Disp)
1818  Disp = ImmDisp;
1819 
1820  // RegNo != 0 specifies a valid segment register,
1821  // and we are parsing a segment override
1822  if (!SM.isMemExpr() && !RegNo)
1823  return X86Operand::CreateImm(Disp, Start, End);
1824 
1825  StringRef ErrMsg;
1826  unsigned BaseReg = SM.getBaseReg();
1827  unsigned IndexReg = SM.getIndexReg();
1828  unsigned Scale = SM.getScale();
1829 
1830  if ((BaseReg || IndexReg) &&
1831  CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, ErrMsg))
1832  return ErrorOperand(Start, ErrMsg);
1833  if (isParsingInlineAsm())
1834  return CreateMemForInlineAsm(RegNo, Disp, BaseReg, IndexReg,
1835  Scale, Start, End, Size, SM.getSymName(),
1836  SM.getIdentifierInfo());
1837  if (!(BaseReg || IndexReg || RegNo))
1838  return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size);
1839  return X86Operand::CreateMem(getPointerWidth(), RegNo, Disp,
1840  BaseReg, IndexReg, Scale, Start, End, Size);
1841 }
1842 
1843 std::unique_ptr<X86Operand> X86AsmParser::ParseATTOperand() {
1844  MCAsmParser &Parser = getParser();
1845  switch (getLexer().getKind()) {
1846  default:
1847  // Parse a memory operand with no segment register.
1848  return ParseMemOperand(0, Parser.getTok().getLoc());
1849  case AsmToken::Percent: {
1850  // Read the register.
1851  unsigned RegNo;
1852  SMLoc Start, End;
1853  if (ParseRegister(RegNo, Start, End)) return nullptr;
1854  if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
1855  Error(Start, "%eiz and %riz can only be used as index registers",
1856  SMRange(Start, End));
1857  return nullptr;
1858  }
1859  if (RegNo == X86::RIP) {
1860  Error(Start, "%rip can only be used as a base register",
1861  SMRange(Start, End));
1862  return nullptr;
1863  }
1864 
1865  // If this is a segment register followed by a ':', then this is the start
1866  // of a memory reference, otherwise this is a normal register reference.
1867  if (getLexer().isNot(AsmToken::Colon))
1868  return X86Operand::CreateReg(RegNo, Start, End);
1869 
1870  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
1871  return ErrorOperand(Start, "invalid segment register");
1872 
1873  getParser().Lex(); // Eat the colon.
1874  return ParseMemOperand(RegNo, Start);
1875  }
1876  case AsmToken::Dollar: {
1877  // $42 -> immediate.
1878  SMLoc Start = Parser.getTok().getLoc(), End;
1879  Parser.Lex();
1880  const MCExpr *Val;
1881  if (getParser().parseExpression(Val, End))
1882  return nullptr;
1883  return X86Operand::CreateImm(Val, Start, End);
1884  }
1885  case AsmToken::LCurly:{
1886  SMLoc Start = Parser.getTok().getLoc(), End;
1887  if (getSTI().getFeatureBits()[X86::FeatureAVX512])
1888  return ParseRoundingModeOp(Start, End);
1889  return ErrorOperand(Start, "Unexpected '{' in expression");
1890  }
1891  }
1892 }
1893 
1894 // true on failure, false otherwise
1895 // If no {z} mark was found - Parser doesn't advance
1896 bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
1897  const SMLoc &StartLoc) {
1898  MCAsmParser &Parser = getParser();
1899  // Assuming we are just pass the '{' mark, quering the next token
1900  // Searched for {z}, but none was found. Return false, as no parsing error was
1901  // encountered
1902  if (!(getLexer().is(AsmToken::Identifier) &&
1903  (getLexer().getTok().getIdentifier() == "z")))
1904  return false;
1905  Parser.Lex(); // Eat z
1906  // Query and eat the '}' mark
1907  if (!getLexer().is(AsmToken::RCurly))
1908  return Error(getLexer().getLoc(), "Expected } at this point");
1909  Parser.Lex(); // Eat '}'
1910  // Assign Z with the {z} mark opernad
1911  Z = X86Operand::CreateToken("{z}", StartLoc);
1912  return false;
1913 }
1914 
1915 // true on failure, false otherwise
1916 bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
1917  const MCParsedAsmOperand &Op) {
1918  MCAsmParser &Parser = getParser();
1919  if(getSTI().getFeatureBits()[X86::FeatureAVX512]) {
1920  if (getLexer().is(AsmToken::LCurly)) {
1921  // Eat "{" and mark the current place.
1922  const SMLoc consumedToken = consumeToken();
1923  // Distinguish {1to<NUM>} from {%k<NUM>}.
1924  if(getLexer().is(AsmToken::Integer)) {
1925  // Parse memory broadcasting ({1to<NUM>}).
1926  if (getLexer().getTok().getIntVal() != 1)
1927  return TokError("Expected 1to<NUM> at this point");
1928  Parser.Lex(); // Eat "1" of 1to8
1929  if (!getLexer().is(AsmToken::Identifier) ||
1930  !getLexer().getTok().getIdentifier().startswith("to"))
1931  return TokError("Expected 1to<NUM> at this point");
1932  // Recognize only reasonable suffixes.
1933  const char *BroadcastPrimitive =
1934  StringSwitch<const char*>(getLexer().getTok().getIdentifier())
1935  .Case("to2", "{1to2}")
1936  .Case("to4", "{1to4}")
1937  .Case("to8", "{1to8}")
1938  .Case("to16", "{1to16}")
1939  .Default(nullptr);
1940  if (!BroadcastPrimitive)
1941  return TokError("Invalid memory broadcast primitive.");
1942  Parser.Lex(); // Eat "toN" of 1toN
1943  if (!getLexer().is(AsmToken::RCurly))
1944  return TokError("Expected } at this point");
1945  Parser.Lex(); // Eat "}"
1946  Operands.push_back(X86Operand::CreateToken(BroadcastPrimitive,
1947  consumedToken));
1948  // No AVX512 specific primitives can pass
1949  // after memory broadcasting, so return.
1950  return false;
1951  } else {
1952  // Parse either {k}{z}, {z}{k}, {k} or {z}
1953  // last one have no meaning, but GCC accepts it
1954  // Currently, we're just pass a '{' mark
1955  std::unique_ptr<X86Operand> Z;
1956  if (ParseZ(Z, consumedToken))
1957  return true;
1958  // Reaching here means that parsing of the allegadly '{z}' mark yielded
1959  // no errors.
1960  // Query for the need of further parsing for a {%k<NUM>} mark
1961  if (!Z || getLexer().is(AsmToken::LCurly)) {
1962  SMLoc StartLoc = Z ? consumeToken() : consumedToken;
1963  // Parse an op-mask register mark ({%k<NUM>}), which is now to be
1964  // expected
1965  unsigned RegNo;
1966  SMLoc RegLoc;
1967  if (!ParseRegister(RegNo, RegLoc, StartLoc) &&
1968  X86MCRegisterClasses[X86::VK1RegClassID].contains(RegNo)) {
1969  if (RegNo == X86::K0)
1970  return Error(RegLoc, "Register k0 can't be used as write mask");
1971  if (!getLexer().is(AsmToken::RCurly))
1972  return Error(getLexer().getLoc(), "Expected } at this point");
1973  Operands.push_back(X86Operand::CreateToken("{", StartLoc));
1974  Operands.push_back(
1975  X86Operand::CreateReg(RegNo, StartLoc, StartLoc));
1976  Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
1977  } else
1978  return Error(getLexer().getLoc(),
1979  "Expected an op-mask register at this point");
1980  // {%k<NUM>} mark is found, inquire for {z}
1981  if (getLexer().is(AsmToken::LCurly) && !Z) {
1982  // Have we've found a parsing error, or found no (expected) {z} mark
1983  // - report an error
1984  if (ParseZ(Z, consumeToken()) || !Z)
1985  return Error(getLexer().getLoc(),
1986  "Expected a {z} mark at this point");
1987 
1988  }
1989  // '{z}' on its own is meaningless, hence should be ignored.
1990  // on the contrary - have it been accompanied by a K register,
1991  // allow it.
1992  if (Z)
1993  Operands.push_back(std::move(Z));
1994  }
1995  }
1996  }
1997  }
1998  return false;
1999 }
2000 
2001 /// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
2002 /// has already been parsed if present.
2003 std::unique_ptr<X86Operand> X86AsmParser::ParseMemOperand(unsigned SegReg,
2004  SMLoc MemStart) {
2005 
2006  MCAsmParser &Parser = getParser();
2007  // We have to disambiguate a parenthesized expression "(4+5)" from the start
2008  // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
2009  // only way to do this without lookahead is to eat the '(' and see what is
2010  // after it.
2011  const MCExpr *Disp = MCConstantExpr::create(0, getParser().getContext());
2012  if (getLexer().isNot(AsmToken::LParen)) {
2013  SMLoc ExprEnd;
2014  if (getParser().parseExpression(Disp, ExprEnd)) return nullptr;
2015 
2016  // After parsing the base expression we could either have a parenthesized
2017  // memory address or not. If not, return now. If so, eat the (.
2018  if (getLexer().isNot(AsmToken::LParen)) {
2019  // Unless we have a segment register, treat this as an immediate.
2020  if (SegReg == 0)
2021  return X86Operand::CreateMem(getPointerWidth(), Disp, MemStart, ExprEnd);
2022  return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
2023  MemStart, ExprEnd);
2024  }
2025 
2026  // Eat the '('.
2027  Parser.Lex();
2028  } else {
2029  // Okay, we have a '('. We don't know if this is an expression or not, but
2030  // so we have to eat the ( to see beyond it.
2031  SMLoc LParenLoc = Parser.getTok().getLoc();
2032  Parser.Lex(); // Eat the '('.
2033 
2034  if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
2035  // Nothing to do here, fall into the code below with the '(' part of the
2036  // memory operand consumed.
2037  } else {
2038  SMLoc ExprEnd;
2039  getLexer().UnLex(AsmToken(AsmToken::LParen, "("));
2040 
2041  // It must be either an parenthesized expression, or an expression that
2042  // begins from a parenthesized expression, parse it now. Example: (1+2) or
2043  // (1+2)+3
2044  if (getParser().parseExpression(Disp, ExprEnd))
2045  return nullptr;
2046 
2047  // After parsing the base expression we could either have a parenthesized
2048  // memory address or not. If not, return now. If so, eat the (.
2049  if (getLexer().isNot(AsmToken::LParen)) {
2050  // Unless we have a segment register, treat this as an immediate.
2051  if (SegReg == 0)
2052  return X86Operand::CreateMem(getPointerWidth(), Disp, LParenLoc,
2053  ExprEnd);
2054  return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
2055  MemStart, ExprEnd);
2056  }
2057 
2058  // Eat the '('.
2059  Parser.Lex();
2060  }
2061  }
2062 
2063  // If we reached here, then we just ate the ( of the memory operand. Process
2064  // the rest of the memory operand.
2065  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
2066  SMLoc IndexLoc, BaseLoc;
2067 
2068  if (getLexer().is(AsmToken::Percent)) {
2069  SMLoc StartLoc, EndLoc;
2070  BaseLoc = Parser.getTok().getLoc();
2071  if (ParseRegister(BaseReg, StartLoc, EndLoc)) return nullptr;
2072  if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
2073  Error(StartLoc, "eiz and riz can only be used as index registers",
2074  SMRange(StartLoc, EndLoc));
2075  return nullptr;
2076  }
2077  }
2078 
2079  if (getLexer().is(AsmToken::Comma)) {
2080  Parser.Lex(); // Eat the comma.
2081  IndexLoc = Parser.getTok().getLoc();
2082 
2083  // Following the comma we should have either an index register, or a scale
2084  // value. We don't support the later form, but we want to parse it
2085  // correctly.
2086  //
2087  // Not that even though it would be completely consistent to support syntax
2088  // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
2089  if (getLexer().is(AsmToken::Percent)) {
2090  SMLoc L;
2091  if (ParseRegister(IndexReg, L, L))
2092  return nullptr;
2093  if (BaseReg == X86::RIP) {
2094  Error(IndexLoc, "%rip as base register can not have an index register");
2095  return nullptr;
2096  }
2097  if (IndexReg == X86::RIP) {
2098  Error(IndexLoc, "%rip is not allowed as an index register");
2099  return nullptr;
2100  }
2101 
2102  if (getLexer().isNot(AsmToken::RParen)) {
2103  // Parse the scale amount:
2104  // ::= ',' [scale-expression]
2105  if (getLexer().isNot(AsmToken::Comma)) {
2106  Error(Parser.getTok().getLoc(),
2107  "expected comma in scale expression");
2108  return nullptr;
2109  }
2110  Parser.Lex(); // Eat the comma.
2111 
2112  if (getLexer().isNot(AsmToken::RParen)) {
2113  SMLoc Loc = Parser.getTok().getLoc();
2114 
2115  int64_t ScaleVal;
2116  if (getParser().parseAbsoluteExpression(ScaleVal)){
2117  Error(Loc, "expected scale expression");
2118  return nullptr;
2119  }
2120 
2121  // Validate the scale amount.
2122  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2123  ScaleVal != 1) {
2124  Error(Loc, "scale factor in 16-bit address must be 1");
2125  return nullptr;
2126  }
2127  if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 &&
2128  ScaleVal != 8) {
2129  Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
2130  return nullptr;
2131  }
2132  Scale = (unsigned)ScaleVal;
2133  }
2134  }
2135  } else if (getLexer().isNot(AsmToken::RParen)) {
2136  // A scale amount without an index is ignored.
2137  // index.
2138  SMLoc Loc = Parser.getTok().getLoc();
2139 
2140  int64_t Value;
2141  if (getParser().parseAbsoluteExpression(Value))
2142  return nullptr;
2143 
2144  if (Value != 1)
2145  Warning(Loc, "scale factor without index register is ignored");
2146  Scale = 1;
2147  }
2148  }
2149 
2150  // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
2151  if (getLexer().isNot(AsmToken::RParen)) {
2152  Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
2153  return nullptr;
2154  }
2155  SMLoc MemEnd = Parser.getTok().getEndLoc();
2156  Parser.Lex(); // Eat the ')'.
2157 
2158  // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
2159  // and then only in non-64-bit modes. Except for DX, which is a special case
2160  // because an unofficial form of in/out instructions uses it.
2161  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2162  (is64BitMode() || (BaseReg != X86::BX && BaseReg != X86::BP &&
2163  BaseReg != X86::SI && BaseReg != X86::DI)) &&
2164  BaseReg != X86::DX) {
2165  Error(BaseLoc, "invalid 16-bit base register");
2166  return nullptr;
2167  }
2168  if (BaseReg == 0 &&
2169  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
2170  Error(IndexLoc, "16-bit memory operand may not include only index register");
2171  return nullptr;
2172  }
2173 
2174  StringRef ErrMsg;
2175  if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, ErrMsg)) {
2176  Error(BaseLoc, ErrMsg);
2177  return nullptr;
2178  }
2179 
2180  if (SegReg || BaseReg || IndexReg)
2181  return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
2182  IndexReg, Scale, MemStart, MemEnd);
2183  return X86Operand::CreateMem(getPointerWidth(), Disp, MemStart, MemEnd);
2184 }
2185 
2186 bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
2187  SMLoc NameLoc, OperandVector &Operands) {
2188  MCAsmParser &Parser = getParser();
2189  InstInfo = &Info;
2190  StringRef PatchedName = Name;
2191 
2192  if ((Name.equals("jmp") || Name.equals("jc") || Name.equals("jz")) &&
2193  isParsingIntelSyntax() && isParsingInlineAsm()) {
2194  StringRef NextTok = Parser.getTok().getString();
2195  if (NextTok == "short") {
2196  SMLoc NameEndLoc =
2197  NameLoc.getFromPointer(NameLoc.getPointer() + Name.size());
2198  // Eat the short keyword
2199  Parser.Lex();
2200  // MS ignores the short keyword, it determines the jmp type based
2201  // on the distance of the label
2202  InstInfo->AsmRewrites->emplace_back(AOK_Skip, NameEndLoc,
2203  NextTok.size() + 1);
2204  }
2205  }
2206 
2207  // FIXME: Hack to recognize setneb as setne.
2208  if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
2209  PatchedName != "setb" && PatchedName != "setnb")
2210  PatchedName = PatchedName.substr(0, Name.size()-1);
2211 
2212  // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
2213  if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
2214  (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
2215  PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
2216  bool IsVCMP = PatchedName[0] == 'v';
2217  unsigned CCIdx = IsVCMP ? 4 : 3;
2218  unsigned ComparisonCode = StringSwitch<unsigned>(
2219  PatchedName.slice(CCIdx, PatchedName.size() - 2))
2220  .Case("eq", 0x00)
2221  .Case("eq_oq", 0x00)
2222  .Case("lt", 0x01)
2223  .Case("lt_os", 0x01)
2224  .Case("le", 0x02)
2225  .Case("le_os", 0x02)
2226  .Case("unord", 0x03)
2227  .Case("unord_q", 0x03)
2228  .Case("neq", 0x04)
2229  .Case("neq_uq", 0x04)
2230  .Case("nlt", 0x05)
2231  .Case("nlt_us", 0x05)
2232  .Case("nle", 0x06)
2233  .Case("nle_us", 0x06)
2234  .Case("ord", 0x07)
2235  .Case("ord_q", 0x07)
2236  /* AVX only from here */
2237  .Case("eq_uq", 0x08)
2238  .Case("nge", 0x09)
2239  .Case("nge_us", 0x09)
2240  .Case("ngt", 0x0A)
2241  .Case("ngt_us", 0x0A)
2242  .Case("false", 0x0B)
2243  .Case("false_oq", 0x0B)
2244  .Case("neq_oq", 0x0C)
2245  .Case("ge", 0x0D)
2246  .Case("ge_os", 0x0D)
2247  .Case("gt", 0x0E)
2248  .Case("gt_os", 0x0E)
2249  .Case("true", 0x0F)
2250  .Case("true_uq", 0x0F)
2251  .Case("eq_os", 0x10)
2252  .Case("lt_oq", 0x11)
2253  .Case("le_oq", 0x12)
2254  .Case("unord_s", 0x13)
2255  .Case("neq_us", 0x14)
2256  .Case("nlt_uq", 0x15)
2257  .Case("nle_uq", 0x16)
2258  .Case("ord_s", 0x17)
2259  .Case("eq_us", 0x18)
2260  .Case("nge_uq", 0x19)
2261  .Case("ngt_uq", 0x1A)
2262  .Case("false_os", 0x1B)
2263  .Case("neq_os", 0x1C)
2264  .Case("ge_oq", 0x1D)
2265  .Case("gt_oq", 0x1E)
2266  .Case("true_us", 0x1F)
2267  .Default(~0U);
2268  if (ComparisonCode != ~0U && (IsVCMP || ComparisonCode < 8)) {
2269 
2270  Operands.push_back(X86Operand::CreateToken(PatchedName.slice(0, CCIdx),
2271  NameLoc));
2272 
2273  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
2274  getParser().getContext());
2275  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2276 
2277  PatchedName = PatchedName.substr(PatchedName.size() - 2);
2278  }
2279  }
2280 
2281  // FIXME: Hack to recognize vpcmp<comparison code>{ub,uw,ud,uq,b,w,d,q}.
2282  if (PatchedName.startswith("vpcmp") &&
2283  (PatchedName.endswith("b") || PatchedName.endswith("w") ||
2284  PatchedName.endswith("d") || PatchedName.endswith("q"))) {
2285  unsigned CCIdx = PatchedName.drop_back().back() == 'u' ? 2 : 1;
2286  unsigned ComparisonCode = StringSwitch<unsigned>(
2287  PatchedName.slice(5, PatchedName.size() - CCIdx))
2288  .Case("eq", 0x0) // Only allowed on unsigned. Checked below.
2289  .Case("lt", 0x1)
2290  .Case("le", 0x2)
2291  //.Case("false", 0x3) // Not a documented alias.
2292  .Case("neq", 0x4)
2293  .Case("nlt", 0x5)
2294  .Case("nle", 0x6)
2295  //.Case("true", 0x7) // Not a documented alias.
2296  .Default(~0U);
2297  if (ComparisonCode != ~0U && (ComparisonCode != 0 || CCIdx == 2)) {
2298  Operands.push_back(X86Operand::CreateToken("vpcmp", NameLoc));
2299 
2300  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
2301  getParser().getContext());
2302  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2303 
2304  PatchedName = PatchedName.substr(PatchedName.size() - CCIdx);
2305  }
2306  }
2307 
2308  // FIXME: Hack to recognize vpcom<comparison code>{ub,uw,ud,uq,b,w,d,q}.
2309  if (PatchedName.startswith("vpcom") &&
2310  (PatchedName.endswith("b") || PatchedName.endswith("w") ||
2311  PatchedName.endswith("d") || PatchedName.endswith("q"))) {
2312  unsigned CCIdx = PatchedName.drop_back().back() == 'u' ? 2 : 1;
2313  unsigned ComparisonCode = StringSwitch<unsigned>(
2314  PatchedName.slice(5, PatchedName.size() - CCIdx))
2315  .Case("lt", 0x0)
2316  .Case("le", 0x1)
2317  .Case("gt", 0x2)
2318  .Case("ge", 0x3)
2319  .Case("eq", 0x4)
2320  .Case("neq", 0x5)
2321  .Case("false", 0x6)
2322  .Case("true", 0x7)
2323  .Default(~0U);
2324  if (ComparisonCode != ~0U) {
2325  Operands.push_back(X86Operand::CreateToken("vpcom", NameLoc));
2326 
2327  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
2328  getParser().getContext());
2329  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2330 
2331  PatchedName = PatchedName.substr(PatchedName.size() - CCIdx);
2332  }
2333  }
2334 
2335 
2336  // Determine whether this is an instruction prefix.
2337  // FIXME:
2338  // Enhance prefixes integrity robustness. for example, following forms
2339  // are currently tolerated:
2340  // repz repnz <insn> ; GAS errors for the use of two similar prefixes
2341  // lock addq %rax, %rbx ; Destination operand must be of memory type
2342  // xacquire <insn> ; xacquire must be accompanied by 'lock'
2344  .Cases("rex64", "data32", "data16", true)
2345  .Cases("xacquire", "xrelease", true)
2346  .Cases("acquire", "release", isParsingIntelSyntax())
2347  .Default(false);
2348 
2349  auto isLockRepeatPrefix = [](StringRef N) {
2350  return StringSwitch<bool>(N)
2351  .Cases("lock", "rep", "repe", "repz", "repne", "repnz", true)
2352  .Default(false);
2353  };
2354 
2355  bool CurlyAsEndOfStatement = false;
2356 
2357  unsigned Flags = X86::IP_NO_PREFIX;
2358  while (isLockRepeatPrefix(Name.lower())) {
2359  unsigned Prefix =
2361  .Cases("lock", "lock", X86::IP_HAS_LOCK)
2362  .Cases("rep", "repe", "repz", X86::IP_HAS_REPEAT)
2363  .Cases("repne", "repnz", X86::IP_HAS_REPEAT_NE)
2364  .Default(X86::IP_NO_PREFIX); // Invalid prefix (impossible)
2365  Flags |= Prefix;
2366  Name = Parser.getTok().getString();
2367  Parser.Lex(); // eat the prefix
2368  // Hack: we could have something like
2369  // "lock; cmpxchg16b $1" or "lock\0A\09incl" or "lock/incl"
2370  while (Name.startswith(";") || Name.startswith("\n") ||
2371  Name.startswith("\t") || Name.startswith("/")) {
2372  Name = Parser.getTok().getString();
2373  Parser.Lex(); // go to next prefix or instr
2374  }
2375  }
2376 
2377  if (Flags)
2378  PatchedName = Name;
2379  Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
2380 
2381  // This does the actual operand parsing. Don't parse any more if we have a
2382  // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
2383  // just want to parse the "lock" as the first instruction and the "incl" as
2384  // the next one.
2385  if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
2386  // Parse '*' modifier.
2387  if (getLexer().is(AsmToken::Star))
2388  Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
2389 
2390  // Read the operands.
2391  while(1) {
2392  if (std::unique_ptr<X86Operand> Op = ParseOperand()) {
2393  Operands.push_back(std::move(Op));
2394  if (HandleAVX512Operand(Operands, *Operands.back()))
2395  return true;
2396  } else {
2397  return true;
2398  }
2399  // check for comma and eat it
2400  if (getLexer().is(AsmToken::Comma))
2401  Parser.Lex();
2402  else
2403  break;
2404  }
2405 
2406  // In MS inline asm curly braces mark the beginning/end of a block,
2407  // therefore they should be interepreted as end of statement
2408  CurlyAsEndOfStatement =
2409  isParsingIntelSyntax() && isParsingInlineAsm() &&
2410  (getLexer().is(AsmToken::LCurly) || getLexer().is(AsmToken::RCurly));
2411  if (getLexer().isNot(AsmToken::EndOfStatement) && !CurlyAsEndOfStatement)
2412  return TokError("unexpected token in argument list");
2413  }
2414 
2415  // Consume the EndOfStatement or the prefix separator Slash
2416  if (getLexer().is(AsmToken::EndOfStatement) ||
2417  (isPrefix && getLexer().is(AsmToken::Slash)))
2418  Parser.Lex();
2419  else if (CurlyAsEndOfStatement)
2420  // Add an actual EndOfStatement before the curly brace
2421  Info.AsmRewrites->emplace_back(AOK_EndOfStatement,
2422  getLexer().getTok().getLoc(), 0);
2423 
2424  // This is for gas compatibility and cannot be done in td.
2425  // Adding "p" for some floating point with no argument.
2426  // For example: fsub --> fsubp
2427  bool IsFp =
2428  Name == "fsub" || Name == "fdiv" || Name == "fsubr" || Name == "fdivr";
2429  if (IsFp && Operands.size() == 1) {
2430  const char *Repl = StringSwitch<const char *>(Name)
2431  .Case("fsub", "fsubp")
2432  .Case("fdiv", "fdivp")
2433  .Case("fsubr", "fsubrp")
2434  .Case("fdivr", "fdivrp");
2435  static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl);
2436  }
2437 
2438  // Moving a 32 or 16 bit value into a segment register has the same
2439  // behavior. Modify such instructions to always take shorter form.
2440  if ((Name == "mov" || Name == "movw" || Name == "movl") &&
2441  (Operands.size() == 3)) {
2442  X86Operand &Op1 = (X86Operand &)*Operands[1];
2443  X86Operand &Op2 = (X86Operand &)*Operands[2];
2444  SMLoc Loc = Op1.getEndLoc();
2445  if (Op1.isReg() && Op2.isReg() &&
2446  X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(
2447  Op2.getReg()) &&
2448  (X86MCRegisterClasses[X86::GR16RegClassID].contains(Op1.getReg()) ||
2449  X86MCRegisterClasses[X86::GR32RegClassID].contains(Op1.getReg()))) {
2450  // Change instruction name to match new instruction.
2451  if (Name != "mov" && Name[3] == (is16BitMode() ? 'l' : 'w')) {
2452  Name = is16BitMode() ? "movw" : "movl";
2453  Operands[0] = X86Operand::CreateToken(Name, NameLoc);
2454  }
2455  // Select the correct equivalent 16-/32-bit source register.
2456  unsigned Reg =
2457  getX86SubSuperRegisterOrZero(Op1.getReg(), is16BitMode() ? 16 : 32);
2458  Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc);
2459  }
2460  }
2461 
2462  // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
2463  // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
2464  // documented form in various unofficial manuals, so a lot of code uses it.
2465  if ((Name == "outb" || Name == "outsb" || Name == "outw" || Name == "outsw" ||
2466  Name == "outl" || Name == "outsl" || Name == "out" || Name == "outs") &&
2467  Operands.size() == 3) {
2468  X86Operand &Op = (X86Operand &)*Operands.back();
2469  if (Op.isMem() && Op.Mem.SegReg == 0 &&
2470  isa<MCConstantExpr>(Op.Mem.Disp) &&
2471  cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2472  Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2473  SMLoc Loc = Op.getEndLoc();
2474  Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
2475  }
2476  }
2477  // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al".
2478  if ((Name == "inb" || Name == "insb" || Name == "inw" || Name == "insw" ||
2479  Name == "inl" || Name == "insl" || Name == "in" || Name == "ins") &&
2480  Operands.size() == 3) {
2481  X86Operand &Op = (X86Operand &)*Operands[1];
2482  if (Op.isMem() && Op.Mem.SegReg == 0 &&
2483  isa<MCConstantExpr>(Op.Mem.Disp) &&
2484  cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2485  Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2486  SMLoc Loc = Op.getEndLoc();
2487  Operands[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
2488  }
2489  }
2490 
2492  bool HadVerifyError = false;
2493 
2494  // Append default arguments to "ins[bwld]"
2495  if (Name.startswith("ins") &&
2496  (Operands.size() == 1 || Operands.size() == 3) &&
2497  (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
2498  Name == "ins")) {
2499 
2500  AddDefaultSrcDestOperands(TmpOperands,
2501  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),
2502  DefaultMemDIOperand(NameLoc));
2503  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2504  }
2505 
2506  // Append default arguments to "outs[bwld]"
2507  if (Name.startswith("outs") &&
2508  (Operands.size() == 1 || Operands.size() == 3) &&
2509  (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
2510  Name == "outsd" || Name == "outs")) {
2511  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
2512  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2513  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2514  }
2515 
2516  // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
2517  // values of $SIREG according to the mode. It would be nice if this
2518  // could be achieved with InstAlias in the tables.
2519  if (Name.startswith("lods") &&
2520  (Operands.size() == 1 || Operands.size() == 2) &&
2521  (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
2522  Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) {
2523  TmpOperands.push_back(DefaultMemSIOperand(NameLoc));
2524  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2525  }
2526 
2527  // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
2528  // values of $DIREG according to the mode. It would be nice if this
2529  // could be achieved with InstAlias in the tables.
2530  if (Name.startswith("stos") &&
2531  (Operands.size() == 1 || Operands.size() == 2) &&
2532  (Name == "stos" || Name == "stosb" || Name == "stosw" ||
2533  Name == "stosl" || Name == "stosd" || Name == "stosq")) {
2534  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
2535  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2536  }
2537 
2538  // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
2539  // values of $DIREG according to the mode. It would be nice if this
2540  // could be achieved with InstAlias in the tables.
2541  if (Name.startswith("scas") &&
2542  (Operands.size() == 1 || Operands.size() == 2) &&
2543  (Name == "scas" || Name == "scasb" || Name == "scasw" ||
2544  Name == "scasl" || Name == "scasd" || Name == "scasq")) {
2545  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
2546  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2547  }
2548 
2549  // Add default SI and DI operands to "cmps[bwlq]".
2550  if (Name.startswith("cmps") &&
2551  (Operands.size() == 1 || Operands.size() == 3) &&
2552  (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
2553  Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
2554  AddDefaultSrcDestOperands(TmpOperands, DefaultMemDIOperand(NameLoc),
2555  DefaultMemSIOperand(NameLoc));
2556  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2557  }
2558 
2559  // Add default SI and DI operands to "movs[bwlq]".
2560  if (((Name.startswith("movs") &&
2561  (Name == "movs" || Name == "movsb" || Name == "movsw" ||
2562  Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
2563  (Name.startswith("smov") &&
2564  (Name == "smov" || Name == "smovb" || Name == "smovw" ||
2565  Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
2566  (Operands.size() == 1 || Operands.size() == 3)) {
2567  if (Name == "movsd" && Operands.size() == 1 && !isParsingIntelSyntax())
2568  Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
2569  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
2570  DefaultMemDIOperand(NameLoc));
2571  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2572  }
2573 
2574  // Check if we encountered an error for one the string insturctions
2575  if (HadVerifyError) {
2576  return HadVerifyError;
2577  }
2578 
2579  // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
2580  // "shift <op>".
2581  if ((Name.startswith("shr") || Name.startswith("sar") ||
2582  Name.startswith("shl") || Name.startswith("sal") ||
2583  Name.startswith("rcl") || Name.startswith("rcr") ||
2584  Name.startswith("rol") || Name.startswith("ror")) &&
2585  Operands.size() == 3) {
2586  if (isParsingIntelSyntax()) {
2587  // Intel syntax
2588  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[2]);
2589  if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) &&
2590  cast<MCConstantExpr>(Op1.getImm())->getValue() == 1)
2591  Operands.pop_back();
2592  } else {
2593  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2594  if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) &&
2595  cast<MCConstantExpr>(Op1.getImm())->getValue() == 1)
2596  Operands.erase(Operands.begin() + 1);
2597  }
2598  }
2599 
2600  // Transforms "int $3" into "int3" as a size optimization. We can't write an
2601  // instalias with an immediate operand yet.
2602  if (Name == "int" && Operands.size() == 2) {
2603  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2604  if (Op1.isImm())
2605  if (auto *CE = dyn_cast<MCConstantExpr>(Op1.getImm()))
2606  if (CE->getValue() == 3) {
2607  Operands.erase(Operands.begin() + 1);
2608  static_cast<X86Operand &>(*Operands[0]).setTokenValue("int3");
2609  }
2610  }
2611 
2612  // Transforms "xlat mem8" into "xlatb"
2613  if ((Name == "xlat" || Name == "xlatb") && Operands.size() == 2) {
2614  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2615  if (Op1.isMem8()) {
2616  Warning(Op1.getStartLoc(), "memory operand is only for determining the "
2617  "size, (R|E)BX will be used for the location");
2618  Operands.pop_back();
2619  static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb");
2620  }
2621  }
2622 
2623  if (Flags)
2624  Operands.push_back(X86Operand::CreatePrefix(Flags, NameLoc, NameLoc));
2625  return false;
2626 }
2627 
2628 bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
2629  return false;
2630 }
2631 
2632 bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
2633  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
2634 
2635  switch (Inst.getOpcode()) {
2636  case X86::VGATHERDPDYrm:
2637  case X86::VGATHERDPDrm:
2638  case X86::VGATHERDPSYrm:
2639  case X86::VGATHERDPSrm:
2640  case X86::VGATHERQPDYrm:
2641  case X86::VGATHERQPDrm:
2642  case X86::VGATHERQPSYrm:
2643  case X86::VGATHERQPSrm:
2644  case X86::VPGATHERDDYrm:
2645  case X86::VPGATHERDDrm:
2646  case X86::VPGATHERDQYrm:
2647  case X86::VPGATHERDQrm:
2648  case X86::VPGATHERQDYrm:
2649  case X86::VPGATHERQDrm:
2650  case X86::VPGATHERQQYrm:
2651  case X86::VPGATHERQQrm: {
2652  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
2653  unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg());
2654  unsigned Index =
2656  if (Dest == Mask || Dest == Index || Mask == Index)
2657  return Warning(Ops[0]->getStartLoc(), "mask, index, and destination "
2658  "registers should be distinct");
2659  break;
2660  }
2661  case X86::VGATHERDPDZ128rm:
2662  case X86::VGATHERDPDZ256rm:
2663  case X86::VGATHERDPDZrm:
2664  case X86::VGATHERDPSZ128rm:
2665  case X86::VGATHERDPSZ256rm:
2666  case X86::VGATHERDPSZrm:
2667  case X86::VGATHERQPDZ128rm:
2668  case X86::VGATHERQPDZ256rm:
2669  case X86::VGATHERQPDZrm:
2670  case X86::VGATHERQPSZ128rm:
2671  case X86::VGATHERQPSZ256rm:
2672  case X86::VGATHERQPSZrm:
2673  case X86::VPGATHERDDZ128rm:
2674  case X86::VPGATHERDDZ256rm:
2675  case X86::VPGATHERDDZrm:
2676  case X86::VPGATHERDQZ128rm:
2677  case X86::VPGATHERDQZ256rm:
2678  case X86::VPGATHERDQZrm:
2679  case X86::VPGATHERQDZ128rm:
2680  case X86::VPGATHERQDZ256rm:
2681  case X86::VPGATHERQDZrm:
2682  case X86::VPGATHERQQZ128rm:
2683  case X86::VPGATHERQQZ256rm:
2684  case X86::VPGATHERQQZrm: {
2685  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
2686  unsigned Index =
2688  if (Dest == Index)
2689  return Warning(Ops[0]->getStartLoc(), "index and destination registers "
2690  "should be distinct");
2691  break;
2692  }
2693  }
2694 
2695  return false;
2696 }
2697 
2698 static const char *getSubtargetFeatureName(uint64_t Val);
2699 
2700 void X86AsmParser::EmitInstruction(MCInst &Inst, OperandVector &Operands,
2701  MCStreamer &Out) {
2702  Instrumentation->InstrumentAndEmitInstruction(
2703  Inst, Operands, getContext(), MII, Out,
2704  getParser().shouldPrintSchedInfo());
2705 }
2706 
2707 bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2708  OperandVector &Operands,
2709  MCStreamer &Out, uint64_t &ErrorInfo,
2710  bool MatchingInlineAsm) {
2711  if (isParsingIntelSyntax())
2712  return MatchAndEmitIntelInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
2713  MatchingInlineAsm);
2714  return MatchAndEmitATTInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
2715  MatchingInlineAsm);
2716 }
2717 
2718 void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op,
2719  OperandVector &Operands, MCStreamer &Out,
2720  bool MatchingInlineAsm) {
2721  // FIXME: This should be replaced with a real .td file alias mechanism.
2722  // Also, MatchInstructionImpl should actually *do* the EmitInstruction
2723  // call.
2724  const char *Repl = StringSwitch<const char *>(Op.getToken())
2725  .Case("finit", "fninit")
2726  .Case("fsave", "fnsave")
2727  .Case("fstcw", "fnstcw")
2728  .Case("fstcww", "fnstcw")
2729  .Case("fstenv", "fnstenv")
2730  .Case("fstsw", "fnstsw")
2731  .Case("fstsww", "fnstsw")
2732  .Case("fclex", "fnclex")
2733  .Default(nullptr);
2734  if (Repl) {
2735  MCInst Inst;
2736  Inst.setOpcode(X86::WAIT);
2737  Inst.setLoc(IDLoc);
2738  if (!MatchingInlineAsm)
2739  EmitInstruction(Inst, Operands, Out);
2740  Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
2741  }
2742 }
2743 
2744 bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo,
2745  bool MatchingInlineAsm) {
2746  assert(ErrorInfo && "Unknown missing feature!");
2747  SmallString<126> Msg;
2748  raw_svector_ostream OS(Msg);
2749  OS << "instruction requires:";
2750  uint64_t Mask = 1;
2751  for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
2752  if (ErrorInfo & Mask)
2753  OS << ' ' << getSubtargetFeatureName(ErrorInfo & Mask);
2754  Mask <<= 1;
2755  }
2756  return Error(IDLoc, OS.str(), SMRange(), MatchingInlineAsm);
2757 }
2758 
2759 static unsigned getPrefixes(OperandVector &Operands) {
2760  unsigned Result = 0;
2761  X86Operand &Prefix = static_cast<X86Operand &>(*Operands.back());
2762  if (Prefix.isPrefix()) {
2763  Result = Prefix.getPrefix();
2764  Operands.pop_back();
2765  }
2766  return Result;
2767 }
2768 
2769 bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
2770  OperandVector &Operands,
2771  MCStreamer &Out,
2772  uint64_t &ErrorInfo,
2773  bool MatchingInlineAsm) {
2774  assert(!Operands.empty() && "Unexpect empty operand list!");
2775  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
2776  assert(Op.isToken() && "Leading operand should always be a mnemonic!");
2777  SMRange EmptyRange = None;
2778 
2779  // First, handle aliases that expand to multiple instructions.
2780  MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
2781 
2782  bool WasOriginallyInvalidOperand = false;
2783  unsigned Prefixes = getPrefixes(Operands);
2784 
2785  MCInst Inst;
2786 
2787  if (Prefixes)
2788  Inst.setFlags(Prefixes);
2789 
2790  // First, try a direct match.
2791  switch (MatchInstruction(Operands, Inst, ErrorInfo, MatchingInlineAsm,
2792  isParsingIntelSyntax())) {
2793  default: llvm_unreachable("Unexpected match result!");
2794  case Match_Success:
2795  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
2796  return true;
2797  // Some instructions need post-processing to, for example, tweak which
2798  // encoding is selected. Loop on it while changes happen so the
2799  // individual transformations can chain off each other.
2800  if (!MatchingInlineAsm)
2801  while (processInstruction(Inst, Operands))
2802  ;
2803 
2804  Inst.setLoc(IDLoc);
2805  if (!MatchingInlineAsm)
2806  EmitInstruction(Inst, Operands, Out);
2807  Opcode = Inst.getOpcode();
2808  return false;
2809  case Match_MissingFeature:
2810  return ErrorMissingFeature(IDLoc, ErrorInfo, MatchingInlineAsm);
2811  case Match_InvalidOperand:
2812  WasOriginallyInvalidOperand = true;
2813  break;
2814  case Match_MnemonicFail:
2815  break;
2816  }
2817 
2818  // FIXME: Ideally, we would only attempt suffix matches for things which are
2819  // valid prefixes, and we could just infer the right unambiguous
2820  // type. However, that requires substantially more matcher support than the
2821  // following hack.
2822 
2823  // Change the operand to point to a temporary token.
2824  StringRef Base = Op.getToken();
2825  SmallString<16> Tmp;
2826  Tmp += Base;
2827  Tmp += ' ';
2828  Op.setTokenValue(Tmp);
2829 
2830  // If this instruction starts with an 'f', then it is a floating point stack
2831  // instruction. These come in up to three forms for 32-bit, 64-bit, and
2832  // 80-bit floating point, which use the suffixes s,l,t respectively.
2833  //
2834  // Otherwise, we assume that this may be an integer instruction, which comes
2835  // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
2836  const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
2837 
2838  // Check for the various suffix matches.
2839  uint64_t ErrorInfoIgnore;
2840  uint64_t ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
2841  unsigned Match[4];
2842 
2843  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) {
2844  Tmp.back() = Suffixes[I];
2845  Match[I] = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
2846  MatchingInlineAsm, isParsingIntelSyntax());
2847  // If this returned as a missing feature failure, remember that.
2848  if (Match[I] == Match_MissingFeature)
2849  ErrorInfoMissingFeature = ErrorInfoIgnore;
2850  }
2851 
2852  // Restore the old token.
2853  Op.setTokenValue(Base);
2854 
2855  // If exactly one matched, then we treat that as a successful match (and the
2856  // instruction will already have been filled in correctly, since the failing
2857  // matches won't have modified it).
2858  unsigned NumSuccessfulMatches =
2859  std::count(std::begin(Match), std::end(Match), Match_Success);
2860  if (NumSuccessfulMatches == 1) {
2861  Inst.setLoc(IDLoc);
2862  if (!MatchingInlineAsm)
2863  EmitInstruction(Inst, Operands, Out);
2864  Opcode = Inst.getOpcode();
2865  return false;
2866  }
2867 
2868  // Otherwise, the match failed, try to produce a decent error message.
2869 
2870  // If we had multiple suffix matches, then identify this as an ambiguous
2871  // match.
2872  if (NumSuccessfulMatches > 1) {
2873  char MatchChars[4];
2874  unsigned NumMatches = 0;
2875  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I)
2876  if (Match[I] == Match_Success)
2877  MatchChars[NumMatches++] = Suffixes[I];
2878 
2879  SmallString<126> Msg;
2880  raw_svector_ostream OS(Msg);
2881  OS << "ambiguous instructions require an explicit suffix (could be ";
2882  for (unsigned i = 0; i != NumMatches; ++i) {
2883  if (i != 0)
2884  OS << ", ";
2885  if (i + 1 == NumMatches)
2886  OS << "or ";
2887  OS << "'" << Base << MatchChars[i] << "'";
2888  }
2889  OS << ")";
2890  Error(IDLoc, OS.str(), EmptyRange, MatchingInlineAsm);
2891  return true;
2892  }
2893 
2894  // Okay, we know that none of the variants matched successfully.
2895 
2896  // If all of the instructions reported an invalid mnemonic, then the original
2897  // mnemonic was invalid.
2898  if (std::count(std::begin(Match), std::end(Match), Match_MnemonicFail) == 4) {
2899  if (!WasOriginallyInvalidOperand) {
2900  return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
2901  Op.getLocRange(), MatchingInlineAsm);
2902  }
2903 
2904  // Recover location info for the operand if we know which was the problem.
2905  if (ErrorInfo != ~0ULL) {
2906  if (ErrorInfo >= Operands.size())
2907  return Error(IDLoc, "too few operands for instruction", EmptyRange,
2908  MatchingInlineAsm);
2909 
2910  X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo];
2911  if (Operand.getStartLoc().isValid()) {
2912  SMRange OperandRange = Operand.getLocRange();
2913  return Error(Operand.getStartLoc(), "invalid operand for instruction",
2914  OperandRange, MatchingInlineAsm);
2915  }
2916  }
2917 
2918  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
2919  MatchingInlineAsm);
2920  }
2921 
2922  // If one instruction matched with a missing feature, report this as a
2923  // missing feature.
2924  if (std::count(std::begin(Match), std::end(Match),
2925  Match_MissingFeature) == 1) {
2926  ErrorInfo = ErrorInfoMissingFeature;
2927  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature,
2928  MatchingInlineAsm);
2929  }
2930 
2931  // If one instruction matched with an invalid operand, report this as an
2932  // operand failure.
2933  if (std::count(std::begin(Match), std::end(Match),
2934  Match_InvalidOperand) == 1) {
2935  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
2936  MatchingInlineAsm);
2937  }
2938 
2939  // If all of these were an outright failure, report it in a useless way.
2940  Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
2941  EmptyRange, MatchingInlineAsm);
2942  return true;
2943 }
2944 
2945 bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
2946  OperandVector &Operands,
2947  MCStreamer &Out,
2948  uint64_t &ErrorInfo,
2949  bool MatchingInlineAsm) {
2950  assert(!Operands.empty() && "Unexpect empty operand list!");
2951  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
2952  assert(Op.isToken() && "Leading operand should always be a mnemonic!");
2953  StringRef Mnemonic = Op.getToken();
2954  SMRange EmptyRange = None;
2955  StringRef Base = Op.getToken();
2956  unsigned Prefixes = getPrefixes(Operands);
2957 
2958  // First, handle aliases that expand to multiple instructions.
2959  MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
2960 
2961  MCInst Inst;
2962 
2963  if (Prefixes)
2964  Inst.setFlags(Prefixes);
2965 
2966  // Find one unsized memory operand, if present.
2967  X86Operand *UnsizedMemOp = nullptr;
2968  for (const auto &Op : Operands) {
2969  X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
2970  if (X86Op->isMemUnsized()) {
2971  UnsizedMemOp = X86Op;
2972  // Have we found an unqualified memory operand,
2973  // break. IA allows only one memory operand.
2974  break;
2975  }
2976  }
2977 
2978  // Allow some instructions to have implicitly pointer-sized operands. This is
2979  // compatible with gas.
2980  if (UnsizedMemOp) {
2981  static const char *const PtrSizedInstrs[] = {"call", "jmp", "push"};
2982  for (const char *Instr : PtrSizedInstrs) {
2983  if (Mnemonic == Instr) {
2984  UnsizedMemOp->Mem.Size = getPointerWidth();
2985  break;
2986  }
2987  }
2988  }
2989 
2991  uint64_t ErrorInfoMissingFeature = 0;
2992 
2993  // If unsized push has immediate operand we should default the default pointer
2994  // size for the size.
2995  if (Mnemonic == "push" && Operands.size() == 2) {
2996  auto *X86Op = static_cast<X86Operand *>(Operands[1].get());
2997  if (X86Op->isImm()) {
2998  // If it's not a constant fall through and let remainder take care of it.
2999  const auto *CE = dyn_cast<MCConstantExpr>(X86Op->getImm());
3000  unsigned Size = getPointerWidth();
3001  if (CE &&
3002  (isIntN(Size, CE->getValue()) || isUIntN(Size, CE->getValue()))) {
3003  SmallString<16> Tmp;
3004  Tmp += Base;
3005  Tmp += (is64BitMode())
3006  ? "q"
3007  : (is32BitMode()) ? "l" : (is16BitMode()) ? "w" : " ";
3008  Op.setTokenValue(Tmp);
3009  // Do match in ATT mode to allow explicit suffix usage.
3010  Match.push_back(MatchInstruction(Operands, Inst, ErrorInfo,
3011  MatchingInlineAsm,
3012  false /*isParsingIntelSyntax()*/));
3013  Op.setTokenValue(Base);
3014  }
3015  }
3016  }
3017 
3018  // If an unsized memory operand is present, try to match with each memory
3019  // operand size. In Intel assembly, the size is not part of the instruction
3020  // mnemonic.
3021  if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
3022  static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
3023  for (unsigned Size : MopSizes) {
3024  UnsizedMemOp->Mem.Size = Size;
3025  uint64_t ErrorInfoIgnore;
3026  unsigned LastOpcode = Inst.getOpcode();
3027  unsigned M = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
3028  MatchingInlineAsm, isParsingIntelSyntax());
3029  if (Match.empty() || LastOpcode != Inst.getOpcode())
3030  Match.push_back(M);
3031 
3032  // If this returned as a missing feature failure, remember that.
3033  if (Match.back() == Match_MissingFeature)
3034  ErrorInfoMissingFeature = ErrorInfoIgnore;
3035  }
3036 
3037  // Restore the size of the unsized memory operand if we modified it.
3038  UnsizedMemOp->Mem.Size = 0;
3039  }
3040 
3041  // If we haven't matched anything yet, this is not a basic integer or FPU
3042  // operation. There shouldn't be any ambiguity in our mnemonic table, so try
3043  // matching with the unsized operand.
3044  if (Match.empty()) {
3045  Match.push_back(MatchInstruction(
3046  Operands, Inst, ErrorInfo, MatchingInlineAsm, isParsingIntelSyntax()));
3047  // If this returned as a missing feature failure, remember that.
3048  if (Match.back() == Match_MissingFeature)
3049  ErrorInfoMissingFeature = ErrorInfo;
3050  }
3051 
3052  // Restore the size of the unsized memory operand if we modified it.
3053  if (UnsizedMemOp)
3054  UnsizedMemOp->Mem.Size = 0;
3055 
3056  // If it's a bad mnemonic, all results will be the same.
3057  if (Match.back() == Match_MnemonicFail) {
3058  return Error(IDLoc, "invalid instruction mnemonic '" + Mnemonic + "'",
3059  Op.getLocRange(), MatchingInlineAsm);
3060  }
3061 
3062  unsigned NumSuccessfulMatches =
3063  std::count(std::begin(Match), std::end(Match), Match_Success);
3064 
3065  // If matching was ambiguous and we had size information from the frontend,
3066  // try again with that. This handles cases like "movxz eax, m8/m16".
3067  if (UnsizedMemOp && NumSuccessfulMatches > 1 &&
3068  UnsizedMemOp->getMemFrontendSize()) {
3069  UnsizedMemOp->Mem.Size = UnsizedMemOp->getMemFrontendSize();
3070  unsigned M = MatchInstruction(
3071  Operands, Inst, ErrorInfo, MatchingInlineAsm, isParsingIntelSyntax());
3072  if (M == Match_Success)
3073  NumSuccessfulMatches = 1;
3074 
3075  // Add a rewrite that encodes the size information we used from the
3076  // frontend.
3077  InstInfo->AsmRewrites->emplace_back(
3078  AOK_SizeDirective, UnsizedMemOp->getStartLoc(),
3079  /*Len=*/0, UnsizedMemOp->getMemFrontendSize());
3080  }
3081 
3082  // If exactly one matched, then we treat that as a successful match (and the
3083  // instruction will already have been filled in correctly, since the failing
3084  // matches won't have modified it).
3085  if (NumSuccessfulMatches == 1) {
3086  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
3087  return true;
3088  // Some instructions need post-processing to, for example, tweak which
3089  // encoding is selected. Loop on it while changes happen so the individual
3090  // transformations can chain off each other.
3091  if (!MatchingInlineAsm)
3092  while (processInstruction(Inst, Operands))
3093  ;
3094  Inst.setLoc(IDLoc);
3095  if (!MatchingInlineAsm)
3096  EmitInstruction(Inst, Operands, Out);
3097  Opcode = Inst.getOpcode();
3098  return false;
3099  } else if (NumSuccessfulMatches > 1) {
3100  assert(UnsizedMemOp &&
3101  "multiple matches only possible with unsized memory operands");
3102  return Error(UnsizedMemOp->getStartLoc(),
3103  "ambiguous operand size for instruction '" + Mnemonic + "\'",
3104  UnsizedMemOp->getLocRange());
3105  }
3106 
3107  // If one instruction matched with a missing feature, report this as a
3108  // missing feature.
3109  if (std::count(std::begin(Match), std::end(Match),
3110  Match_MissingFeature) == 1) {
3111  ErrorInfo = ErrorInfoMissingFeature;
3112  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature,
3113  MatchingInlineAsm);
3114  }
3115 
3116  // If one instruction matched with an invalid operand, report this as an
3117  // operand failure.
3118  if (std::count(std::begin(Match), std::end(Match),
3119  Match_InvalidOperand) == 1) {
3120  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
3121  MatchingInlineAsm);
3122  }
3123 
3124  // If all of these were an outright failure, report it in a useless way.
3125  return Error(IDLoc, "unknown instruction mnemonic", EmptyRange,
3126  MatchingInlineAsm);
3127 }
3128 
3129 bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
3130  return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
3131 }
3132 
3133 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
3134  MCAsmParser &Parser = getParser();
3135  StringRef IDVal = DirectiveID.getIdentifier();
3136  if (IDVal == ".word")
3137  return ParseDirectiveWord(2, DirectiveID.getLoc());
3138  else if (IDVal.startswith(".code"))
3139  return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
3140  else if (IDVal.startswith(".att_syntax")) {
3141  getParser().setParsingInlineAsm(false);
3142  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3143  if (Parser.getTok().getString() == "prefix")
3144  Parser.Lex();
3145  else if (Parser.getTok().getString() == "noprefix")
3146  return Error(DirectiveID.getLoc(), "'.att_syntax noprefix' is not "
3147  "supported: registers must have a "
3148  "'%' prefix in .att_syntax");
3149  }
3150  getParser().setAssemblerDialect(0);
3151  return false;
3152  } else if (IDVal.startswith(".intel_syntax")) {
3153  getParser().setAssemblerDialect(1);
3154  getParser().setParsingInlineAsm(true);
3155  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3156  if (Parser.getTok().getString() == "noprefix")
3157  Parser.Lex();
3158  else if (Parser.getTok().getString() == "prefix")
3159  return Error(DirectiveID.getLoc(), "'.intel_syntax prefix' is not "
3160  "supported: registers must not have "
3161  "a '%' prefix in .intel_syntax");
3162  }
3163  return false;
3164  } else if (IDVal == ".even")
3165  return parseDirectiveEven(DirectiveID.getLoc());
3166  else if (IDVal == ".cv_fpo_proc")
3167  return parseDirectiveFPOProc(DirectiveID.getLoc());
3168  else if (IDVal == ".cv_fpo_setframe")
3169  return parseDirectiveFPOSetFrame(DirectiveID.getLoc());
3170  else if (IDVal == ".cv_fpo_pushreg")
3171  return parseDirectiveFPOPushReg(DirectiveID.getLoc());
3172  else if (IDVal == ".cv_fpo_stackalloc")
3173  return parseDirectiveFPOStackAlloc(DirectiveID.getLoc());
3174  else if (IDVal == ".cv_fpo_endprologue")
3175  return parseDirectiveFPOEndPrologue(DirectiveID.getLoc());
3176  else if (IDVal == ".cv_fpo_endproc")
3177  return parseDirectiveFPOEndProc(DirectiveID.getLoc());
3178 
3179  return true;
3180 }
3181 
3182 /// parseDirectiveEven
3183 /// ::= .even
3184 bool X86AsmParser::parseDirectiveEven(SMLoc L) {
3185  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3186  TokError("unexpected token in directive");
3187  return false;
3188  }
3189  const MCSection *Section = getStreamer().getCurrentSectionOnly();
3190  if (!Section) {
3191  getStreamer().InitSections(false);
3192  Section = getStreamer().getCurrentSectionOnly();
3193  }
3194  if (Section->UseCodeAlign())
3195  getStreamer().EmitCodeAlignment(2, 0);
3196  else
3197  getStreamer().EmitValueToAlignment(2, 0, 1, 0);
3198  return false;
3199 }
3200 /// ParseDirectiveWord
3201 /// ::= .word [ expression (, expression)* ]
3202 bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
3203  MCAsmParser &Parser = getParser();
3204  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3205  for (;;) {
3206  const MCExpr *Value;
3207  SMLoc ExprLoc = getLexer().getLoc();
3208  if (getParser().parseExpression(Value))
3209  return false;
3210 
3211  if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
3212  assert(Size <= 8 && "Invalid size");
3213  uint64_t IntValue = MCE->getValue();
3214  if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
3215  return Error(ExprLoc, "literal value out of range for directive");
3216  getStreamer().EmitIntValue(IntValue, Size);
3217  } else {
3218  getStreamer().EmitValue(Value, Size, ExprLoc);
3219  }
3220 
3221  if (getLexer().is(AsmToken::EndOfStatement))
3222  break;
3223 
3224  // FIXME: Improve diagnostic.
3225  if (getLexer().isNot(AsmToken::Comma)) {
3226  Error(L, "unexpected token in directive");
3227  return false;
3228  }
3229  Parser.Lex();
3230  }
3231  }
3232 
3233  Parser.Lex();
3234  return false;
3235 }
3236 
3237 /// ParseDirectiveCode
3238 /// ::= .code16 | .code32 | .code64
3239 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
3240  MCAsmParser &Parser = getParser();
3241  Code16GCC = false;
3242  if (IDVal == ".code16") {
3243  Parser.Lex();
3244  if (!is16BitMode()) {
3245  SwitchMode(X86::Mode16Bit);
3246  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3247  }
3248  } else if (IDVal == ".code16gcc") {
3249  // .code16gcc parses as if in 32-bit mode, but emits code in 16-bit mode.
3250  Parser.Lex();
3251  Code16GCC = true;
3252  if (!is16BitMode()) {
3253  SwitchMode(X86::Mode16Bit);
3254  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3255  }
3256  } else if (IDVal == ".code32") {
3257  Parser.Lex();
3258  if (!is32BitMode()) {
3259  SwitchMode(X86::Mode32Bit);
3260  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3261  }
3262  } else if (IDVal == ".code64") {
3263  Parser.Lex();
3264  if (!is64BitMode()) {
3265  SwitchMode(X86::Mode64Bit);
3266  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
3267  }
3268  } else {
3269  Error(L, "unknown directive " + IDVal);
3270  return false;
3271  }
3272 
3273  return false;
3274 }
3275 
3276 // .cv_fpo_proc foo
3277 bool X86AsmParser::parseDirectiveFPOProc(SMLoc L) {
3278  MCAsmParser &Parser = getParser();
3279  StringRef ProcName;
3280  int64_t ParamsSize;
3281  if (Parser.parseIdentifier(ProcName))
3282  return Parser.TokError("expected symbol name");
3283  if (Parser.parseIntToken(ParamsSize, "expected parameter byte count"))
3284  return true;
3285  if (!isUIntN(32, ParamsSize))
3286  return Parser.TokError("parameters size out of range");
3287  if (Parser.parseEOL("unexpected tokens"))
3288  return addErrorSuffix(" in '.cv_fpo_proc' directive");
3289  MCSymbol *ProcSym = getContext().getOrCreateSymbol(ProcName);
3290  return getTargetStreamer().emitFPOProc(ProcSym, ParamsSize, L);
3291 }
3292 
3293 // .cv_fpo_setframe ebp
3294 bool X86AsmParser::parseDirectiveFPOSetFrame(SMLoc L) {
3295  MCAsmParser &Parser = getParser();
3296  unsigned Reg;
3297  SMLoc DummyLoc;
3298  if (ParseRegister(Reg, DummyLoc, DummyLoc) ||
3299  Parser.parseEOL("unexpected tokens"))
3300  return addErrorSuffix(" in '.cv_fpo_setframe' directive");
3301  return getTargetStreamer().emitFPOSetFrame(Reg, L);
3302 }
3303 
3304 // .cv_fpo_pushreg ebx
3305 bool X86AsmParser::parseDirectiveFPOPushReg(SMLoc L) {
3306  MCAsmParser &Parser = getParser();
3307  unsigned Reg;
3308  SMLoc DummyLoc;
3309  if (ParseRegister(Reg, DummyLoc, DummyLoc) ||
3310  Parser.parseEOL("unexpected tokens"))
3311  return addErrorSuffix(" in '.cv_fpo_pushreg' directive");
3312  return getTargetStreamer().emitFPOPushReg(Reg, L);
3313 }
3314 
3315 // .cv_fpo_stackalloc 20
3316 bool X86AsmParser::parseDirectiveFPOStackAlloc(SMLoc L) {
3317  MCAsmParser &Parser = getParser();
3318  int64_t Offset;
3319  if (Parser.parseIntToken(Offset, "expected offset") ||
3320  Parser.parseEOL("unexpected tokens"))
3321  return addErrorSuffix(" in '.cv_fpo_stackalloc' directive");
3322  return getTargetStreamer().emitFPOStackAlloc(Offset, L);
3323 }
3324 
3325 // .cv_fpo_endprologue
3326 bool X86AsmParser::parseDirectiveFPOEndPrologue(SMLoc L) {
3327  MCAsmParser &Parser = getParser();
3328  if (Parser.parseEOL("unexpected tokens"))
3329  return addErrorSuffix(" in '.cv_fpo_endprologue' directive");
3330  return getTargetStreamer().emitFPOEndPrologue(L);
3331 }
3332 
3333 // .cv_fpo_endproc
3334 bool X86AsmParser::parseDirectiveFPOEndProc(SMLoc L) {
3335  MCAsmParser &Parser = getParser();
3336  if (Parser.parseEOL("unexpected tokens"))
3337  return addErrorSuffix(" in '.cv_fpo_endproc' directive");
3338  return getTargetStreamer().emitFPOEndProc(L);
3339 }
3340 
3341 // Force static initialization.
3342 extern "C" void LLVMInitializeX86AsmParser() {
3345 }
3346 
3347 #define GET_REGISTER_MATCHER
3348 #define GET_MATCHER_IMPLEMENTATION
3349 #define GET_SUBTARGET_FEATURE_NAME
3350 #include "X86GenAsmMatcher.inc"
static const char * getSubtargetFeatureName(uint64_t Val)
Represents a range in source code.
Definition: SMLoc.h:49
Instances of this class represent a uniqued identifier for a section in the current translation unit...
Definition: MCSection.h:39
static bool checkScale(unsigned Scale, StringRef &ErrMsg)
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:244
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmLexer.h:116
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1542
unsigned getMemFrontendSize() const
Definition: X86Operand.h:149
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:235
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:783
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:305
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
SMRange getLocRange() const
getLocRange - Get the range between the first and last token of this operand.
Definition: X86Operand.h:93
SmallVectorImpl< AsmRewrite > * AsmRewrites
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
LLVM_NODISCARD bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Definition: StringRef.h:176
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:110
bool isKind(IdKind kind) const
Definition: MCAsmParser.h:66
MCTargetAsmParser - Generic interface to target specific assembly parsers.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:138
Target specific streamer interface.
Definition: MCStreamer.h:80
bool isNot(TokenKind K) const
Definition: MCAsmLexer.h:89
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:489
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:33
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, StringRef SymName=StringRef(), void *OpDecl=nullptr, unsigned FrontendSize=0)
Create an absolute memory operand.
Definition: X86Operand.h:535
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:128
bool parseIntToken(int64_t &V, const Twine &ErrMsg)
Definition: MCAsmParser.cpp:58
return AArch64::GPR64RegClass contains(Reg)
static ModuleSymbolTable::Symbol getSym(DataRefImpl &Symb)
StringRef getToken() const
Definition: X86Operand.h:100
amode Optimize addressing mode
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:279
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
Definition: MCAsmLexer.h:105
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
void LLVMInitializeX86AsmParser()
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
unsigned getPrefix() const
Definition: X86Operand.h:115
bool isMemUnsized() const
Definition: X86Operand.h:233
SMLoc getEndLoc() const override
getEndLoc - Get the location of the last token of this operand.
Definition: X86Operand.h:89
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:476
bool isImm() const override
isImm - Is this an immediate operand?
Definition: X86Operand.h:156
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Reg
All possible values of the reg field in the ModR/M byte.
Target independent representation for an assembler token.
Definition: MCAsmLexer.h:27
bool isMem8() const
Definition: X86Operand.h:236
zlib-gnu style compression
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
static std::unique_ptr< X86Operand > CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:526
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:29
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:267
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(const char(&S)[N], const T &Value)
Definition: StringSwitch.h:74
unsigned getReg() const override
Definition: X86Operand.h:110
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:51
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:26
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:598
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:443
LLVM_NODISCARD std::string upper() const
Convert the given ASCII string to uppercase.
Definition: StringRef.cpp:131
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
virtual void eatToEndOfStatement()=0
Skip to the end of the current statement, for error recovery.
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(adl_begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:874
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isPrefix() const
Definition: X86Operand.h:396
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:749
FeatureBitset ToggleFeature(uint64_t FB)
ToggleFeature - Toggle a feature and returns the re-computed feature bits.
const char * getPointer() const
Definition: SMLoc.h:35
virtual MCContext & getContext()=0
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:43
Streaming machine code generation interface.
Definition: MCStreamer.h:169
unsigned const MachineRegisterInfo * MRI
X86Operand - Instances of this class represent a parsed X86 machine instruction.
Definition: X86Operand.h:31
MCTargetStreamer * getTargetStreamer()
Definition: MCStreamer.h:236
Container class for subtarget features.
SMLoc getEndLoc() const
Definition: MCAsmLexer.cpp:30
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:116
static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg, unsigned Scale, StringRef &ErrMsg)
}
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
const MCExpr * getImm() const
Definition: X86Operand.h:120
static const unsigned End
int64_t getIntVal() const
Definition: MCAsmLexer.h:121
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE int compare(StringRef RHS) const
compare - Compare two strings; the result is -1, 0, or 1 if this string is lexicographically less tha...
Definition: StringRef.h:184
bool Error(SMLoc L, const Twine &Msg, SMRange Range=None)
Return an error at the location L, with the message Msg.
Definition: MCAsmParser.cpp:87
static const char * getRegisterName(unsigned RegNo)
virtual bool UseCodeAlign() const =0
Return true if a .align directive should use "optimized nops" to fill instead of 0s.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:390
iterator erase(const_iterator CI)
Definition: SmallVector.h:449
LLVM_NODISCARD char back() const
back - Get the last character in the string.
Definition: StringRef.h:149
void setLoc(SMLoc loc)
Definition: MCInst.h:177
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SMLoc getStartLoc() const override
getStartLoc - Get the location of the first token of this operand.
Definition: X86Operand.h:86
LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(const T &Value) const
Definition: StringSwitch.h:244
unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef drop_back(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with the last N elements dropped.
Definition: StringRef.h:654
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:497
X86AsmInstrumentation * CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, const MCContext &Ctx, const MCSubtargetInfo *&STI)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef drop_front(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with the first N elements dropped.
Definition: StringRef.h:645
static bool is32ExtendedReg(unsigned RegNo)
is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) registers? e...
Definition: X86BaseInfo.h:776
void setFlags(unsigned F)
Definition: MCInst.h:174
MCStreamer & getStreamer()
Definition: MCStreamer.h:88
void setOpcode(unsigned Op)
Definition: MCInst.h:171
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:260
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:864
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:180
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:727
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:720
struct MemOp Mem
Definition: X86Operand.h:75
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: StringRef.h:710
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:385
StringRef str()
Return a StringRef for the vector contents.
Definition: raw_ostream.h:514
X86 target streamer implementing x86-only assembly directives.
static bool isPrefix(const IndicesVector &Prefix, const IndicesVector &Longer)
Returns true if Prefix is a prefix of longer.
bool is(TokenKind K) const
Definition: MCAsmLexer.h:88
Class for arbitrary precision integers.
Definition: APInt.h:69
bool isValid() const
Definition: SMLoc.h:30
Base class for user error types.
Definition: Error.h:331
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:169
static std::unique_ptr< X86Operand > CreateToken(StringRef Str, SMLoc Loc)
Definition: X86Operand.h:498
VariableIdentifier Var
Definition: MCAsmParser.h:64
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:52
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:37
static std::unique_ptr< X86Operand > CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc, bool AddressOf=false, SMLoc OffsetOfLoc=SMLoc(), StringRef SymName=StringRef(), void *OpDecl=nullptr)
Definition: X86Operand.h:507
.code64 (X86)
Definition: MCDirectives.h:53
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Cases(const char(&S0)[N0], const char(&S1)[N1], const T &Value)
Definition: StringSwitch.h:107
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:61
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
static unsigned getPrefixes(OperandVector &Operands)
MCSubtargetInfo - Generic base class for all target subtargets.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
Target & getTheX86_32Target()
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:203
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:123
static std::unique_ptr< X86Operand > CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:520
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool TokError(const Twine &Msg, SMRange Range=None)
Report an error at the current lexer location.
Definition: MCAsmParser.cpp:83
LLVM Value Representation.
Definition: Value.h:73
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
static unsigned MatchRegisterName(StringRef Name)
Maps from the set of all register names to a register number.
bool parseEOL(const Twine &ErrMsg)
Definition: MCAsmParser.cpp:42
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
bool isReg() const override
isReg - Is this a register operand?
Definition: X86Operand.h:397
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
const MCExpr * Disp
Definition: X86Operand.h:59
virtual bool parseIdentifier(StringRef &Res)=0
Parse an identifier or string (as a quoted identifier) and set Res to the identifier contents...
Represents a location in source code.
Definition: SMLoc.h:24
unsigned getOpcode() const
Definition: MCInst.h:172
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:385
Target & getTheX86_64Target()
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:159
bool isMem() const override
isMem - Is this a memory operand?
Definition: X86Operand.h:232