LLVM  9.0.0svn
X86AsmParser.cpp
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1 //===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "MCTargetDesc/X86MCExpr.h"
13 #include "X86AsmInstrumentation.h"
14 #include "X86AsmParserCommon.h"
15 #include "X86Operand.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallString.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/MC/MCSection.h"
31 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/MC/MCSymbol.h"
34 #include "llvm/Support/SourceMgr.h"
37 #include <algorithm>
38 #include <memory>
39 
40 using namespace llvm;
41 
42 static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
43  if (Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
44  ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
45  return true;
46  }
47  return false;
48 }
49 
50 namespace {
51 
52 static const char OpPrecedence[] = {
53  0, // IC_OR
54  1, // IC_XOR
55  2, // IC_AND
56  3, // IC_LSHIFT
57  3, // IC_RSHIFT
58  4, // IC_PLUS
59  4, // IC_MINUS
60  5, // IC_MULTIPLY
61  5, // IC_DIVIDE
62  5, // IC_MOD
63  6, // IC_NOT
64  7, // IC_NEG
65  8, // IC_RPAREN
66  9, // IC_LPAREN
67  0, // IC_IMM
68  0 // IC_REGISTER
69 };
70 
71 class X86AsmParser : public MCTargetAsmParser {
72  ParseInstructionInfo *InstInfo;
73  std::unique_ptr<X86AsmInstrumentation> Instrumentation;
74  bool Code16GCC;
75 
76 private:
77  SMLoc consumeToken() {
78  MCAsmParser &Parser = getParser();
79  SMLoc Result = Parser.getTok().getLoc();
80  Parser.Lex();
81  return Result;
82  }
83 
84  X86TargetStreamer &getTargetStreamer() {
85  assert(getParser().getStreamer().getTargetStreamer() &&
86  "do not have a target streamer");
87  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
88  return static_cast<X86TargetStreamer &>(TS);
89  }
90 
91  unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst,
92  uint64_t &ErrorInfo, bool matchingInlineAsm,
93  unsigned VariantID = 0) {
94  // In Code16GCC mode, match as 32-bit.
95  if (Code16GCC)
96  SwitchMode(X86::Mode32Bit);
97  unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo,
98  matchingInlineAsm, VariantID);
99  if (Code16GCC)
100  SwitchMode(X86::Mode16Bit);
101  return rv;
102  }
103 
104  enum InfixCalculatorTok {
105  IC_OR = 0,
106  IC_XOR,
107  IC_AND,
108  IC_LSHIFT,
109  IC_RSHIFT,
110  IC_PLUS,
111  IC_MINUS,
112  IC_MULTIPLY,
113  IC_DIVIDE,
114  IC_MOD,
115  IC_NOT,
116  IC_NEG,
117  IC_RPAREN,
118  IC_LPAREN,
119  IC_IMM,
120  IC_REGISTER
121  };
122 
123  enum IntelOperatorKind {
124  IOK_INVALID = 0,
125  IOK_LENGTH,
126  IOK_SIZE,
127  IOK_TYPE,
128  IOK_OFFSET
129  };
130 
131  class InfixCalculator {
132  typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
133  SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
134  SmallVector<ICToken, 4> PostfixStack;
135 
136  bool isUnaryOperator(const InfixCalculatorTok Op) {
137  return Op == IC_NEG || Op == IC_NOT;
138  }
139 
140  public:
141  int64_t popOperand() {
142  assert (!PostfixStack.empty() && "Poped an empty stack!");
143  ICToken Op = PostfixStack.pop_back_val();
144  if (!(Op.first == IC_IMM || Op.first == IC_REGISTER))
145  return -1; // The invalid Scale value will be caught later by checkScale
146  return Op.second;
147  }
148  void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
149  assert ((Op == IC_IMM || Op == IC_REGISTER) &&
150  "Unexpected operand!");
151  PostfixStack.push_back(std::make_pair(Op, Val));
152  }
153 
154  void popOperator() { InfixOperatorStack.pop_back(); }
155  void pushOperator(InfixCalculatorTok Op) {
156  // Push the new operator if the stack is empty.
157  if (InfixOperatorStack.empty()) {
158  InfixOperatorStack.push_back(Op);
159  return;
160  }
161 
162  // Push the new operator if it has a higher precedence than the operator
163  // on the top of the stack or the operator on the top of the stack is a
164  // left parentheses.
165  unsigned Idx = InfixOperatorStack.size() - 1;
166  InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
167  if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
168  InfixOperatorStack.push_back(Op);
169  return;
170  }
171 
172  // The operator on the top of the stack has higher precedence than the
173  // new operator.
174  unsigned ParenCount = 0;
175  while (1) {
176  // Nothing to process.
177  if (InfixOperatorStack.empty())
178  break;
179 
180  Idx = InfixOperatorStack.size() - 1;
181  StackOp = InfixOperatorStack[Idx];
182  if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
183  break;
184 
185  // If we have an even parentheses count and we see a left parentheses,
186  // then stop processing.
187  if (!ParenCount && StackOp == IC_LPAREN)
188  break;
189 
190  if (StackOp == IC_RPAREN) {
191  ++ParenCount;
192  InfixOperatorStack.pop_back();
193  } else if (StackOp == IC_LPAREN) {
194  --ParenCount;
195  InfixOperatorStack.pop_back();
196  } else {
197  InfixOperatorStack.pop_back();
198  PostfixStack.push_back(std::make_pair(StackOp, 0));
199  }
200  }
201  // Push the new operator.
202  InfixOperatorStack.push_back(Op);
203  }
204 
205  int64_t execute() {
206  // Push any remaining operators onto the postfix stack.
207  while (!InfixOperatorStack.empty()) {
208  InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
209  if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
210  PostfixStack.push_back(std::make_pair(StackOp, 0));
211  }
212 
213  if (PostfixStack.empty())
214  return 0;
215 
216  SmallVector<ICToken, 16> OperandStack;
217  for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
218  ICToken Op = PostfixStack[i];
219  if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
220  OperandStack.push_back(Op);
221  } else if (isUnaryOperator(Op.first)) {
222  assert (OperandStack.size() > 0 && "Too few operands.");
223  ICToken Operand = OperandStack.pop_back_val();
224  assert (Operand.first == IC_IMM &&
225  "Unary operation with a register!");
226  switch (Op.first) {
227  default:
228  report_fatal_error("Unexpected operator!");
229  break;
230  case IC_NEG:
231  OperandStack.push_back(std::make_pair(IC_IMM, -Operand.second));
232  break;
233  case IC_NOT:
234  OperandStack.push_back(std::make_pair(IC_IMM, ~Operand.second));
235  break;
236  }
237  } else {
238  assert (OperandStack.size() > 1 && "Too few operands.");
239  int64_t Val;
240  ICToken Op2 = OperandStack.pop_back_val();
241  ICToken Op1 = OperandStack.pop_back_val();
242  switch (Op.first) {
243  default:
244  report_fatal_error("Unexpected operator!");
245  break;
246  case IC_PLUS:
247  Val = Op1.second + Op2.second;
248  OperandStack.push_back(std::make_pair(IC_IMM, Val));
249  break;
250  case IC_MINUS:
251  Val = Op1.second - Op2.second;
252  OperandStack.push_back(std::make_pair(IC_IMM, Val));
253  break;
254  case IC_MULTIPLY:
255  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
256  "Multiply operation with an immediate and a register!");
257  Val = Op1.second * Op2.second;
258  OperandStack.push_back(std::make_pair(IC_IMM, Val));
259  break;
260  case IC_DIVIDE:
261  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
262  "Divide operation with an immediate and a register!");
263  assert (Op2.second != 0 && "Division by zero!");
264  Val = Op1.second / Op2.second;
265  OperandStack.push_back(std::make_pair(IC_IMM, Val));
266  break;
267  case IC_MOD:
268  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
269  "Modulo operation with an immediate and a register!");
270  Val = Op1.second % Op2.second;
271  OperandStack.push_back(std::make_pair(IC_IMM, Val));
272  break;
273  case IC_OR:
274  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
275  "Or operation with an immediate and a register!");
276  Val = Op1.second | Op2.second;
277  OperandStack.push_back(std::make_pair(IC_IMM, Val));
278  break;
279  case IC_XOR:
280  assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
281  "Xor operation with an immediate and a register!");
282  Val = Op1.second ^ Op2.second;
283  OperandStack.push_back(std::make_pair(IC_IMM, Val));
284  break;
285  case IC_AND:
286  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
287  "And operation with an immediate and a register!");
288  Val = Op1.second & Op2.second;
289  OperandStack.push_back(std::make_pair(IC_IMM, Val));
290  break;
291  case IC_LSHIFT:
292  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
293  "Left shift operation with an immediate and a register!");
294  Val = Op1.second << Op2.second;
295  OperandStack.push_back(std::make_pair(IC_IMM, Val));
296  break;
297  case IC_RSHIFT:
298  assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
299  "Right shift operation with an immediate and a register!");
300  Val = Op1.second >> Op2.second;
301  OperandStack.push_back(std::make_pair(IC_IMM, Val));
302  break;
303  }
304  }
305  }
306  assert (OperandStack.size() == 1 && "Expected a single result.");
307  return OperandStack.pop_back_val().second;
308  }
309  };
310 
311  enum IntelExprState {
312  IES_INIT,
313  IES_OR,
314  IES_XOR,
315  IES_AND,
316  IES_LSHIFT,
317  IES_RSHIFT,
318  IES_PLUS,
319  IES_MINUS,
320  IES_NOT,
321  IES_MULTIPLY,
322  IES_DIVIDE,
323  IES_MOD,
324  IES_LBRAC,
325  IES_RBRAC,
326  IES_LPAREN,
327  IES_RPAREN,
328  IES_REGISTER,
329  IES_INTEGER,
330  IES_IDENTIFIER,
331  IES_ERROR
332  };
333 
334  class IntelExprStateMachine {
335  IntelExprState State, PrevState;
336  unsigned BaseReg, IndexReg, TmpReg, Scale;
337  int64_t Imm;
338  const MCExpr *Sym;
339  StringRef SymName;
340  InfixCalculator IC;
342  short BracCount;
343  bool MemExpr;
344 
345  public:
346  IntelExprStateMachine()
347  : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),
348  TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0),
349  MemExpr(false) {}
350 
351  void addImm(int64_t imm) { Imm += imm; }
352  short getBracCount() { return BracCount; }
353  bool isMemExpr() { return MemExpr; }
354  unsigned getBaseReg() { return BaseReg; }
355  unsigned getIndexReg() { return IndexReg; }
356  unsigned getScale() { return Scale; }
357  const MCExpr *getSym() { return Sym; }
358  StringRef getSymName() { return SymName; }
359  int64_t getImm() { return Imm + IC.execute(); }
360  bool isValidEndState() {
361  return State == IES_RBRAC || State == IES_INTEGER;
362  }
363  bool hadError() { return State == IES_ERROR; }
364  InlineAsmIdentifierInfo &getIdentifierInfo() { return Info; }
365 
366  void onOr() {
367  IntelExprState CurrState = State;
368  switch (State) {
369  default:
370  State = IES_ERROR;
371  break;
372  case IES_INTEGER:
373  case IES_RPAREN:
374  case IES_REGISTER:
375  State = IES_OR;
376  IC.pushOperator(IC_OR);
377  break;
378  }
379  PrevState = CurrState;
380  }
381  void onXor() {
382  IntelExprState CurrState = State;
383  switch (State) {
384  default:
385  State = IES_ERROR;
386  break;
387  case IES_INTEGER:
388  case IES_RPAREN:
389  case IES_REGISTER:
390  State = IES_XOR;
391  IC.pushOperator(IC_XOR);
392  break;
393  }
394  PrevState = CurrState;
395  }
396  void onAnd() {
397  IntelExprState CurrState = State;
398  switch (State) {
399  default:
400  State = IES_ERROR;
401  break;
402  case IES_INTEGER:
403  case IES_RPAREN:
404  case IES_REGISTER:
405  State = IES_AND;
406  IC.pushOperator(IC_AND);
407  break;
408  }
409  PrevState = CurrState;
410  }
411  void onLShift() {
412  IntelExprState CurrState = State;
413  switch (State) {
414  default:
415  State = IES_ERROR;
416  break;
417  case IES_INTEGER:
418  case IES_RPAREN:
419  case IES_REGISTER:
420  State = IES_LSHIFT;
421  IC.pushOperator(IC_LSHIFT);
422  break;
423  }
424  PrevState = CurrState;
425  }
426  void onRShift() {
427  IntelExprState CurrState = State;
428  switch (State) {
429  default:
430  State = IES_ERROR;
431  break;
432  case IES_INTEGER:
433  case IES_RPAREN:
434  case IES_REGISTER:
435  State = IES_RSHIFT;
436  IC.pushOperator(IC_RSHIFT);
437  break;
438  }
439  PrevState = CurrState;
440  }
441  bool onPlus(StringRef &ErrMsg) {
442  IntelExprState CurrState = State;
443  switch (State) {
444  default:
445  State = IES_ERROR;
446  break;
447  case IES_INTEGER:
448  case IES_RPAREN:
449  case IES_REGISTER:
450  State = IES_PLUS;
451  IC.pushOperator(IC_PLUS);
452  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
453  // If we already have a BaseReg, then assume this is the IndexReg with
454  // no explicit scale.
455  if (!BaseReg) {
456  BaseReg = TmpReg;
457  } else {
458  if (IndexReg) {
459  ErrMsg = "BaseReg/IndexReg already set!";
460  return true;
461  }
462  IndexReg = TmpReg;
463  Scale = 0;
464  }
465  }
466  break;
467  }
468  PrevState = CurrState;
469  return false;
470  }
471  bool onMinus(StringRef &ErrMsg) {
472  IntelExprState CurrState = State;
473  switch (State) {
474  default:
475  State = IES_ERROR;
476  break;
477  case IES_OR:
478  case IES_XOR:
479  case IES_AND:
480  case IES_LSHIFT:
481  case IES_RSHIFT:
482  case IES_PLUS:
483  case IES_NOT:
484  case IES_MULTIPLY:
485  case IES_DIVIDE:
486  case IES_MOD:
487  case IES_LPAREN:
488  case IES_RPAREN:
489  case IES_LBRAC:
490  case IES_RBRAC:
491  case IES_INTEGER:
492  case IES_REGISTER:
493  case IES_INIT:
494  State = IES_MINUS;
495  // push minus operator if it is not a negate operator
496  if (CurrState == IES_REGISTER || CurrState == IES_RPAREN ||
497  CurrState == IES_INTEGER || CurrState == IES_RBRAC)
498  IC.pushOperator(IC_MINUS);
499  else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
500  // We have negate operator for Scale: it's illegal
501  ErrMsg = "Scale can't be negative";
502  return true;
503  } else
504  IC.pushOperator(IC_NEG);
505  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
506  // If we already have a BaseReg, then assume this is the IndexReg with
507  // no explicit scale.
508  if (!BaseReg) {
509  BaseReg = TmpReg;
510  } else {
511  if (IndexReg) {
512  ErrMsg = "BaseReg/IndexReg already set!";
513  return true;
514  }
515  IndexReg = TmpReg;
516  Scale = 0;
517  }
518  }
519  break;
520  }
521  PrevState = CurrState;
522  return false;
523  }
524  void onNot() {
525  IntelExprState CurrState = State;
526  switch (State) {
527  default:
528  State = IES_ERROR;
529  break;
530  case IES_OR:
531  case IES_XOR:
532  case IES_AND:
533  case IES_LSHIFT:
534  case IES_RSHIFT:
535  case IES_PLUS:
536  case IES_MINUS:
537  case IES_NOT:
538  case IES_MULTIPLY:
539  case IES_DIVIDE:
540  case IES_MOD:
541  case IES_LPAREN:
542  case IES_LBRAC:
543  case IES_INIT:
544  State = IES_NOT;
545  IC.pushOperator(IC_NOT);
546  break;
547  }
548  PrevState = CurrState;
549  }
550 
551  bool onRegister(unsigned Reg, StringRef &ErrMsg) {
552  IntelExprState CurrState = State;
553  switch (State) {
554  default:
555  State = IES_ERROR;
556  break;
557  case IES_PLUS:
558  case IES_LPAREN:
559  case IES_LBRAC:
560  State = IES_REGISTER;
561  TmpReg = Reg;
562  IC.pushOperand(IC_REGISTER);
563  break;
564  case IES_MULTIPLY:
565  // Index Register - Scale * Register
566  if (PrevState == IES_INTEGER) {
567  if (IndexReg) {
568  ErrMsg = "BaseReg/IndexReg already set!";
569  return true;
570  }
571  State = IES_REGISTER;
572  IndexReg = Reg;
573  // Get the scale and replace the 'Scale * Register' with '0'.
574  Scale = IC.popOperand();
575  if (checkScale(Scale, ErrMsg))
576  return true;
577  IC.pushOperand(IC_IMM);
578  IC.popOperator();
579  } else {
580  State = IES_ERROR;
581  }
582  break;
583  }
584  PrevState = CurrState;
585  return false;
586  }
587  bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName,
588  const InlineAsmIdentifierInfo &IDInfo,
589  bool ParsingInlineAsm, StringRef &ErrMsg) {
590  // InlineAsm: Treat an enum value as an integer
591  if (ParsingInlineAsm)
593  return onInteger(IDInfo.Enum.EnumVal, ErrMsg);
594  // Treat a symbolic constant like an integer
595  if (auto *CE = dyn_cast<MCConstantExpr>(SymRef))
596  return onInteger(CE->getValue(), ErrMsg);
597  PrevState = State;
598  bool HasSymbol = Sym != nullptr;
599  switch (State) {
600  default:
601  State = IES_ERROR;
602  break;
603  case IES_PLUS:
604  case IES_MINUS:
605  case IES_NOT:
606  case IES_INIT:
607  case IES_LBRAC:
608  MemExpr = true;
609  State = IES_INTEGER;
610  Sym = SymRef;
611  SymName = SymRefName;
612  IC.pushOperand(IC_IMM);
613  if (ParsingInlineAsm)
614  Info = IDInfo;
615  break;
616  }
617  if (HasSymbol)
618  ErrMsg = "cannot use more than one symbol in memory operand";
619  return HasSymbol;
620  }
621  bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
622  IntelExprState CurrState = State;
623  switch (State) {
624  default:
625  State = IES_ERROR;
626  break;
627  case IES_PLUS:
628  case IES_MINUS:
629  case IES_NOT:
630  case IES_OR:
631  case IES_XOR:
632  case IES_AND:
633  case IES_LSHIFT:
634  case IES_RSHIFT:
635  case IES_DIVIDE:
636  case IES_MOD:
637  case IES_MULTIPLY:
638  case IES_LPAREN:
639  case IES_INIT:
640  case IES_LBRAC:
641  State = IES_INTEGER;
642  if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
643  // Index Register - Register * Scale
644  if (IndexReg) {
645  ErrMsg = "BaseReg/IndexReg already set!";
646  return true;
647  }
648  IndexReg = TmpReg;
649  Scale = TmpInt;
650  if (checkScale(Scale, ErrMsg))
651  return true;
652  // Get the scale and replace the 'Register * Scale' with '0'.
653  IC.popOperator();
654  } else {
655  IC.pushOperand(IC_IMM, TmpInt);
656  }
657  break;
658  }
659  PrevState = CurrState;
660  return false;
661  }
662  void onStar() {
663  PrevState = State;
664  switch (State) {
665  default:
666  State = IES_ERROR;
667  break;
668  case IES_INTEGER:
669  case IES_REGISTER:
670  case IES_RPAREN:
671  State = IES_MULTIPLY;
672  IC.pushOperator(IC_MULTIPLY);
673  break;
674  }
675  }
676  void onDivide() {
677  PrevState = State;
678  switch (State) {
679  default:
680  State = IES_ERROR;
681  break;
682  case IES_INTEGER:
683  case IES_RPAREN:
684  State = IES_DIVIDE;
685  IC.pushOperator(IC_DIVIDE);
686  break;
687  }
688  }
689  void onMod() {
690  PrevState = State;
691  switch (State) {
692  default:
693  State = IES_ERROR;
694  break;
695  case IES_INTEGER:
696  case IES_RPAREN:
697  State = IES_MOD;
698  IC.pushOperator(IC_MOD);
699  break;
700  }
701  }
702  bool onLBrac() {
703  if (BracCount)
704  return true;
705  PrevState = State;
706  switch (State) {
707  default:
708  State = IES_ERROR;
709  break;
710  case IES_RBRAC:
711  case IES_INTEGER:
712  case IES_RPAREN:
713  State = IES_PLUS;
714  IC.pushOperator(IC_PLUS);
715  break;
716  case IES_INIT:
717  assert(!BracCount && "BracCount should be zero on parsing's start");
718  State = IES_LBRAC;
719  break;
720  }
721  MemExpr = true;
722  BracCount++;
723  return false;
724  }
725  bool onRBrac() {
726  IntelExprState CurrState = State;
727  switch (State) {
728  default:
729  State = IES_ERROR;
730  break;
731  case IES_INTEGER:
732  case IES_REGISTER:
733  case IES_RPAREN:
734  if (BracCount-- != 1)
735  return true;
736  State = IES_RBRAC;
737  if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
738  // If we already have a BaseReg, then assume this is the IndexReg with
739  // no explicit scale.
740  if (!BaseReg) {
741  BaseReg = TmpReg;
742  } else {
743  assert (!IndexReg && "BaseReg/IndexReg already set!");
744  IndexReg = TmpReg;
745  Scale = 0;
746  }
747  }
748  break;
749  }
750  PrevState = CurrState;
751  return false;
752  }
753  void onLParen() {
754  IntelExprState CurrState = State;
755  switch (State) {
756  default:
757  State = IES_ERROR;
758  break;
759  case IES_PLUS:
760  case IES_MINUS:
761  case IES_NOT:
762  case IES_OR:
763  case IES_XOR:
764  case IES_AND:
765  case IES_LSHIFT:
766  case IES_RSHIFT:
767  case IES_MULTIPLY:
768  case IES_DIVIDE:
769  case IES_MOD:
770  case IES_LPAREN:
771  case IES_INIT:
772  case IES_LBRAC:
773  State = IES_LPAREN;
774  IC.pushOperator(IC_LPAREN);
775  break;
776  }
777  PrevState = CurrState;
778  }
779  void onRParen() {
780  PrevState = State;
781  switch (State) {
782  default:
783  State = IES_ERROR;
784  break;
785  case IES_INTEGER:
786  case IES_REGISTER:
787  case IES_RPAREN:
788  State = IES_RPAREN;
789  IC.pushOperator(IC_RPAREN);
790  break;
791  }
792  }
793  };
794 
795  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
796  bool MatchingInlineAsm = false) {
797  MCAsmParser &Parser = getParser();
798  if (MatchingInlineAsm) {
799  if (!getLexer().isAtStartOfStatement())
800  Parser.eatToEndOfStatement();
801  return false;
802  }
803  return Parser.Error(L, Msg, Range);
804  }
805 
806  std::nullptr_t ErrorOperand(SMLoc Loc, StringRef Msg, SMRange R = SMRange()) {
807  Error(Loc, Msg, R);
808  return nullptr;
809  }
810 
811  std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
812  std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc);
813  bool IsSIReg(unsigned Reg);
814  unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
815  void
816  AddDefaultSrcDestOperands(OperandVector &Operands,
817  std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
818  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
819  bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
820  OperandVector &FinalOperands);
821  std::unique_ptr<X86Operand> ParseOperand();
822  std::unique_ptr<X86Operand> ParseATTOperand();
823  std::unique_ptr<X86Operand> ParseIntelOperand();
824  std::unique_ptr<X86Operand> ParseIntelOffsetOfOperator();
825  bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End);
826  unsigned IdentifyIntelInlineAsmOperator(StringRef Name);
827  unsigned ParseIntelInlineAsmOperator(unsigned OpKind);
828  std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start);
829  bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM);
830  void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start,
831  SMLoc End);
832  bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
833  bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier,
835  bool IsUnevaluatedOperand, SMLoc &End);
836 
837  std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg,
838  const MCExpr *&Disp,
839  const SMLoc &StartLoc,
840  SMLoc &EndLoc);
841 
842  bool ParseIntelMemoryOperandSize(unsigned &Size);
843  std::unique_ptr<X86Operand>
844  CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
845  unsigned IndexReg, unsigned Scale, SMLoc Start,
846  SMLoc End, unsigned Size, StringRef Identifier,
847  const InlineAsmIdentifierInfo &Info);
848 
849  bool parseDirectiveEven(SMLoc L);
850  bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
851 
852  /// CodeView FPO data directives.
853  bool parseDirectiveFPOProc(SMLoc L);
854  bool parseDirectiveFPOSetFrame(SMLoc L);
855  bool parseDirectiveFPOPushReg(SMLoc L);
856  bool parseDirectiveFPOStackAlloc(SMLoc L);
857  bool parseDirectiveFPOStackAlign(SMLoc L);
858  bool parseDirectiveFPOEndPrologue(SMLoc L);
859  bool parseDirectiveFPOEndProc(SMLoc L);
860  bool parseDirectiveFPOData(SMLoc L);
861 
862  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
863  bool processInstruction(MCInst &Inst, const OperandVector &Ops);
864 
865  /// Wrapper around MCStreamer::EmitInstruction(). Possibly adds
866  /// instrumentation around Inst.
867  void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
868 
869  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
870  OperandVector &Operands, MCStreamer &Out,
871  uint64_t &ErrorInfo,
872  bool MatchingInlineAsm) override;
873 
874  void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
875  MCStreamer &Out, bool MatchingInlineAsm);
876 
877  bool ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo,
878  bool MatchingInlineAsm);
879 
880  bool MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
881  OperandVector &Operands, MCStreamer &Out,
882  uint64_t &ErrorInfo,
883  bool MatchingInlineAsm);
884 
885  bool MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
886  OperandVector &Operands, MCStreamer &Out,
887  uint64_t &ErrorInfo,
888  bool MatchingInlineAsm);
889 
890  bool OmitRegisterFromClobberLists(unsigned RegNo) override;
891 
892  /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
893  /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
894  /// return false if no parsing errors occurred, true otherwise.
895  bool HandleAVX512Operand(OperandVector &Operands,
896  const MCParsedAsmOperand &Op);
897 
898  bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
899 
900  bool is64BitMode() const {
901  // FIXME: Can tablegen auto-generate this?
902  return getSTI().getFeatureBits()[X86::Mode64Bit];
903  }
904  bool is32BitMode() const {
905  // FIXME: Can tablegen auto-generate this?
906  return getSTI().getFeatureBits()[X86::Mode32Bit];
907  }
908  bool is16BitMode() const {
909  // FIXME: Can tablegen auto-generate this?
910  return getSTI().getFeatureBits()[X86::Mode16Bit];
911  }
912  void SwitchMode(unsigned mode) {
913  MCSubtargetInfo &STI = copySTI();
914  FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
915  FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
916  uint64_t FB = ComputeAvailableFeatures(
917  STI.ToggleFeature(OldMode.flip(mode)));
918  setAvailableFeatures(FB);
919 
920  assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
921  }
922 
923  unsigned getPointerWidth() {
924  if (is16BitMode()) return 16;
925  if (is32BitMode()) return 32;
926  if (is64BitMode()) return 64;
927  llvm_unreachable("invalid mode");
928  }
929 
930  bool isParsingIntelSyntax() {
931  return getParser().getAssemblerDialect();
932  }
933 
934  /// @name Auto-generated Matcher Functions
935  /// {
936 
937 #define GET_ASSEMBLER_HEADER
938 #include "X86GenAsmMatcher.inc"
939 
940  /// }
941 
942 public:
943 
944  X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
945  const MCInstrInfo &mii, const MCTargetOptions &Options)
946  : MCTargetAsmParser(Options, sti, mii), InstInfo(nullptr),
947  Code16GCC(false) {
948 
949  Parser.addAliasForDirective(".word", ".2byte");
950 
951  // Initialize the set of available features.
952  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
953  Instrumentation.reset(
954  CreateX86AsmInstrumentation(Options, Parser.getContext(), STI));
955  }
956 
957  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
958 
959  void SetFrameRegister(unsigned RegNo) override;
960 
961  bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) override;
962 
963  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
964  SMLoc NameLoc, OperandVector &Operands) override;
965 
966  bool ParseDirective(AsmToken DirectiveID) override;
967 };
968 } // end anonymous namespace
969 
970 /// @name Auto-generated Match Functions
971 /// {
972 
973 static unsigned MatchRegisterName(StringRef Name);
974 
975 /// }
976 
977 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,
978  unsigned Scale, bool Is64BitMode,
979  StringRef &ErrMsg) {
980  // If we have both a base register and an index register make sure they are
981  // both 64-bit or 32-bit registers.
982  // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
983 
984  if (BaseReg != 0 &&
985  !(BaseReg == X86::RIP || BaseReg == X86::EIP ||
986  X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) ||
987  X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) ||
988  X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg))) {
989  ErrMsg = "invalid base+index expression";
990  return true;
991  }
992 
993  if (IndexReg != 0 &&
994  !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||
995  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
996  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
997  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
998  X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
999  X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
1000  X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg))) {
1001  ErrMsg = "invalid base+index expression";
1002  return true;
1003  }
1004 
1005  if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||
1006  IndexReg == X86::EIP || IndexReg == X86::RIP ||
1007  IndexReg == X86::ESP || IndexReg == X86::RSP) {
1008  ErrMsg = "invalid base+index expression";
1009  return true;
1010  }
1011 
1012  // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
1013  // and then only in non-64-bit modes.
1014  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
1015  (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&
1016  BaseReg != X86::SI && BaseReg != X86::DI))) {
1017  ErrMsg = "invalid 16-bit base register";
1018  return true;
1019  }
1020 
1021  if (BaseReg == 0 &&
1022  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
1023  ErrMsg = "16-bit memory operand may not include only index register";
1024  return true;
1025  }
1026 
1027  if (BaseReg != 0 && IndexReg != 0) {
1028  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
1029  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1030  X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1031  IndexReg == X86::EIZ)) {
1032  ErrMsg = "base register is 64-bit, but index register is not";
1033  return true;
1034  }
1035  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
1036  (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
1037  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
1038  IndexReg == X86::RIZ)) {
1039  ErrMsg = "base register is 32-bit, but index register is not";
1040  return true;
1041  }
1042  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
1043  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
1044  X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
1045  ErrMsg = "base register is 16-bit, but index register is not";
1046  return true;
1047  }
1048  if ((BaseReg != X86::BX && BaseReg != X86::BP) ||
1049  (IndexReg != X86::SI && IndexReg != X86::DI)) {
1050  ErrMsg = "invalid 16-bit base/index register combination";
1051  return true;
1052  }
1053  }
1054  }
1055 
1056  // RIP/EIP-relative addressing is only supported in 64-bit mode.
1057  if (!Is64BitMode && BaseReg != 0 &&
1058  (BaseReg == X86::RIP || BaseReg == X86::EIP)) {
1059  ErrMsg = "IP-relative addressing requires 64-bit mode";
1060  return true;
1061  }
1062 
1063  return checkScale(Scale, ErrMsg);
1064 }
1065 
1066 bool X86AsmParser::ParseRegister(unsigned &RegNo,
1067  SMLoc &StartLoc, SMLoc &EndLoc) {
1068  MCAsmParser &Parser = getParser();
1069  RegNo = 0;
1070  const AsmToken &PercentTok = Parser.getTok();
1071  StartLoc = PercentTok.getLoc();
1072 
1073  // If we encounter a %, ignore it. This code handles registers with and
1074  // without the prefix, unprefixed registers can occur in cfi directives.
1075  if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
1076  Parser.Lex(); // Eat percent token.
1077 
1078  const AsmToken &Tok = Parser.getTok();
1079  EndLoc = Tok.getEndLoc();
1080 
1081  if (Tok.isNot(AsmToken::Identifier)) {
1082  if (isParsingIntelSyntax()) return true;
1083  return Error(StartLoc, "invalid register name",
1084  SMRange(StartLoc, EndLoc));
1085  }
1086 
1087  RegNo = MatchRegisterName(Tok.getString());
1088 
1089  // If the match failed, try the register name as lowercase.
1090  if (RegNo == 0)
1091  RegNo = MatchRegisterName(Tok.getString().lower());
1092 
1093  // The "flags" register cannot be referenced directly.
1094  // Treat it as an identifier instead.
1095  if (isParsingInlineAsm() && isParsingIntelSyntax() && RegNo == X86::EFLAGS)
1096  RegNo = 0;
1097 
1098  if (!is64BitMode()) {
1099  // FIXME: This should be done using Requires<Not64BitMode> and
1100  // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1101  // checked.
1102  // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
1103  // REX prefix.
1104  if (RegNo == X86::RIZ || RegNo == X86::RIP ||
1105  X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
1107  X86II::isX86_64ExtendedReg(RegNo)) {
1108  StringRef RegName = Tok.getString();
1109  Parser.Lex(); // Eat register name.
1110  return Error(StartLoc,
1111  "register %" + RegName + " is only available in 64-bit mode",
1112  SMRange(StartLoc, EndLoc));
1113  }
1114  }
1115 
1116  // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1117  if (RegNo == X86::ST0) {
1118  Parser.Lex(); // Eat 'st'
1119 
1120  // Check to see if we have '(4)' after %st.
1121  if (getLexer().isNot(AsmToken::LParen))
1122  return false;
1123  // Lex the paren.
1124  getParser().Lex();
1125 
1126  const AsmToken &IntTok = Parser.getTok();
1127  if (IntTok.isNot(AsmToken::Integer))
1128  return Error(IntTok.getLoc(), "expected stack index");
1129  switch (IntTok.getIntVal()) {
1130  case 0: RegNo = X86::ST0; break;
1131  case 1: RegNo = X86::ST1; break;
1132  case 2: RegNo = X86::ST2; break;
1133  case 3: RegNo = X86::ST3; break;
1134  case 4: RegNo = X86::ST4; break;
1135  case 5: RegNo = X86::ST5; break;
1136  case 6: RegNo = X86::ST6; break;
1137  case 7: RegNo = X86::ST7; break;
1138  default: return Error(IntTok.getLoc(), "invalid stack index");
1139  }
1140 
1141  if (getParser().Lex().isNot(AsmToken::RParen))
1142  return Error(Parser.getTok().getLoc(), "expected ')'");
1143 
1144  EndLoc = Parser.getTok().getEndLoc();
1145  Parser.Lex(); // Eat ')'
1146  return false;
1147  }
1148 
1149  EndLoc = Parser.getTok().getEndLoc();
1150 
1151  // If this is "db[0-15]", match it as an alias
1152  // for dr[0-15].
1153  if (RegNo == 0 && Tok.getString().startswith("db")) {
1154  if (Tok.getString().size() == 3) {
1155  switch (Tok.getString()[2]) {
1156  case '0': RegNo = X86::DR0; break;
1157  case '1': RegNo = X86::DR1; break;
1158  case '2': RegNo = X86::DR2; break;
1159  case '3': RegNo = X86::DR3; break;
1160  case '4': RegNo = X86::DR4; break;
1161  case '5': RegNo = X86::DR5; break;
1162  case '6': RegNo = X86::DR6; break;
1163  case '7': RegNo = X86::DR7; break;
1164  case '8': RegNo = X86::DR8; break;
1165  case '9': RegNo = X86::DR9; break;
1166  }
1167  } else if (Tok.getString().size() == 4 && Tok.getString()[2] == '1') {
1168  switch (Tok.getString()[3]) {
1169  case '0': RegNo = X86::DR10; break;
1170  case '1': RegNo = X86::DR11; break;
1171  case '2': RegNo = X86::DR12; break;
1172  case '3': RegNo = X86::DR13; break;
1173  case '4': RegNo = X86::DR14; break;
1174  case '5': RegNo = X86::DR15; break;
1175  }
1176  }
1177 
1178  if (RegNo != 0) {
1179  EndLoc = Parser.getTok().getEndLoc();
1180  Parser.Lex(); // Eat it.
1181  return false;
1182  }
1183  }
1184 
1185  if (RegNo == 0) {
1186  if (isParsingIntelSyntax()) return true;
1187  return Error(StartLoc, "invalid register name",
1188  SMRange(StartLoc, EndLoc));
1189  }
1190 
1191  Parser.Lex(); // Eat identifier token.
1192  return false;
1193 }
1194 
1195 void X86AsmParser::SetFrameRegister(unsigned RegNo) {
1196  Instrumentation->SetInitialFrameRegister(RegNo);
1197 }
1198 
1199 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1200  bool Parse32 = is32BitMode() || Code16GCC;
1201  unsigned Basereg = is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI);
1202  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1203  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1204  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1205  Loc, Loc, 0);
1206 }
1207 
1208 std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
1209  bool Parse32 = is32BitMode() || Code16GCC;
1210  unsigned Basereg = is64BitMode() ? X86::RDI : (Parse32 ? X86::EDI : X86::DI);
1211  const MCExpr *Disp = MCConstantExpr::create(0, getContext());
1212  return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1213  /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
1214  Loc, Loc, 0);
1215 }
1216 
1217 bool X86AsmParser::IsSIReg(unsigned Reg) {
1218  switch (Reg) {
1219  default: llvm_unreachable("Only (R|E)SI and (R|E)DI are expected!");
1220  case X86::RSI:
1221  case X86::ESI:
1222  case X86::SI:
1223  return true;
1224  case X86::RDI:
1225  case X86::EDI:
1226  case X86::DI:
1227  return false;
1228  }
1229 }
1230 
1231 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg,
1232  bool IsSIReg) {
1233  switch (RegClassID) {
1234  default: llvm_unreachable("Unexpected register class");
1235  case X86::GR64RegClassID:
1236  return IsSIReg ? X86::RSI : X86::RDI;
1237  case X86::GR32RegClassID:
1238  return IsSIReg ? X86::ESI : X86::EDI;
1239  case X86::GR16RegClassID:
1240  return IsSIReg ? X86::SI : X86::DI;
1241  }
1242 }
1243 
1244 void X86AsmParser::AddDefaultSrcDestOperands(
1245  OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1246  std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) {
1247  if (isParsingIntelSyntax()) {
1248  Operands.push_back(std::move(Dst));
1249  Operands.push_back(std::move(Src));
1250  }
1251  else {
1252  Operands.push_back(std::move(Src));
1253  Operands.push_back(std::move(Dst));
1254  }
1255 }
1256 
1257 bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
1258  OperandVector &FinalOperands) {
1259 
1260  if (OrigOperands.size() > 1) {
1261  // Check if sizes match, OrigOperands also contains the instruction name
1262  assert(OrigOperands.size() == FinalOperands.size() + 1 &&
1263  "Operand size mismatch");
1264 
1266  // Verify types match
1267  int RegClassID = -1;
1268  for (unsigned int i = 0; i < FinalOperands.size(); ++i) {
1269  X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]);
1270  X86Operand &FinalOp = static_cast<X86Operand &>(*FinalOperands[i]);
1271 
1272  if (FinalOp.isReg() &&
1273  (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg()))
1274  // Return false and let a normal complaint about bogus operands happen
1275  return false;
1276 
1277  if (FinalOp.isMem()) {
1278 
1279  if (!OrigOp.isMem())
1280  // Return false and let a normal complaint about bogus operands happen
1281  return false;
1282 
1283  unsigned OrigReg = OrigOp.Mem.BaseReg;
1284  unsigned FinalReg = FinalOp.Mem.BaseReg;
1285 
1286  // If we've already encounterd a register class, make sure all register
1287  // bases are of the same register class
1288  if (RegClassID != -1 &&
1289  !X86MCRegisterClasses[RegClassID].contains(OrigReg)) {
1290  return Error(OrigOp.getStartLoc(),
1291  "mismatching source and destination index registers");
1292  }
1293 
1294  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg))
1295  RegClassID = X86::GR64RegClassID;
1296  else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg))
1297  RegClassID = X86::GR32RegClassID;
1298  else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg))
1299  RegClassID = X86::GR16RegClassID;
1300  else
1301  // Unexpected register class type
1302  // Return false and let a normal complaint about bogus operands happen
1303  return false;
1304 
1305  bool IsSI = IsSIReg(FinalReg);
1306  FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI);
1307 
1308  if (FinalReg != OrigReg) {
1309  std::string RegName = IsSI ? "ES:(R|E)SI" : "ES:(R|E)DI";
1310  Warnings.push_back(std::make_pair(
1311  OrigOp.getStartLoc(),
1312  "memory operand is only for determining the size, " + RegName +
1313  " will be used for the location"));
1314  }
1315 
1316  FinalOp.Mem.Size = OrigOp.Mem.Size;
1317  FinalOp.Mem.SegReg = OrigOp.Mem.SegReg;
1318  FinalOp.Mem.BaseReg = FinalReg;
1319  }
1320  }
1321 
1322  // Produce warnings only if all the operands passed the adjustment - prevent
1323  // legal cases like "movsd (%rax), %xmm0" mistakenly produce warnings
1324  for (auto &WarningMsg : Warnings) {
1325  Warning(WarningMsg.first, WarningMsg.second);
1326  }
1327 
1328  // Remove old operands
1329  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1330  OrigOperands.pop_back();
1331  }
1332  // OrigOperands.append(FinalOperands.begin(), FinalOperands.end());
1333  for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1334  OrigOperands.push_back(std::move(FinalOperands[i]));
1335 
1336  return false;
1337 }
1338 
1339 std::unique_ptr<X86Operand> X86AsmParser::ParseOperand() {
1340  if (isParsingIntelSyntax())
1341  return ParseIntelOperand();
1342  return ParseATTOperand();
1343 }
1344 
1345 std::unique_ptr<X86Operand> X86AsmParser::CreateMemForInlineAsm(
1346  unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1347  unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier,
1348  const InlineAsmIdentifierInfo &Info) {
1349  // If we found a decl other than a VarDecl, then assume it is a FuncDecl or
1350  // some other label reference.
1352  // Insert an explicit size if the user didn't have one.
1353  if (!Size) {
1354  Size = getPointerWidth();
1355  InstInfo->AsmRewrites->emplace_back(AOK_SizeDirective, Start,
1356  /*Len=*/0, Size);
1357  }
1358  // Create an absolute memory reference in order to match against
1359  // instructions taking a PC relative operand.
1360  return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size,
1361  Identifier, Info.Label.Decl);
1362  }
1363  // We either have a direct symbol reference, or an offset from a symbol. The
1364  // parser always puts the symbol on the LHS, so look there for size
1365  // calculation purposes.
1366  unsigned FrontendSize = 0;
1367  void *Decl = nullptr;
1368  bool IsGlobalLV = false;
1370  // Size is in terms of bits in this context.
1371  FrontendSize = Info.Var.Type * 8;
1372  Decl = Info.Var.Decl;
1373  IsGlobalLV = Info.Var.IsGlobalLV;
1374  }
1375  // It is widely common for MS InlineAsm to use a global variable and one/two
1376  // registers in a mmory expression, and though unaccessible via rip/eip.
1377  if (IsGlobalLV && (BaseReg || IndexReg)) {
1378  return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End);
1379  // Otherwise, we set the base register to a non-zero value
1380  // if we don't know the actual value at this time. This is necessary to
1381  // get the matching correct in some cases.
1382  } else {
1383  BaseReg = BaseReg ? BaseReg : 1;
1384  return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
1385  IndexReg, Scale, Start, End, Size, Identifier,
1386  Decl, FrontendSize);
1387  }
1388 }
1389 
1390 // Some binary bitwise operators have a named synonymous
1391 // Query a candidate string for being such a named operator
1392 // and if so - invoke the appropriate handler
1393 bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM) {
1394  // A named operator should be either lower or upper case, but not a mix
1395  if (Name.compare(Name.lower()) && Name.compare(Name.upper()))
1396  return false;
1397  if (Name.equals_lower("not"))
1398  SM.onNot();
1399  else if (Name.equals_lower("or"))
1400  SM.onOr();
1401  else if (Name.equals_lower("shl"))
1402  SM.onLShift();
1403  else if (Name.equals_lower("shr"))
1404  SM.onRShift();
1405  else if (Name.equals_lower("xor"))
1406  SM.onXor();
1407  else if (Name.equals_lower("and"))
1408  SM.onAnd();
1409  else if (Name.equals_lower("mod"))
1410  SM.onMod();
1411  else
1412  return false;
1413  return true;
1414 }
1415 
1416 bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
1417  MCAsmParser &Parser = getParser();
1418  const AsmToken &Tok = Parser.getTok();
1419  StringRef ErrMsg;
1420 
1422  bool Done = false;
1423  while (!Done) {
1424  bool UpdateLocLex = true;
1425  AsmToken::TokenKind TK = getLexer().getKind();
1426 
1427  switch (TK) {
1428  default:
1429  if ((Done = SM.isValidEndState()))
1430  break;
1431  return Error(Tok.getLoc(), "unknown token in expression");
1433  Done = true;
1434  break;
1435  case AsmToken::Real:
1436  // DotOperator: [ebx].0
1437  UpdateLocLex = false;
1438  if (ParseIntelDotOperator(SM, End))
1439  return true;
1440  break;
1441  case AsmToken::At:
1442  case AsmToken::String:
1443  case AsmToken::Identifier: {
1444  SMLoc IdentLoc = Tok.getLoc();
1445  StringRef Identifier = Tok.getString();
1446  UpdateLocLex = false;
1447  // Register
1448  unsigned Reg;
1449  if (Tok.is(AsmToken::Identifier) && !ParseRegister(Reg, IdentLoc, End)) {
1450  if (SM.onRegister(Reg, ErrMsg))
1451  return Error(Tok.getLoc(), ErrMsg);
1452  break;
1453  }
1454  // Operator synonymous ("not", "or" etc.)
1455  if ((UpdateLocLex = ParseIntelNamedOperator(Identifier, SM)))
1456  break;
1457  // Symbol reference, when parsing assembly content
1459  const MCExpr *Val;
1460  if (!isParsingInlineAsm()) {
1461  if (getParser().parsePrimaryExpr(Val, End)) {
1462  return Error(Tok.getLoc(), "Unexpected identifier!");
1463  } else if (SM.onIdentifierExpr(Val, Identifier, Info, false, ErrMsg)) {
1464  return Error(IdentLoc, ErrMsg);
1465  } else
1466  break;
1467  }
1468  // MS InlineAsm operators (TYPE/LENGTH/SIZE)
1469  if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Identifier)) {
1470  if (OpKind == IOK_OFFSET)
1471  return Error(IdentLoc, "Dealing OFFSET operator as part of"
1472  "a compound immediate expression is yet to be supported");
1473  if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) {
1474  if (SM.onInteger(Val, ErrMsg))
1475  return Error(IdentLoc, ErrMsg);
1476  } else
1477  return true;
1478  break;
1479  }
1480  // MS Dot Operator expression
1481  if (Identifier.count('.') && PrevTK == AsmToken::RBrac) {
1482  if (ParseIntelDotOperator(SM, End))
1483  return true;
1484  break;
1485  }
1486  // MS InlineAsm identifier
1487  // Call parseIdentifier() to combine @ with the identifier behind it.
1488  if (TK == AsmToken::At && Parser.parseIdentifier(Identifier))
1489  return Error(IdentLoc, "expected identifier");
1490  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, false, End))
1491  return true;
1492  else if (SM.onIdentifierExpr(Val, Identifier, Info, true, ErrMsg))
1493  return Error(IdentLoc, ErrMsg);
1494  break;
1495  }
1496  case AsmToken::Integer: {
1497  // Look for 'b' or 'f' following an Integer as a directional label
1498  SMLoc Loc = getTok().getLoc();
1499  int64_t IntVal = getTok().getIntVal();
1500  End = consumeToken();
1501  UpdateLocLex = false;
1502  if (getLexer().getKind() == AsmToken::Identifier) {
1503  StringRef IDVal = getTok().getString();
1504  if (IDVal == "f" || IDVal == "b") {
1505  MCSymbol *Sym =
1506  getContext().getDirectionalLocalSymbol(IntVal, IDVal == "b");
1508  const MCExpr *Val =
1509  MCSymbolRefExpr::create(Sym, Variant, getContext());
1510  if (IDVal == "b" && Sym->isUndefined())
1511  return Error(Loc, "invalid reference to undefined symbol");
1512  StringRef Identifier = Sym->getName();
1514  if (SM.onIdentifierExpr(Val, Identifier, Info,
1515  isParsingInlineAsm(), ErrMsg))
1516  return Error(Loc, ErrMsg);
1517  End = consumeToken();
1518  } else {
1519  if (SM.onInteger(IntVal, ErrMsg))
1520  return Error(Loc, ErrMsg);
1521  }
1522  } else {
1523  if (SM.onInteger(IntVal, ErrMsg))
1524  return Error(Loc, ErrMsg);
1525  }
1526  break;
1527  }
1528  case AsmToken::Plus:
1529  if (SM.onPlus(ErrMsg))
1530  return Error(getTok().getLoc(), ErrMsg);
1531  break;
1532  case AsmToken::Minus:
1533  if (SM.onMinus(ErrMsg))
1534  return Error(getTok().getLoc(), ErrMsg);
1535  break;
1536  case AsmToken::Tilde: SM.onNot(); break;
1537  case AsmToken::Star: SM.onStar(); break;
1538  case AsmToken::Slash: SM.onDivide(); break;
1539  case AsmToken::Percent: SM.onMod(); break;
1540  case AsmToken::Pipe: SM.onOr(); break;
1541  case AsmToken::Caret: SM.onXor(); break;
1542  case AsmToken::Amp: SM.onAnd(); break;
1543  case AsmToken::LessLess:
1544  SM.onLShift(); break;
1546  SM.onRShift(); break;
1547  case AsmToken::LBrac:
1548  if (SM.onLBrac())
1549  return Error(Tok.getLoc(), "unexpected bracket encountered");
1550  break;
1551  case AsmToken::RBrac:
1552  if (SM.onRBrac())
1553  return Error(Tok.getLoc(), "unexpected bracket encountered");
1554  break;
1555  case AsmToken::LParen: SM.onLParen(); break;
1556  case AsmToken::RParen: SM.onRParen(); break;
1557  }
1558  if (SM.hadError())
1559  return Error(Tok.getLoc(), "unknown token in expression");
1560 
1561  if (!Done && UpdateLocLex)
1562  End = consumeToken();
1563 
1564  PrevTK = TK;
1565  }
1566  return false;
1567 }
1568 
1569 void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM,
1570  SMLoc Start, SMLoc End) {
1571  SMLoc Loc = Start;
1572  unsigned ExprLen = End.getPointer() - Start.getPointer();
1573  // Skip everything before a symbol displacement (if we have one)
1574  if (SM.getSym()) {
1575  StringRef SymName = SM.getSymName();
1576  if (unsigned Len = SymName.data() - Start.getPointer())
1577  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Start, Len);
1578  Loc = SMLoc::getFromPointer(SymName.data() + SymName.size());
1579  ExprLen = End.getPointer() - (SymName.data() + SymName.size());
1580  // If we have only a symbol than there's no need for complex rewrite,
1581  // simply skip everything after it
1582  if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) {
1583  if (ExprLen)
1584  InstInfo->AsmRewrites->emplace_back(AOK_Skip, Loc, ExprLen);
1585  return;
1586  }
1587  }
1588  // Build an Intel Expression rewrite
1589  StringRef BaseRegStr;
1590  StringRef IndexRegStr;
1591  if (SM.getBaseReg())
1592  BaseRegStr = X86IntelInstPrinter::getRegisterName(SM.getBaseReg());
1593  if (SM.getIndexReg())
1594  IndexRegStr = X86IntelInstPrinter::getRegisterName(SM.getIndexReg());
1595  // Emit it
1596  IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), SM.getImm(), SM.isMemExpr());
1597  InstInfo->AsmRewrites->emplace_back(Loc, ExprLen, Expr);
1598 }
1599 
1600 // Inline assembly may use variable names with namespace alias qualifiers.
1601 bool X86AsmParser::ParseIntelInlineAsmIdentifier(const MCExpr *&Val,
1602  StringRef &Identifier,
1604  bool IsUnevaluatedOperand,
1605  SMLoc &End) {
1606  MCAsmParser &Parser = getParser();
1607  assert(isParsingInlineAsm() && "Expected to be parsing inline assembly.");
1608  Val = nullptr;
1609 
1610  StringRef LineBuf(Identifier.data());
1611  SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
1612 
1613  const AsmToken &Tok = Parser.getTok();
1614  SMLoc Loc = Tok.getLoc();
1615 
1616  // Advance the token stream until the end of the current token is
1617  // after the end of what the frontend claimed.
1618  const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
1619  do {
1620  End = Tok.getEndLoc();
1621  getLexer().Lex();
1622  } while (End.getPointer() < EndPtr);
1623  Identifier = LineBuf;
1624 
1625  // The frontend should end parsing on an assembler token boundary, unless it
1626  // failed parsing.
1627  assert((End.getPointer() == EndPtr ||
1629  "frontend claimed part of a token?");
1630 
1631  // If the identifier lookup was unsuccessful, assume that we are dealing with
1632  // a label.
1634  StringRef InternalName =
1635  SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(),
1636  Loc, false);
1637  assert(InternalName.size() && "We should have an internal name here.");
1638  // Push a rewrite for replacing the identifier name with the internal name.
1639  InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(),
1640  InternalName);
1642  return false;
1643  // Create the symbol reference.
1644  MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
1646  Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext());
1647  return false;
1648 }
1649 
1650 //ParseRoundingModeOp - Parse AVX-512 rounding mode operand
1651 std::unique_ptr<X86Operand>
1652 X86AsmParser::ParseRoundingModeOp(SMLoc Start) {
1653  MCAsmParser &Parser = getParser();
1654  const AsmToken &Tok = Parser.getTok();
1655  // Eat "{" and mark the current place.
1656  const SMLoc consumedToken = consumeToken();
1657  if (Tok.isNot(AsmToken::Identifier))
1658  return ErrorOperand(Tok.getLoc(), "Expected an identifier after {");
1659  if (Tok.getIdentifier().startswith("r")){
1660  int rndMode = StringSwitch<int>(Tok.getIdentifier())
1665  .Default(-1);
1666  if (-1 == rndMode)
1667  return ErrorOperand(Tok.getLoc(), "Invalid rounding mode.");
1668  Parser.Lex(); // Eat "r*" of r*-sae
1669  if (!getLexer().is(AsmToken::Minus))
1670  return ErrorOperand(Tok.getLoc(), "Expected - at this point");
1671  Parser.Lex(); // Eat "-"
1672  Parser.Lex(); // Eat the sae
1673  if (!getLexer().is(AsmToken::RCurly))
1674  return ErrorOperand(Tok.getLoc(), "Expected } at this point");
1675  SMLoc End = Tok.getEndLoc();
1676  Parser.Lex(); // Eat "}"
1677  const MCExpr *RndModeOp =
1678  MCConstantExpr::create(rndMode, Parser.getContext());
1679  return X86Operand::CreateImm(RndModeOp, Start, End);
1680  }
1681  if(Tok.getIdentifier().equals("sae")){
1682  Parser.Lex(); // Eat the sae
1683  if (!getLexer().is(AsmToken::RCurly))
1684  return ErrorOperand(Tok.getLoc(), "Expected } at this point");
1685  Parser.Lex(); // Eat "}"
1686  return X86Operand::CreateToken("{sae}", consumedToken);
1687  }
1688  return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1689 }
1690 
1691 /// Parse the '.' operator.
1692 bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End) {
1693  const AsmToken &Tok = getTok();
1694  unsigned Offset;
1695 
1696  // Drop the optional '.'.
1697  StringRef DotDispStr = Tok.getString();
1698  if (DotDispStr.startswith("."))
1699  DotDispStr = DotDispStr.drop_front(1);
1700 
1701  // .Imm gets lexed as a real.
1702  if (Tok.is(AsmToken::Real)) {
1703  APInt DotDisp;
1704  DotDispStr.getAsInteger(10, DotDisp);
1705  Offset = DotDisp.getZExtValue();
1706  } else if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1707  std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1708  if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
1709  Offset))
1710  return Error(Tok.getLoc(), "Unable to lookup field reference!");
1711  } else
1712  return Error(Tok.getLoc(), "Unexpected token type!");
1713 
1714  // Eat the DotExpression and update End
1715  End = SMLoc::getFromPointer(DotDispStr.data());
1716  const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size();
1717  while (Tok.getLoc().getPointer() < DotExprEndLoc)
1718  Lex();
1719  SM.addImm(Offset);
1720  return false;
1721 }
1722 
1723 /// Parse the 'offset' operator. This operator is used to specify the
1724 /// location rather then the content of a variable.
1725 std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOffsetOfOperator() {
1726  MCAsmParser &Parser = getParser();
1727  const AsmToken &Tok = Parser.getTok();
1728  SMLoc OffsetOfLoc = Tok.getLoc();
1729  Parser.Lex(); // Eat offset.
1730 
1731  const MCExpr *Val;
1733  SMLoc Start = Tok.getLoc(), End;
1734  StringRef Identifier = Tok.getString();
1735  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
1736  /*Unevaluated=*/false, End))
1737  return nullptr;
1738 
1739  void *Decl = nullptr;
1740  // FIXME: MS evaluates "offset <Constant>" to the underlying integral
1742  return ErrorOperand(Start, "offset operator cannot yet handle constants");
1743  else if (Info.isKind(InlineAsmIdentifierInfo::IK_Var))
1744  Decl = Info.Var.Decl;
1745  // Don't emit the offset operator.
1746  InstInfo->AsmRewrites->emplace_back(AOK_Skip, OffsetOfLoc, 7);
1747 
1748  // The offset operator will have an 'r' constraint, thus we need to create
1749  // register operand to ensure proper matching. Just pick a GPR based on
1750  // the size of a pointer.
1751  bool Parse32 = is32BitMode() || Code16GCC;
1752  unsigned RegNo = is64BitMode() ? X86::RBX : (Parse32 ? X86::EBX : X86::BX);
1753 
1754  return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
1755  OffsetOfLoc, Identifier, Decl);
1756 }
1757 
1758 // Query a candidate string for being an Intel assembly operator
1759 // Report back its kind, or IOK_INVALID if does not evaluated as a known one
1760 unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
1762  .Cases("TYPE","type",IOK_TYPE)
1763  .Cases("SIZE","size",IOK_SIZE)
1764  .Cases("LENGTH","length",IOK_LENGTH)
1765  .Cases("OFFSET","offset",IOK_OFFSET)
1766  .Default(IOK_INVALID);
1767 }
1768 
1769 /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
1770 /// returns the number of elements in an array. It returns the value 1 for
1771 /// non-array variables. The SIZE operator returns the size of a C or C++
1772 /// variable. A variable's size is the product of its LENGTH and TYPE. The
1773 /// TYPE operator returns the size of a C or C++ type or variable. If the
1774 /// variable is an array, TYPE returns the size of a single element.
1775 unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) {
1776  MCAsmParser &Parser = getParser();
1777  const AsmToken &Tok = Parser.getTok();
1778  Parser.Lex(); // Eat operator.
1779 
1780  const MCExpr *Val = nullptr;
1782  SMLoc Start = Tok.getLoc(), End;
1783  StringRef Identifier = Tok.getString();
1784  if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
1785  /*Unevaluated=*/true, End))
1786  return 0;
1787 
1789  Error(Start, "unable to lookup expression");
1790  return 0;
1791  }
1792 
1793  unsigned CVal = 0;
1794  switch(OpKind) {
1795  default: llvm_unreachable("Unexpected operand kind!");
1796  case IOK_LENGTH: CVal = Info.Var.Length; break;
1797  case IOK_SIZE: CVal = Info.Var.Size; break;
1798  case IOK_TYPE: CVal = Info.Var.Type; break;
1799  }
1800 
1801  return CVal;
1802 }
1803 
1804 bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
1805  Size = StringSwitch<unsigned>(getTok().getString())
1806  .Cases("BYTE", "byte", 8)
1807  .Cases("WORD", "word", 16)
1808  .Cases("DWORD", "dword", 32)
1809  .Cases("FLOAT", "float", 32)
1810  .Cases("LONG", "long", 32)
1811  .Cases("FWORD", "fword", 48)
1812  .Cases("DOUBLE", "double", 64)
1813  .Cases("QWORD", "qword", 64)
1814  .Cases("MMWORD","mmword", 64)
1815  .Cases("XWORD", "xword", 80)
1816  .Cases("TBYTE", "tbyte", 80)
1817  .Cases("XMMWORD", "xmmword", 128)
1818  .Cases("YMMWORD", "ymmword", 256)
1819  .Cases("ZMMWORD", "zmmword", 512)
1820  .Default(0);
1821  if (Size) {
1822  const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word).
1823  if (!(Tok.getString().equals("PTR") || Tok.getString().equals("ptr")))
1824  return Error(Tok.getLoc(), "Expected 'PTR' or 'ptr' token!");
1825  Lex(); // Eat ptr.
1826  }
1827  return false;
1828 }
1829 
1830 std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
1831  MCAsmParser &Parser = getParser();
1832  const AsmToken &Tok = Parser.getTok();
1833  SMLoc Start, End;
1834 
1835  // FIXME: Offset operator
1836  // Should be handled as part of immediate expression, as other operators
1837  // Currently, only supported as a stand-alone operand
1838  if (isParsingInlineAsm())
1839  if (IdentifyIntelInlineAsmOperator(Tok.getString()) == IOK_OFFSET)
1840  return ParseIntelOffsetOfOperator();
1841 
1842  // Parse optional Size directive.
1843  unsigned Size;
1844  if (ParseIntelMemoryOperandSize(Size))
1845  return nullptr;
1846  bool PtrInOperand = bool(Size);
1847 
1848  Start = Tok.getLoc();
1849 
1850  // Rounding mode operand.
1851  if (getLexer().is(AsmToken::LCurly))
1852  return ParseRoundingModeOp(Start);
1853 
1854  // Register operand.
1855  unsigned RegNo = 0;
1856  if (Tok.is(AsmToken::Identifier) && !ParseRegister(RegNo, Start, End)) {
1857  if (RegNo == X86::RIP)
1858  return ErrorOperand(Start, "rip can only be used as a base register");
1859  // A Register followed by ':' is considered a segment override
1860  if (Tok.isNot(AsmToken::Colon))
1861  return !PtrInOperand ? X86Operand::CreateReg(RegNo, Start, End) :
1862  ErrorOperand(Start, "expected memory operand after 'ptr', "
1863  "found register operand instead");
1864  // An alleged segment override. check if we have a valid segment register
1865  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
1866  return ErrorOperand(Start, "invalid segment register");
1867  // Eat ':' and update Start location
1868  Start = Lex().getLoc();
1869  }
1870 
1871  // Immediates and Memory
1872  IntelExprStateMachine SM;
1873  if (ParseIntelExpression(SM, End))
1874  return nullptr;
1875 
1876  if (isParsingInlineAsm())
1877  RewriteIntelExpression(SM, Start, Tok.getLoc());
1878 
1879  int64_t Imm = SM.getImm();
1880  const MCExpr *Disp = SM.getSym();
1881  const MCExpr *ImmDisp = MCConstantExpr::create(Imm, getContext());
1882  if (Disp && Imm)
1883  Disp = MCBinaryExpr::createAdd(Disp, ImmDisp, getContext());
1884  if (!Disp)
1885  Disp = ImmDisp;
1886 
1887  // RegNo != 0 specifies a valid segment register,
1888  // and we are parsing a segment override
1889  if (!SM.isMemExpr() && !RegNo)
1890  return X86Operand::CreateImm(Disp, Start, End);
1891 
1892  StringRef ErrMsg;
1893  unsigned BaseReg = SM.getBaseReg();
1894  unsigned IndexReg = SM.getIndexReg();
1895  unsigned Scale = SM.getScale();
1896 
1897  if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&
1898  (IndexReg == X86::ESP || IndexReg == X86::RSP))
1899  std::swap(BaseReg, IndexReg);
1900 
1901  // If BaseReg is a vector register and IndexReg is not, swap them unless
1902  // Scale was specified in which case it would be an error.
1903  if (Scale == 0 &&
1904  !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
1905  X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
1906  X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&
1907  (X86MCRegisterClasses[X86::VR128XRegClassID].contains(BaseReg) ||
1908  X86MCRegisterClasses[X86::VR256XRegClassID].contains(BaseReg) ||
1909  X86MCRegisterClasses[X86::VR512RegClassID].contains(BaseReg)))
1910  std::swap(BaseReg, IndexReg);
1911 
1912  if (Scale != 0 &&
1913  X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))
1914  return ErrorOperand(Start, "16-bit addresses cannot have a scale");
1915 
1916  // If there was no explicit scale specified, change it to 1.
1917  if (Scale == 0)
1918  Scale = 1;
1919 
1920  // If this is a 16-bit addressing mode with the base and index in the wrong
1921  // order, swap them so CheckBaseRegAndIndexRegAndScale doesn't fail. It is
1922  // shared with att syntax where order matters.
1923  if ((BaseReg == X86::SI || BaseReg == X86::DI) &&
1924  (IndexReg == X86::BX || IndexReg == X86::BP))
1925  std::swap(BaseReg, IndexReg);
1926 
1927  if ((BaseReg || IndexReg) &&
1928  CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
1929  ErrMsg))
1930  return ErrorOperand(Start, ErrMsg);
1931  if (isParsingInlineAsm())
1932  return CreateMemForInlineAsm(RegNo, Disp, BaseReg, IndexReg,
1933  Scale, Start, End, Size, SM.getSymName(),
1934  SM.getIdentifierInfo());
1935  if (!(BaseReg || IndexReg || RegNo))
1936  return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size);
1937  return X86Operand::CreateMem(getPointerWidth(), RegNo, Disp,
1938  BaseReg, IndexReg, Scale, Start, End, Size);
1939 }
1940 
1941 std::unique_ptr<X86Operand> X86AsmParser::ParseATTOperand() {
1942  MCAsmParser &Parser = getParser();
1943  switch (getLexer().getKind()) {
1944  case AsmToken::Dollar: {
1945  // $42 or $ID -> immediate.
1946  SMLoc Start = Parser.getTok().getLoc(), End;
1947  Parser.Lex();
1948  const MCExpr *Val;
1949  // This is an immediate, so we should not parse a register. Do a precheck
1950  // for '%' to supercede intra-register parse errors.
1951  SMLoc L = Parser.getTok().getLoc();
1952  if (check(getLexer().is(AsmToken::Percent), L,
1953  "expected immediate expression") ||
1954  getParser().parseExpression(Val, End) ||
1955  check(isa<X86MCExpr>(Val), L, "expected immediate expression"))
1956  return nullptr;
1957  return X86Operand::CreateImm(Val, Start, End);
1958  }
1959  case AsmToken::LCurly: {
1960  SMLoc Start = Parser.getTok().getLoc();
1961  return ParseRoundingModeOp(Start);
1962  }
1963  default: {
1964  // This a memory operand or a register. We have some parsing complications
1965  // as a '(' may be part of an immediate expression or the addressing mode
1966  // block. This is complicated by the fact that an assembler-level variable
1967  // may refer either to a register or an immediate expression.
1968 
1969  SMLoc Loc = Parser.getTok().getLoc(), EndLoc;
1970  const MCExpr *Expr = nullptr;
1971  unsigned Reg = 0;
1972  if (getLexer().isNot(AsmToken::LParen)) {
1973  // No '(' so this is either a displacement expression or a register.
1974  if (Parser.parseExpression(Expr, EndLoc))
1975  return nullptr;
1976  if (auto *RE = dyn_cast<X86MCExpr>(Expr)) {
1977  // Segment Register. Reset Expr and copy value to register.
1978  Expr = nullptr;
1979  Reg = RE->getRegNo();
1980 
1981  // Sanity check register.
1982  if (Reg == X86::EIZ || Reg == X86::RIZ)
1983  return ErrorOperand(
1984  Loc, "%eiz and %riz can only be used as index registers",
1985  SMRange(Loc, EndLoc));
1986  if (Reg == X86::RIP)
1987  return ErrorOperand(Loc, "%rip can only be used as a base register",
1988  SMRange(Loc, EndLoc));
1989  // Return register that are not segment prefixes immediately.
1990  if (!Parser.parseOptionalToken(AsmToken::Colon))
1991  return X86Operand::CreateReg(Reg, Loc, EndLoc);
1992  if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(Reg))
1993  return ErrorOperand(Loc, "invalid segment register");
1994  }
1995  }
1996  // This is a Memory operand.
1997  return ParseMemOperand(Reg, Expr, Loc, EndLoc);
1998  }
1999  }
2000 }
2001 
2002 // true on failure, false otherwise
2003 // If no {z} mark was found - Parser doesn't advance
2004 bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
2005  const SMLoc &StartLoc) {
2006  MCAsmParser &Parser = getParser();
2007  // Assuming we are just pass the '{' mark, quering the next token
2008  // Searched for {z}, but none was found. Return false, as no parsing error was
2009  // encountered
2010  if (!(getLexer().is(AsmToken::Identifier) &&
2011  (getLexer().getTok().getIdentifier() == "z")))
2012  return false;
2013  Parser.Lex(); // Eat z
2014  // Query and eat the '}' mark
2015  if (!getLexer().is(AsmToken::RCurly))
2016  return Error(getLexer().getLoc(), "Expected } at this point");
2017  Parser.Lex(); // Eat '}'
2018  // Assign Z with the {z} mark opernad
2019  Z = X86Operand::CreateToken("{z}", StartLoc);
2020  return false;
2021 }
2022 
2023 // true on failure, false otherwise
2024 bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
2025  const MCParsedAsmOperand &Op) {
2026  MCAsmParser &Parser = getParser();
2027  if (getLexer().is(AsmToken::LCurly)) {
2028  // Eat "{" and mark the current place.
2029  const SMLoc consumedToken = consumeToken();
2030  // Distinguish {1to<NUM>} from {%k<NUM>}.
2031  if(getLexer().is(AsmToken::Integer)) {
2032  // Parse memory broadcasting ({1to<NUM>}).
2033  if (getLexer().getTok().getIntVal() != 1)
2034  return TokError("Expected 1to<NUM> at this point");
2035  Parser.Lex(); // Eat "1" of 1to8
2036  if (!getLexer().is(AsmToken::Identifier) ||
2037  !getLexer().getTok().getIdentifier().startswith("to"))
2038  return TokError("Expected 1to<NUM> at this point");
2039  // Recognize only reasonable suffixes.
2040  const char *BroadcastPrimitive =
2041  StringSwitch<const char*>(getLexer().getTok().getIdentifier())
2042  .Case("to2", "{1to2}")
2043  .Case("to4", "{1to4}")
2044  .Case("to8", "{1to8}")
2045  .Case("to16", "{1to16}")
2046  .Default(nullptr);
2047  if (!BroadcastPrimitive)
2048  return TokError("Invalid memory broadcast primitive.");
2049  Parser.Lex(); // Eat "toN" of 1toN
2050  if (!getLexer().is(AsmToken::RCurly))
2051  return TokError("Expected } at this point");
2052  Parser.Lex(); // Eat "}"
2053  Operands.push_back(X86Operand::CreateToken(BroadcastPrimitive,
2054  consumedToken));
2055  // No AVX512 specific primitives can pass
2056  // after memory broadcasting, so return.
2057  return false;
2058  } else {
2059  // Parse either {k}{z}, {z}{k}, {k} or {z}
2060  // last one have no meaning, but GCC accepts it
2061  // Currently, we're just pass a '{' mark
2062  std::unique_ptr<X86Operand> Z;
2063  if (ParseZ(Z, consumedToken))
2064  return true;
2065  // Reaching here means that parsing of the allegadly '{z}' mark yielded
2066  // no errors.
2067  // Query for the need of further parsing for a {%k<NUM>} mark
2068  if (!Z || getLexer().is(AsmToken::LCurly)) {
2069  SMLoc StartLoc = Z ? consumeToken() : consumedToken;
2070  // Parse an op-mask register mark ({%k<NUM>}), which is now to be
2071  // expected
2072  unsigned RegNo;
2073  SMLoc RegLoc;
2074  if (!ParseRegister(RegNo, RegLoc, StartLoc) &&
2075  X86MCRegisterClasses[X86::VK1RegClassID].contains(RegNo)) {
2076  if (RegNo == X86::K0)
2077  return Error(RegLoc, "Register k0 can't be used as write mask");
2078  if (!getLexer().is(AsmToken::RCurly))
2079  return Error(getLexer().getLoc(), "Expected } at this point");
2080  Operands.push_back(X86Operand::CreateToken("{", StartLoc));
2081  Operands.push_back(
2082  X86Operand::CreateReg(RegNo, StartLoc, StartLoc));
2083  Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
2084  } else
2085  return Error(getLexer().getLoc(),
2086  "Expected an op-mask register at this point");
2087  // {%k<NUM>} mark is found, inquire for {z}
2088  if (getLexer().is(AsmToken::LCurly) && !Z) {
2089  // Have we've found a parsing error, or found no (expected) {z} mark
2090  // - report an error
2091  if (ParseZ(Z, consumeToken()) || !Z)
2092  return Error(getLexer().getLoc(),
2093  "Expected a {z} mark at this point");
2094 
2095  }
2096  // '{z}' on its own is meaningless, hence should be ignored.
2097  // on the contrary - have it been accompanied by a K register,
2098  // allow it.
2099  if (Z)
2100  Operands.push_back(std::move(Z));
2101  }
2102  }
2103  }
2104  return false;
2105 }
2106 
2107 /// ParseMemOperand: 'seg : disp(basereg, indexreg, scale)'. The '%ds:' prefix
2108 /// has already been parsed if present. disp may be provided as well.
2109 std::unique_ptr<X86Operand> X86AsmParser::ParseMemOperand(unsigned SegReg,
2110  const MCExpr *&Disp,
2111  const SMLoc &StartLoc,
2112  SMLoc &EndLoc) {
2113  MCAsmParser &Parser = getParser();
2114  SMLoc Loc;
2115  // Based on the initial passed values, we may be in any of these cases, we are
2116  // in one of these cases (with current position (*)):
2117 
2118  // 1. seg : * disp (base-index-scale-expr)
2119  // 2. seg : *(disp) (base-index-scale-expr)
2120  // 3. seg : *(base-index-scale-expr)
2121  // 4. disp *(base-index-scale-expr)
2122  // 5. *(disp) (base-index-scale-expr)
2123  // 6. *(base-index-scale-expr)
2124  // 7. disp *
2125  // 8. *(disp)
2126 
2127  // If we do not have an displacement yet, check if we're in cases 4 or 6 by
2128  // checking if the first object after the parenthesis is a register (or an
2129  // identifier referring to a register) and parse the displacement or default
2130  // to 0 as appropriate.
2131  auto isAtMemOperand = [this]() {
2132  if (this->getLexer().isNot(AsmToken::LParen))
2133  return false;
2134  AsmToken Buf[2];
2135  StringRef Id;
2136  auto TokCount = this->getLexer().peekTokens(Buf, true);
2137  if (TokCount == 0)
2138  return false;
2139  switch (Buf[0].getKind()) {
2140  case AsmToken::Percent:
2141  case AsmToken::Comma:
2142  return true;
2143  // These lower cases are doing a peekIdentifier.
2144  case AsmToken::At:
2145  case AsmToken::Dollar:
2146  if ((TokCount > 1) &&
2147  (Buf[1].is(AsmToken::Identifier) || Buf[1].is(AsmToken::String)) &&
2148  (Buf[0].getLoc().getPointer() + 1 == Buf[1].getLoc().getPointer()))
2149  Id = StringRef(Buf[0].getLoc().getPointer(),
2150  Buf[1].getIdentifier().size() + 1);
2151  break;
2152  case AsmToken::Identifier:
2153  case AsmToken::String:
2154  Id = Buf[0].getIdentifier();
2155  break;
2156  default:
2157  return false;
2158  }
2159  // We have an ID. Check if it is bound to a register.
2160  if (!Id.empty()) {
2161  MCSymbol *Sym = this->getContext().getOrCreateSymbol(Id);
2162  if (Sym->isVariable()) {
2163  auto V = Sym->getVariableValue(/*SetUsed*/ false);
2164  return isa<X86MCExpr>(V);
2165  }
2166  }
2167  return false;
2168  };
2169 
2170  if (!Disp) {
2171  // Parse immediate if we're not at a mem operand yet.
2172  if (!isAtMemOperand()) {
2173  if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(Disp, EndLoc))
2174  return nullptr;
2175  assert(!isa<X86MCExpr>(Disp) && "Expected non-register here.");
2176  } else {
2177  // Disp is implicitly zero if we haven't parsed it yet.
2178  Disp = MCConstantExpr::create(0, Parser.getContext());
2179  }
2180  }
2181 
2182  // We are now either at the end of the operand or at the '(' at the start of a
2183  // base-index-scale-expr.
2184 
2185  if (!parseOptionalToken(AsmToken::LParen)) {
2186  if (SegReg == 0)
2187  return X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc);
2188  return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
2189  StartLoc, EndLoc);
2190  }
2191 
2192  // If we reached here, then eat the '(' and Process
2193  // the rest of the memory operand.
2194  unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
2195  SMLoc BaseLoc = getLexer().getLoc();
2196  const MCExpr *E;
2197  StringRef ErrMsg;
2198 
2199  // Parse BaseReg if one is provided.
2200  if (getLexer().isNot(AsmToken::Comma) && getLexer().isNot(AsmToken::RParen)) {
2201  if (Parser.parseExpression(E, EndLoc) ||
2202  check(!isa<X86MCExpr>(E), BaseLoc, "expected register here"))
2203  return nullptr;
2204 
2205  // Sanity check register.
2206  BaseReg = cast<X86MCExpr>(E)->getRegNo();
2207  if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)
2208  return ErrorOperand(BaseLoc,
2209  "eiz and riz can only be used as index registers",
2210  SMRange(BaseLoc, EndLoc));
2211  }
2212 
2213  if (parseOptionalToken(AsmToken::Comma)) {
2214  // Following the comma we should have either an index register, or a scale
2215  // value. We don't support the later form, but we want to parse it
2216  // correctly.
2217  //
2218  // Even though it would be completely consistent to support syntax like
2219  // "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
2220  if (getLexer().isNot(AsmToken::RParen)) {
2221  if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(E, EndLoc))
2222  return nullptr;
2223 
2224  if (!isa<X86MCExpr>(E)) {
2225  // We've parsed an unexpected Scale Value instead of an index
2226  // register. Interpret it as an absolute.
2227  int64_t ScaleVal;
2228  if (!E->evaluateAsAbsolute(ScaleVal, getStreamer().getAssemblerPtr()))
2229  return ErrorOperand(Loc, "expected absolute expression");
2230  if (ScaleVal != 1)
2231  Warning(Loc, "scale factor without index register is ignored");
2232  Scale = 1;
2233  } else { // IndexReg Found.
2234  IndexReg = cast<X86MCExpr>(E)->getRegNo();
2235 
2236  if (BaseReg == X86::RIP)
2237  return ErrorOperand(
2238  Loc, "%rip as base register can not have an index register");
2239  if (IndexReg == X86::RIP)
2240  return ErrorOperand(Loc, "%rip is not allowed as an index register");
2241 
2242  if (parseOptionalToken(AsmToken::Comma)) {
2243  // Parse the scale amount:
2244  // ::= ',' [scale-expression]
2245 
2246  // A scale amount without an index is ignored.
2247  if (getLexer().isNot(AsmToken::RParen)) {
2248  int64_t ScaleVal;
2249  if (Parser.parseTokenLoc(Loc) ||
2250  Parser.parseAbsoluteExpression(ScaleVal))
2251  return ErrorOperand(Loc, "expected scale expression");
2252  Scale = (unsigned)ScaleVal;
2253  // Validate the scale amount.
2254  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2255  Scale != 1)
2256  return ErrorOperand(Loc,
2257  "scale factor in 16-bit address must be 1");
2258  if (checkScale(Scale, ErrMsg))
2259  return ErrorOperand(Loc, ErrMsg);
2260  }
2261  }
2262  }
2263  }
2264  }
2265 
2266  // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
2267  if (parseToken(AsmToken::RParen, "unexpected token in memory operand"))
2268  return nullptr;
2269 
2270  // This is to support otherwise illegal operand (%dx) found in various
2271  // unofficial manuals examples (e.g. "out[s]?[bwl]? %al, (%dx)") and must now
2272  // be supported. Mark such DX variants separately fix only in special cases.
2273  if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&
2274  isa<MCConstantExpr>(Disp) && cast<MCConstantExpr>(Disp)->getValue() == 0)
2275  return X86Operand::CreateDXReg(BaseLoc, BaseLoc);
2276 
2277  if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
2278  ErrMsg))
2279  return ErrorOperand(BaseLoc, ErrMsg);
2280 
2281  if (SegReg || BaseReg || IndexReg)
2282  return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
2283  IndexReg, Scale, StartLoc, EndLoc);
2284  return X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc);
2285 }
2286 
2287 // Parse either a standard primary expression or a register.
2288 bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
2289  MCAsmParser &Parser = getParser();
2290  // See if this is a register first.
2291  if (getTok().is(AsmToken::Percent) ||
2292  (isParsingIntelSyntax() && getTok().is(AsmToken::Identifier) &&
2293  MatchRegisterName(Parser.getTok().getString()))) {
2294  SMLoc StartLoc = Parser.getTok().getLoc();
2295  unsigned RegNo;
2296  if (ParseRegister(RegNo, StartLoc, EndLoc))
2297  return true;
2298  Res = X86MCExpr::create(RegNo, Parser.getContext());
2299  return false;
2300  }
2301  return Parser.parsePrimaryExpr(Res, EndLoc);
2302 }
2303 
2304 bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
2305  SMLoc NameLoc, OperandVector &Operands) {
2306  MCAsmParser &Parser = getParser();
2307  InstInfo = &Info;
2308  StringRef PatchedName = Name;
2309 
2310  if ((Name.equals("jmp") || Name.equals("jc") || Name.equals("jz")) &&
2311  isParsingIntelSyntax() && isParsingInlineAsm()) {
2312  StringRef NextTok = Parser.getTok().getString();
2313  if (NextTok == "short") {
2314  SMLoc NameEndLoc =
2315  NameLoc.getFromPointer(NameLoc.getPointer() + Name.size());
2316  // Eat the short keyword
2317  Parser.Lex();
2318  // MS ignores the short keyword, it determines the jmp type based
2319  // on the distance of the label
2320  InstInfo->AsmRewrites->emplace_back(AOK_Skip, NameEndLoc,
2321  NextTok.size() + 1);
2322  }
2323  }
2324 
2325  // FIXME: Hack to recognize setneb as setne.
2326  if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
2327  PatchedName != "setb" && PatchedName != "setnb")
2328  PatchedName = PatchedName.substr(0, Name.size()-1);
2329 
2330  // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
2331  if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
2332  (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
2333  PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
2334  bool IsVCMP = PatchedName[0] == 'v';
2335  unsigned CCIdx = IsVCMP ? 4 : 3;
2336  unsigned ComparisonCode = StringSwitch<unsigned>(
2337  PatchedName.slice(CCIdx, PatchedName.size() - 2))
2338  .Case("eq", 0x00)
2339  .Case("eq_oq", 0x00)
2340  .Case("lt", 0x01)
2341  .Case("lt_os", 0x01)
2342  .Case("le", 0x02)
2343  .Case("le_os", 0x02)
2344  .Case("unord", 0x03)
2345  .Case("unord_q", 0x03)
2346  .Case("neq", 0x04)
2347  .Case("neq_uq", 0x04)
2348  .Case("nlt", 0x05)
2349  .Case("nlt_us", 0x05)
2350  .Case("nle", 0x06)
2351  .Case("nle_us", 0x06)
2352  .Case("ord", 0x07)
2353  .Case("ord_q", 0x07)
2354  /* AVX only from here */
2355  .Case("eq_uq", 0x08)
2356  .Case("nge", 0x09)
2357  .Case("nge_us", 0x09)
2358  .Case("ngt", 0x0A)
2359  .Case("ngt_us", 0x0A)
2360  .Case("false", 0x0B)
2361  .Case("false_oq", 0x0B)
2362  .Case("neq_oq", 0x0C)
2363  .Case("ge", 0x0D)
2364  .Case("ge_os", 0x0D)
2365  .Case("gt", 0x0E)
2366  .Case("gt_os", 0x0E)
2367  .Case("true", 0x0F)
2368  .Case("true_uq", 0x0F)
2369  .Case("eq_os", 0x10)
2370  .Case("lt_oq", 0x11)
2371  .Case("le_oq", 0x12)
2372  .Case("unord_s", 0x13)
2373  .Case("neq_us", 0x14)
2374  .Case("nlt_uq", 0x15)
2375  .Case("nle_uq", 0x16)
2376  .Case("ord_s", 0x17)
2377  .Case("eq_us", 0x18)
2378  .Case("nge_uq", 0x19)
2379  .Case("ngt_uq", 0x1A)
2380  .Case("false_os", 0x1B)
2381  .Case("neq_os", 0x1C)
2382  .Case("ge_oq", 0x1D)
2383  .Case("gt_oq", 0x1E)
2384  .Case("true_us", 0x1F)
2385  .Default(~0U);
2386  if (ComparisonCode != ~0U && (IsVCMP || ComparisonCode < 8)) {
2387 
2388  Operands.push_back(X86Operand::CreateToken(PatchedName.slice(0, CCIdx),
2389  NameLoc));
2390 
2391  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
2392  getParser().getContext());
2393  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2394 
2395  PatchedName = PatchedName.substr(PatchedName.size() - 2);
2396  }
2397  }
2398 
2399  // FIXME: Hack to recognize vpcmp<comparison code>{ub,uw,ud,uq,b,w,d,q}.
2400  if (PatchedName.startswith("vpcmp") &&
2401  (PatchedName.endswith("b") || PatchedName.endswith("w") ||
2402  PatchedName.endswith("d") || PatchedName.endswith("q"))) {
2403  unsigned CCIdx = PatchedName.drop_back().back() == 'u' ? 2 : 1;
2404  unsigned ComparisonCode = StringSwitch<unsigned>(
2405  PatchedName.slice(5, PatchedName.size() - CCIdx))
2406  .Case("eq", 0x0) // Only allowed on unsigned. Checked below.
2407  .Case("lt", 0x1)
2408  .Case("le", 0x2)
2409  //.Case("false", 0x3) // Not a documented alias.
2410  .Case("neq", 0x4)
2411  .Case("nlt", 0x5)
2412  .Case("nle", 0x6)
2413  //.Case("true", 0x7) // Not a documented alias.
2414  .Default(~0U);
2415  if (ComparisonCode != ~0U && (ComparisonCode != 0 || CCIdx == 2)) {
2416  Operands.push_back(X86Operand::CreateToken("vpcmp", NameLoc));
2417 
2418  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
2419  getParser().getContext());
2420  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2421 
2422  PatchedName = PatchedName.substr(PatchedName.size() - CCIdx);
2423  }
2424  }
2425 
2426  // FIXME: Hack to recognize vpcom<comparison code>{ub,uw,ud,uq,b,w,d,q}.
2427  if (PatchedName.startswith("vpcom") &&
2428  (PatchedName.endswith("b") || PatchedName.endswith("w") ||
2429  PatchedName.endswith("d") || PatchedName.endswith("q"))) {
2430  unsigned CCIdx = PatchedName.drop_back().back() == 'u' ? 2 : 1;
2431  unsigned ComparisonCode = StringSwitch<unsigned>(
2432  PatchedName.slice(5, PatchedName.size() - CCIdx))
2433  .Case("lt", 0x0)
2434  .Case("le", 0x1)
2435  .Case("gt", 0x2)
2436  .Case("ge", 0x3)
2437  .Case("eq", 0x4)
2438  .Case("neq", 0x5)
2439  .Case("false", 0x6)
2440  .Case("true", 0x7)
2441  .Default(~0U);
2442  if (ComparisonCode != ~0U) {
2443  Operands.push_back(X86Operand::CreateToken("vpcom", NameLoc));
2444 
2445  const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
2446  getParser().getContext());
2447  Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2448 
2449  PatchedName = PatchedName.substr(PatchedName.size() - CCIdx);
2450  }
2451  }
2452 
2453 
2454  // Determine whether this is an instruction prefix.
2455  // FIXME:
2456  // Enhance prefixes integrity robustness. for example, following forms
2457  // are currently tolerated:
2458  // repz repnz <insn> ; GAS errors for the use of two similar prefixes
2459  // lock addq %rax, %rbx ; Destination operand must be of memory type
2460  // xacquire <insn> ; xacquire must be accompanied by 'lock'
2462  .Cases("rex64", "data32", "data16", true)
2463  .Cases("xacquire", "xrelease", true)
2464  .Cases("acquire", "release", isParsingIntelSyntax())
2465  .Default(false);
2466 
2467  auto isLockRepeatNtPrefix = [](StringRef N) {
2468  return StringSwitch<bool>(N)
2469  .Cases("lock", "rep", "repe", "repz", "repne", "repnz", "notrack", true)
2470  .Default(false);
2471  };
2472 
2473  bool CurlyAsEndOfStatement = false;
2474 
2475  unsigned Flags = X86::IP_NO_PREFIX;
2476  while (isLockRepeatNtPrefix(Name.lower())) {
2477  unsigned Prefix =
2479  .Cases("lock", "lock", X86::IP_HAS_LOCK)
2480  .Cases("rep", "repe", "repz", X86::IP_HAS_REPEAT)
2481  .Cases("repne", "repnz", X86::IP_HAS_REPEAT_NE)
2482  .Cases("notrack", "notrack", X86::IP_HAS_NOTRACK)
2483  .Default(X86::IP_NO_PREFIX); // Invalid prefix (impossible)
2484  Flags |= Prefix;
2485  if (getLexer().is(AsmToken::EndOfStatement)) {
2486  // We don't have real instr with the given prefix
2487  // let's use the prefix as the instr.
2488  // TODO: there could be several prefixes one after another
2489  Flags = X86::IP_NO_PREFIX;
2490  break;
2491  }
2492  Name = Parser.getTok().getString();
2493  Parser.Lex(); // eat the prefix
2494  // Hack: we could have something like "rep # some comment" or
2495  // "lock; cmpxchg16b $1" or "lock\0A\09incl" or "lock/incl"
2496  while (Name.startswith(";") || Name.startswith("\n") ||
2497  Name.startswith("#") || Name.startswith("\t") ||
2498  Name.startswith("/")) {
2499  Name = Parser.getTok().getString();
2500  Parser.Lex(); // go to next prefix or instr
2501  }
2502  }
2503 
2504  if (Flags)
2505  PatchedName = Name;
2506 
2507  // Hacks to handle 'data16' and 'data32'
2508  if (PatchedName == "data16" && is16BitMode()) {
2509  return Error(NameLoc, "redundant data16 prefix");
2510  }
2511  if (PatchedName == "data32") {
2512  if (is32BitMode())
2513  return Error(NameLoc, "redundant data32 prefix");
2514  if (is64BitMode())
2515  return Error(NameLoc, "'data32' is not supported in 64-bit mode");
2516  // Hack to 'data16' for the table lookup.
2517  PatchedName = "data16";
2518  }
2519 
2520  Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
2521 
2522  // This does the actual operand parsing. Don't parse any more if we have a
2523  // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
2524  // just want to parse the "lock" as the first instruction and the "incl" as
2525  // the next one.
2526  if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
2527  // Parse '*' modifier.
2528  if (getLexer().is(AsmToken::Star))
2529  Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
2530 
2531  // Read the operands.
2532  while(1) {
2533  if (std::unique_ptr<X86Operand> Op = ParseOperand()) {
2534  Operands.push_back(std::move(Op));
2535  if (HandleAVX512Operand(Operands, *Operands.back()))
2536  return true;
2537  } else {
2538  return true;
2539  }
2540  // check for comma and eat it
2541  if (getLexer().is(AsmToken::Comma))
2542  Parser.Lex();
2543  else
2544  break;
2545  }
2546 
2547  // In MS inline asm curly braces mark the beginning/end of a block,
2548  // therefore they should be interepreted as end of statement
2549  CurlyAsEndOfStatement =
2550  isParsingIntelSyntax() && isParsingInlineAsm() &&
2551  (getLexer().is(AsmToken::LCurly) || getLexer().is(AsmToken::RCurly));
2552  if (getLexer().isNot(AsmToken::EndOfStatement) && !CurlyAsEndOfStatement)
2553  return TokError("unexpected token in argument list");
2554  }
2555 
2556  // Consume the EndOfStatement or the prefix separator Slash
2557  if (getLexer().is(AsmToken::EndOfStatement) ||
2558  (isPrefix && getLexer().is(AsmToken::Slash)))
2559  Parser.Lex();
2560  else if (CurlyAsEndOfStatement)
2561  // Add an actual EndOfStatement before the curly brace
2562  Info.AsmRewrites->emplace_back(AOK_EndOfStatement,
2563  getLexer().getTok().getLoc(), 0);
2564 
2565  // This is for gas compatibility and cannot be done in td.
2566  // Adding "p" for some floating point with no argument.
2567  // For example: fsub --> fsubp
2568  bool IsFp =
2569  Name == "fsub" || Name == "fdiv" || Name == "fsubr" || Name == "fdivr";
2570  if (IsFp && Operands.size() == 1) {
2571  const char *Repl = StringSwitch<const char *>(Name)
2572  .Case("fsub", "fsubp")
2573  .Case("fdiv", "fdivp")
2574  .Case("fsubr", "fsubrp")
2575  .Case("fdivr", "fdivrp");
2576  static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl);
2577  }
2578 
2579  // Moving a 32 or 16 bit value into a segment register has the same
2580  // behavior. Modify such instructions to always take shorter form.
2581  if ((Name == "mov" || Name == "movw" || Name == "movl") &&
2582  (Operands.size() == 3)) {
2583  X86Operand &Op1 = (X86Operand &)*Operands[1];
2584  X86Operand &Op2 = (X86Operand &)*Operands[2];
2585  SMLoc Loc = Op1.getEndLoc();
2586  if (Op1.isReg() && Op2.isReg() &&
2587  X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(
2588  Op2.getReg()) &&
2589  (X86MCRegisterClasses[X86::GR16RegClassID].contains(Op1.getReg()) ||
2590  X86MCRegisterClasses[X86::GR32RegClassID].contains(Op1.getReg()))) {
2591  // Change instruction name to match new instruction.
2592  if (Name != "mov" && Name[3] == (is16BitMode() ? 'l' : 'w')) {
2593  Name = is16BitMode() ? "movw" : "movl";
2594  Operands[0] = X86Operand::CreateToken(Name, NameLoc);
2595  }
2596  // Select the correct equivalent 16-/32-bit source register.
2597  unsigned Reg =
2598  getX86SubSuperRegisterOrZero(Op1.getReg(), is16BitMode() ? 16 : 32);
2599  Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc);
2600  }
2601  }
2602 
2603  // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
2604  // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
2605  // documented form in various unofficial manuals, so a lot of code uses it.
2606  if ((Name == "outb" || Name == "outsb" || Name == "outw" || Name == "outsw" ||
2607  Name == "outl" || Name == "outsl" || Name == "out" || Name == "outs") &&
2608  Operands.size() == 3) {
2609  X86Operand &Op = (X86Operand &)*Operands.back();
2610  if (Op.isDXReg())
2611  Operands.back() = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
2612  Op.getEndLoc());
2613  }
2614  // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al".
2615  if ((Name == "inb" || Name == "insb" || Name == "inw" || Name == "insw" ||
2616  Name == "inl" || Name == "insl" || Name == "in" || Name == "ins") &&
2617  Operands.size() == 3) {
2618  X86Operand &Op = (X86Operand &)*Operands[1];
2619  if (Op.isDXReg())
2620  Operands[1] = X86Operand::CreateReg(X86::DX, Op.getStartLoc(),
2621  Op.getEndLoc());
2622  }
2623 
2625  bool HadVerifyError = false;
2626 
2627  // Append default arguments to "ins[bwld]"
2628  if (Name.startswith("ins") &&
2629  (Operands.size() == 1 || Operands.size() == 3) &&
2630  (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
2631  Name == "ins")) {
2632 
2633  AddDefaultSrcDestOperands(TmpOperands,
2634  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),
2635  DefaultMemDIOperand(NameLoc));
2636  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2637  }
2638 
2639  // Append default arguments to "outs[bwld]"
2640  if (Name.startswith("outs") &&
2641  (Operands.size() == 1 || Operands.size() == 3) &&
2642  (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
2643  Name == "outsd" || Name == "outs")) {
2644  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
2645  X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
2646  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2647  }
2648 
2649  // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
2650  // values of $SIREG according to the mode. It would be nice if this
2651  // could be achieved with InstAlias in the tables.
2652  if (Name.startswith("lods") &&
2653  (Operands.size() == 1 || Operands.size() == 2) &&
2654  (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
2655  Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) {
2656  TmpOperands.push_back(DefaultMemSIOperand(NameLoc));
2657  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2658  }
2659 
2660  // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
2661  // values of $DIREG according to the mode. It would be nice if this
2662  // could be achieved with InstAlias in the tables.
2663  if (Name.startswith("stos") &&
2664  (Operands.size() == 1 || Operands.size() == 2) &&
2665  (Name == "stos" || Name == "stosb" || Name == "stosw" ||
2666  Name == "stosl" || Name == "stosd" || Name == "stosq")) {
2667  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
2668  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2669  }
2670 
2671  // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
2672  // values of $DIREG according to the mode. It would be nice if this
2673  // could be achieved with InstAlias in the tables.
2674  if (Name.startswith("scas") &&
2675  (Operands.size() == 1 || Operands.size() == 2) &&
2676  (Name == "scas" || Name == "scasb" || Name == "scasw" ||
2677  Name == "scasl" || Name == "scasd" || Name == "scasq")) {
2678  TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
2679  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2680  }
2681 
2682  // Add default SI and DI operands to "cmps[bwlq]".
2683  if (Name.startswith("cmps") &&
2684  (Operands.size() == 1 || Operands.size() == 3) &&
2685  (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
2686  Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
2687  AddDefaultSrcDestOperands(TmpOperands, DefaultMemDIOperand(NameLoc),
2688  DefaultMemSIOperand(NameLoc));
2689  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2690  }
2691 
2692  // Add default SI and DI operands to "movs[bwlq]".
2693  if (((Name.startswith("movs") &&
2694  (Name == "movs" || Name == "movsb" || Name == "movsw" ||
2695  Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
2696  (Name.startswith("smov") &&
2697  (Name == "smov" || Name == "smovb" || Name == "smovw" ||
2698  Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
2699  (Operands.size() == 1 || Operands.size() == 3)) {
2700  if (Name == "movsd" && Operands.size() == 1 && !isParsingIntelSyntax())
2701  Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
2702  AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
2703  DefaultMemDIOperand(NameLoc));
2704  HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2705  }
2706 
2707  // Check if we encountered an error for one the string insturctions
2708  if (HadVerifyError) {
2709  return HadVerifyError;
2710  }
2711 
2712  // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
2713  // "shift <op>".
2714  if ((Name.startswith("shr") || Name.startswith("sar") ||
2715  Name.startswith("shl") || Name.startswith("sal") ||
2716  Name.startswith("rcl") || Name.startswith("rcr") ||
2717  Name.startswith("rol") || Name.startswith("ror")) &&
2718  Operands.size() == 3) {
2719  if (isParsingIntelSyntax()) {
2720  // Intel syntax
2721  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[2]);
2722  if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) &&
2723  cast<MCConstantExpr>(Op1.getImm())->getValue() == 1)
2724  Operands.pop_back();
2725  } else {
2726  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2727  if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) &&
2728  cast<MCConstantExpr>(Op1.getImm())->getValue() == 1)
2729  Operands.erase(Operands.begin() + 1);
2730  }
2731  }
2732 
2733  // Transforms "int $3" into "int3" as a size optimization. We can't write an
2734  // instalias with an immediate operand yet.
2735  if (Name == "int" && Operands.size() == 2) {
2736  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2737  if (Op1.isImm())
2738  if (auto *CE = dyn_cast<MCConstantExpr>(Op1.getImm()))
2739  if (CE->getValue() == 3) {
2740  Operands.erase(Operands.begin() + 1);
2741  static_cast<X86Operand &>(*Operands[0]).setTokenValue("int3");
2742  }
2743  }
2744 
2745  // Transforms "xlat mem8" into "xlatb"
2746  if ((Name == "xlat" || Name == "xlatb") && Operands.size() == 2) {
2747  X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2748  if (Op1.isMem8()) {
2749  Warning(Op1.getStartLoc(), "memory operand is only for determining the "
2750  "size, (R|E)BX will be used for the location");
2751  Operands.pop_back();
2752  static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb");
2753  }
2754  }
2755 
2756  if (Flags)
2757  Operands.push_back(X86Operand::CreatePrefix(Flags, NameLoc, NameLoc));
2758  return false;
2759 }
2760 
2761 bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
2762  return false;
2763 }
2764 
2765 bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
2766  const MCRegisterInfo *MRI = getContext().getRegisterInfo();
2767 
2768  switch (Inst.getOpcode()) {
2769  case X86::VGATHERDPDYrm:
2770  case X86::VGATHERDPDrm:
2771  case X86::VGATHERDPSYrm:
2772  case X86::VGATHERDPSrm:
2773  case X86::VGATHERQPDYrm:
2774  case X86::VGATHERQPDrm:
2775  case X86::VGATHERQPSYrm:
2776  case X86::VGATHERQPSrm:
2777  case X86::VPGATHERDDYrm:
2778  case X86::VPGATHERDDrm:
2779  case X86::VPGATHERDQYrm:
2780  case X86::VPGATHERDQrm:
2781  case X86::VPGATHERQDYrm:
2782  case X86::VPGATHERQDrm:
2783  case X86::VPGATHERQQYrm:
2784  case X86::VPGATHERQQrm: {
2785  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
2786  unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg());
2787  unsigned Index =
2789  if (Dest == Mask || Dest == Index || Mask == Index)
2790  return Warning(Ops[0]->getStartLoc(), "mask, index, and destination "
2791  "registers should be distinct");
2792  break;
2793  }
2794  case X86::VGATHERDPDZ128rm:
2795  case X86::VGATHERDPDZ256rm:
2796  case X86::VGATHERDPDZrm:
2797  case X86::VGATHERDPSZ128rm:
2798  case X86::VGATHERDPSZ256rm:
2799  case X86::VGATHERDPSZrm:
2800  case X86::VGATHERQPDZ128rm:
2801  case X86::VGATHERQPDZ256rm:
2802  case X86::VGATHERQPDZrm:
2803  case X86::VGATHERQPSZ128rm:
2804  case X86::VGATHERQPSZ256rm:
2805  case X86::VGATHERQPSZrm:
2806  case X86::VPGATHERDDZ128rm:
2807  case X86::VPGATHERDDZ256rm:
2808  case X86::VPGATHERDDZrm:
2809  case X86::VPGATHERDQZ128rm:
2810  case X86::VPGATHERDQZ256rm:
2811  case X86::VPGATHERDQZrm:
2812  case X86::VPGATHERQDZ128rm:
2813  case X86::VPGATHERQDZ256rm:
2814  case X86::VPGATHERQDZrm:
2815  case X86::VPGATHERQQZ128rm:
2816  case X86::VPGATHERQQZ256rm:
2817  case X86::VPGATHERQQZrm: {
2818  unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg());
2819  unsigned Index =
2821  if (Dest == Index)
2822  return Warning(Ops[0]->getStartLoc(), "index and destination registers "
2823  "should be distinct");
2824  break;
2825  }
2826  case X86::V4FMADDPSrm:
2827  case X86::V4FMADDPSrmk:
2828  case X86::V4FMADDPSrmkz:
2829  case X86::V4FMADDSSrm:
2830  case X86::V4FMADDSSrmk:
2831  case X86::V4FMADDSSrmkz:
2832  case X86::V4FNMADDPSrm:
2833  case X86::V4FNMADDPSrmk:
2834  case X86::V4FNMADDPSrmkz:
2835  case X86::V4FNMADDSSrm:
2836  case X86::V4FNMADDSSrmk:
2837  case X86::V4FNMADDSSrmkz:
2838  case X86::VP4DPWSSDSrm:
2839  case X86::VP4DPWSSDSrmk:
2840  case X86::VP4DPWSSDSrmkz:
2841  case X86::VP4DPWSSDrm:
2842  case X86::VP4DPWSSDrmk:
2843  case X86::VP4DPWSSDrmkz: {
2844  unsigned Src2 = Inst.getOperand(Inst.getNumOperands() -
2846  unsigned Src2Enc = MRI->getEncodingValue(Src2);
2847  if (Src2Enc % 4 != 0) {
2849  unsigned GroupStart = (Src2Enc / 4) * 4;
2850  unsigned GroupEnd = GroupStart + 3;
2851  return Warning(Ops[0]->getStartLoc(),
2852  "source register '" + RegName + "' implicitly denotes '" +
2853  RegName.take_front(3) + Twine(GroupStart) + "' to '" +
2854  RegName.take_front(3) + Twine(GroupEnd) +
2855  "' source group");
2856  }
2857  break;
2858  }
2859  }
2860 
2861  return false;
2862 }
2863 
2864 static const char *getSubtargetFeatureName(uint64_t Val);
2865 
2866 void X86AsmParser::EmitInstruction(MCInst &Inst, OperandVector &Operands,
2867  MCStreamer &Out) {
2868  Instrumentation->InstrumentAndEmitInstruction(
2869  Inst, Operands, getContext(), MII, Out);
2870 }
2871 
2872 bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2873  OperandVector &Operands,
2874  MCStreamer &Out, uint64_t &ErrorInfo,
2875  bool MatchingInlineAsm) {
2876  if (isParsingIntelSyntax())
2877  return MatchAndEmitIntelInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
2878  MatchingInlineAsm);
2879  return MatchAndEmitATTInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
2880  MatchingInlineAsm);
2881 }
2882 
2883 void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op,
2884  OperandVector &Operands, MCStreamer &Out,
2885  bool MatchingInlineAsm) {
2886  // FIXME: This should be replaced with a real .td file alias mechanism.
2887  // Also, MatchInstructionImpl should actually *do* the EmitInstruction
2888  // call.
2889  const char *Repl = StringSwitch<const char *>(Op.getToken())
2890  .Case("finit", "fninit")
2891  .Case("fsave", "fnsave")
2892  .Case("fstcw", "fnstcw")
2893  .Case("fstcww", "fnstcw")
2894  .Case("fstenv", "fnstenv")
2895  .Case("fstsw", "fnstsw")
2896  .Case("fstsww", "fnstsw")
2897  .Case("fclex", "fnclex")
2898  .Default(nullptr);
2899  if (Repl) {
2900  MCInst Inst;
2901  Inst.setOpcode(X86::WAIT);
2902  Inst.setLoc(IDLoc);
2903  if (!MatchingInlineAsm)
2904  EmitInstruction(Inst, Operands, Out);
2905  Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
2906  }
2907 }
2908 
2909 bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo,
2910  bool MatchingInlineAsm) {
2911  assert(ErrorInfo && "Unknown missing feature!");
2912  SmallString<126> Msg;
2913  raw_svector_ostream OS(Msg);
2914  OS << "instruction requires:";
2915  uint64_t Mask = 1;
2916  for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
2917  if (ErrorInfo & Mask)
2918  OS << ' ' << getSubtargetFeatureName(ErrorInfo & Mask);
2919  Mask <<= 1;
2920  }
2921  return Error(IDLoc, OS.str(), SMRange(), MatchingInlineAsm);
2922 }
2923 
2924 static unsigned getPrefixes(OperandVector &Operands) {
2925  unsigned Result = 0;
2926  X86Operand &Prefix = static_cast<X86Operand &>(*Operands.back());
2927  if (Prefix.isPrefix()) {
2928  Result = Prefix.getPrefix();
2929  Operands.pop_back();
2930  }
2931  return Result;
2932 }
2933 
2934 bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
2935  OperandVector &Operands,
2936  MCStreamer &Out,
2937  uint64_t &ErrorInfo,
2938  bool MatchingInlineAsm) {
2939  assert(!Operands.empty() && "Unexpect empty operand list!");
2940  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
2941  assert(Op.isToken() && "Leading operand should always be a mnemonic!");
2942  SMRange EmptyRange = None;
2943 
2944  // First, handle aliases that expand to multiple instructions.
2945  MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
2946 
2947  bool WasOriginallyInvalidOperand = false;
2948  unsigned Prefixes = getPrefixes(Operands);
2949 
2950  MCInst Inst;
2951 
2952  if (Prefixes)
2953  Inst.setFlags(Prefixes);
2954 
2955  // First, try a direct match.
2956  switch (MatchInstruction(Operands, Inst, ErrorInfo, MatchingInlineAsm,
2957  isParsingIntelSyntax())) {
2958  default: llvm_unreachable("Unexpected match result!");
2959  case Match_Success:
2960  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
2961  return true;
2962  // Some instructions need post-processing to, for example, tweak which
2963  // encoding is selected. Loop on it while changes happen so the
2964  // individual transformations can chain off each other.
2965  if (!MatchingInlineAsm)
2966  while (processInstruction(Inst, Operands))
2967  ;
2968 
2969  Inst.setLoc(IDLoc);
2970  if (!MatchingInlineAsm)
2971  EmitInstruction(Inst, Operands, Out);
2972  Opcode = Inst.getOpcode();
2973  return false;
2974  case Match_MissingFeature:
2975  return ErrorMissingFeature(IDLoc, ErrorInfo, MatchingInlineAsm);
2976  case Match_InvalidOperand:
2977  WasOriginallyInvalidOperand = true;
2978  break;
2979  case Match_MnemonicFail:
2980  break;
2981  }
2982 
2983  // FIXME: Ideally, we would only attempt suffix matches for things which are
2984  // valid prefixes, and we could just infer the right unambiguous
2985  // type. However, that requires substantially more matcher support than the
2986  // following hack.
2987 
2988  // Change the operand to point to a temporary token.
2989  StringRef Base = Op.getToken();
2990  SmallString<16> Tmp;
2991  Tmp += Base;
2992  Tmp += ' ';
2993  Op.setTokenValue(Tmp);
2994 
2995  // If this instruction starts with an 'f', then it is a floating point stack
2996  // instruction. These come in up to three forms for 32-bit, 64-bit, and
2997  // 80-bit floating point, which use the suffixes s,l,t respectively.
2998  //
2999  // Otherwise, we assume that this may be an integer instruction, which comes
3000  // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
3001  const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
3002 
3003  // Check for the various suffix matches.
3004  uint64_t ErrorInfoIgnore;
3005  uint64_t ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
3006  unsigned Match[4];
3007 
3008  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) {
3009  Tmp.back() = Suffixes[I];
3010  Match[I] = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
3011  MatchingInlineAsm, isParsingIntelSyntax());
3012  // If this returned as a missing feature failure, remember that.
3013  if (Match[I] == Match_MissingFeature)
3014  ErrorInfoMissingFeature = ErrorInfoIgnore;
3015  }
3016 
3017  // Restore the old token.
3018  Op.setTokenValue(Base);
3019 
3020  // If exactly one matched, then we treat that as a successful match (and the
3021  // instruction will already have been filled in correctly, since the failing
3022  // matches won't have modified it).
3023  unsigned NumSuccessfulMatches =
3024  std::count(std::begin(Match), std::end(Match), Match_Success);
3025  if (NumSuccessfulMatches == 1) {
3026  Inst.setLoc(IDLoc);
3027  if (!MatchingInlineAsm)
3028  EmitInstruction(Inst, Operands, Out);
3029  Opcode = Inst.getOpcode();
3030  return false;
3031  }
3032 
3033  // Otherwise, the match failed, try to produce a decent error message.
3034 
3035  // If we had multiple suffix matches, then identify this as an ambiguous
3036  // match.
3037  if (NumSuccessfulMatches > 1) {
3038  char MatchChars[4];
3039  unsigned NumMatches = 0;
3040  for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I)
3041  if (Match[I] == Match_Success)
3042  MatchChars[NumMatches++] = Suffixes[I];
3043 
3044  SmallString<126> Msg;
3045  raw_svector_ostream OS(Msg);
3046  OS << "ambiguous instructions require an explicit suffix (could be ";
3047  for (unsigned i = 0; i != NumMatches; ++i) {
3048  if (i != 0)
3049  OS << ", ";
3050  if (i + 1 == NumMatches)
3051  OS << "or ";
3052  OS << "'" << Base << MatchChars[i] << "'";
3053  }
3054  OS << ")";
3055  Error(IDLoc, OS.str(), EmptyRange, MatchingInlineAsm);
3056  return true;
3057  }
3058 
3059  // Okay, we know that none of the variants matched successfully.
3060 
3061  // If all of the instructions reported an invalid mnemonic, then the original
3062  // mnemonic was invalid.
3063  if (std::count(std::begin(Match), std::end(Match), Match_MnemonicFail) == 4) {
3064  if (!WasOriginallyInvalidOperand) {
3065  return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
3066  Op.getLocRange(), MatchingInlineAsm);
3067  }
3068 
3069  // Recover location info for the operand if we know which was the problem.
3070  if (ErrorInfo != ~0ULL) {
3071  if (ErrorInfo >= Operands.size())
3072  return Error(IDLoc, "too few operands for instruction", EmptyRange,
3073  MatchingInlineAsm);
3074 
3075  X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo];
3076  if (Operand.getStartLoc().isValid()) {
3077  SMRange OperandRange = Operand.getLocRange();
3078  return Error(Operand.getStartLoc(), "invalid operand for instruction",
3079  OperandRange, MatchingInlineAsm);
3080  }
3081  }
3082 
3083  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
3084  MatchingInlineAsm);
3085  }
3086 
3087  // If one instruction matched with a missing feature, report this as a
3088  // missing feature.
3089  if (std::count(std::begin(Match), std::end(Match),
3090  Match_MissingFeature) == 1) {
3091  ErrorInfo = ErrorInfoMissingFeature;
3092  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature,
3093  MatchingInlineAsm);
3094  }
3095 
3096  // If one instruction matched with an invalid operand, report this as an
3097  // operand failure.
3098  if (std::count(std::begin(Match), std::end(Match),
3099  Match_InvalidOperand) == 1) {
3100  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
3101  MatchingInlineAsm);
3102  }
3103 
3104  // If all of these were an outright failure, report it in a useless way.
3105  Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
3106  EmptyRange, MatchingInlineAsm);
3107  return true;
3108 }
3109 
3110 bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
3111  OperandVector &Operands,
3112  MCStreamer &Out,
3113  uint64_t &ErrorInfo,
3114  bool MatchingInlineAsm) {
3115  assert(!Operands.empty() && "Unexpect empty operand list!");
3116  X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
3117  assert(Op.isToken() && "Leading operand should always be a mnemonic!");
3118  StringRef Mnemonic = Op.getToken();
3119  SMRange EmptyRange = None;
3120  StringRef Base = Op.getToken();
3121  unsigned Prefixes = getPrefixes(Operands);
3122 
3123  // First, handle aliases that expand to multiple instructions.
3124  MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
3125 
3126  MCInst Inst;
3127 
3128  if (Prefixes)
3129  Inst.setFlags(Prefixes);
3130 
3131  // Find one unsized memory operand, if present.
3132  X86Operand *UnsizedMemOp = nullptr;
3133  for (const auto &Op : Operands) {
3134  X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
3135  if (X86Op->isMemUnsized()) {
3136  UnsizedMemOp = X86Op;
3137  // Have we found an unqualified memory operand,
3138  // break. IA allows only one memory operand.
3139  break;
3140  }
3141  }
3142 
3143  // Allow some instructions to have implicitly pointer-sized operands. This is
3144  // compatible with gas.
3145  if (UnsizedMemOp) {
3146  static const char *const PtrSizedInstrs[] = {"call", "jmp", "push"};
3147  for (const char *Instr : PtrSizedInstrs) {
3148  if (Mnemonic == Instr) {
3149  UnsizedMemOp->Mem.Size = getPointerWidth();
3150  break;
3151  }
3152  }
3153  }
3154 
3156  uint64_t ErrorInfoMissingFeature = 0;
3157 
3158  // If unsized push has immediate operand we should default the default pointer
3159  // size for the size.
3160  if (Mnemonic == "push" && Operands.size() == 2) {
3161  auto *X86Op = static_cast<X86Operand *>(Operands[1].get());
3162  if (X86Op->isImm()) {
3163  // If it's not a constant fall through and let remainder take care of it.
3164  const auto *CE = dyn_cast<MCConstantExpr>(X86Op->getImm());
3165  unsigned Size = getPointerWidth();
3166  if (CE &&
3167  (isIntN(Size, CE->getValue()) || isUIntN(Size, CE->getValue()))) {
3168  SmallString<16> Tmp;
3169  Tmp += Base;
3170  Tmp += (is64BitMode())
3171  ? "q"
3172  : (is32BitMode()) ? "l" : (is16BitMode()) ? "w" : " ";
3173  Op.setTokenValue(Tmp);
3174  // Do match in ATT mode to allow explicit suffix usage.
3175  Match.push_back(MatchInstruction(Operands, Inst, ErrorInfo,
3176  MatchingInlineAsm,
3177  false /*isParsingIntelSyntax()*/));
3178  Op.setTokenValue(Base);
3179  }
3180  }
3181  }
3182 
3183  // If an unsized memory operand is present, try to match with each memory
3184  // operand size. In Intel assembly, the size is not part of the instruction
3185  // mnemonic.
3186  if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
3187  static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
3188  for (unsigned Size : MopSizes) {
3189  UnsizedMemOp->Mem.Size = Size;
3190  uint64_t ErrorInfoIgnore;
3191  unsigned LastOpcode = Inst.getOpcode();
3192  unsigned M = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
3193  MatchingInlineAsm, isParsingIntelSyntax());
3194  if (Match.empty() || LastOpcode != Inst.getOpcode())
3195  Match.push_back(M);
3196 
3197  // If this returned as a missing feature failure, remember that.
3198  if (Match.back() == Match_MissingFeature)
3199  ErrorInfoMissingFeature = ErrorInfoIgnore;
3200  }
3201 
3202  // Restore the size of the unsized memory operand if we modified it.
3203  UnsizedMemOp->Mem.Size = 0;
3204  }
3205 
3206  // If we haven't matched anything yet, this is not a basic integer or FPU
3207  // operation. There shouldn't be any ambiguity in our mnemonic table, so try
3208  // matching with the unsized operand.
3209  if (Match.empty()) {
3210  Match.push_back(MatchInstruction(
3211  Operands, Inst, ErrorInfo, MatchingInlineAsm, isParsingIntelSyntax()));
3212  // If this returned as a missing feature failure, remember that.
3213  if (Match.back() == Match_MissingFeature)
3214  ErrorInfoMissingFeature = ErrorInfo;
3215  }
3216 
3217  // Restore the size of the unsized memory operand if we modified it.
3218  if (UnsizedMemOp)
3219  UnsizedMemOp->Mem.Size = 0;
3220 
3221  // If it's a bad mnemonic, all results will be the same.
3222  if (Match.back() == Match_MnemonicFail) {
3223  return Error(IDLoc, "invalid instruction mnemonic '" + Mnemonic + "'",
3224  Op.getLocRange(), MatchingInlineAsm);
3225  }
3226 
3227  unsigned NumSuccessfulMatches =
3228  std::count(std::begin(Match), std::end(Match), Match_Success);
3229 
3230  // If matching was ambiguous and we had size information from the frontend,
3231  // try again with that. This handles cases like "movxz eax, m8/m16".
3232  if (UnsizedMemOp && NumSuccessfulMatches > 1 &&
3233  UnsizedMemOp->getMemFrontendSize()) {
3234  UnsizedMemOp->Mem.Size = UnsizedMemOp->getMemFrontendSize();
3235  unsigned M = MatchInstruction(
3236  Operands, Inst, ErrorInfo, MatchingInlineAsm, isParsingIntelSyntax());
3237  if (M == Match_Success)
3238  NumSuccessfulMatches = 1;
3239 
3240  // Add a rewrite that encodes the size information we used from the
3241  // frontend.
3242  InstInfo->AsmRewrites->emplace_back(
3243  AOK_SizeDirective, UnsizedMemOp->getStartLoc(),
3244  /*Len=*/0, UnsizedMemOp->getMemFrontendSize());
3245  }
3246 
3247  // If exactly one matched, then we treat that as a successful match (and the
3248  // instruction will already have been filled in correctly, since the failing
3249  // matches won't have modified it).
3250  if (NumSuccessfulMatches == 1) {
3251  if (!MatchingInlineAsm && validateInstruction(Inst, Operands))
3252  return true;
3253  // Some instructions need post-processing to, for example, tweak which
3254  // encoding is selected. Loop on it while changes happen so the individual
3255  // transformations can chain off each other.
3256  if (!MatchingInlineAsm)
3257  while (processInstruction(Inst, Operands))
3258  ;
3259  Inst.setLoc(IDLoc);
3260  if (!MatchingInlineAsm)
3261  EmitInstruction(Inst, Operands, Out);
3262  Opcode = Inst.getOpcode();
3263  return false;
3264  } else if (NumSuccessfulMatches > 1) {
3265  assert(UnsizedMemOp &&
3266  "multiple matches only possible with unsized memory operands");
3267  return Error(UnsizedMemOp->getStartLoc(),
3268  "ambiguous operand size for instruction '" + Mnemonic + "\'",
3269  UnsizedMemOp->getLocRange());
3270  }
3271 
3272  // If one instruction matched with a missing feature, report this as a
3273  // missing feature.
3274  if (std::count(std::begin(Match), std::end(Match),
3275  Match_MissingFeature) == 1) {
3276  ErrorInfo = ErrorInfoMissingFeature;
3277  return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature,
3278  MatchingInlineAsm);
3279  }
3280 
3281  // If one instruction matched with an invalid operand, report this as an
3282  // operand failure.
3283  if (std::count(std::begin(Match), std::end(Match),
3284  Match_InvalidOperand) == 1) {
3285  return Error(IDLoc, "invalid operand for instruction", EmptyRange,
3286  MatchingInlineAsm);
3287  }
3288 
3289  // If all of these were an outright failure, report it in a useless way.
3290  return Error(IDLoc, "unknown instruction mnemonic", EmptyRange,
3291  MatchingInlineAsm);
3292 }
3293 
3294 bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
3295  return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
3296 }
3297 
3298 bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
3299  MCAsmParser &Parser = getParser();
3300  StringRef IDVal = DirectiveID.getIdentifier();
3301  if (IDVal.startswith(".code"))
3302  return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
3303  else if (IDVal.startswith(".att_syntax")) {
3304  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3305  if (Parser.getTok().getString() == "prefix")
3306  Parser.Lex();
3307  else if (Parser.getTok().getString() == "noprefix")
3308  return Error(DirectiveID.getLoc(), "'.att_syntax noprefix' is not "
3309  "supported: registers must have a "
3310  "'%' prefix in .att_syntax");
3311  }
3312  getParser().setAssemblerDialect(0);
3313  return false;
3314  } else if (IDVal.startswith(".intel_syntax")) {
3315  getParser().setAssemblerDialect(1);
3316  if (getLexer().isNot(AsmToken::EndOfStatement)) {
3317  if (Parser.getTok().getString() == "noprefix")
3318  Parser.Lex();
3319  else if (Parser.getTok().getString() == "prefix")
3320  return Error(DirectiveID.getLoc(), "'.intel_syntax prefix' is not "
3321  "supported: registers must not have "
3322  "a '%' prefix in .intel_syntax");
3323  }
3324  return false;
3325  } else if (IDVal == ".even")
3326  return parseDirectiveEven(DirectiveID.getLoc());
3327  else if (IDVal == ".cv_fpo_proc")
3328  return parseDirectiveFPOProc(DirectiveID.getLoc());
3329  else if (IDVal == ".cv_fpo_setframe")
3330  return parseDirectiveFPOSetFrame(DirectiveID.getLoc());
3331  else if (IDVal == ".cv_fpo_pushreg")
3332  return parseDirectiveFPOPushReg(DirectiveID.getLoc());
3333  else if (IDVal == ".cv_fpo_stackalloc")
3334  return parseDirectiveFPOStackAlloc(DirectiveID.getLoc());
3335  else if (IDVal == ".cv_fpo_stackalign")
3336  return parseDirectiveFPOStackAlign(DirectiveID.getLoc());
3337  else if (IDVal == ".cv_fpo_endprologue")
3338  return parseDirectiveFPOEndPrologue(DirectiveID.getLoc());
3339  else if (IDVal == ".cv_fpo_endproc")
3340  return parseDirectiveFPOEndProc(DirectiveID.getLoc());
3341 
3342  return true;
3343 }
3344 
3345 /// parseDirectiveEven
3346 /// ::= .even
3347 bool X86AsmParser::parseDirectiveEven(SMLoc L) {
3348  if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
3349  return false;
3350 
3351  const MCSection *Section = getStreamer().getCurrentSectionOnly();
3352  if (!Section) {
3353  getStreamer().InitSections(false);
3354  Section = getStreamer().getCurrentSectionOnly();
3355  }
3356  if (Section->UseCodeAlign())
3357  getStreamer().EmitCodeAlignment(2, 0);
3358  else
3359  getStreamer().EmitValueToAlignment(2, 0, 1, 0);
3360  return false;
3361 }
3362 
3363 /// ParseDirectiveCode
3364 /// ::= .code16 | .code32 | .code64
3365 bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
3366  MCAsmParser &Parser = getParser();
3367  Code16GCC = false;
3368  if (IDVal == ".code16") {
3369  Parser.Lex();
3370  if (!is16BitMode()) {
3371  SwitchMode(X86::Mode16Bit);
3372  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3373  }
3374  } else if (IDVal == ".code16gcc") {
3375  // .code16gcc parses as if in 32-bit mode, but emits code in 16-bit mode.
3376  Parser.Lex();
3377  Code16GCC = true;
3378  if (!is16BitMode()) {
3379  SwitchMode(X86::Mode16Bit);
3380  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3381  }
3382  } else if (IDVal == ".code32") {
3383  Parser.Lex();
3384  if (!is32BitMode()) {
3385  SwitchMode(X86::Mode32Bit);
3386  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3387  }
3388  } else if (IDVal == ".code64") {
3389  Parser.Lex();
3390  if (!is64BitMode()) {
3391  SwitchMode(X86::Mode64Bit);
3392  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
3393  }
3394  } else {
3395  Error(L, "unknown directive " + IDVal);
3396  return false;
3397  }
3398 
3399  return false;
3400 }
3401 
3402 // .cv_fpo_proc foo
3403 bool X86AsmParser::parseDirectiveFPOProc(SMLoc L) {
3404  MCAsmParser &Parser = getParser();
3405  StringRef ProcName;
3406  int64_t ParamsSize;
3407  if (Parser.parseIdentifier(ProcName))
3408  return Parser.TokError("expected symbol name");
3409  if (Parser.parseIntToken(ParamsSize, "expected parameter byte count"))
3410  return true;
3411  if (!isUIntN(32, ParamsSize))
3412  return Parser.TokError("parameters size out of range");
3413  if (Parser.parseEOL("unexpected tokens"))
3414  return addErrorSuffix(" in '.cv_fpo_proc' directive");
3415  MCSymbol *ProcSym = getContext().getOrCreateSymbol(ProcName);
3416  return getTargetStreamer().emitFPOProc(ProcSym, ParamsSize, L);
3417 }
3418 
3419 // .cv_fpo_setframe ebp
3420 bool X86AsmParser::parseDirectiveFPOSetFrame(SMLoc L) {
3421  MCAsmParser &Parser = getParser();
3422  unsigned Reg;
3423  SMLoc DummyLoc;
3424  if (ParseRegister(Reg, DummyLoc, DummyLoc) ||
3425  Parser.parseEOL("unexpected tokens"))
3426  return addErrorSuffix(" in '.cv_fpo_setframe' directive");
3427  return getTargetStreamer().emitFPOSetFrame(Reg, L);
3428 }
3429 
3430 // .cv_fpo_pushreg ebx
3431 bool X86AsmParser::parseDirectiveFPOPushReg(SMLoc L) {
3432  MCAsmParser &Parser = getParser();
3433  unsigned Reg;
3434  SMLoc DummyLoc;
3435  if (ParseRegister(Reg, DummyLoc, DummyLoc) ||
3436  Parser.parseEOL("unexpected tokens"))
3437  return addErrorSuffix(" in '.cv_fpo_pushreg' directive");
3438  return getTargetStreamer().emitFPOPushReg(Reg, L);
3439 }
3440 
3441 // .cv_fpo_stackalloc 20
3442 bool X86AsmParser::parseDirectiveFPOStackAlloc(SMLoc L) {
3443  MCAsmParser &Parser = getParser();
3444  int64_t Offset;
3445  if (Parser.parseIntToken(Offset, "expected offset") ||
3446  Parser.parseEOL("unexpected tokens"))
3447  return addErrorSuffix(" in '.cv_fpo_stackalloc' directive");
3448  return getTargetStreamer().emitFPOStackAlloc(Offset, L);
3449 }
3450 
3451 // .cv_fpo_stackalign 8
3452 bool X86AsmParser::parseDirectiveFPOStackAlign(SMLoc L) {
3453  MCAsmParser &Parser = getParser();
3454  int64_t Offset;
3455  if (Parser.parseIntToken(Offset, "expected offset") ||
3456  Parser.parseEOL("unexpected tokens"))
3457  return addErrorSuffix(" in '.cv_fpo_stackalign' directive");
3458  return getTargetStreamer().emitFPOStackAlign(Offset, L);
3459 }
3460 
3461 // .cv_fpo_endprologue
3462 bool X86AsmParser::parseDirectiveFPOEndPrologue(SMLoc L) {
3463  MCAsmParser &Parser = getParser();
3464  if (Parser.parseEOL("unexpected tokens"))
3465  return addErrorSuffix(" in '.cv_fpo_endprologue' directive");
3466  return getTargetStreamer().emitFPOEndPrologue(L);
3467 }
3468 
3469 // .cv_fpo_endproc
3470 bool X86AsmParser::parseDirectiveFPOEndProc(SMLoc L) {
3471  MCAsmParser &Parser = getParser();
3472  if (Parser.parseEOL("unexpected tokens"))
3473  return addErrorSuffix(" in '.cv_fpo_endproc' directive");
3474  return getTargetStreamer().emitFPOEndProc(L);
3475 }
3476 
3477 // Force static initialization.
3478 extern "C" void LLVMInitializeX86AsmParser() {
3481 }
3482 
3483 #define GET_REGISTER_MATCHER
3484 #define GET_MATCHER_IMPLEMENTATION
3485 #define GET_SUBTARGET_FEATURE_NAME
3486 #include "X86GenAsmMatcher.inc"
static const char * getSubtargetFeatureName(uint64_t Val)
Represents a range in source code.
Definition: SMLoc.h:48
Instances of this class represent a uniqued identifier for a section in the current translation unit...
Definition: MCSection.h:38
static bool checkScale(unsigned Scale, StringRef &ErrMsg)
LLVM_NODISCARD StringRef take_front(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with only the first N elements remaining.
Definition: StringRef.h:587
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:258
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmMacro.h:110
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
unsigned getMemFrontendSize() const
Definition: X86Operand.h:197
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:249
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:803
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:267
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:322
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
SMRange getLocRange() const
getLocRange - Get the range between the first and last token of this operand.
Definition: X86Operand.h:93
bool isVariable() const
isVariable - Check if this is a variable symbol.
Definition: MCSymbol.h:293
SmallVectorImpl< AsmRewrite > * AsmRewrites
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
LLVM_NODISCARD bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Definition: StringRef.h:167
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:109
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
bool isKind(IdKind kind) const
Definition: MCAsmParser.h:65
MCTargetAsmParser - Generic interface to target specific assembly parsers.
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:256
LLVM_NODISCARD int compare(StringRef RHS) const
compare - Compare two strings; the result is -1, 0, or 1 if this string is lexicographically less tha...
Definition: StringRef.h:174
Target specific streamer interface.
Definition: MCStreamer.h:83
unsigned Reg
bool isNot(TokenKind K) const
Definition: MCAsmMacro.h:83
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:509
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:33
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, StringRef SymName=StringRef(), void *OpDecl=nullptr, unsigned FrontendSize=0)
Create an absolute memory operand.
Definition: X86Operand.h:566
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
bool parseIntToken(int64_t &V, const Twine &ErrMsg)
Definition: MCAsmParser.cpp:58
return AArch64::GPR64RegClass contains(Reg)
static ModuleSymbolTable::Symbol getSym(DataRefImpl &Symb)
StringRef getToken() const
Definition: X86Operand.h:148
amode Optimize addressing mode
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
Definition: MCAsmMacro.h:99
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
void LLVMInitializeX86AsmParser()
const FeatureBitset & getFeatureBits() const
unsigned getPrefix() const
Definition: X86Operand.h:163
bool isMemUnsized() const
Definition: X86Operand.h:281
SMLoc getEndLoc() const override
getEndLoc - Get the location of the last token of this operand.
Definition: X86Operand.h:89
LLVM_NODISCARD StringRef drop_front(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with the first N elements dropped.
Definition: StringRef.h:620
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:457
bool isImm() const override
isImm - Is this an immediate operand?
Definition: X86Operand.h:204
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
LLVM_NODISCARD StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: StringRef.h:679
static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg, unsigned Scale, bool Is64BitMode, StringRef &ErrMsg)
}
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:578
bool isMem8() const
Definition: X86Operand.h:284
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
zlib-gnu style compression
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
static std::unique_ptr< X86Operand > CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:557
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:29
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
unsigned getReg() const override
Definition: X86Operand.h:158
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:51
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:27
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:460
LLVM_NODISCARD std::string upper() const
Convert the given ASCII string to uppercase.
Definition: StringRef.cpp:115
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
virtual void eatToEndOfStatement()=0
Skip to the end of the current statement, for error recovery.
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(adl_begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1251
static const X86MCExpr * create(int64_t RegNo, MCContext &Ctx)
Definition: X86MCExpr.h:36
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isPrefix() const
Definition: X86Operand.h:444
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:769
virtual void addAliasForDirective(StringRef Directive, StringRef Alias)=0
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
const char * getPointer() const
Definition: SMLoc.h:34
virtual MCContext & getContext()=0
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
Streaming machine code generation interface.
Definition: MCStreamer.h:188
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
Definition: StringSwitch.h:88
unsigned const MachineRegisterInfo * MRI
X86Operand - Instances of this class represent a parsed X86 machine instruction.
Definition: X86Operand.h:31
MCTargetStreamer * getTargetStreamer()
Definition: MCStreamer.h:257
Container class for subtarget features.
SMLoc getEndLoc() const
Definition: MCAsmLexer.cpp:31
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse a primary expression.
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
const MCExpr * getImm() const
Definition: X86Operand.h:168
bool parseTokenLoc(SMLoc &Loc)
Definition: MCAsmParser.cpp:37
int64_t getIntVal() const
Definition: MCAsmMacro.h:115
unsigned getNumOperands() const
Definition: MCInst.h:181
static std::unique_ptr< X86Operand > CreateDXReg(SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:546
bool Error(SMLoc L, const Twine &Msg, SMRange Range=None)
Return an error at the location L, with the message Msg.
Definition: MCAsmParser.cpp:87
static const char * getRegisterName(unsigned RegNo)
virtual bool UseCodeAlign() const =0
Return true if a .align directive should use "optimized nops" to fill instead of 0s.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:397
iterator erase(const_iterator CI)
Definition: SmallVector.h:437
size_t size() const
Definition: SmallVector.h:52
LLVM_NODISCARD char back() const
back - Get the last character in the string.
Definition: StringRef.h:141
void setLoc(SMLoc loc)
Definition: MCInst.h:176
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SMLoc getStartLoc() const override
getStartLoc - Get the location of the first token of this operand.
Definition: X86Operand.h:86
unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
X86AsmInstrumentation * CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, const MCContext &Ctx, const MCSubtargetInfo *&STI)
void setFlags(unsigned F)
Definition: MCInst.h:173
MCStreamer & getStreamer()
Definition: MCStreamer.h:91
void setOpcode(unsigned Op)
Definition: MCInst.h:170
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1166
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:256
static unsigned MatchRegisterName(StringRef Name)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:839
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
struct MemOp Mem
Definition: X86Operand.h:75
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:373
StringRef str()
Return a StringRef for the vector contents.
Definition: raw_ostream.h:534
X86 target streamer implementing x86-only assembly directives.
static bool isPrefix(const IndicesVector &Prefix, const IndicesVector &Longer)
Returns true if Prefix is a prefix of longer.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
bool is(TokenKind K) const
Definition: MCAsmMacro.h:82
Class for arbitrary precision integers.
Definition: APInt.h:69
bool isValid() const
Definition: SMLoc.h:29
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Base class for user error types.
Definition: Error.h:344
static std::unique_ptr< X86Operand > CreateToken(StringRef Str, SMLoc Loc)
Definition: X86Operand.h:524
VariableIdentifier Var
Definition: MCAsmParser.h:63
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:52
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
static std::unique_ptr< X86Operand > CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc, bool AddressOf=false, SMLoc OffsetOfLoc=SMLoc(), StringRef SymName=StringRef(), void *OpDecl=nullptr)
Definition: X86Operand.h:533
.code64 (X86)
Definition: MCDirectives.h:53
LLVM_NODISCARD bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:160
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
static unsigned getPrefixes(OperandVector &Operands)
Generic base class for all target subtargets.
virtual bool parseAbsoluteExpression(int64_t &Res)=0
Parse an expression which must evaluate to an absolute value.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
Target & getTheX86_32Target()
uint32_t Size
Definition: Profile.cpp:46
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:202
bool isDXReg() const
Definition: X86Operand.h:446
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:107
static std::unique_ptr< X86Operand > CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:551
LLVM_NODISCARD const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:122
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool TokError(const Twine &Msg, SMRange Range=None)
Report an error at the current lexer location.
Definition: MCAsmParser.cpp:83
const MCExpr * getVariableValue(bool SetUsed=true) const
getVariableValue - Get the value for variable symbols.
Definition: MCSymbol.h:298
LLVM_NODISCARD StringRef drop_back(size_t N=1) const
Return a StringRef equal to &#39;this&#39; but with the last N elements dropped.
Definition: StringRef.h:628
bool parseEOL(const Twine &ErrMsg)
Definition: MCAsmParser.cpp:42
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
bool parseOptionalToken(AsmToken::TokenKind T)
Attempt to parse and consume token, returning true on success.
Definition: MCAsmParser.cpp:66
bool isReg() const override
isReg - Is this a register operand?
Definition: X86Operand.h:445
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual bool parseIdentifier(StringRef &Res)=0
Parse an identifier or string (as a quoted identifier) and set Res to the identifier contents...
Represents a location in source code.
Definition: SMLoc.h:23
unsigned getOpcode() const
Definition: MCInst.h:171
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:392
Target & getTheX86_64Target()
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:163
bool isMem() const override
isMem - Is this a memory operand?
Definition: X86Operand.h:280