60#define DEBUG_TYPE "machinelicm"
64 cl::desc(
"MachineLICM should avoid speculation"),
69 cl::desc(
"MachineLICM should hoist even cheap instructions"),
85 cl::desc(
"Do not hoist instructions if target"
86 "block is N times hotter than the source."),
93 cl::desc(
"Disable hoisting instructions to"
97 "disable the feature"),
99 "enable the feature when using profile data"),
101 "enable the feature with/wo profile data")));
104 "Number of machine instructions hoisted out of loops");
106 "Number of instructions hoisted in low reg pressure situation");
108 "Number of high latency instructions hoisted");
110 "Number of hoisted machine instructions CSEed");
112 "Number of machine instructions hoisted out of loops post regalloc");
114 "Number of stores of const phys reg hoisted out of loops");
116 "Number of instructions not hoisted due to block frequency");
119 enum HoistResult { NotHoisted = 1, Hoisted = 2, ErasedMI = 4 };
121 class MachineLICMImpl {
128 bool PreRegAlloc =
false;
129 bool HasProfileData =
false;
140 bool Changed =
false;
141 bool FirstInLoop =
false;
155 It->second = std::move(ExitBlocks);
185 unsigned SpeculationState = SpeculateUnknown;
188 MachineLICMImpl(
bool PreRegAlloc,
Pass *LegacyPass,
190 : PreRegAlloc(PreRegAlloc), LegacyPass(LegacyPass), MFAM(MFAM) {
191 assert((LegacyPass || MFAM) &&
"LegacyPass or MFAM must be provided");
192 assert(!(LegacyPass && MFAM) &&
193 "LegacyPass and MFAM cannot be provided at the same time");
198 void releaseMemory() {
204 ExitBlockMap.
clear();
209 struct CandidateInfo {
215 :
MI(mi),
Def(def), FI(fi) {}
257 void ExitScopeIfDone(
269 bool ConsiderUnseenAsDef);
272 bool ConsiderUnseenAsDef =
false);
277 std::vector<MachineInstr *> &PrevMIs);
281 DenseMap<
unsigned, std::vector<MachineInstr *>>::iterator &CI);
290 void InitializeLoadsHoistableLoops();
302 MachineLICMBase(
char &
ID,
bool PreRegAlloc)
318 class MachineLICM :
public MachineLICMBase {
321 MachineLICM() : MachineLICMBase(
ID,
false) {
326 class EarlyMachineLICM :
public MachineLICMBase {
329 EarlyMachineLICM() : MachineLICMBase(
ID,
true) {
337char EarlyMachineLICM::ID;
343 "Machine Loop Invariant Code Motion",
false,
false)
361 if (skipFunction(MF.getFunction()))
364 MachineLICMImpl Impl(PreRegAlloc,
this,
nullptr);
368#define GET_RESULT(RESULT, GETTER, INFIX) \
370 ? &LegacyPass->getAnalysis<RESULT##INFIX##WrapperPass>().GETTER() \
371 : &MFAM->getResult<RESULT##Analysis>(MF))
380 MachineDomTreeUpdater::UpdateStrategy::Lazy);
387 Changed = FirstInLoop =
false;
389 TII = ST.getInstrInfo();
390 TLI = ST.getTargetLowering();
391 TRI = ST.getRegisterInfo();
394 SchedModel.
init(&ST);
406 unsigned NumRPS =
TRI->getNumRegPressureSets();
407 RegPressure.resize(NumRPS);
408 std::fill(RegPressure.begin(), RegPressure.end(), 0);
410 for (
unsigned i = 0, e = NumRPS; i != e; ++i)
411 RegLimit[i] =
TRI->getRegPressureSetLimit(MF, i);
415 InitializeLoadsHoistableLoops();
418 while (!Worklist.
empty()) {
423 HoistRegionPostRA(CurLoop, CurPreheader);
429 HoistOutOfLoop(
N, CurLoop, CurPreheader);
445 if (
MI->memoperands_empty())
448 if (!
MemOp->isStore() || !
MemOp->getPseudoValue())
451 dyn_cast<FixedStackPseudoSourceValue>(
MemOp->getPseudoValue())) {
452 if (
Value->getFrameIndex() == FI)
493 const unsigned NumRegs =
TRI.getNumRegs();
494 const unsigned MaskWords = (NumRegs + 31) / 32;
495 for (
unsigned K = 0; K < MaskWords; ++K) {
497 for (
unsigned Bit = 0; Bit < 32; ++Bit) {
498 const unsigned PhysReg = (K * 32) + Bit;
499 if (PhysReg == NumRegs)
502 if (PhysReg && !((Word >> Bit) & 1)) {
504 RUsFromRegsNotInMask.
set(*RUI);
509 RUs |= RUsFromRegsNotInMask;
519 bool RuledOut =
false;
520 bool HasNonInvariantUse =
false;
525 int FI = MO.getIndex();
526 if (!StoredFIs.
count(FI) &&
530 HasNonInvariantUse =
true;
536 if (MO.isRegMask()) {
546 assert(
Reg.isPhysical() &&
"Not expecting virtual register!");
549 if (!HasNonInvariantUse) {
553 if (RUDefs.
test(*RUI) || RUClobbers.
test(*RUI)) {
554 HasNonInvariantUse =
true;
562 if (MO.isImplicit()) {
564 RUClobbers.
set(*RUI);
584 if (RUDefs.
test(*RUI)) {
585 RUClobbers.
set(*RUI);
587 }
else if (RUClobbers.
test(*RUI)) {
599 if (Def && !RuledOut) {
600 int FI = std::numeric_limits<int>::min();
601 if ((!HasNonInvariantUse && IsLICMCandidate(*
MI, CurLoop)) ||
609void MachineLICMImpl::HoistRegionPostRA(
MachineLoop *CurLoop,
615 unsigned NumRegUnits =
TRI->getNumRegUnits();
628 if (
ML &&
ML->getHeader()->isEHPad())
continue;
633 for (
const auto &LI : BB->liveins()) {
639 if (
const uint32_t *Mask = BB->getBeginClobberMask(
TRI))
642 SpeculationState = SpeculateUnknown;
644 ProcessMI(&
MI, RUDefs, RUClobbers, StoredFIs, Candidates, CurLoop);
650 if (TI != Preheader->
end()) {
670 for (CandidateInfo &Candidate : Candidates) {
671 if (Candidate.FI != std::numeric_limits<int>::min() &&
672 StoredFIs.
count(Candidate.FI))
675 unsigned Def = Candidate.Def;
678 if (RUClobbers.
test(*RUI) || TermRUs.test(*RUI)) {
692 if (RUDefs.
test(*RUI) || RUClobbers.
test(*RUI)) {
705 HoistPostRA(
MI, Candidate.Def, CurLoop, CurPreheader);
713 if (!BB->isLiveIn(Reg))
719 if (
TRI->regsOverlap(Reg, MO.getReg()))
746 assert(!
MI->isDebugInstr() &&
"Should not hoist debug inst");
752 AddToLiveIns(Def, CurLoop);
762 if (SpeculationState != SpeculateUnknown)
763 return SpeculationState == SpeculateFalse;
771 SpeculationState = SpeculateTrue;
776 SpeculationState = SpeculateFalse;
784bool MachineLICMImpl::isTriviallyReMaterializable(
786 if (!
TII->isTriviallyReMaterializable(
MI))
790 if (MO.getReg().isVirtual())
812void MachineLICMImpl::ExitScopeIfDone(
816 if (OpenChildren[
Node])
820 ExitScope(
Node->getBlock());
823 if (!Parent || --OpenChildren[Parent] != 0)
847 while (!WorkList.
empty()) {
855 if (
ML &&
ML->getHeader()->isEHPad())
863 unsigned NumChildren =
Node->getNumChildren();
871 OpenChildren[
Node] = NumChildren;
877 ParentMap[Child] =
Node;
889 InitRegPressure(Preheader);
898 SpeculationState = SpeculateUnknown;
900 unsigned HoistRes = HoistResult::NotHoisted;
901 HoistRes = Hoist(&
MI, Preheader, CurLoop);
902 if (HoistRes & HoistResult::NotHoisted) {
907 L =
L->getParentLoop())
910 while (!InnerLoopWorkList.
empty()) {
913 if (InnerLoopPreheader) {
914 HoistRes = Hoist(&
MI, InnerLoopPreheader, InnerLoop);
915 if (HoistRes & HoistResult::Hoisted)
921 if (HoistRes & HoistResult::ErasedMI)
924 UpdateRegPressure(&
MI);
928 ExitScopeIfDone(
Node, OpenChildren, ParentMap);
954 UpdateRegPressure(&
MI,
true);
959 bool ConsiderUnseenAsDef) {
960 auto Cost = calcRegisterCost(
MI,
true, ConsiderUnseenAsDef);
961 for (
const auto &RPIdAndCost :
Cost) {
962 unsigned Class = RPIdAndCost.first;
963 if (
static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second)
977MachineLICMImpl::calcRegisterCost(
const MachineInstr *
MI,
bool ConsiderSeen,
978 bool ConsiderUnseenAsDef) {
980 if (
MI->isImplicitDef())
982 for (
unsigned i = 0, e =
MI->getDesc().getNumOperands(); i != e; ++i) {
987 if (!
Reg.isVirtual())
991 bool isNew = ConsiderSeen ? RegSeen.
insert(Reg).second :
false;
997 RCCost =
W.RegWeight;
1000 if (isNew && !isKill && ConsiderUnseenAsDef)
1002 RCCost =
W.RegWeight;
1003 else if (!isNew && isKill)
1004 RCCost = -
W.RegWeight;
1008 const int *PS =
TRI->getRegClassPressureSets(RC);
1009 for (; *PS != -1; ++PS)
1010 Cost[*PS] += RCCost;
1018 assert(
MI.mayLoad() &&
"Expected MI that loads!");
1022 if (
MI.memoperands_empty())
1027 if (PSV->isGOT() || PSV->isConstantPool())
1044 bool FoundCallerPresReg =
false;
1045 if (!
MI.mayStore() ||
MI.hasUnmodeledSideEffects() ||
1046 (
MI.getNumOperands() == 0))
1055 if (Reg.isVirtual())
1057 if (Reg.isVirtual())
1059 if (!
TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *
MI.getMF()))
1062 FoundCallerPresReg =
true;
1063 }
else if (!MO.
isImm()) {
1067 return FoundCallerPresReg;
1085 Register CopySrcReg =
MI.getOperand(1).getReg();
1089 if (!
TRI->isCallerPreservedPhysReg(CopySrcReg.
asMCReg(), *MF))
1092 Register CopyDstReg =
MI.getOperand(0).getReg();
1107 bool DontMoveAcrossStore = !
HoistConstLoads || !AllowedToHoistLoads[CurLoop];
1108 if ((!
I.isSafeToMove(DontMoveAcrossStore)) &&
1121 !IsGuaranteedToExecute(
I.getParent(), CurLoop)) {
1130 if (
I.isConvergent())
1133 if (!
TII->shouldHoist(
I, CurLoop))
1142 if (!IsLICMCandidate(
I, CurLoop)) {
1143 LLVM_DEBUG(
dbgs() <<
"LICM: Instruction not a LICM candidate\n");
1155 MI = Work.pop_back_val();
1158 if (!
Reg.isVirtual())
1162 if (
UseMI.isPHI()) {
1176 Work.push_back(&
UseMI);
1179 }
while (!Work.empty());
1185bool MachineLICMImpl::HasHighOperandLatency(
MachineInstr &
MI,
unsigned DefIdx,
1188 if (
MRI->use_nodbg_empty(Reg))
1192 if (
UseMI.isCopyLike())
1196 for (
unsigned i = 0, e =
UseMI.getNumOperands(); i != e; ++i) {
1204 if (
TII->hasHighOperandLatency(SchedModel,
MRI,
MI, DefIdx,
UseMI, i))
1217bool MachineLICMImpl::IsCheapInstruction(
MachineInstr &
MI)
const {
1221 bool isCheap =
false;
1222 unsigned NumDefs =
MI.getDesc().getNumDefs();
1223 for (
unsigned i = 0, e =
MI.getNumOperands(); NumDefs && i != e; ++i) {
1229 if (
Reg.isPhysical())
1232 if (!
TII->hasLowDefLatency(SchedModel,
MI, i))
1242bool MachineLICMImpl::CanCauseHighRegPressure(
1244 for (
const auto &RPIdAndCost :
Cost) {
1245 if (RPIdAndCost.second <= 0)
1248 unsigned Class = RPIdAndCost.first;
1249 int Limit = RegLimit[
Class];
1256 for (
const auto &RP : BackTrace)
1257 if (
static_cast<int>(RP[Class]) + RPIdAndCost.second >= Limit)
1267void MachineLICMImpl::UpdateBackTraceRegPressure(
const MachineInstr *
MI) {
1270 auto Cost = calcRegisterCost(
MI,
false,
1274 for (
auto &RP : BackTrace)
1275 for (
const auto &RPIdAndCost :
Cost)
1276 RP[RPIdAndCost.first] += RPIdAndCost.second;
1283 if (
MI.isImplicitDef())
1301 bool CheapInstr = IsCheapInstruction(
MI);
1302 bool CreatesCopy = HasLoopPHIUse(&
MI, CurLoop);
1305 if (CheapInstr && CreatesCopy) {
1312 if (isTriviallyReMaterializable(
MI))
1317 for (
unsigned i = 0, e =
MI.getDesc().getNumOperands(); i != e; ++i) {
1322 if (!
Reg.isVirtual())
1324 if (MO.
isDef() && HasHighOperandLatency(
MI, i, Reg, CurLoop)) {
1337 auto Cost = calcRegisterCost(&
MI,
false,
1342 if (!CanCauseHighRegPressure(
Cost, CheapInstr)) {
1358 (!IsGuaranteedToExecute(
MI.getParent(), CurLoop) && !MayCSE(&
MI))) {
1366 if (
MI.isCopy() ||
MI.isRegSequence()) {
1371 return !UseOp.isReg() || UseOp.getReg().isVirtual() ||
1372 MRI->isConstantPhysReg(UseOp.getReg());
1374 IsLoopInvariantInst(
MI, CurLoop) &&
1375 any_of(
MRI->use_nodbg_instructions(DefReg),
1376 [&CurLoop,
this, DefReg,
1378 if (!CurLoop->contains(&UseMI))
1385 if (CanCauseHighRegPressure(Cost, false) &&
1386 !CurLoop->isLoopInvariant(UseMI, DefReg))
1396 if (!isTriviallyReMaterializable(
MI) &&
1397 !
MI.isDereferenceableInvariantLoad()) {
1411 if (
MI->canFoldAsLoad())
1417 if (!
MI->isDereferenceableInvariantLoad())
1421 unsigned LoadRegIndex;
1423 TII->getOpcodeAfterMemoryUnfold(
MI->getOpcode(),
1427 if (NewOpc == 0)
return nullptr;
1440 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
1443 "Unfolded a load into multiple instructions!");
1450 if (!IsLoopInvariantInst(*NewMIs[0], CurLoop) ||
1451 !IsProfitableToHoist(*NewMIs[0], CurLoop)) {
1452 NewMIs[0]->eraseFromParent();
1453 NewMIs[1]->eraseFromParent();
1458 UpdateRegPressure(NewMIs[1]);
1463 if (
MI->shouldUpdateCallSiteInfo())
1466 MI->eraseFromParent();
1480void MachineLICMImpl::InitializeLoadsHoistableLoops() {
1486 while (!Worklist.empty()) {
1487 auto *
L = Worklist.pop_back_val();
1488 AllowedToHoistLoads[
L] =
true;
1490 Worklist.insert(Worklist.end(),
L->getSubLoops().begin(),
1491 L->getSubLoops().end());
1504 if (!AllowedToHoistLoads[
Loop])
1506 for (
auto &
MI : *
MBB) {
1507 if (!
MI.isLoadFoldBarrier() && !
MI.mayStore() && !
MI.isCall() &&
1508 !(
MI.mayLoad() &&
MI.hasOrderedMemoryRef()))
1511 AllowedToHoistLoads[
L] =
false;
1522 std::vector<MachineInstr *> &PrevMIs) {
1524 if (
TII->produceSameValue(*
MI, *PrevMI, (PreRegAlloc ?
MRI :
nullptr)))
1534bool MachineLICMImpl::EliminateCSE(
1536 DenseMap<
unsigned, std::vector<MachineInstr *>>::iterator &CI) {
1539 if (
MI->isImplicitDef())
1544 if (
MI->mayLoad() && !
MI->isDereferenceableInvariantLoad())
1553 for (
unsigned i = 0, e =
MI->getNumOperands(); i != e; ++i) {
1558 MO.
getReg() == Dup->getOperand(i).getReg()) &&
1559 "Instructions with different phys regs are not identical!");
1566 for (
unsigned i = 0, e = Defs.
size(); i != e; ++i) {
1567 unsigned Idx = Defs[i];
1572 if (!
MRI->constrainRegClass(DupReg,
MRI->getRegClass(Reg))) {
1574 for (
unsigned j = 0;
j != i; ++
j)
1575 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
1580 for (
unsigned Idx : Defs) {
1583 MRI->replaceRegWith(Reg, DupReg);
1584 MRI->clearKillFlags(DupReg);
1586 if (!
MRI->use_nodbg_empty(DupReg))
1587 Dup->getOperand(
Idx).setIsDead(
false);
1590 MI->eraseFromParent();
1600 if (
MI->mayLoad() && !
MI->isDereferenceableInvariantLoad())
1603 unsigned Opcode =
MI->getOpcode();
1604 for (
auto &Map : CSEMap) {
1608 Map.second.find(Opcode);
1611 if (CI ==
Map.second.end() ||
MI->isImplicitDef())
1613 if (LookForDuplicate(
MI, CI->second) !=
nullptr)
1631 isTgtHotterThanSrc(SrcBlock, Preheader)) {
1632 ++NumNotHoistedDueToHotness;
1633 return HoistResult::NotHoisted;
1636 bool HasExtractHoistableLoad =
false;
1637 if (!IsLoopInvariantInst(*
MI, CurLoop) ||
1638 !IsProfitableToHoist(*
MI, CurLoop)) {
1640 MI = ExtractHoistableLoad(
MI, CurLoop);
1642 return HoistResult::NotHoisted;
1643 HasExtractHoistableLoad =
true;
1654 dbgs() <<
"Hoisting " << *
MI;
1655 if (
MI->getParent()->getBasicBlock())
1665 InitCSEMap(Preheader);
1666 FirstInLoop =
false;
1670 unsigned Opcode =
MI->getOpcode();
1671 bool HasCSEDone =
false;
1672 for (
auto &Map : CSEMap) {
1676 Map.second.find(Opcode);
1677 if (CI !=
Map.second.end()) {
1678 if (EliminateCSE(
MI, CI)) {
1693 assert(!
MI->isDebugInstr() &&
"Should not hoist debug inst");
1697 UpdateBackTraceRegPressure(
MI);
1706 CSEMap[Preheader][Opcode].push_back(
MI);
1712 if (HasCSEDone || HasExtractHoistableLoad)
1713 return HoistResult::Hoisted | HoistResult::ErasedMI;
1714 return HoistResult::Hoisted;
1719MachineLICMImpl::getCurPreheader(
MachineLoop *CurLoop,
1728 if (!CurPreheader) {
1730 if (!CurPreheader) {
1738 MFAM,
nullptr, MDTU);
1739 if (!CurPreheader) {
1745 return CurPreheader;
1760 double Ratio = (double)DstBF / SrcBF;
1766template <
typename DerivedT,
bool PreRegAlloc>
1769 bool Changed = MachineLICMImpl(PreRegAlloc,
nullptr, &MFAM).run(MF);
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
This file implements the BitVector class.
COFF::MachineTypes Machine
Analysis containing CSE Info
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
const HexagonInstrInfo * TII
static bool isExitBlock(BasicBlock *BB, const SmallVectorImpl< BasicBlock * > &ExitBlocks)
Return true if the specified block is in the list.
Machine Loop Invariant Code false early machinelicm
static cl::opt< bool > HoistConstStores("hoist-const-stores", cl::desc("Hoist invariant stores"), cl::init(true), cl::Hidden)
#define GET_RESULT(RESULT, GETTER, INFIX)
static cl::opt< UseBFI > DisableHoistingToHotterBlocks("disable-hoisting-to-hotter-blocks", cl::desc("Disable hoisting instructions to" " hotter blocks"), cl::init(UseBFI::PGO), cl::Hidden, cl::values(clEnumValN(UseBFI::None, "none", "disable the feature"), clEnumValN(UseBFI::PGO, "pgo", "enable the feature when using profile data"), clEnumValN(UseBFI::All, "all", "enable the feature with/wo profile data")))
static bool mayLoadFromGOTOrConstantPool(MachineInstr &MI)
Return true if this machine instruction loads from global offset table or constant pool.
static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI)
static cl::opt< bool > HoistConstLoads("hoist-const-loads", cl::desc("Hoist invariant loads"), cl::init(true), cl::Hidden)
Machine Loop Invariant Code Motion
static cl::opt< bool > AvoidSpeculation("avoid-speculation", cl::desc("MachineLICM should avoid speculation"), cl::init(true), cl::Hidden)
static bool InstructionStoresToFI(const MachineInstr *MI, int FI)
Return true if instruction stores to the specified frame.
static bool isCopyFeedingInvariantStore(const MachineInstr &MI, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI)
static void applyBitsNotInRegMaskToRegUnitsMask(const TargetRegisterInfo &TRI, BitVector &RUs, const uint32_t *Mask)
static cl::opt< bool > HoistCheapInsts("hoist-cheap-insts", cl::desc("MachineLICM should hoist even cheap instructions"), cl::init(false), cl::Hidden)
static bool isInvariantStore(const MachineInstr &MI, const TargetRegisterInfo *TRI, const MachineRegisterInfo *MRI)
static cl::opt< unsigned > BlockFrequencyRatioThreshold("block-freq-ratio-threshold", cl::desc("Do not hoist instructions if target" "block is N times hotter than the source."), cl::init(100), cl::Hidden)
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
This file describes how to lower LLVM code to machine code.
A manager for alias analyses.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
AAResults & getAAResults()
A container for analyses that lazily runs them and caches their results.
PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)
Get the result of an analysis pass for a given IR unit.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
bool test(unsigned Idx) const
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
std::pair< iterator, bool > try_emplace(KeyT &&Key, Ts &&...Args)
Base class for the actual dominator tree node.
DomTreeNodeBase< NodeT > * getNode(const NodeT *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
bool hasProfileData(bool IncludeSynthetic=false) const
Return true if the function is annotated with profile data.
DomTreeT & getDomTree()
Flush DomTree updates and return DomTree.
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
void getExitBlocks(SmallVectorImpl< BlockT * > &ExitBlocks) const
Return all of the successor blocks of this loop.
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
BlockT * getHeader() const
iterator_range< block_iterator > blocks() const
BlockT * getLoopPredecessor() const
If the given loop's header has exactly one unique predecessor outside the loop, return it.
BlockT * getLoopPreheader() const
If there is a preheader for this loop, return it.
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Represents a single loop in the control flow graph.
Describe properties that are true of each instruction in the target description file.
bool isValid() const
Returns true if this iterator is not yet at the end.
Wrapper class representing physical registers. Should be passed by value.
unsigned pred_size() const
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P, std::vector< SparseBitVector<> > *LiveInSets=nullptr, MachineDomTreeUpdater *MDTU=nullptr)
Split the critical edge from this block to the given successor block, and return the newly created bl...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned succ_size() const
pred_iterator pred_begin()
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
Analysis pass which computes a MachineDominatorTree.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool dominates(const MachineInstr *A, const MachineInstr *B) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
void eraseCallSiteInfo(const MachineInstr *MI)
Following functions update call site info.
Representation of each machine instruction.
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
Analysis pass that exposes the MachineLoopInfo for a machine function.
bool isLoopInvariant(MachineInstr &I, const Register ExcludeReg=0) const
Returns true if the instruction is loop invariant.
A description of a memory reference used in the backend.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
AnalysisType & getAnalysis() const
getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information ...
A set of analyses that are preserved following a run of a transformation pass.
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Implements a dense probed hash-table based set with some number of buckets stored inline.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
TargetSubtargetInfo - Generic base class for all target subtargets.
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
Reg
All possible values of the reg field in the ModR/M byte.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
initializer< Ty > init(const Ty &Val)
PointerTypeMap run(const Module &M)
Compute the PointerTypeMap for the module M.
NodeAddr< DefNode * > Def
This is an optimization pass for GlobalISel generic memory operations.
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
auto reverse(ContainerTy &&C)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void initializeMachineLICMPass(PassRegistry &)
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
void initializeEarlyMachineLICMPass(PassRegistry &)
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...