LLVM  15.0.0git
AccelTable.h
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1 //==- include/llvm/CodeGen/AccelTable.h - Accelerator Tables -----*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file contains support for writing accelerator tables.
10 ///
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_ACCELTABLE_H
14 #define LLVM_CODEGEN_ACCELTABLE_H
15 
16 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/StringMap.h"
19 #include "llvm/ADT/StringRef.h"
21 #include "llvm/CodeGen/DIE.h"
23 #include "llvm/Support/Allocator.h"
24 #include "llvm/Support/DJB.h"
25 #include "llvm/Support/Debug.h"
26 #include <cstdint>
27 #include <vector>
28 
29 /// \file
30 /// The DWARF and Apple accelerator tables are an indirect hash table optimized
31 /// for null lookup rather than access to known data. The Apple accelerator
32 /// tables are a precursor of the newer DWARF v5 accelerator tables. Both
33 /// formats share common design ideas.
34 ///
35 /// The Apple accelerator table are output into an on-disk format that looks
36 /// like this:
37 ///
38 /// .------------------.
39 /// | HEADER |
40 /// |------------------|
41 /// | BUCKETS |
42 /// |------------------|
43 /// | HASHES |
44 /// |------------------|
45 /// | OFFSETS |
46 /// |------------------|
47 /// | DATA |
48 /// `------------------'
49 ///
50 /// The header contains a magic number, version, type of hash function,
51 /// the number of buckets, total number of hashes, and room for a special struct
52 /// of data and the length of that struct.
53 ///
54 /// The buckets contain an index (e.g. 6) into the hashes array. The hashes
55 /// section contains all of the 32-bit hash values in contiguous memory, and the
56 /// offsets contain the offset into the data area for the particular hash.
57 ///
58 /// For a lookup example, we could hash a function name and take it modulo the
59 /// number of buckets giving us our bucket. From there we take the bucket value
60 /// as an index into the hashes table and look at each successive hash as long
61 /// as the hash value is still the same modulo result (bucket value) as earlier.
62 /// If we have a match we look at that same entry in the offsets table and grab
63 /// the offset in the data for our final match.
64 ///
65 /// The DWARF v5 accelerator table consists of zero or more name indices that
66 /// are output into an on-disk format that looks like this:
67 ///
68 /// .------------------.
69 /// | HEADER |
70 /// |------------------|
71 /// | CU LIST |
72 /// |------------------|
73 /// | LOCAL TU LIST |
74 /// |------------------|
75 /// | FOREIGN TU LIST |
76 /// |------------------|
77 /// | HASH TABLE |
78 /// |------------------|
79 /// | NAME TABLE |
80 /// |------------------|
81 /// | ABBREV TABLE |
82 /// |------------------|
83 /// | ENTRY POOL |
84 /// `------------------'
85 ///
86 /// For the full documentation please refer to the DWARF 5 standard.
87 ///
88 ///
89 /// This file defines the class template AccelTable, which is represents an
90 /// abstract view of an Accelerator table, without any notion of an on-disk
91 /// layout. This class is parameterized by an entry type, which should derive
92 /// from AccelTableData. This is the type of individual entries in the table,
93 /// and it should store the data necessary to emit them. AppleAccelTableData is
94 /// the base class for Apple Accelerator Table entries, which have a uniform
95 /// structure based on a sequence of Atoms. There are different sub-classes
96 /// derived from AppleAccelTable, which differ in the set of Atoms and how they
97 /// obtain their values.
98 ///
99 /// An Apple Accelerator Table can be serialized by calling emitAppleAccelTable
100 /// function.
101 
102 namespace llvm {
103 
104 class AsmPrinter;
105 class DwarfCompileUnit;
106 class DwarfDebug;
107 class MCSymbol;
108 class raw_ostream;
109 
110 /// Interface which the different types of accelerator table data have to
111 /// conform. It serves as a base class for different values of the template
112 /// argument of the AccelTable class template.
114 public:
115  virtual ~AccelTableData() = default;
116 
117  bool operator<(const AccelTableData &Other) const {
118  return order() < Other.order();
119  }
120 
121  // Subclasses should implement:
122  // static uint32_t hash(StringRef Name);
123 
124 #ifndef NDEBUG
125  virtual void print(raw_ostream &OS) const = 0;
126 #endif
127 protected:
128  virtual uint64_t order() const = 0;
129 };
130 
131 /// A base class holding non-template-dependant functionality of the AccelTable
132 /// class. Clients should not use this class directly but rather instantiate
133 /// AccelTable with a type derived from AccelTableData.
135 public:
137 
138  /// Represents a group of entries with identical name (and hence, hash value).
139  struct HashData {
142  std::vector<AccelTableData *> Values;
144 
146  : Name(Name), HashValue(Hash(Name.getString())) {}
147 
148 #ifndef NDEBUG
149  void print(raw_ostream &OS) const;
150  void dump() const { print(dbgs()); }
151 #endif
152  };
153  using HashList = std::vector<HashData *>;
154  using BucketList = std::vector<HashList>;
155 
156 protected:
157  /// Allocator for HashData and Values.
159 
162 
166 
169 
170  void computeBucketCount();
171 
173 
174 public:
177  uint32_t getBucketCount() const { return BucketCount; }
179  uint32_t getUniqueNameCount() const { return Entries.size(); }
180 
181 #ifndef NDEBUG
182  void print(raw_ostream &OS) const;
183  void dump() const { print(dbgs()); }
184 #endif
185 
186  AccelTableBase(const AccelTableBase &) = delete;
187  void operator=(const AccelTableBase &) = delete;
188 };
189 
190 /// This class holds an abstract representation of an Accelerator Table,
191 /// consisting of a sequence of buckets, each bucket containint a sequence of
192 /// HashData entries. The class is parameterized by the type of entries it
193 /// holds. The type template parameter also defines the hash function to use for
194 /// hashing names.
195 template <typename DataT> class AccelTable : public AccelTableBase {
196 public:
197  AccelTable() : AccelTableBase(DataT::hash) {}
198 
199  template <typename... Types>
200  void addName(DwarfStringPoolEntryRef Name, Types &&... Args);
201 };
202 
203 template <typename AccelTableDataT>
204 template <typename... Types>
206  Types &&... Args) {
207  assert(Buckets.empty() && "Already finalized!");
208  // If the string is in the list already then add this die to the list
209  // otherwise add a new one.
210  auto Iter = Entries.try_emplace(Name.getString(), Name, Hash).first;
211  assert(Iter->second.Name == Name);
212  Iter->second.Values.push_back(
213  new (Allocator) AccelTableDataT(std::forward<Types>(Args)...));
214 }
215 
216 /// A base class for different implementations of Data classes for Apple
217 /// Accelerator Tables. The columns in the table are defined by the static Atoms
218 /// variable defined on the subclasses.
220 public:
221  /// An Atom defines the form of the data in an Apple accelerator table.
222  /// Conceptually it is a column in the accelerator consisting of a type and a
223  /// specification of the form of its data.
224  struct Atom {
225  /// Atom Type.
226  const uint16_t Type;
227  /// DWARF Form.
228  const uint16_t Form;
229 
231 
232 #ifndef NDEBUG
233  void print(raw_ostream &OS) const;
234  void dump() const { print(dbgs()); }
235 #endif
236  };
237  // Subclasses should define:
238  // static constexpr Atom Atoms[];
239 
240  virtual void emit(AsmPrinter *Asm) const = 0;
241 
242  static uint32_t hash(StringRef Buffer) { return djbHash(Buffer); }
243 };
244 
245 /// The Data class implementation for DWARF v5 accelerator table. Unlike the
246 /// Apple Data classes, this class is just a DIE wrapper, and does not know to
247 /// serialize itself. The complete serialization logic is in the
248 /// emitDWARF5AccelTable function.
250 public:
252 
254 
255 #ifndef NDEBUG
256  void print(raw_ostream &OS) const override;
257 #endif
258 
259  const DIE &getDie() const { return Die; }
260  uint64_t getDieOffset() const { return Die.getOffset(); }
261  unsigned getDieTag() const { return Die.getTag(); }
262 
263 protected:
264  const DIE &Die;
265 
266  uint64_t order() const override { return Die.getOffset(); }
267 };
268 
270 public:
272 
274  unsigned CUIndex)
276 
277 #ifndef NDEBUG
278  void print(raw_ostream &OS) const override;
279 #endif
280 
281  uint64_t getDieOffset() const { return DieOffset; }
282  unsigned getDieTag() const { return DieTag; }
283  unsigned getCUIndex() const { return CUIndex; }
284 
285 protected:
287  unsigned DieTag;
288  unsigned CUIndex;
289 
290  uint64_t order() const override { return DieOffset; }
291 };
292 
293 void emitAppleAccelTableImpl(AsmPrinter *Asm, AccelTableBase &Contents,
294  StringRef Prefix, const MCSymbol *SecBegin,
295  ArrayRef<AppleAccelTableData::Atom> Atoms);
296 
297 /// Emit an Apple Accelerator Table consisting of entries in the specified
298 /// AccelTable. The DataT template parameter should be derived from
299 /// AppleAccelTableData.
300 template <typename DataT>
302  StringRef Prefix, const MCSymbol *SecBegin) {
303  static_assert(std::is_convertible<DataT *, AppleAccelTableData *>::value, "");
304  emitAppleAccelTableImpl(Asm, Contents, Prefix, SecBegin, DataT::Atoms);
305 }
306 
307 void emitDWARF5AccelTable(AsmPrinter *Asm,
308  AccelTable<DWARF5AccelTableData> &Contents,
309  const DwarfDebug &DD,
310  ArrayRef<std::unique_ptr<DwarfCompileUnit>> CUs);
311 
313  AsmPrinter *Asm, AccelTable<DWARF5AccelTableStaticData> &Contents,
314  ArrayRef<MCSymbol *> CUs,
315  llvm::function_ref<unsigned(const DWARF5AccelTableStaticData &)>
316  getCUIndexForEntry);
317 
318 /// Accelerator table data implementation for simple Apple accelerator tables
319 /// with just a DIE reference.
321 public:
323 
324  void emit(AsmPrinter *Asm) const override;
325 
326  static constexpr Atom Atoms[] = {
327  Atom(dwarf::DW_ATOM_die_offset, dwarf::DW_FORM_data4)};
328 
329 #ifndef NDEBUG
330  void print(raw_ostream &OS) const override;
331 #endif
332 protected:
333  uint64_t order() const override { return Die.getOffset(); }
334 
335  const DIE &Die;
336 };
337 
338 /// Accelerator table data implementation for Apple type accelerator tables.
340 public:
342 
343  void emit(AsmPrinter *Asm) const override;
344 
345  static constexpr Atom Atoms[] = {
346  Atom(dwarf::DW_ATOM_die_offset, dwarf::DW_FORM_data4),
347  Atom(dwarf::DW_ATOM_die_tag, dwarf::DW_FORM_data2),
348  Atom(dwarf::DW_ATOM_type_flags, dwarf::DW_FORM_data1)};
349 
350 #ifndef NDEBUG
351  void print(raw_ostream &OS) const override;
352 #endif
353 };
354 
355 /// Accelerator table data implementation for simple Apple accelerator tables
356 /// with a DIE offset but no actual DIE pointer.
358 public:
360 
361  void emit(AsmPrinter *Asm) const override;
362 
363  static constexpr Atom Atoms[] = {
364  Atom(dwarf::DW_ATOM_die_offset, dwarf::DW_FORM_data4)};
365 
366 #ifndef NDEBUG
367  void print(raw_ostream &OS) const override;
368 #endif
369 protected:
370  uint64_t order() const override { return Offset; }
371 
373 };
374 
375 /// Accelerator table data implementation for type accelerator tables with
376 /// a DIE offset but no actual DIE pointer.
378 public:
385 
386  void emit(AsmPrinter *Asm) const override;
387 
388  static constexpr Atom Atoms[] = {
389  Atom(dwarf::DW_ATOM_die_offset, dwarf::DW_FORM_data4),
390  Atom(dwarf::DW_ATOM_die_tag, dwarf::DW_FORM_data2),
391  Atom(5, dwarf::DW_FORM_data1), Atom(6, dwarf::DW_FORM_data4)};
392 
393 #ifndef NDEBUG
394  void print(raw_ostream &OS) const override;
395 #endif
396 protected:
397  uint64_t order() const override { return Offset; }
398 
402 };
403 
404 } // end namespace llvm
405 
406 #endif // LLVM_CODEGEN_ACCELTABLE_H
llvm::InlinePass::AlwaysInliner
@ AlwaysInliner
AMDGPUCombinerHelper
Definition: AMDGPUCombinerHelper.h:20
MipsGenSubtargetInfo
Signposts
static ManagedStatic< SignpostEmitter > Signposts
Allows llvm::Timer to emit signposts when supported.
Definition: Timer.cpp:56
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:437
CSKYGenInstrInfo
block
we get the following basic block
Definition: README_ALTIVEC.txt:95
llvm::objcarc::ARCInstKind::User
@ User
could "use" a pointer
is
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That is
Definition: README.txt:725
llvm::DWARF5AccelTableStaticData::order
uint64_t order() const override
Definition: AccelTable.h:290
SPIRVGenRegisterInfo
ARCGenRegisterInfo
llvm::AccelTableBase::HashData::dump
void dump() const
Definition: AccelTable.h:150
llvm::DWARF5AccelTableStaticData::DieTag
unsigned DieTag
Definition: AccelTable.h:287
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
SPIRVGenInstrInfo
intrinsic
QP Compare Ordered outs ins xscmpudp No intrinsic
Definition: README_P9.txt:303
llvm::AccelTableBase::getBucketCount
uint32_t getBucketCount() const
Definition: AccelTable.h:177
llvm::RegAllocType::PBQP
@ PBQP
llvm::dwarf::Constants
Constants
Definition: Dwarf.h:432
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
Pass
print lazy value Lazy Value Info Printer Pass
Definition: LazyValueInfo.cpp:1979
it
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in it
Definition: README-SSE.txt:81
SET
#define SET(ID, TYPE, VAL)
llvm::lltok::Error
@ Error
Definition: LLToken.h:21
LanaiGenSubtargetInfo
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
DJB.h
llvm::object::RelocationResolver
uint64_t(*)(uint64_t Type, uint64_t Offset, uint64_t S, uint64_t LocData, int64_t Addend) RelocationResolver
Definition: RelocationResolver.h:30
ARMGenSubtargetInfo
llvm::cl::Prefix
@ Prefix
Definition: CommandLine.h:160
llvm::AccelTableBase::UniqueHashCount
uint32_t UniqueHashCount
Definition: AccelTable.h:165
llvm::SSAContext
GenericSSAContext< Function > SSAContext
Definition: SSAContext.h:48
MSP430GenInstrInfo
cpp
test_demangle cpp
Definition: README.txt:55
M68kDisassembler
A disassembler class for M68k.
Definition: M68kDisassembler.cpp:100
llvm::AppleAccelTableStaticOffsetData::Offset
uint32_t Offset
Definition: AccelTable.h:372
LanaiGenInstrInfo
AMDGPUMCInstLower
Definition: AMDGPUMCInstLower.h:29
StringRef.h
llvm::AppleAccelTableData::Atom::Form
const uint16_t Form
DWARF Form.
Definition: AccelTable.h:228
llvm::dwarf::DW_ATOM_die_offset
@ DW_ATOM_die_offset
Marker as the end of a list of atoms.
Definition: Dwarf.h:509
XCoreGenRegisterInfo
llvm::DWARF5AccelTableStaticData::DieOffset
uint64_t DieOffset
Definition: AccelTable.h:286
llvm::Statistic
TrackingStatistic Statistic
Definition: Statistic.h:160
llvm::AliasAnalysis
AAResults AliasAnalysis
Temporary typedef for legacy code that uses a generic AliasAnalysis pointer or reference.
Definition: AliasAnalysis.h:1002
SparcGenSubtargetInfo
AArch64GenRegisterInfo
tools
The object format emitted by the WebAssembly backed is documented see the home tools
Definition: README.txt:16
llvm::dwarf::Form
Form
Definition: Dwarf.h:132
td
Decimal Convert From to National Zoned Signed int_ppc_altivec_bcdcfno int_ppc_altivec_bcdcfzo int_ppc_altivec_bcdctno int_ppc_altivec_bcdctzo int_ppc_altivec_bcdcfsqo int_ppc_altivec_bcdctsqo int_ppc_altivec_bcdcpsgno int_ppc_altivec_bcdsetsgno int_ppc_altivec_bcdso int_ppc_altivec_bcduso int_ppc_altivec_bcdsro i e VA byte[7] Decimal(Unsigned) Truncate Define DAG Node in PPCInstrInfo td
Definition: README_P9.txt:166
MSP430GenSubtargetInfo
llvm::AccelTableBase::Hash
HashFn * Hash
Definition: AccelTable.h:163
llvm::AccelTable::addName
void addName(DwarfStringPoolEntryRef Name, Types &&... Args)
Definition: AccelTable.h:205
Allocator.h
MSP430GenRegisterInfo
llvm::CGSCCPassManager
PassManager< LazyCallGraph::SCC, CGSCCAnalysisManager, LazyCallGraph &, CGSCCUpdateResult & > CGSCCPassManager
The CGSCC pass manager.
Definition: CGSCCPassManager.h:144
llvm::lltok::APSInt
@ APSInt
Definition: LLToken.h:438
Passes
const char * Passes
Definition: PassBuilderBindings.cpp:46
to
Should compile to
Definition: README.txt:449
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
Instructions
Code Generation Notes for reduce the size of the ISel and reduce repetition in the implementation In a small number of this can cause even when no optimisation has taken place Instructions
Definition: MSA.txt:11
llvm::AppleAccelTableStaticTypeData::ObjCClassIsImplementation
bool ObjCClassIsImplementation
Definition: AccelTable.h:401
AMDGPUSubtarget
#define AMDGPUSubtarget
Definition: AMDGPUInstructionSelector.cpp:42
llvm::AccelTableBase::Hashes
HashList Hashes
Definition: AccelTable.h:167
llvm::AppleAccelTableData::Atom::dump
void dump() const
Definition: AccelTable.h:234
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:855
SystemZGenInstrInfo
LanaiGenRegisterInfo
impl
place backedge safepoints impl
Definition: PlaceSafepoints.cpp:613
llvm::AccelTableBase::Entries
StringEntries Entries
Definition: AccelTable.h:161
llvm::DIE
A structured debug information entry.
Definition: DIE.h:739
add_llvm_component_library
add_llvm_component_library(LLVMFuzzerCLI FuzzerCLI.cpp PARTIAL_SOURCES_INTENDED ADDITIONAL_HEADER_DIRS ${LLVM_MAIN_INCLUDE_DIR}/llvm/FuzzMutate LINK_COMPONENTS Support) add_llvm_component_library(LLVMFuzzMutate IRMutator.cpp OpDescriptor.cpp Operations.cpp RandomIRBuilder.cpp PARTIAL_SOURCES_INTENDED ADDITIONAL_HEADER_DIRS $
Definition: CMakeLists.txt:3
llvm::AppleAccelTableTypeData::print
void print(raw_ostream &OS) const override
Definition: AccelTable.cpp:693
llvm::AccelTable
This class holds an abstract representation of an Accelerator Table, consisting of a sequence of buck...
Definition: AccelTable.h:195
patch
this could be done in SelectionDAGISel along with other special bytes It would be nice to revert this patch
Definition: README.txt:104
llvm::DIE::getTag
dwarf::Tag getTag() const
Definition: DIE.h:775
llvm::DWARF5AccelTableStaticData::CUIndex
unsigned CUIndex
Definition: AccelTable.h:288
llvm::dwarf::Tag
Tag
Definition: Dwarf.h:105
llvm::msgpack::Type::Binary
@ Binary
llvm::AppleAccelTableOffsetData::AppleAccelTableOffsetData
AppleAccelTableOffsetData(const DIE &D)
Definition: AccelTable.h:322
and
We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 and
Definition: README.txt:1271
x86
Note that only the low bits of effective_addr2 are used On bit we don t eliminate the computation of the top half of effective_addr2 because we don t have whole function selection dags On x86
Definition: README.txt:318
SpecialSubKind::allocator
@ allocator
llvm::AppleAccelTableData::Atom::Atom
constexpr Atom(uint16_t Type, uint16_t Form)
Definition: AccelTable.h:230
llvm::WinEH::EncodingType::ARM
@ ARM
Windows AXP64.
llvm::AccelTableData::order
virtual uint64_t order() const =0
llvm::AccelTableData
Interface which the different types of accelerator table data have to conform.
Definition: AccelTable.h:113
RISCVGenInstrInfo
DirectXGenRegisterInfo
endif
__FakeVCSRevision h endif() endif() set(generated_files "$
Definition: CMakeLists.txt:16
llvm::AppleAccelTableStaticTypeData::order
uint64_t order() const override
Definition: AccelTable.h:397
llvm::DwarfStringPoolEntryRef
String pool entry reference.
Definition: DwarfStringPoolEntry.h:31
R600GenInstrInfo
library
Itanium Name Demangler i e convert the string _Z1fv into and both[sub] projects need to demangle but neither can depend on each other *libcxxabi needs the demangler to implement which is part of the itanium ABI spec *LLVM needs a copy for a bunch of and cannot rely on the system s __cxa_demangle because it a might not be and b may not be up to date on the latest language features The copy of the demangler in LLVM has some extra stuff that aren t needed in which depend on the shared generic components Despite these we want to keep the core generic demangling library identical between both copies to simplify development and testing If you re working on the generic library
Definition: README.txt:36
AVRGenSubtargetInfo
attrs
function attrs
Definition: FunctionAttrs.cpp:1941
else
CodeGen else() add_llvm_component_group(Native) add_llvm_component_group(NativeCodeGen) endif() LLVMBuildResolveComponentsLink() LLVMBuildGenerateCFragment(OUTPUT $
Definition: CMakeLists.txt:58
LiveDebugValues
Definition: InstrRefBasedImpl.h:30
llvm::AccelTableBase::operator=
void operator=(const AccelTableBase &)=delete
elseif
rpmalloc rpmalloc c elseif(LLVM_INTEGRATED_CRT_ALLOC MATCHES "snmalloc$") set(ALLOCATOR_FILES "$
Definition: CMakeLists.txt:92
HexagonGenInstrInfo
XCoreGenSubtargetInfo
llvm::AppleAccelTableStaticOffsetData::order
uint64_t order() const override
Definition: AccelTable.h:370
llvm::AccelTableData::operator<
bool operator<(const AccelTableData &Other) const
Definition: AccelTable.h:117
SPIRVGenSubtargetInfo
llvm::AccelTableBase::computeBucketCount
void computeBucketCount()
Definition: AccelTable.cpp:33
X86GenRegisterInfo
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::DWARF5AccelTableData::print
void print(raw_ostream &OS) const override
Definition: AccelTable.cpp:679
VEGenSubtargetInfo
include
include(LLVM-Build) add_subdirectory(IR) add_subdirectory(FuzzMutate) add_subdirectory(FileCheck) add_subdirectory(InterfaceStub) add_subdirectory(IRReader) add_subdirectory(CodeGen) add_subdirectory(BinaryFormat) add_subdirectory(Bitcode) add_subdirectory(Bitstream) add_subdirectory(DWARFLinker) add_subdirectory(Extensions) add_subdirectory(Frontend) add_subdirectory(Transforms) add_subdirectory(Linker) add_subdirectory(Analysis) add_subdirectory(LTO) add_subdirectory(MC) add_subdirectory(MCA) add_subdirectory(ObjCopy) add_subdirectory(Object) add_subdirectory(ObjectYAML) add_subdirectory(Option) add_subdirectory(Remarks) add_subdirectory(Debuginfod) add_subdirectory(DebugInfo) add_subdirectory(DWP) add_subdirectory(ExecutionEngine) add_subdirectory(Target) add_subdirectory(AsmParser) add_subdirectory(LineEditor) add_subdirectory(ProfileData) add_subdirectory(Passes) add_subdirectory(TextAPI) add_subdirectory(ToolDrivers) add_subdirectory(XRay) if(LLVM_INCLUDE_TESTS) add_subdirectory(Testing) endif() add_subdirectory(WindowsDriver) add_subdirectory(WindowsManifest) set(LLVMCONFIGLIBRARYDEPENDENCIESINC "$
Definition: CMakeLists.txt:1
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::emitAppleAccelTable
void emitAppleAccelTable(AsmPrinter *Asm, AccelTable< DataT > &Contents, StringRef Prefix, const MCSymbol *SecBegin)
Emit an Apple Accelerator Table consisting of entries in the specified AccelTable.
Definition: AccelTable.h:301
BranchRelaxation
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
AArch64GenInstrInfo
MipsGenRegisterInfo
llvm::MODULE
@ MODULE
Definition: Attributor.h:5032
llvm::orc::tpctypes::LookupResult
std::vector< JITTargetAddress > LookupResult
Definition: TargetProcessControlTypes.h:119
llvm::objcopy::FileFormat::ELF
@ ELF
llvm::SmallVector
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
Definition: SmallVector.h:1112
llvm::AppleAccelTableStaticTypeData::Tag
uint16_t Tag
Definition: AccelTable.h:400
llvm::cl::apply
void apply(Opt *O, const Mod &M, const Mods &... Ms)
Definition: CommandLine.h:1280
llvm::AppleAccelTableStaticTypeData::emit
void emit(AsmPrinter *Asm) const override
Definition: AccelTable.cpp:607
LoongArchGenInstrInfo
AVRGenInstrInfo
llvm::AppleAccelTableData::emit
virtual void emit(AsmPrinter *Asm) const =0
llvm::AccelTableBase::AccelTableBase
AccelTableBase(HashFn *Hash)
Definition: AccelTable.h:172
llvm::dwarf::DW_ATOM_die_tag
@ DW_ATOM_die_tag
Definition: Dwarf.h:512
llvm::AppleAccelTableData::Atom
An Atom defines the form of the data in an Apple accelerator table.
Definition: AccelTable.h:224
llvm::zlib::compress
void compress(StringRef InputBuffer, SmallVectorImpl< char > &CompressedBuffer, int Level=DefaultCompression)
Definition: Compression.cpp:49
LoopPredication
static cl::opt< bool > LoopPredication("indvars-predicate-loops", cl::Hidden, cl::init(true), cl::desc("Predicate conditions in read only loops"))
BPFGenSubtargetInfo
llvm::AccelTableBase::HashData
Represents a group of entries with identical name (and hence, hash value).
Definition: AccelTable.h:139
source_group
source_group(${group} FILES ${ARGN}) endmacro() if(LLVM_ENABLE_DIA_SDK) include_directories(SYSTEM $
Definition: CMakeLists.txt:3
llvm::AppleAccelTableData::hash
static uint32_t hash(StringRef Buffer)
Definition: AccelTable.h:242
X86GenInstrInfo
t
bitcast float %x to i32 %s=and i32 %t, 2147483647 %d=bitcast i32 %s to float ret float %d } declare float @fabsf(float %n) define float @bar(float %x) nounwind { %d=call float @fabsf(float %x) ret float %d } This IR(from PR6194):target datalayout="e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple="x86_64-apple-darwin10.0.0" %0=type { double, double } %struct.float3=type { float, float, float } define void @test(%0, %struct.float3 *nocapture %res) nounwind noinline ssp { entry:%tmp18=extractvalue %0 %0, 0 t
Definition: README-SSE.txt:788
SPIRVObjectWriter
Definition: SPIRVObjectWriter.cpp:17
llvm::AccelTableBase::Allocator
BumpPtrAllocator Allocator
Allocator for HashData and Values.
Definition: AccelTable.h:158
llvm::AppleAccelTableStaticOffsetData
Accelerator table data implementation for simple Apple accelerator tables with a DIE offset but no ac...
Definition: AccelTable.h:357
M68kGenInstrInfo
group
bb420 i The CBE manages to mtctr r0 r11 stbx r9 addi bdz later b loop This could be much the loop would be a single dispatch group
Definition: README.txt:61
NVPTXGenInstrInfo
opt
arm prera ldst opt
Definition: ARMLoadStoreOptimizer.cpp:2191
llvm::AppleAccelTableStaticOffsetData::emit
void emit(AsmPrinter *Asm) const override
Definition: AccelTable.cpp:603
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
list
llvm DebugInfo PDB Native list(APPEND LIBPDB_ADDITIONAL_HEADER_DIRS "${LLVM_MAIN_INCLUDE_DIR}/llvm/DebugInfo/PDB") add_llvm_component_library(LLVMDebugInfoPDB GenericError.cpp IPDBSourceFile.cpp PDB.cpp PDBContext.cpp PDBExtras.cpp PDBInterfaceAnchors.cpp PDBSymbol.cpp PDBSymbolAnnotation.cpp PDBSymbolBlock.cpp PDBSymbolCompiland.cpp PDBSymbolCompilandDetails.cpp PDBSymbolCompilandEnv.cpp PDBSymbolCustom.cpp PDBSymbolData.cpp PDBSymbolExe.cpp PDBSymbolFunc.cpp PDBSymbolFuncDebugEnd.cpp PDBSymbolFuncDebugStart.cpp PDBSymbolLabel.cpp PDBSymbolPublicSymbol.cpp PDBSymbolThunk.cpp PDBSymbolTypeArray.cpp PDBSymbolTypeBaseClass.cpp PDBSymbolTypeBuiltin.cpp PDBSymbolTypeCustom.cpp PDBSymbolTypeDimension.cpp PDBSymbolTypeEnum.cpp PDBSymbolTypeFriend.cpp PDBSymbolTypeFunctionArg.cpp PDBSymbolTypeFunctionSig.cpp PDBSymbolTypeManaged.cpp PDBSymbolTypePointer.cpp PDBSymbolTypeTypedef.cpp PDBSymbolTypeUDT.cpp PDBSymbolTypeVTable.cpp PDBSymbolTypeVTableShape.cpp PDBSymbolUnknown.cpp PDBSymbolUsingNamespace.cpp PDBSymDumper.cpp UDTLayout.cpp $
Definition: CMakeLists.txt:100
ARMGenRegisterInfo
be
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can be
Definition: README.txt:14
AArch64GenSubtargetInfo
llvm::AccelTable::AccelTable
AccelTable()
Definition: AccelTable.h:197
InlineInfo
@ InlineInfo
Definition: FunctionInfo.cpp:24
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::ExceptionHandling::Wasm
@ Wasm
WebAssembly Exception Handling.
HexagonGenSubtargetInfo
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::SPIRV::BuiltIn::Layer
@ Layer
llvm::AppleAccelTableStaticOffsetData::AppleAccelTableStaticOffsetData
AppleAccelTableStaticOffsetData(uint32_t Offset)
Definition: AccelTable.h:359
Annotation2Metadata
Annotation2Metadata
Definition: Annotation2Metadata.cpp:96
Bitcode
write Write Bitcode
Definition: BitcodeWriterPass.cpp:73
llvm::AccelTableBase::HashData::HashValue
uint32_t HashValue
Definition: AccelTable.h:141
DwarfStringPoolEntry.h
IR
Statically lint checks LLVM IR
Definition: Lint.cpp:751
STLFunctionalExtras.h
LoongArchGenSubtargetInfo
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
StringMap.h
llvm::AccelTableBase::HashData::Sym
MCSymbol * Sym
Definition: AccelTable.h:143
BPFGenRegisterInfo
llvm::pdb::PDB_ColorItem::Path
@ Path
llvm::AccelTableBase
A base class holding non-template-dependant functionality of the AccelTable class.
Definition: AccelTable.h:134
llvm::NVPTX::PTXLdStInstCode::Scalar
@ Scalar
Definition: NVPTX.h:122
c
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int int c
Definition: README.txt:418
llvm::emitAppleAccelTableImpl
void emitAppleAccelTableImpl(AsmPrinter *Asm, AccelTableBase &Contents, StringRef Prefix, const MCSymbol *SecBegin, ArrayRef< AppleAccelTableData::Atom > Atoms)
Definition: AccelTable.cpp:538
only
dot regions only
Definition: RegionPrinter.cpp:194
add_subdirectory
add_subdirectory(IR) add_subdirectory(Support) add_subdirectory(Frontend) if(NOT "$
Definition: CMakeLists.txt:1
add_pdb_impl_folder
diaguids lib LIBPDB_ADDITIONAL_LIBRARIES add_pdb_impl_folder(DIA DIA/DIADataStream.cpp DIA/DIAEnumDebugStreams.cpp DIA/DIAEnumFrameData.cpp DIA/DIAEnumInjectedSources.cpp DIA/DIAEnumLineNumbers.cpp DIA/DIAEnumSectionContribs.cpp DIA/DIAEnumSourceFiles.cpp DIA/DIAEnumSymbols.cpp DIA/DIAEnumTables.cpp DIA/DIAError.cpp DIA/DIAFrameData.cpp DIA/DIAInjectedSource.cpp DIA/DIALineNumber.cpp DIA/DIARawSymbol.cpp DIA/DIASectionContrib.cpp DIA/DIASession.cpp DIA/DIASourceFile.cpp DIA/DIATable.cpp) set(LIBPDB_ADDITIONAL_HEADER_DIRS "$
Definition: CMakeLists.txt:19
llvm::LoopPassManager
PassManager< Loop, LoopAnalysisManager, LoopStandardAnalysisResults &, LPMUpdater & > LoopPassManager
The Loop pass manager.
Definition: LoopPassManager.h:217
NVPTXGenSubtargetInfo
llvm::StringMap< HashData, BumpPtrAllocator & >
DIE.h
llvm::AppleAccelTableTypeData::emit
void emit(AsmPrinter *Asm) const override
Definition: AccelTable.cpp:595
ARCGenInstrInfo
X86GenSubtargetInfo
llvm::AppleAccelTableTypeData::AppleAccelTableTypeData
AppleAccelTableTypeData(const DIE &D)
Definition: AccelTable.h:341
llvm::OutputFileType::Object
@ Object
PPCGenSubtargetInfo
WebAssemblyGenInstrInfo
gen
llvm::function_ref
An efficient, type-erasing, non-owning reference to a callable.
Definition: STLFunctionalExtras.h:36
llvm::DWARF5AccelTableStaticData::hash
static uint32_t hash(StringRef Name)
Definition: AccelTable.h:271
rpmalloc
LLVM_HAS_NOGLOBAL_CTOR_MUTEX rpmalloc
Definition: CMakeLists.txt:86
AMDGPURegBankCombinerHelper
Definition: AMDGPURegBankCombiner.cpp:34
llvm::AccelTableBase::print
void print(raw_ostream &OS) const
Definition: AccelTable.cpp:660
LoongArchGenRegisterInfo
ARMGenInstrInfo
llvm::HighlightColor::Remark
@ Remark
Verifier
verify safepoint Safepoint IR Verifier
Definition: SafepointIRVerifier.cpp:251
llvm::DWARF5AccelTableData::getDieOffset
uint64_t getDieOffset() const
Definition: AccelTable.h:260
needed
We should do a little better with eliminating dead stores The stores to the stack are dead since a and b are not needed
Definition: README_ALTIVEC.txt:212
llvm::AccelTableBase::getUniqueNameCount
uint32_t getUniqueNameCount() const
Definition: AccelTable.h:179
AVRGenRegisterInfo
HexagonGenRegisterInfo
inc
Current eax eax eax ret Ideal eax eax ret Re implement atomic builtins x86 does not have to use add to implement these it can use inc
Definition: README.txt:1367
llvm::MachO::Architecture
Architecture
Defines the architecture slices that are supported by Text-based Stub files.
Definition: Architecture.h:27
llvm::remarks::Format::YAML
@ YAML
LICM
loop versioning Loop Versioning For LICM
Definition: LoopVersioningLICM.cpp:656
llvm::DWARF5AccelTableData::Die
const DIE & Die
Definition: AccelTable.h:264
llvm::AccelTableBase::BucketList
std::vector< HashList > BucketList
Definition: AccelTable.h:154
uint64_t
llvm::DWARF5AccelTableStaticData::print
void print(raw_ostream &OS) const override
Definition: AccelTable.cpp:684
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::find
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1637
R600MCInstLower
Definition: R600MCInstLower.cpp:22
llvm::caseFoldingDjbHash
uint32_t caseFoldingDjbHash(StringRef Buffer, uint32_t H=5381)
Computes the Bernstein hash after folding the input according to the Dwarf 5 standard case folding ru...
Definition: DJB.cpp:71
llvm::AccelTableBase::HashData::Values
std::vector< AccelTableData * > Values
Definition: AccelTable.h:142
llvm::DWARF5AccelTableStaticData
Definition: AccelTable.h:269
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:63
llvm::DWARF5AccelTableData::getDie
const DIE & getDie() const
Definition: AccelTable.h:259
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::AppleAccelTableStaticTypeData::QualifiedNameHash
uint32_t QualifiedNameHash
Definition: AccelTable.h:399
Remarks
annotation Annotation Remarks
Definition: AnnotationRemarks.cpp:115
SystemZGenSubtargetInfo
R600GenRegisterInfo
I
#define I(x, y, z)
Definition: MD5.cpp:58
Debug
bool Debug
Definition: PassBuilderBindings.cpp:51
DirectXGenSubtargetInfo
llvm::AppleAccelTableStaticOffsetData::Atoms
static constexpr Atom Atoms[]
Definition: AccelTable.h:363
Attributes
AMDGPU Kernel Attributes
Definition: AMDGPULowerKernelAttributes.cpp:244
llvm::AccelTableBase::getUniqueHashCount
uint32_t getUniqueHashCount() const
Definition: AccelTable.h:178
ArrayRef.h
llvm::pdb::PDB_ReaderType::Native
@ Native
message
message(STATUS "Targeting ${t}") add_subdirectory($
Definition: CMakeLists.txt:33
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AppleAccelTableStaticTypeData::AppleAccelTableStaticTypeData
AppleAccelTableStaticTypeData(uint32_t Offset, uint16_t Tag, bool ObjCClassIsImplementation, uint32_t QualifiedNameHash)
Definition: AccelTable.h:379
MergedLoadStoreMotion
mldst MergedLoadStoreMotion
Definition: MergedLoadStoreMotion.cpp:405
llvm::AppleAccelTableStaticTypeData
Accelerator table data implementation for type accelerator tables with a DIE offset but no actual DIE...
Definition: AccelTable.h:377
removed
currently compiles eax eax je LBB0_3 testl eax jne LBB0_4 the testl could be removed
Definition: README.txt:1552
PreferPredicateTy::Option
Option
Definition: LoopVectorize.cpp:210
llvm::ISD::BasicBlock
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:71
BPFGenInstrInfo
llvm::codeview::CodeViewContainer::ObjectFile
@ ObjectFile
VEGenRegisterInfo
CSKYGenRegisterInfo
register
should just be implemented with a CLZ instruction Since there are other e that share this it would be best to implement this in a target independent as zero is the default value for the binary encoder e add r0 add r5 Register operands should be distinct That when the encoding does not require two syntactical operands to refer to the same register
Definition: README.txt:726
llvm::StringMapImpl::size
unsigned size() const
Definition: StringMap.h:95
isel
amdgpu isel
Definition: AMDGPUISelDAGToDAG.cpp:109
llvm::DWARF5AccelTableStaticData::getCUIndex
unsigned getCUIndex() const
Definition: AccelTable.h:283
llvm::AppleAccelTableData::Atom::Type
const uint16_t Type
Atom Type.
Definition: AccelTable.h:226
llvm::InstrProfKind::MemProf
@ MemProf
info
lazy value info
Definition: LazyValueInfo.cpp:58
llvm::AppleAccelTableOffsetData::print
void print(raw_ostream &OS) const override
Definition: AccelTable.cpp:689
add_llvm_library
add_llvm_library(LLVMTestingSupport Annotations.cpp Error.cpp SupportHelpers.cpp BUILDTREE_ONLY ADDITIONAL_HEADER_DIRS ${LLVM_MAIN_INCLUDE_DIR}/llvm/Testing/Support LINK_COMPONENTS Support) target_link_libraries(LLVMTestingSupport PRIVATE llvm_gtest) if(HOST_WINNT AND "$
Definition: CMakeLists.txt:1
llvm::AccelTableBase::Buckets
BucketList Buckets
Definition: AccelTable.h:168
Scheduler
Machine Instruction Scheduler
Definition: MachineScheduler.cpp:223
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Mips16HardFloat
static cl::opt< bool > Mips16HardFloat("mips16-hard-float", cl::NotHidden, cl::desc("Enable mips16 hard float."), cl::init(false))
RegUsageInfoCollector
RegUsageInfoCollector
Definition: RegUsageInfoCollector.cpp:72
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
Dwarf.h
llvm::msf::Magic
static const char Magic[]
Definition: MSFCommon.h:23
llvm::AppleAccelTableStaticTypeData::print
void print(raw_ostream &OS) const override
Definition: AccelTable.cpp:702
llvm::AppleAccelTableOffsetData::order
uint64_t order() const override
Definition: AccelTable.h:333
if
if(llvm_vc STREQUAL "") set(fake_version_inc "$
Definition: CMakeLists.txt:14
llvm::cl::Sink
@ Sink
Definition: CommandLine.h:167
llvm::FlattenCFG
bool FlattenCFG(BasicBlock *BB, AAResults *AA=nullptr)
This function is used to flatten a CFG.
Definition: FlattenCFG.cpp:547
VEGenInstrInfo
CSKYGenSubtargetInfo
uint32_t
SparcGenRegisterInfo
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
Module
Machine Check Debug Module
Definition: MachineCheckDebugify.cpp:122
Profile
Load MIR Sample Profile
Definition: MIRSampleProfile.cpp:70
llvm::DemoteRegToStack
AllocaInst * DemoteRegToStack(Instruction &X, bool VolatileLoads=false, Instruction *AllocaPoint=nullptr)
This function takes a virtual register computed by an Instruction and replaces it with a slot in the ...
Definition: DemoteRegToStack.cpp:22
AMDGPUGenInstrInfo
llvm::CloneFunction
Function * CloneFunction(Function *F, ValueToValueMapTy &VMap, ClonedCodeInfo *CodeInfo=nullptr)
Return a copy of the specified function and add it to that function's module.
Definition: CloneFunction.cpp:281
macro
macro(add_pdb_impl_folder group) list(APPEND PDB_IMPL_SOURCES $
Definition: CMakeLists.txt:1
ARCGenSubtargetInfo
llvm::AccelTableBase::dump
void dump() const
Definition: AccelTable.h:183
llvm::DWARF5AccelTableData
The Data class implementation for DWARF v5 accelerator table.
Definition: AccelTable.h:249
writer
we should consider alternate ways to model stack dependencies Lots of things could be done in WebAssemblyTargetTransformInfo cpp there are numerous optimization related hooks that can be overridden in WebAssemblyTargetLowering Instead of the OptimizeReturned which should consider preserving the returned attribute through to MachineInstrs and extending the MemIntrinsicResults pass to do this optimization on calls too That would also let the WebAssemblyPeephole pass clean up dead defs for such as it does for stores Consider implementing and or getMachineCombinerPatterns Find a clean way to fix the problem which leads to the Shrink Wrapping pass being run after the WebAssembly PEI pass When setting multiple variables to the same we currently get code like const It could be done with a smaller encoding like local tee $pop5 local $pop6 WebAssembly registers are implicitly initialized to zero Explicit zeroing is therefore often redundant and could be optimized away Small indices may use smaller encodings than large indices WebAssemblyRegColoring and or WebAssemblyRegRenumbering should sort registers according to their usage frequency to maximize the usage of smaller encodings Many cases of irreducible control flow could be transformed more optimally than via the transform in WebAssemblyFixIrreducibleControlFlow cpp It may also be worthwhile to do transforms before register particularly when duplicating to allow register coloring to be aware of the duplication WebAssemblyRegStackify could use AliasAnalysis to reorder loads and stores more aggressively WebAssemblyRegStackify is currently a greedy algorithm This means for a binary however wasm doesn t actually require this WebAssemblyRegStackify could be or possibly to take full advantage of what WebAssembly permits Add support for mergeable sections in the Wasm writer
Definition: README.txt:154
llvm::BuryPointer
void BuryPointer(const void *Ptr)
Definition: BuryPointer.cpp:15
WebAssemblyGenSubtargetInfo
llvm::DWARF5AccelTableData::getDieTag
unsigned getDieTag() const
Definition: AccelTable.h:261
Analysis
block Block Frequency Analysis
Definition: BlockFrequencyInfo.cpp:301
Threading
dfa jump DFA Jump Threading
Definition: DFAJumpThreading.cpp:209
llvm::cl::Optional
@ Optional
Definition: CommandLine.h:115
SparcGenInstrInfo
ConstantFold
static Constant * ConstantFold(Instruction *I, const DataLayout &DL, const SmallDenseMap< Value *, Constant * > &ConstantPool)
Try to fold instruction I into a constant.
Definition: SimplifyCFG.cpp:5532
llvm::pdb::PDB_DataKind::Local
@ Local
CFG
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to CFG
Definition: README.txt:39
Signals
static const int Signals[]
Definition: CrashRecoveryContext.cpp:346
llvm::DWARF5AccelTableStaticData::DWARF5AccelTableStaticData
DWARF5AccelTableStaticData(uint64_t DieOffset, unsigned DieTag, unsigned CUIndex)
Definition: AccelTable.h:273
PPCGenInstrInfo
AMDGPUGenSubtargetInfo
add_llvm_component_group
tools llvm config LibraryDependencies inc add_llvm_component_group(all-targets LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD}) add_llvm_component_group(Engine) if(TARGET $
Definition: CMakeLists.txt:51
llvm::AppleAccelTableData
A base class for different implementations of Data classes for Apple Accelerator Tables.
Definition: AccelTable.h:219
tables
we compile this esp call L1 $pb L1 esp je LBB1_2 esp ret but is currently always computed in the entry block It would be better to sink the picbase computation down into the block for the as it is the only one that uses it This happens for a lot of code with early outs Another example is loads of which are usually emitted into the entry block on targets like x86 If not used in all paths through a they should be sunk into the ones that do In this whole function isel would also handle this Investigate lowering of sparse switch statements into perfect hash tables
Definition: README.txt:439
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::AccelTableBase::getBuckets
ArrayRef< HashList > getBuckets() const
Definition: AccelTable.h:176
llvm::InlinePass::ModuleInliner
@ ModuleInliner
uint16_t
can
This might compile to this xmm1 xorps xmm0 movss xmm0 ret Now consider if the code caused xmm1 to get spilled This might produce this xmm1 movaps xmm0 movaps xmm1 movss xmm0 ret since the reload is only used by these we could fold it into the producing something like xmm1 movaps xmm0 ret saving two instructions The basic idea is that a reload from a spill can
Definition: README-SSE.txt:269
or
compiles or
Definition: README.txt:606
llvm::DWARF5AccelTableStaticData::getDieOffset
uint64_t getDieOffset() const
Definition: AccelTable.h:281
llvm::pdb::PDB_ReaderType::DIA
@ DIA
AMDGPUGenRegisterInfo
RISCVGenRegisterInfo
llvm::AppleAccelTableTypeData::Atoms
static constexpr Atom Atoms[]
Definition: AccelTable.h:345
llvm::LoopRotation
bool LoopRotation(Loop *L, LoopInfo *LI, const TargetTransformInfo *TTI, AssumptionCache *AC, DominatorTree *DT, ScalarEvolution *SE, MemorySSAUpdater *MSSAU, const SimplifyQuery &SQ, bool RotationOnly, unsigned Threshold, bool IsUtilMode, bool PrepareForLTO=false)
Convert a loop into a loop with bottom test.
Definition: LoopRotationUtils.cpp:825
llvm::AppleAccelTableOffsetData
Accelerator table data implementation for simple Apple accelerator tables with just a DIE reference.
Definition: AccelTable.h:320
find_first_existing_vc_file
find_first_existing_vc_file("${LLVM_MAIN_SRC_DIR}" llvm_vc) set(version_inc "$
Definition: CMakeLists.txt:1
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
ppc
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including ppc
Definition: README.txt:567
PPCGenRegisterInfo
SystemZGenRegisterInfo
llvm::AsmPrinter
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:81
v3
we get the following basic r4 lvx v3
Definition: README_ALTIVEC.txt:95
Inliner
partial Partial Inliner
Definition: PartialInlining.cpp:1523
AMDGPUPostLegalizerCombinerHelper
Definition: AMDGPUPostLegalizerCombiner.cpp:34
llvm::DWARF5AccelTableData::hash
static uint32_t hash(StringRef Name)
Definition: AccelTable.h:251
R600GenSubtargetInfo
R600ExpandSpecialInstrs
R600ExpandSpecialInstrs
Definition: R600ExpandSpecialInstrs.cpp:53
llvm::AppleAccelTableOffsetData::Atoms
static constexpr Atom Atoms[]
Definition: AccelTable.h:326
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::NVPTX::PTXLdStInstCode::GLOBAL
@ GLOBAL
Definition: NVPTX.h:109
llvm::sys::RWMutex
SmartRWMutex< false > RWMutex
Definition: RWMutex.h:162
llvm::AccelTableBase::HashData::HashData
HashData(DwarfStringPoolEntryRef Name, HashFn *Hash)
Definition: AccelTable.h:145
This
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical This
Definition: README.txt:418
WebAssemblyGenRegisterInfo
llvm::DWARF5AccelTableData::order
uint64_t order() const override
Definition: AccelTable.h:266
Evaluator
aa Exhaustive Alias Analysis Precision Evaluator
Definition: AliasAnalysisEvaluator.cpp:415
llvm::AppleAccelTableStaticTypeData::Atoms
static constexpr Atom Atoms[]
Definition: AccelTable.h:388
set
VCSRevision h set(generate_vcs_version_script "${LLVM_CMAKE_DIR}/GenerateVersionFromVCS.cmake") if(LLVM_APPEND_VC_REV) set(llvm_source_dir $
Definition: CMakeLists.txt:6
llvm::DWARF5AccelTableStaticData::getDieTag
unsigned getDieTag() const
Definition: AccelTable.h:282
Currently
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in and only one load from a constant double ret double C Currently
Definition: README-SSE.txt:89
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:142
llvm::LoopAnalysisManager
AnalysisManager< Loop, LoopStandardAnalysisResults & > LoopAnalysisManager
The loop analysis manager.
Definition: LoopAnalysisManager.h:75
llvm::CloneModule
std::unique_ptr< Module > CloneModule(const Module &M)
Return an exact copy of the specified module.
Definition: CloneModule.cpp:37
llvm::AccelTableData::~AccelTableData
virtual ~AccelTableData()=default
LineType::Metadata
@ Metadata
llvm::AccelTableBase::HashData::print
void print(raw_ostream &OS) const
Definition: AccelTable.cpp:647
DirectXGenInstrInfo
llvm::AccelTableBase::BucketCount
uint32_t BucketCount
Definition: AccelTable.h:164
RISCVGenSubtargetInfo
LLVM
MIPS Relocation Principles In LLVM
Definition: Relocation.txt:3
llvm::AccelTableBase::HashFn
uint32_t(StringRef) HashFn
Definition: AccelTable.h:136
PPC
should just be implemented with a CLZ instruction Since there are other e PPC
Definition: README.txt:709
llvm::AppleAccelTableTypeData
Accelerator table data implementation for Apple type accelerator tables.
Definition: AccelTable.h:339
llvm::AccelTableBase::HashList
std::vector< HashData * > HashList
Definition: AccelTable.h:153
llvm::InlineFunction
InlineResult InlineFunction(CallBase &CB, InlineFunctionInfo &IFI, AAResults *CalleeAAR=nullptr, bool InsertLifetime=true, Function *ForwardVarArgsTo=nullptr)
This function inlines the called function into the basic block of the caller.
Definition: InlineFunction.cpp:1748
lowering
amdgpu printf runtime AMDGPU Printf lowering
Definition: AMDGPUPrintfRuntimeBinding.cpp:88
llvm::msgpack::Type
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:48
h
the multiplication has a latency of four as opposed to two cycles for the movl lea variant It appears gcc place string data with linkonce linkage in section coalesced instead of section coalesced Take a look at darwin h
Definition: README.txt:261
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::AccelTableData::print
virtual void print(raw_ostream &OS) const =0
llvm::InliningAdvisorMode::Release
@ Release
llvm::AppleAccelTableStaticOffsetData::print
void print(raw_ostream &OS) const override
Definition: AccelTable.cpp:698
XCoreGenInstrInfo
llvm::dwarf::DW_ATOM_type_flags
@ DW_ATOM_type_flags
Definition: Dwarf.h:513
llvm::djbHash
uint32_t djbHash(StringRef Buffer, uint32_t H=5381)
The Bernstein hash function used by the DWARF accelerator tables.
Definition: DJB.h:21
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::EngineKind::Interpreter
@ Interpreter
Definition: ExecutionEngine.h:525
llvm::MachineSSAContext
GenericSSAContext< MachineFunction > MachineSSAContext
Definition: MachineSSAContext.h:55
matcher
Code Generation Notes for reduce the size of the ISel matcher
Definition: MSA.txt:5
llvm::AppleAccelTableOffsetData::emit
void emit(AsmPrinter *Asm) const override
Definition: AccelTable.cpp:589
llvm::DIE::getOffset
unsigned getOffset() const
Get the compile/type unit relative offset of this DIE.
Definition: DIE.h:777
llvm::AppleAccelTableData::Atom::print
void print(raw_ostream &OS) const
Definition: AccelTable.cpp:629
X86
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
Definition: README.txt:568
llvm::SplitModule
void SplitModule(Module &M, unsigned N, function_ref< void(std::unique_ptr< Module > MPart)> ModuleCallback, bool PreserveLocals=false)
Splits the module M into N linkable partitions.
Definition: SplitModule.cpp:251
MemorySSA
early cse Early CSE w MemorySSA
Definition: EarlyCSE.cpp:1775
Interval
std::pair< uint64_t, uint64_t > Interval
Definition: MappedBlockStream.cpp:37
packetizer
hexagon packetizer
Definition: HexagonVLIWPacketizer.cpp:131
llvm::DWARF5AccelTableData::DWARF5AccelTableData
DWARF5AccelTableData(const DIE &Die)
Definition: AccelTable.h:253
Debug.h
MipsGenInstrInfo
M68kGenSubtargetInfo
llvm::AccelTableBase::finalize
void finalize(AsmPrinter *Asm, StringRef Prefix)
Definition: AccelTable.cpp:53
NVPTXGenRegisterInfo
llvm::DwarfLinkerAccelTableKind::Dwarf
@ Dwarf
DWARF v5 .debug_names.
llvm::codeview::PublicSymFlags::Function
@ Function
llvm::ISD::MCSymbol
@ MCSymbol
Definition: ISDOpcodes.h:172
SpecialSubKind::string
@ string
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1236
M68kGenRegisterInfo
llvm::irsymtab::build
Error build(ArrayRef< Module * > Mods, SmallVector< char, 0 > &Symtab, StringTableBuilder &StrtabBuilder, BumpPtrAllocator &Alloc)
Fills in Symtab and StrtabBuilder with a valid symbol and string table for Mods.
Definition: IRSymtab.cpp:365
llvm::AppleAccelTableOffsetData::Die
const DIE & Die
Definition: AccelTable.h:335
llvm::AccelTableBase::HashData::Name
DwarfStringPoolEntryRef Name
Definition: AccelTable.h:140
llvm::emitDWARF5AccelTable
void emitDWARF5AccelTable(AsmPrinter *Asm, AccelTable< DWARF5AccelTableData > &Contents, const DwarfDebug &DD, ArrayRef< std::unique_ptr< DwarfCompileUnit >> CUs)
Definition: AccelTable.cpp:545