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31 #define DEBUG_TYPE "mccodeemitter"
41 mutable unsigned Offset;
45 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
57 unsigned getMemOpValue(
const MCInst &
MI,
unsigned Op,
61 unsigned getPCRelImmOpValue(
const MCInst &
MI,
unsigned Op,
65 unsigned getCGImmOpValue(
const MCInst &
MI,
unsigned Op,
69 unsigned getCCOpValue(
const MCInst &
MI,
unsigned Op,
75 : Ctx(ctx), MCII(MCII) {}
92 uint64_t BinaryOpCode = getBinaryCodeForInstr(
MI,
Fixups, STI);
93 size_t WordCount =
Size / 2;
101 unsigned MSP430MCCodeEmitter::getMachineOpValue(
const MCInst &
MI,
120 unsigned MSP430MCCodeEmitter::getMemOpValue(
const MCInst &
MI,
unsigned Op,
121 SmallVectorImpl<MCFixup> &
Fixups,
122 const MCSubtargetInfo &STI)
const {
123 const MCOperand &MO1 =
MI.getOperand(
Op);
124 assert(MO1.isReg() &&
"Register operand expected");
127 const MCOperand &MO2 =
MI.getOperand(
Op + 1);
130 return ((
unsigned)MO2.getImm() << 4) |
Reg;
133 assert(MO2.isExpr() &&
"Expr operand expected");
152 unsigned MSP430MCCodeEmitter::getPCRelImmOpValue(
const MCInst &
MI,
unsigned Op,
153 SmallVectorImpl<MCFixup> &
Fixups,
154 const MCSubtargetInfo &STI)
const {
155 const MCOperand &MO =
MI.getOperand(
Op);
159 assert(MO.isExpr() &&
"Expr operand expected");
165 unsigned MSP430MCCodeEmitter::getCGImmOpValue(
const MCInst &
MI,
unsigned Op,
166 SmallVectorImpl<MCFixup> &
Fixups,
167 const MCSubtargetInfo &STI)
const {
168 const MCOperand &MO =
MI.getOperand(
Op);
169 assert(MO.isImm() &&
"Expr operand expected");
171 int64_t Imm = MO.getImm();
180 case -1:
return 0x33;
184 unsigned MSP430MCCodeEmitter::getCCOpValue(
const MCInst &
MI,
unsigned Op,
185 SmallVectorImpl<MCFixup> &
Fixups,
186 const MCSubtargetInfo &STI)
const {
187 const MCOperand &MO =
MI.getOperand(
Op);
188 assert(MO.isImm() &&
"Immediate operand expected");
189 switch (MO.getImm()) {
208 #include "MSP430GenMCCodeEmitter.inc"
This class represents lattice values for constants.
static Lanai::Fixups FixupKind(const MCExpr *Expr)
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
void encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Instances of this class represent a single low-level machine instruction.
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Describe properties that are true of each instruction in the target description file.
This class implements an extremely fast bulk output stream that can only output to a stream.
This file declares a class to represent arbitrary precision floating point values and provide a varie...
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
MSP430MCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
MCCodeEmitter * createMSP430MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Creates a machine code emitter for MSP430.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
Interface to description of machine instruction set.
MCCodeEmitter - Generic instruction encoding interface.
const MCExpr * getExpr() const
MCFixupKind
Extensible enumeration to represent the type of a fixup.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Instances of this class represent operands of the MCInst class.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Generic base class for all target subtargets.
unsigned getReg() const
Returns the register number.