LLVM 19.0.0git
MSP430MCCodeEmitter.cpp
Go to the documentation of this file.
1//===-- MSP430MCCodeEmitter.cpp - Convert MSP430 code to machine code -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the MSP430MCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MSP430.h"
16
17#include "llvm/ADT/APFloat.h"
20#include "llvm/MC/MCContext.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCFixup.h"
23#include "llvm/MC/MCInst.h"
24#include "llvm/MC/MCInstrInfo.h"
27#include "llvm/Support/Endian.h"
30
31#define DEBUG_TYPE "mccodeemitter"
32
33namespace llvm {
34
36 MCContext &Ctx;
37 MCInstrInfo const &MCII;
38
39 // Offset keeps track of current word number being emitted
40 // inside a particular instruction.
41 mutable unsigned Offset;
42
43 /// TableGen'erated function for getting the binary encoding for an
44 /// instruction.
45 uint64_t getBinaryCodeForInstr(const MCInst &MI,
47 const MCSubtargetInfo &STI) const;
48
49 /// Returns the binary encoding of operands.
50 ///
51 /// If an operand requires relocation, the relocation is recorded
52 /// and zero is returned.
53 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
55 const MCSubtargetInfo &STI) const;
56
57 unsigned getMemOpValue(const MCInst &MI, unsigned Op,
59 const MCSubtargetInfo &STI) const;
60
61 unsigned getPCRelImmOpValue(const MCInst &MI, unsigned Op,
63 const MCSubtargetInfo &STI) const;
64
65 unsigned getCGImmOpValue(const MCInst &MI, unsigned Op,
67 const MCSubtargetInfo &STI) const;
68
69 unsigned getCCOpValue(const MCInst &MI, unsigned Op,
71 const MCSubtargetInfo &STI) const;
72
73public:
75 : Ctx(ctx), MCII(MCII) {}
76
79 const MCSubtargetInfo &STI) const override;
80};
81
85 const MCSubtargetInfo &STI) const {
86 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
87 // Get byte count of instruction.
88 unsigned Size = Desc.getSize();
89
90 // Initialize fixup offset
91 Offset = 2;
92
93 uint64_t BinaryOpCode = getBinaryCodeForInstr(MI, Fixups, STI);
94 size_t WordCount = Size / 2;
95
96 while (WordCount--) {
97 support::endian::write(CB, (uint16_t)BinaryOpCode,
99 BinaryOpCode >>= 16;
100 }
101}
102
103unsigned MSP430MCCodeEmitter::getMachineOpValue(const MCInst &MI,
104 const MCOperand &MO,
106 const MCSubtargetInfo &STI) const {
107 if (MO.isReg())
108 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
109
110 if (MO.isImm()) {
111 Offset += 2;
112 return MO.getImm();
113 }
114
115 assert(MO.isExpr() && "Expected expr operand");
116 Fixups.push_back(MCFixup::create(Offset, MO.getExpr(),
117 static_cast<MCFixupKind>(MSP430::fixup_16_byte), MI.getLoc()));
118 Offset += 2;
119 return 0;
120}
121
122unsigned MSP430MCCodeEmitter::getMemOpValue(const MCInst &MI, unsigned Op,
123 SmallVectorImpl<MCFixup> &Fixups,
124 const MCSubtargetInfo &STI) const {
125 const MCOperand &MO1 = MI.getOperand(Op);
126 assert(MO1.isReg() && "Register operand expected");
127 unsigned Reg = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg());
128
129 const MCOperand &MO2 = MI.getOperand(Op + 1);
130 if (MO2.isImm()) {
131 Offset += 2;
132 return ((unsigned)MO2.getImm() << 4) | Reg;
133 }
134
135 assert(MO2.isExpr() && "Expr operand expected");
137 switch (Reg) {
138 case 0:
140 break;
141 case 2:
143 break;
144 default:
146 break;
147 }
148 Fixups.push_back(MCFixup::create(Offset, MO2.getExpr(),
149 static_cast<MCFixupKind>(FixupKind), MI.getLoc()));
150 Offset += 2;
151 return Reg;
152}
153
154unsigned MSP430MCCodeEmitter::getPCRelImmOpValue(const MCInst &MI, unsigned Op,
155 SmallVectorImpl<MCFixup> &Fixups,
156 const MCSubtargetInfo &STI) const {
157 const MCOperand &MO = MI.getOperand(Op);
158 if (MO.isImm())
159 return MO.getImm();
160
161 assert(MO.isExpr() && "Expr operand expected");
162 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
163 static_cast<MCFixupKind>(MSP430::fixup_10_pcrel), MI.getLoc()));
164 return 0;
165}
166
167unsigned MSP430MCCodeEmitter::getCGImmOpValue(const MCInst &MI, unsigned Op,
168 SmallVectorImpl<MCFixup> &Fixups,
169 const MCSubtargetInfo &STI) const {
170 const MCOperand &MO = MI.getOperand(Op);
171 assert(MO.isImm() && "Expr operand expected");
172
173 int64_t Imm = MO.getImm();
174 switch (Imm) {
175 default:
176 llvm_unreachable("Invalid immediate value");
177 case 4: return 0x22;
178 case 8: return 0x32;
179 case 0: return 0x03;
180 case 1: return 0x13;
181 case 2: return 0x23;
182 case -1: return 0x33;
183 }
184}
185
186unsigned MSP430MCCodeEmitter::getCCOpValue(const MCInst &MI, unsigned Op,
187 SmallVectorImpl<MCFixup> &Fixups,
188 const MCSubtargetInfo &STI) const {
189 const MCOperand &MO = MI.getOperand(Op);
190 assert(MO.isImm() && "Immediate operand expected");
191 switch (MO.getImm()) {
192 case MSP430CC::COND_NE: return 0;
193 case MSP430CC::COND_E: return 1;
194 case MSP430CC::COND_LO: return 2;
195 case MSP430CC::COND_HS: return 3;
196 case MSP430CC::COND_N: return 4;
197 case MSP430CC::COND_GE: return 5;
198 case MSP430CC::COND_L: return 6;
199 default:
200 llvm_unreachable("Unknown condition code");
201 }
202}
203
205 MCContext &Ctx) {
206 return new MSP430MCCodeEmitter(Ctx, MCII);
207}
208
209#include "MSP430GenMCCodeEmitter.inc"
210
211} // end of namespace llvm
This file declares a class to represent arbitrary precision floating point values and provide a varie...
uint64_t Size
IRTranslator LLVM IR MI
unsigned Reg
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This class represents an Operation in the Expression.
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Context object for machine code objects.
Definition: MCContext.h:76
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:448
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
int64_t getImm() const
Definition: MCInst.h:80
bool isImm() const
Definition: MCInst.h:62
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
const MCExpr * getExpr() const
Definition: MCInst.h:114
bool isExpr() const
Definition: MCInst.h:65
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Generic base class for all target subtargets.
void encodeInstruction(const MCInst &MI, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const override
Encode the given Inst to bytes and append to CB.
MSP430MCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ COND_LO
Definition: MSP430.h:26
@ COND_N
Definition: MSP430.h:29
@ COND_L
Definition: MSP430.h:28
@ COND_E
Definition: MSP430.h:23
@ COND_GE
Definition: MSP430.h:27
@ COND_NE
Definition: MSP430.h:24
@ COND_HS
Definition: MSP430.h:25
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:91
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCCodeEmitter * createMSP430MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Creates a machine code emitter for MSP430.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
DWARFExpression::Operation Op
Description of the encoding of one expression Op.