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17 #ifndef LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
26 class AMDGPUTargetLowering;
55 unsigned AddrSpace)
const;
57 unsigned AddrSpace)
const;
59 unsigned AddrSpace)
const;
71 #endif // LLVM_LIB_TARGET_AMDGPU_R600TARGETTRANSFORMINFO_H
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
This is an optimization pass for GlobalISel generic memory operations.
Represents a single loop in the control flow graph.
The main scalar evolution driver.
unsigned getHardwareNumberOfRegisters(bool Vec) const
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
unsigned getMaxInterleaveFactor(unsigned VF)
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
Base class which can be used to help build a TTI implementation.
const R600Subtarget * getST() const
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const
unsigned getMinVectorRegisterBitWidth() const
R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
const char LLVMTargetMachineRef TM
unsigned getNumberOfRegisters(bool Vec) const
LLVM Value Representation.
const AMDGPUTargetLowering * getTLI() const