LLVM 20.0.0git
RetireStage.cpp
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1//===---------------------- RetireStage.cpp ---------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file defines the retire stage of an instruction pipeline.
11/// The RetireStage represents the process logic that interacts with the
12/// simulated RetireControlUnit hardware.
13///
14//===----------------------------------------------------------------------===//
15
18#include "llvm/Support/Debug.h"
19
20#define DEBUG_TYPE "llvm-mca"
21
22namespace llvm {
23namespace mca {
24
26 PRF.cycleStart();
27
28 const unsigned MaxRetirePerCycle = RCU.getMaxRetirePerCycle();
29 unsigned NumRetired = 0;
30 while (!RCU.isEmpty()) {
31 if (MaxRetirePerCycle != 0 && NumRetired == MaxRetirePerCycle)
32 break;
33 const RetireControlUnit::RUToken &Current = RCU.getCurrentToken();
34 if (!Current.Executed)
35 break;
38 NumRetired++;
39 }
40
41 return llvm::ErrorSuccess();
42}
43
45 PRF.cycleEnd();
46 return llvm::ErrorSuccess();
47}
48
50 Instruction &IS = *IR.getInstruction();
51
52 PRF.onInstructionExecuted(&IS);
53 unsigned TokenID = IS.getRCUTokenID();
55 RCU.onInstructionExecuted(TokenID);
56
57 return llvm::ErrorSuccess();
58}
59
61 LLVM_DEBUG(llvm::dbgs() << "[E] Instruction Retired: #" << IR << '\n');
63 const Instruction &Inst = *IR.getInstruction();
64
65 // Release the load/store queue entries.
66 if (Inst.isMemOp())
68
69 for (const WriteState &WS : Inst.getDefs())
70 PRF.removeRegisterWrite(WS, FreedRegs);
71 notifyEvent<HWInstructionEvent>(HWInstructionRetiredEvent(IR, FreedRegs));
72}
73
74} // namespace mca
75} // namespace llvm
#define LLVM_DEBUG(X)
Definition: Debug.h:101
This file defines the main interface for hardware event listeners.
Legalize the Machine IR a function s Machine IR
Definition: Legalizer.cpp:81
This file defines the retire stage of a default instruction pipeline.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Subclass of Error for the sole purpose of identifying the success path in the type system.
Definition: Error.h:335
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
An InstRef contains both a SourceMgr index and Instruction pair.
Definition: Instruction.h:720
SmallVectorImpl< WriteState > & getDefs()
Definition: Instruction.h:535
An instruction propagated through the simulated instruction pipeline.
Definition: Instruction.h:600
unsigned getRCUTokenID() const
Definition: Instruction.h:655
virtual void onInstructionRetired(const InstRef &IR)
Definition: LSUnit.cpp:214
unsigned getNumRegisterFiles() const
Definition: RegisterFile.h:293
void removeRegisterWrite(const WriteState &WS, MutableArrayRef< unsigned > FreedPhysRegs)
void onInstructionExecuted(Instruction *IS)
Error cycleEnd() override
Called once at the end of each cycle.
Definition: RetireStage.cpp:44
void notifyInstructionRetired(const InstRef &IR) const
Definition: RetireStage.cpp:60
Error cycleStart() override
Called once at the start of each cycle.
Definition: RetireStage.cpp:25
Error execute(InstRef &IR) override
The primary action that this stage performs on instruction IR.
Definition: RetireStage.cpp:49
Tracks uses of a register definition (e.g.
Definition: Instruction.h:197
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
unsigned getMaxRetirePerCycle() const
static const unsigned UnhandledTokenID
void onInstructionExecuted(unsigned TokenID)
const RUToken & getCurrentToken() const