LLVM 24.0.0git
GCNSchedStrategy.cpp File Reference

This contains a MachineSchedStrategy implementation for maximizing wave occupancy on GCN hardware. More...

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Classes

struct  EarlierIssuingCycle

Macros

#define DEBUG_TYPE   "machine-scheduler"
 Generally, the reason for having multiple scheduling stages is to account for the kernel-wide effect of register usage on occupancy.

Functions

static bool canUsePressureDiffs (const SUnit &SU)
 Checks whether SU can use the cached DAG pressure diffs to compute the current register pressure.
static bool shouldCheckPending (unsigned PendingQueueLimit, SchedBoundary &Zone, const TargetSchedModel *SchedModel)
static SUnit * pickOnlyChoice (unsigned PendingQueueLimit, SchedBoundary &Zone, const TargetSchedModel *SchedModel)
static MachineInstr * getLastMIForRegion (MachineBasicBlock::iterator RegionBegin, MachineBasicBlock::iterator RegionEnd)
static void printScheduleModel (std::set< std::pair< MachineInstr *, unsigned >, EarlierIssuingCycle > &ReadyCycles)
static bool isReachingDefAGPRForm (MachineInstr *RD, const SmallPtrSetImpl< MachineInstr * > &RewriteSet, const DenseSet< Register > &CandSrc2Regs, const SIInstrInfo &TII)
 Returns true if reaching def RD will be in AGPR form after the rewrite and so needs no bridge copy: a candidate MFMA in RewriteSet, an AV_MOV_*_IMM_PSEUDO, or a copy from a candidate src2 reg in CandSrc2Regs.
static bool hasIGLPInstrs (ScheduleDAGInstrs *DAG)

Detailed Description

This contains a MachineSchedStrategy implementation for maximizing wave occupancy on GCN hardware.

This pass will apply multiple scheduling stages to the same function. Regions are first recorded in GCNScheduleDAGMILive::schedule. The actual entry point for the scheduling of those regions is GCNScheduleDAGMILive::runSchedStages.

Definition in file GCNSchedStrategy.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "machine-scheduler"

Generally, the reason for having multiple scheduling stages is to account for the kernel-wide effect of register usage on occupancy.

Usually, only a few scheduling regions will have register pressure high enough to limit occupancy for the kernel, so constraints can be relaxed to improve ILP in other regions.

Definition at line 44 of file GCNSchedStrategy.cpp.

Function Documentation

◆ canUsePressureDiffs()

bool canUsePressureDiffs ( const SUnit & SU)
static

Checks whether SU can use the cached DAG pressure diffs to compute the current register pressure.

This works for the common case, but it has a few exceptions that have been observed through trial and error:

  • Explicit physical register operands
  • Subregister definitions

In both of those cases, PressureDiff doesn't represent the actual pressure, and querying LiveIntervals through the RegPressureTracker is needed to get an accurate value.

We should eventually only use PressureDiff for maximum performance, but this already allows 80% of SUs to take the fast path without changing scheduling at all. Further changes would either change scheduling, or require a lot more logic to recover an accurate pressure estimate from the PressureDiffs.

Definition at line 189 of file GCNSchedStrategy.cpp.

References llvm::const_mi_bundle_ops(), llvm::SUnit::getInstr(), and llvm::SUnit::isInstr().

Referenced by llvm::GCNSchedStrategy::initCandidate().

◆ getLastMIForRegion()

MachineInstr * getLastMIForRegion ( MachineBasicBlock::iterator RegionBegin,
MachineBasicBlock::iterator RegionEnd )
static

◆ hasIGLPInstrs()

◆ isReachingDefAGPRForm()

bool isReachingDefAGPRForm ( MachineInstr * RD,
const SmallPtrSetImpl< MachineInstr * > & RewriteSet,
const DenseSet< Register > & CandSrc2Regs,
const SIInstrInfo & TII )
static

Returns true if reaching def RD will be in AGPR form after the rewrite and so needs no bridge copy: a candidate MFMA in RewriteSet, an AV_MOV_*_IMM_PSEUDO, or a copy from a candidate src2 reg in CandSrc2Regs.

A non-candidate MFMA stays in VGPR form and still needs a bridge.

Definition at line 2229 of file GCNSchedStrategy.cpp.

References llvm::detail::DenseSetImpl< ValueT, MapTy >::contains(), llvm::SmallPtrSetImpl< PtrType >::contains(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::isCopy(), and TII.

◆ pickOnlyChoice()

SUnit * pickOnlyChoice ( unsigned PendingQueueLimit,
SchedBoundary & Zone,
const TargetSchedModel * SchedModel )
static

◆ printScheduleModel()

void printScheduleModel ( std::set< std::pair< MachineInstr *, unsigned >, EarlierIssuingCycle > & ReadyCycles)
static

◆ shouldCheckPending()