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LLVM 24.0.0git
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This contains a MachineSchedStrategy implementation for maximizing wave occupancy on GCN hardware. More...
#include "GCNSchedStrategy.h"#include "AMDGPUIGroupLP.h"#include "GCNHazardRecognizer.h"#include "GCNRegPressure.h"#include "GCNRematStrategy.h"#include "SIMachineFunctionInfo.h"#include "Utils/AMDGPUBaseInfo.h"#include "llvm/ADT/BitVector.h"#include "llvm/ADT/STLExtras.h"#include "llvm/CodeGen/CalcSpillWeights.h"#include "llvm/CodeGen/MachineBasicBlock.h"#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"#include "llvm/CodeGen/MachineOperand.h"#include "llvm/CodeGen/RegisterPressure.h"#include "llvm/MC/MCSchedule.h"#include "llvm/MC/TargetRegistry.h"#include "llvm/Support/ErrorHandling.h"Go to the source code of this file.
Classes | |
| struct | EarlierIssuingCycle |
Macros | |
| #define | DEBUG_TYPE "machine-scheduler" |
| Generally, the reason for having multiple scheduling stages is to account for the kernel-wide effect of register usage on occupancy. | |
Functions | |
| static bool | canUsePressureDiffs (const SUnit &SU) |
Checks whether SU can use the cached DAG pressure diffs to compute the current register pressure. | |
| static bool | shouldCheckPending (unsigned PendingQueueLimit, SchedBoundary &Zone, const TargetSchedModel *SchedModel) |
| static SUnit * | pickOnlyChoice (unsigned PendingQueueLimit, SchedBoundary &Zone, const TargetSchedModel *SchedModel) |
| static MachineInstr * | getLastMIForRegion (MachineBasicBlock::iterator RegionBegin, MachineBasicBlock::iterator RegionEnd) |
| static void | printScheduleModel (std::set< std::pair< MachineInstr *, unsigned >, EarlierIssuingCycle > &ReadyCycles) |
| static bool | isReachingDefAGPRForm (MachineInstr *RD, const SmallPtrSetImpl< MachineInstr * > &RewriteSet, const DenseSet< Register > &CandSrc2Regs, const SIInstrInfo &TII) |
Returns true if reaching def RD will be in AGPR form after the rewrite and so needs no bridge copy: a candidate MFMA in RewriteSet, an AV_MOV_*_IMM_PSEUDO, or a copy from a candidate src2 reg in CandSrc2Regs. | |
| static bool | hasIGLPInstrs (ScheduleDAGInstrs *DAG) |
This contains a MachineSchedStrategy implementation for maximizing wave occupancy on GCN hardware.
This pass will apply multiple scheduling stages to the same function. Regions are first recorded in GCNScheduleDAGMILive::schedule. The actual entry point for the scheduling of those regions is GCNScheduleDAGMILive::runSchedStages.
Definition in file GCNSchedStrategy.cpp.
| #define DEBUG_TYPE "machine-scheduler" |
Generally, the reason for having multiple scheduling stages is to account for the kernel-wide effect of register usage on occupancy.
Usually, only a few scheduling regions will have register pressure high enough to limit occupancy for the kernel, so constraints can be relaxed to improve ILP in other regions.
Definition at line 44 of file GCNSchedStrategy.cpp.
Checks whether SU can use the cached DAG pressure diffs to compute the current register pressure.
This works for the common case, but it has a few exceptions that have been observed through trial and error:
In both of those cases, PressureDiff doesn't represent the actual pressure, and querying LiveIntervals through the RegPressureTracker is needed to get an accurate value.
We should eventually only use PressureDiff for maximum performance, but this already allows 80% of SUs to take the fast path without changing scheduling at all. Further changes would either change scheduling, or require a lot more logic to recover an accurate pressure estimate from the PressureDiffs.
Definition at line 189 of file GCNSchedStrategy.cpp.
References llvm::const_mi_bundle_ops(), llvm::SUnit::getInstr(), and llvm::SUnit::isInstr().
Referenced by llvm::GCNSchedStrategy::initCandidate().
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Definition at line 1083 of file GCNSchedStrategy.cpp.
References assert(), and llvm::skipDebugInstructionsBackward().
Referenced by llvm::RegionPressureMap::buildLiveRegMap().
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Definition at line 2939 of file GCNSchedStrategy.cpp.
References llvm::any_of(), llvm::SIInstrInfo::isIGLPMutationOnly(), MI, and llvm::ScheduleDAG::TII.
Referenced by llvm::GCNPostScheduleDAGMILive::schedule().
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Returns true if reaching def RD will be in AGPR form after the rewrite and so needs no bridge copy: a candidate MFMA in RewriteSet, an AV_MOV_*_IMM_PSEUDO, or a copy from a candidate src2 reg in CandSrc2Regs.
A non-candidate MFMA stays in VGPR form and still needs a bridge.
Definition at line 2229 of file GCNSchedStrategy.cpp.
References llvm::detail::DenseSetImpl< ValueT, MapTy >::contains(), llvm::SmallPtrSetImpl< PtrType >::contains(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::isCopy(), and TII.
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Definition at line 432 of file GCNSchedStrategy.cpp.
References llvm::ReadyQueue::empty(), llvm::SchedBoundary::Pending, llvm::SchedBoundary::pickOnlyChoice(), and shouldCheckPending().
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Definition at line 1889 of file GCNSchedStrategy.cpp.
References llvm::dbgs(), and I.
Referenced by llvm::GCNSchedStage::getScheduleMetrics(), and llvm::GCNSchedStage::getScheduleMetrics().
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Definition at line 424 of file GCNSchedStrategy.cpp.
References llvm::SchedBoundary::Available, llvm::TargetSchedModel::getMicroOpBufferSize(), llvm::TargetSchedModel::hasInstrSchedModel(), llvm::SchedBoundary::Pending, and llvm::ReadyQueue::size().
Referenced by llvm::GCNSchedStrategy::pickNodeFromQueue(), and pickOnlyChoice().