LLVM  10.0.0svn
Host.cpp
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1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the operating system Host concept.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/Config/llvm-config.h"
21 #include "llvm/Support/Debug.h"
25 #include <assert.h>
26 #include <string.h>
27 
28 // Include the platform-specific parts of this class.
29 #ifdef LLVM_ON_UNIX
30 #include "Unix/Host.inc"
31 #endif
32 #ifdef _WIN32
33 #include "Windows/Host.inc"
34 #endif
35 #ifdef _MSC_VER
36 #include <intrin.h>
37 #endif
38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
39 #include <mach/host_info.h>
40 #include <mach/mach.h>
41 #include <mach/mach_host.h>
42 #include <mach/machine.h>
43 #endif
44 
45 #define DEBUG_TYPE "host-detection"
46 
47 //===----------------------------------------------------------------------===//
48 //
49 // Implementations of the CPU detection routines
50 //
51 //===----------------------------------------------------------------------===//
52 
53 using namespace llvm;
54 
55 static std::unique_ptr<llvm::MemoryBuffer>
58  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
59  if (std::error_code EC = Text.getError()) {
60  llvm::errs() << "Can't read "
61  << "/proc/cpuinfo: " << EC.message() << "\n";
62  return nullptr;
63  }
64  return std::move(*Text);
65 }
66 
68  // Access to the Processor Version Register (PVR) on PowerPC is privileged,
69  // and so we must use an operating-system interface to determine the current
70  // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
71  const char *generic = "generic";
72 
73  // The cpu line is second (after the 'processor: 0' line), so if this
74  // buffer is too small then something has changed (or is wrong).
75  StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
76  StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
77 
78  StringRef::const_iterator CIP = CPUInfoStart;
79 
80  StringRef::const_iterator CPUStart = 0;
81  size_t CPULen = 0;
82 
83  // We need to find the first line which starts with cpu, spaces, and a colon.
84  // After the colon, there may be some additional spaces and then the cpu type.
85  while (CIP < CPUInfoEnd && CPUStart == 0) {
86  if (CIP < CPUInfoEnd && *CIP == '\n')
87  ++CIP;
88 
89  if (CIP < CPUInfoEnd && *CIP == 'c') {
90  ++CIP;
91  if (CIP < CPUInfoEnd && *CIP == 'p') {
92  ++CIP;
93  if (CIP < CPUInfoEnd && *CIP == 'u') {
94  ++CIP;
95  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
96  ++CIP;
97 
98  if (CIP < CPUInfoEnd && *CIP == ':') {
99  ++CIP;
100  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
101  ++CIP;
102 
103  if (CIP < CPUInfoEnd) {
104  CPUStart = CIP;
105  while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
106  *CIP != ',' && *CIP != '\n'))
107  ++CIP;
108  CPULen = CIP - CPUStart;
109  }
110  }
111  }
112  }
113  }
114 
115  if (CPUStart == 0)
116  while (CIP < CPUInfoEnd && *CIP != '\n')
117  ++CIP;
118  }
119 
120  if (CPUStart == 0)
121  return generic;
122 
123  return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
124  .Case("604e", "604e")
125  .Case("604", "604")
126  .Case("7400", "7400")
127  .Case("7410", "7400")
128  .Case("7447", "7400")
129  .Case("7455", "7450")
130  .Case("G4", "g4")
131  .Case("POWER4", "970")
132  .Case("PPC970FX", "970")
133  .Case("PPC970MP", "970")
134  .Case("G5", "g5")
135  .Case("POWER5", "g5")
136  .Case("A2", "a2")
137  .Case("POWER6", "pwr6")
138  .Case("POWER7", "pwr7")
139  .Case("POWER8", "pwr8")
140  .Case("POWER8E", "pwr8")
141  .Case("POWER8NVL", "pwr8")
142  .Case("POWER9", "pwr9")
143  .Default(generic);
144 }
145 
147  // The cpuid register on arm is not accessible from user space. On Linux,
148  // it is exposed through the /proc/cpuinfo file.
149 
150  // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
151  // in all cases.
153  ProcCpuinfoContent.split(Lines, "\n");
154 
155  // Look for the CPU implementer line.
156  StringRef Implementer;
157  StringRef Hardware;
158  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
159  if (Lines[I].startswith("CPU implementer"))
160  Implementer = Lines[I].substr(15).ltrim("\t :");
161  if (Lines[I].startswith("Hardware"))
162  Hardware = Lines[I].substr(8).ltrim("\t :");
163  }
164 
165  if (Implementer == "0x41") { // ARM Ltd.
166  // MSM8992/8994 may give cpu part for the core that the kernel is running on,
167  // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
168  if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
169  return "cortex-a53";
170 
171 
172  // Look for the CPU part line.
173  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
174  if (Lines[I].startswith("CPU part"))
175  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
176  // values correspond to the "Part number" in the CP15/c0 register. The
177  // contents are specified in the various processor manuals.
178  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
179  .Case("0x926", "arm926ej-s")
180  .Case("0xb02", "mpcore")
181  .Case("0xb36", "arm1136j-s")
182  .Case("0xb56", "arm1156t2-s")
183  .Case("0xb76", "arm1176jz-s")
184  .Case("0xc08", "cortex-a8")
185  .Case("0xc09", "cortex-a9")
186  .Case("0xc0f", "cortex-a15")
187  .Case("0xc20", "cortex-m0")
188  .Case("0xc23", "cortex-m3")
189  .Case("0xc24", "cortex-m4")
190  .Case("0xd04", "cortex-a35")
191  .Case("0xd03", "cortex-a53")
192  .Case("0xd07", "cortex-a57")
193  .Case("0xd08", "cortex-a72")
194  .Case("0xd09", "cortex-a73")
195  .Case("0xd0a", "cortex-a75")
196  .Case("0xd0b", "cortex-a76")
197  .Default("generic");
198  }
199 
200  if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
201  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
202  if (Lines[I].startswith("CPU part")) {
203  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
204  .Case("0x516", "thunderx2t99")
205  .Case("0x0516", "thunderx2t99")
206  .Case("0xaf", "thunderx2t99")
207  .Case("0x0af", "thunderx2t99")
208  .Case("0xa1", "thunderxt88")
209  .Case("0x0a1", "thunderxt88")
210  .Default("generic");
211  }
212  }
213  }
214 
215  if (Implementer == "0x48") // HiSilicon Technologies, Inc.
216  // Look for the CPU part line.
217  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
218  if (Lines[I].startswith("CPU part"))
219  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
220  // values correspond to the "Part number" in the CP15/c0 register. The
221  // contents are specified in the various processor manuals.
222  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
223  .Case("0xd01", "tsv110")
224  .Default("generic");
225 
226  if (Implementer == "0x51") // Qualcomm Technologies, Inc.
227  // Look for the CPU part line.
228  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
229  if (Lines[I].startswith("CPU part"))
230  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
231  // values correspond to the "Part number" in the CP15/c0 register. The
232  // contents are specified in the various processor manuals.
233  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
234  .Case("0x06f", "krait") // APQ8064
235  .Case("0x201", "kryo")
236  .Case("0x205", "kryo")
237  .Case("0x211", "kryo")
238  .Case("0x800", "cortex-a73")
239  .Case("0x801", "cortex-a73")
240  .Case("0x802", "cortex-a73")
241  .Case("0x803", "cortex-a73")
242  .Case("0x804", "cortex-a73")
243  .Case("0x805", "cortex-a73")
244  .Case("0xc00", "falkor")
245  .Case("0xc01", "saphira")
246  .Default("generic");
247 
248  if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
249  // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
250  // any predictive pattern across variants and parts.
251  unsigned Variant = 0, Part = 0;
252 
253  // Look for the CPU variant line, whose value is a 1 digit hexadecimal
254  // number, corresponding to the Variant bits in the CP15/C0 register.
255  for (auto I : Lines)
256  if (I.consume_front("CPU variant"))
257  I.ltrim("\t :").getAsInteger(0, Variant);
258 
259  // Look for the CPU part line, whose value is a 3 digit hexadecimal
260  // number, corresponding to the PartNum bits in the CP15/C0 register.
261  for (auto I : Lines)
262  if (I.consume_front("CPU part"))
263  I.ltrim("\t :").getAsInteger(0, Part);
264 
265  unsigned Exynos = (Variant << 12) | Part;
266  switch (Exynos) {
267  default:
268  // Default by falling through to Exynos M1.
270 
271  case 0x1001:
272  return "exynos-m1";
273 
274  case 0x4001:
275  return "exynos-m2";
276  }
277  }
278 
279  return "generic";
280 }
281 
283  // STIDP is a privileged operation, so use /proc/cpuinfo instead.
284 
285  // The "processor 0:" line comes after a fair amount of other information,
286  // including a cache breakdown, but this should be plenty.
288  ProcCpuinfoContent.split(Lines, "\n");
289 
290  // Look for the CPU features.
291  SmallVector<StringRef, 32> CPUFeatures;
292  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
293  if (Lines[I].startswith("features")) {
294  size_t Pos = Lines[I].find(":");
295  if (Pos != StringRef::npos) {
296  Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
297  break;
298  }
299  }
300 
301  // We need to check for the presence of vector support independently of
302  // the machine type, since we may only use the vector register set when
303  // supported by the kernel (and hypervisor).
304  bool HaveVectorSupport = false;
305  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
306  if (CPUFeatures[I] == "vx")
307  HaveVectorSupport = true;
308  }
309 
310  // Now check the processor machine type.
311  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
312  if (Lines[I].startswith("processor ")) {
313  size_t Pos = Lines[I].find("machine = ");
314  if (Pos != StringRef::npos) {
315  Pos += sizeof("machine = ") - 1;
316  unsigned int Id;
317  if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
318  if (Id >= 8561 && HaveVectorSupport)
319  return "arch13";
320  if (Id >= 3906 && HaveVectorSupport)
321  return "z14";
322  if (Id >= 2964 && HaveVectorSupport)
323  return "z13";
324  if (Id >= 2827)
325  return "zEC12";
326  if (Id >= 2817)
327  return "z196";
328  }
329  }
330  break;
331  }
332  }
333 
334  return "generic";
335 }
336 
338 #if !defined(__linux__) || !defined(__x86_64__)
339  return "generic";
340 #else
341  uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
342  /* BPF_MOV64_IMM(BPF_REG_0, 0) */
343  { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
344  /* BPF_MOV64_IMM(BPF_REG_2, 1) */
345  0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
346  /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
347  0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
348  /* BPF_MOV64_IMM(BPF_REG_0, 1) */
349  0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
350  /* BPF_EXIT_INSN() */
351  0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
352 
353  uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
354  /* BPF_MOV64_IMM(BPF_REG_0, 0) */
355  { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
356  /* BPF_MOV64_IMM(BPF_REG_2, 1) */
357  0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
358  /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
359  0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
360  /* BPF_MOV64_IMM(BPF_REG_0, 1) */
361  0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
362  /* BPF_EXIT_INSN() */
363  0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
364 
365  struct bpf_prog_load_attr {
366  uint32_t prog_type;
367  uint32_t insn_cnt;
368  uint64_t insns;
369  uint64_t license;
370  uint32_t log_level;
371  uint32_t log_size;
372  uint64_t log_buf;
373  uint32_t kern_version;
374  uint32_t prog_flags;
375  } attr = {};
376  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
377  attr.insn_cnt = 5;
378  attr.insns = (uint64_t)v3_insns;
379  attr.license = (uint64_t)"DUMMY";
380 
381  int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
382  sizeof(attr));
383  if (fd >= 0) {
384  close(fd);
385  return "v3";
386  }
387 
388  /* Clear the whole attr in case its content changed by syscall. */
389  memset(&attr, 0, sizeof(attr));
390  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
391  attr.insn_cnt = 5;
392  attr.insns = (uint64_t)v2_insns;
393  attr.license = (uint64_t)"DUMMY";
394  fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
395  if (fd >= 0) {
396  close(fd);
397  return "v2";
398  }
399  return "v1";
400 #endif
401 }
402 
403 #if defined(__i386__) || defined(_M_IX86) || \
404  defined(__x86_64__) || defined(_M_X64)
405 
406 enum VendorSignatures {
407  SIG_INTEL = 0x756e6547 /* Genu */,
408  SIG_AMD = 0x68747541 /* Auth */
409 };
410 
411 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
412 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
413 // support. Consequently, for i386, the presence of CPUID is checked first
414 // via the corresponding eflags bit.
415 // Removal of cpuid.h header motivated by PR30384
416 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
417 // or test-suite, but are used in external projects e.g. libstdcxx
418 static bool isCpuIdSupported() {
419 #if defined(__GNUC__) || defined(__clang__)
420 #if defined(__i386__)
421  int __cpuid_supported;
422  __asm__(" pushfl\n"
423  " popl %%eax\n"
424  " movl %%eax,%%ecx\n"
425  " xorl $0x00200000,%%eax\n"
426  " pushl %%eax\n"
427  " popfl\n"
428  " pushfl\n"
429  " popl %%eax\n"
430  " movl $0,%0\n"
431  " cmpl %%eax,%%ecx\n"
432  " je 1f\n"
433  " movl $1,%0\n"
434  "1:"
435  : "=r"(__cpuid_supported)
436  :
437  : "eax", "ecx");
438  if (!__cpuid_supported)
439  return false;
440 #endif
441  return true;
442 #endif
443  return true;
444 }
445 
446 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
447 /// the specified arguments. If we can't run cpuid on the host, return true.
448 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
449  unsigned *rECX, unsigned *rEDX) {
450 #if defined(__GNUC__) || defined(__clang__)
451 #if defined(__x86_64__)
452  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
453  // FIXME: should we save this for Clang?
454  __asm__("movq\t%%rbx, %%rsi\n\t"
455  "cpuid\n\t"
456  "xchgq\t%%rbx, %%rsi\n\t"
457  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
458  : "a"(value));
459  return false;
460 #elif defined(__i386__)
461  __asm__("movl\t%%ebx, %%esi\n\t"
462  "cpuid\n\t"
463  "xchgl\t%%ebx, %%esi\n\t"
464  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
465  : "a"(value));
466  return false;
467 #else
468  return true;
469 #endif
470 #elif defined(_MSC_VER)
471  // The MSVC intrinsic is portable across x86 and x64.
472  int registers[4];
473  __cpuid(registers, value);
474  *rEAX = registers[0];
475  *rEBX = registers[1];
476  *rECX = registers[2];
477  *rEDX = registers[3];
478  return false;
479 #else
480  return true;
481 #endif
482 }
483 
484 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
485 /// the 4 values in the specified arguments. If we can't run cpuid on the host,
486 /// return true.
487 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
488  unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
489  unsigned *rEDX) {
490 #if defined(__GNUC__) || defined(__clang__)
491 #if defined(__x86_64__)
492  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
493  // FIXME: should we save this for Clang?
494  __asm__("movq\t%%rbx, %%rsi\n\t"
495  "cpuid\n\t"
496  "xchgq\t%%rbx, %%rsi\n\t"
497  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
498  : "a"(value), "c"(subleaf));
499  return false;
500 #elif defined(__i386__)
501  __asm__("movl\t%%ebx, %%esi\n\t"
502  "cpuid\n\t"
503  "xchgl\t%%ebx, %%esi\n\t"
504  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
505  : "a"(value), "c"(subleaf));
506  return false;
507 #else
508  return true;
509 #endif
510 #elif defined(_MSC_VER)
511  int registers[4];
512  __cpuidex(registers, value, subleaf);
513  *rEAX = registers[0];
514  *rEBX = registers[1];
515  *rECX = registers[2];
516  *rEDX = registers[3];
517  return false;
518 #else
519  return true;
520 #endif
521 }
522 
523 // Read control register 0 (XCR0). Used to detect features such as AVX.
524 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
525 #if defined(__GNUC__) || defined(__clang__)
526  // Check xgetbv; this uses a .byte sequence instead of the instruction
527  // directly because older assemblers do not include support for xgetbv and
528  // there is no easy way to conditionally compile based on the assembler used.
529  __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
530  return false;
531 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
532  unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
533  *rEAX = Result;
534  *rEDX = Result >> 32;
535  return false;
536 #else
537  return true;
538 #endif
539 }
540 
541 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
542  unsigned *Model) {
543  *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
544  *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
545  if (*Family == 6 || *Family == 0xf) {
546  if (*Family == 0xf)
547  // Examine extended family ID if family ID is F.
548  *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
549  // Examine extended model ID if family ID is 6 or F.
550  *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
551  }
552 }
553 
554 static void
555 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
556  unsigned Brand_id, unsigned Features,
557  unsigned Features2, unsigned Features3,
558  unsigned *Type, unsigned *Subtype) {
559  if (Brand_id != 0)
560  return;
561  switch (Family) {
562  case 3:
563  *Type = X86::INTEL_i386;
564  break;
565  case 4:
566  *Type = X86::INTEL_i486;
567  break;
568  case 5:
569  if (Features & (1 << X86::FEATURE_MMX)) {
570  *Type = X86::INTEL_PENTIUM_MMX;
571  break;
572  }
573  *Type = X86::INTEL_PENTIUM;
574  break;
575  case 6:
576  switch (Model) {
577  case 0x01: // Pentium Pro processor
578  *Type = X86::INTEL_PENTIUM_PRO;
579  break;
580  case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
581  // model 03
582  case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
583  // model 05, and Intel Celeron processor, model 05
584  case 0x06: // Celeron processor, model 06
585  *Type = X86::INTEL_PENTIUM_II;
586  break;
587  case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
588  // processor, model 07
589  case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
590  // model 08, and Celeron processor, model 08
591  case 0x0a: // Pentium III Xeon processor, model 0Ah
592  case 0x0b: // Pentium III processor, model 0Bh
593  *Type = X86::INTEL_PENTIUM_III;
594  break;
595  case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
596  case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
597  // 0Dh. All processors are manufactured using the 90 nm process.
598  case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
599  // Integrated Processor with Intel QuickAssist Technology
600  *Type = X86::INTEL_PENTIUM_M;
601  break;
602  case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
603  // 0Eh. All processors are manufactured using the 65 nm process.
604  *Type = X86::INTEL_CORE_DUO;
605  break; // yonah
606  case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
607  // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
608  // mobile processor, Intel Core 2 Extreme processor, Intel
609  // Pentium Dual-Core processor, Intel Xeon processor, model
610  // 0Fh. All processors are manufactured using the 65 nm process.
611  case 0x16: // Intel Celeron processor model 16h. All processors are
612  // manufactured using the 65 nm process
613  *Type = X86::INTEL_CORE2; // "core2"
614  *Subtype = X86::INTEL_CORE2_65;
615  break;
616  case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
617  // 17h. All processors are manufactured using the 45 nm process.
618  //
619  // 45nm: Penryn , Wolfdale, Yorkfield (XE)
620  case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
621  // the 45 nm process.
622  *Type = X86::INTEL_CORE2; // "penryn"
623  *Subtype = X86::INTEL_CORE2_45;
624  break;
625  case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
626  // processors are manufactured using the 45 nm process.
627  case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
628  // As found in a Summer 2010 model iMac.
629  case 0x1f:
630  case 0x2e: // Nehalem EX
631  *Type = X86::INTEL_COREI7; // "nehalem"
632  *Subtype = X86::INTEL_COREI7_NEHALEM;
633  break;
634  case 0x25: // Intel Core i7, laptop version.
635  case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
636  // processors are manufactured using the 32 nm process.
637  case 0x2f: // Westmere EX
638  *Type = X86::INTEL_COREI7; // "westmere"
639  *Subtype = X86::INTEL_COREI7_WESTMERE;
640  break;
641  case 0x2a: // Intel Core i7 processor. All processors are manufactured
642  // using the 32 nm process.
643  case 0x2d:
644  *Type = X86::INTEL_COREI7; //"sandybridge"
645  *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
646  break;
647  case 0x3a:
648  case 0x3e: // Ivy Bridge EP
649  *Type = X86::INTEL_COREI7; // "ivybridge"
650  *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
651  break;
652 
653  // Haswell:
654  case 0x3c:
655  case 0x3f:
656  case 0x45:
657  case 0x46:
658  *Type = X86::INTEL_COREI7; // "haswell"
659  *Subtype = X86::INTEL_COREI7_HASWELL;
660  break;
661 
662  // Broadwell:
663  case 0x3d:
664  case 0x47:
665  case 0x4f:
666  case 0x56:
667  *Type = X86::INTEL_COREI7; // "broadwell"
668  *Subtype = X86::INTEL_COREI7_BROADWELL;
669  break;
670 
671  // Skylake:
672  case 0x4e: // Skylake mobile
673  case 0x5e: // Skylake desktop
674  case 0x8e: // Kaby Lake mobile
675  case 0x9e: // Kaby Lake desktop
676  *Type = X86::INTEL_COREI7; // "skylake"
677  *Subtype = X86::INTEL_COREI7_SKYLAKE;
678  break;
679 
680  // Skylake Xeon:
681  case 0x55:
682  *Type = X86::INTEL_COREI7;
683  if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32)))
684  *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake"
685  else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32)))
686  *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake"
687  else
688  *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
689  break;
690 
691  // Cannonlake:
692  case 0x66:
693  *Type = X86::INTEL_COREI7;
694  *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake"
695  break;
696 
697  // Icelake:
698  case 0x7d:
699  case 0x7e:
700  *Type = X86::INTEL_COREI7;
701  *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client"
702  break;
703 
704  // Icelake Xeon:
705  case 0x6a:
706  case 0x6c:
707  *Type = X86::INTEL_COREI7;
708  *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server"
709  break;
710 
711  case 0x1c: // Most 45 nm Intel Atom processors
712  case 0x26: // 45 nm Atom Lincroft
713  case 0x27: // 32 nm Atom Medfield
714  case 0x35: // 32 nm Atom Midview
715  case 0x36: // 32 nm Atom Midview
716  *Type = X86::INTEL_BONNELL;
717  break; // "bonnell"
718 
719  // Atom Silvermont codes from the Intel software optimization guide.
720  case 0x37:
721  case 0x4a:
722  case 0x4d:
723  case 0x5a:
724  case 0x5d:
725  case 0x4c: // really airmont
726  *Type = X86::INTEL_SILVERMONT;
727  break; // "silvermont"
728  // Goldmont:
729  case 0x5c: // Apollo Lake
730  case 0x5f: // Denverton
731  *Type = X86::INTEL_GOLDMONT;
732  break; // "goldmont"
733  case 0x7a:
734  *Type = X86::INTEL_GOLDMONT_PLUS;
735  break;
736  case 0x86:
737  *Type = X86::INTEL_TREMONT;
738  break;
739 
740  case 0x57:
741  *Type = X86::INTEL_KNL; // knl
742  break;
743 
744  case 0x85:
745  *Type = X86::INTEL_KNM; // knm
746  break;
747 
748  default: // Unknown family 6 CPU, try to guess.
749  // TODO detect tigerlake host
750  if (Features3 & (1 << (X86::FEATURE_AVX512VP2INTERSECT - 64))) {
751  *Type = X86::INTEL_COREI7;
752  *Subtype = X86::INTEL_COREI7_TIGERLAKE;
753  break;
754  }
755 
756  if (Features & (1 << X86::FEATURE_AVX512VBMI2)) {
757  *Type = X86::INTEL_COREI7;
758  *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
759  break;
760  }
761 
762  if (Features & (1 << X86::FEATURE_AVX512VBMI)) {
763  *Type = X86::INTEL_COREI7;
764  *Subtype = X86::INTEL_COREI7_CANNONLAKE;
765  break;
766  }
767 
768  if (Features2 & (1 << (X86::FEATURE_AVX512BF16 - 32))) {
769  *Type = X86::INTEL_COREI7;
770  *Subtype = X86::INTEL_COREI7_COOPERLAKE;
771  break;
772  }
773 
774  if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) {
775  *Type = X86::INTEL_COREI7;
776  *Subtype = X86::INTEL_COREI7_CASCADELAKE;
777  break;
778  }
779 
780  if (Features & (1 << X86::FEATURE_AVX512VL)) {
781  *Type = X86::INTEL_COREI7;
782  *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
783  break;
784  }
785 
786  if (Features & (1 << X86::FEATURE_AVX512ER)) {
787  *Type = X86::INTEL_KNL; // knl
788  break;
789  }
790 
791  if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) {
792  if (Features3 & (1 << (X86::FEATURE_SHA - 64))) {
793  *Type = X86::INTEL_GOLDMONT;
794  } else {
795  *Type = X86::INTEL_COREI7;
796  *Subtype = X86::INTEL_COREI7_SKYLAKE;
797  }
798  break;
799  }
800  if (Features3 & (1 << (X86::FEATURE_ADX - 64))) {
801  *Type = X86::INTEL_COREI7;
802  *Subtype = X86::INTEL_COREI7_BROADWELL;
803  break;
804  }
805  if (Features & (1 << X86::FEATURE_AVX2)) {
806  *Type = X86::INTEL_COREI7;
807  *Subtype = X86::INTEL_COREI7_HASWELL;
808  break;
809  }
810  if (Features & (1 << X86::FEATURE_AVX)) {
811  *Type = X86::INTEL_COREI7;
812  *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
813  break;
814  }
815  if (Features & (1 << X86::FEATURE_SSE4_2)) {
816  if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) {
817  *Type = X86::INTEL_SILVERMONT;
818  } else {
819  *Type = X86::INTEL_COREI7;
820  *Subtype = X86::INTEL_COREI7_NEHALEM;
821  }
822  break;
823  }
824  if (Features & (1 << X86::FEATURE_SSE4_1)) {
825  *Type = X86::INTEL_CORE2; // "penryn"
826  *Subtype = X86::INTEL_CORE2_45;
827  break;
828  }
829  if (Features & (1 << X86::FEATURE_SSSE3)) {
830  if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) {
831  *Type = X86::INTEL_BONNELL; // "bonnell"
832  } else {
833  *Type = X86::INTEL_CORE2; // "core2"
834  *Subtype = X86::INTEL_CORE2_65;
835  }
836  break;
837  }
838  if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) {
839  *Type = X86::INTEL_CORE2; // "core2"
840  *Subtype = X86::INTEL_CORE2_65;
841  break;
842  }
843  if (Features & (1 << X86::FEATURE_SSE3)) {
844  *Type = X86::INTEL_CORE_DUO;
845  break;
846  }
847  if (Features & (1 << X86::FEATURE_SSE2)) {
848  *Type = X86::INTEL_PENTIUM_M;
849  break;
850  }
851  if (Features & (1 << X86::FEATURE_SSE)) {
852  *Type = X86::INTEL_PENTIUM_III;
853  break;
854  }
855  if (Features & (1 << X86::FEATURE_MMX)) {
856  *Type = X86::INTEL_PENTIUM_II;
857  break;
858  }
859  *Type = X86::INTEL_PENTIUM_PRO;
860  break;
861  }
862  break;
863  case 15: {
864  if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) {
865  *Type = X86::INTEL_NOCONA;
866  break;
867  }
868  if (Features & (1 << X86::FEATURE_SSE3)) {
869  *Type = X86::INTEL_PRESCOTT;
870  break;
871  }
872  *Type = X86::INTEL_PENTIUM_IV;
873  break;
874  }
875  default:
876  break; /*"generic"*/
877  }
878 }
879 
880 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
881  unsigned Features, unsigned *Type,
882  unsigned *Subtype) {
883  // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
884  // appears to be no way to generate the wide variety of AMD-specific targets
885  // from the information returned from CPUID.
886  switch (Family) {
887  case 4:
888  *Type = X86::AMD_i486;
889  break;
890  case 5:
891  *Type = X86::AMDPENTIUM;
892  switch (Model) {
893  case 6:
894  case 7:
895  *Subtype = X86::AMDPENTIUM_K6;
896  break; // "k6"
897  case 8:
898  *Subtype = X86::AMDPENTIUM_K62;
899  break; // "k6-2"
900  case 9:
901  case 13:
902  *Subtype = X86::AMDPENTIUM_K63;
903  break; // "k6-3"
904  case 10:
905  *Subtype = X86::AMDPENTIUM_GEODE;
906  break; // "geode"
907  }
908  break;
909  case 6:
910  if (Features & (1 << X86::FEATURE_SSE)) {
911  *Type = X86::AMD_ATHLON_XP;
912  break; // "athlon-xp"
913  }
914  *Type = X86::AMD_ATHLON;
915  break; // "athlon"
916  case 15:
917  if (Features & (1 << X86::FEATURE_SSE3)) {
918  *Type = X86::AMD_K8SSE3;
919  break; // "k8-sse3"
920  }
921  *Type = X86::AMD_K8;
922  break; // "k8"
923  case 16:
924  *Type = X86::AMDFAM10H; // "amdfam10"
925  switch (Model) {
926  case 2:
927  *Subtype = X86::AMDFAM10H_BARCELONA;
928  break;
929  case 4:
930  *Subtype = X86::AMDFAM10H_SHANGHAI;
931  break;
932  case 8:
933  *Subtype = X86::AMDFAM10H_ISTANBUL;
934  break;
935  }
936  break;
937  case 20:
938  *Type = X86::AMD_BTVER1;
939  break; // "btver1";
940  case 21:
941  *Type = X86::AMDFAM15H;
942  if (Model >= 0x60 && Model <= 0x7f) {
943  *Subtype = X86::AMDFAM15H_BDVER4;
944  break; // "bdver4"; 60h-7Fh: Excavator
945  }
946  if (Model >= 0x30 && Model <= 0x3f) {
947  *Subtype = X86::AMDFAM15H_BDVER3;
948  break; // "bdver3"; 30h-3Fh: Steamroller
949  }
950  if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
951  *Subtype = X86::AMDFAM15H_BDVER2;
952  break; // "bdver2"; 02h, 10h-1Fh: Piledriver
953  }
954  if (Model <= 0x0f) {
955  *Subtype = X86::AMDFAM15H_BDVER1;
956  break; // "bdver1"; 00h-0Fh: Bulldozer
957  }
958  break;
959  case 22:
960  *Type = X86::AMD_BTVER2;
961  break; // "btver2"
962  case 23:
963  *Type = X86::AMDFAM17H;
964  if (Model >= 0x30 && Model <= 0x3f) {
965  *Subtype = X86::AMDFAM17H_ZNVER2;
966  break; // "znver2"; 30h-3fh: Zen2
967  }
968  if (Model <= 0x0f) {
969  *Subtype = X86::AMDFAM17H_ZNVER1;
970  break; // "znver1"; 00h-0Fh: Zen1
971  }
972  break;
973  default:
974  break; // "generic"
975  }
976 }
977 
978 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
979  unsigned *FeaturesOut, unsigned *Features2Out,
980  unsigned *Features3Out) {
981  unsigned Features = 0;
982  unsigned Features2 = 0;
983  unsigned Features3 = 0;
984  unsigned EAX, EBX;
985 
986  auto setFeature = [&](unsigned F) {
987  if (F < 32)
988  Features |= 1U << (F & 0x1f);
989  else if (F < 64)
990  Features2 |= 1U << ((F - 32) & 0x1f);
991  else if (F < 96)
992  Features3 |= 1U << ((F - 64) & 0x1f);
993  else
994  llvm_unreachable("Unexpected FeatureBit");
995  };
996 
997  if ((EDX >> 15) & 1)
998  setFeature(X86::FEATURE_CMOV);
999  if ((EDX >> 23) & 1)
1000  setFeature(X86::FEATURE_MMX);
1001  if ((EDX >> 25) & 1)
1002  setFeature(X86::FEATURE_SSE);
1003  if ((EDX >> 26) & 1)
1004  setFeature(X86::FEATURE_SSE2);
1005 
1006  if ((ECX >> 0) & 1)
1007  setFeature(X86::FEATURE_SSE3);
1008  if ((ECX >> 1) & 1)
1009  setFeature(X86::FEATURE_PCLMUL);
1010  if ((ECX >> 9) & 1)
1011  setFeature(X86::FEATURE_SSSE3);
1012  if ((ECX >> 12) & 1)
1013  setFeature(X86::FEATURE_FMA);
1014  if ((ECX >> 19) & 1)
1015  setFeature(X86::FEATURE_SSE4_1);
1016  if ((ECX >> 20) & 1)
1017  setFeature(X86::FEATURE_SSE4_2);
1018  if ((ECX >> 23) & 1)
1019  setFeature(X86::FEATURE_POPCNT);
1020  if ((ECX >> 25) & 1)
1021  setFeature(X86::FEATURE_AES);
1022 
1023  if ((ECX >> 22) & 1)
1024  setFeature(X86::FEATURE_MOVBE);
1025 
1026  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1027  // indicates that the AVX registers will be saved and restored on context
1028  // switch, then we have full AVX support.
1029  const unsigned AVXBits = (1 << 27) | (1 << 28);
1030  bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1031  ((EAX & 0x6) == 0x6);
1032  bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
1033 
1034  if (HasAVX)
1035  setFeature(X86::FEATURE_AVX);
1036 
1037  bool HasLeaf7 =
1038  MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1039 
1040  if (HasLeaf7 && ((EBX >> 3) & 1))
1041  setFeature(X86::FEATURE_BMI);
1042  if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1043  setFeature(X86::FEATURE_AVX2);
1044  if (HasLeaf7 && ((EBX >> 8) & 1))
1045  setFeature(X86::FEATURE_BMI2);
1046  if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
1047  setFeature(X86::FEATURE_AVX512F);
1048  if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1049  setFeature(X86::FEATURE_AVX512DQ);
1050  if (HasLeaf7 && ((EBX >> 19) & 1))
1051  setFeature(X86::FEATURE_ADX);
1052  if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1053  setFeature(X86::FEATURE_AVX512IFMA);
1054  if (HasLeaf7 && ((EBX >> 23) & 1))
1055  setFeature(X86::FEATURE_CLFLUSHOPT);
1056  if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1057  setFeature(X86::FEATURE_AVX512PF);
1058  if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1059  setFeature(X86::FEATURE_AVX512ER);
1060  if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1061  setFeature(X86::FEATURE_AVX512CD);
1062  if (HasLeaf7 && ((EBX >> 29) & 1))
1063  setFeature(X86::FEATURE_SHA);
1064  if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1065  setFeature(X86::FEATURE_AVX512BW);
1066  if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1067  setFeature(X86::FEATURE_AVX512VL);
1068 
1069  if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1070  setFeature(X86::FEATURE_AVX512VBMI);
1071  if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1072  setFeature(X86::FEATURE_AVX512VBMI2);
1073  if (HasLeaf7 && ((ECX >> 8) & 1))
1074  setFeature(X86::FEATURE_GFNI);
1075  if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1076  setFeature(X86::FEATURE_VPCLMULQDQ);
1077  if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1078  setFeature(X86::FEATURE_AVX512VNNI);
1079  if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1080  setFeature(X86::FEATURE_AVX512BITALG);
1081  if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1082  setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1083 
1084  if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1085  setFeature(X86::FEATURE_AVX5124VNNIW);
1086  if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1087  setFeature(X86::FEATURE_AVX5124FMAPS);
1088  if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1089  setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1090 
1091  bool HasLeaf7Subleaf1 =
1092  MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1093  if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1094  setFeature(X86::FEATURE_AVX512BF16);
1095 
1096  unsigned MaxExtLevel;
1097  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1098 
1099  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1100  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1101  if (HasExtLeaf1 && ((ECX >> 6) & 1))
1102  setFeature(X86::FEATURE_SSE4_A);
1103  if (HasExtLeaf1 && ((ECX >> 11) & 1))
1104  setFeature(X86::FEATURE_XOP);
1105  if (HasExtLeaf1 && ((ECX >> 16) & 1))
1106  setFeature(X86::FEATURE_FMA4);
1107 
1108  if (HasExtLeaf1 && ((EDX >> 29) & 1))
1109  setFeature(X86::FEATURE_EM64T);
1110 
1111  *FeaturesOut = Features;
1112  *Features2Out = Features2;
1113  *Features3Out = Features3;
1114 }
1115 
1117  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1118  unsigned MaxLeaf, Vendor;
1119 
1120 #if defined(__GNUC__) || defined(__clang__)
1121  //FIXME: include cpuid.h from clang or copy __get_cpuid_max here
1122  // and simplify it to not invoke __cpuid (like cpu_model.c in
1123  // compiler-rt/lib/builtins/cpu_model.c?
1124  // Opting for the second option.
1125  if(!isCpuIdSupported())
1126  return "generic";
1127 #endif
1128  if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1)
1129  return "generic";
1130  getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1131 
1132  unsigned Brand_id = EBX & 0xff;
1133  unsigned Family = 0, Model = 0;
1134  unsigned Features = 0, Features2 = 0, Features3 = 0;
1135  detectX86FamilyModel(EAX, &Family, &Model);
1136  getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3);
1137 
1138  unsigned Type = 0;
1139  unsigned Subtype = 0;
1140 
1141  if (Vendor == SIG_INTEL) {
1142  getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features,
1143  Features2, Features3, &Type, &Subtype);
1144  } else if (Vendor == SIG_AMD) {
1145  getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
1146  }
1147 
1148  // Check subtypes first since those are more specific.
1149 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \
1150  if (Subtype == X86::ENUM) \
1151  return ARCHNAME;
1152 #include "llvm/Support/X86TargetParser.def"
1153 
1154  // Now check types.
1155 #define X86_CPU_TYPE(ARCHNAME, ENUM) \
1156  if (Type == X86::ENUM) \
1157  return ARCHNAME;
1158 #include "llvm/Support/X86TargetParser.def"
1159 
1160  return "generic";
1161 }
1162 
1163 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
1165  host_basic_info_data_t hostInfo;
1166  mach_msg_type_number_t infoCount;
1167 
1168  infoCount = HOST_BASIC_INFO_COUNT;
1169  mach_port_t hostPort = mach_host_self();
1170  host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1171  &infoCount);
1172  mach_port_deallocate(mach_task_self(), hostPort);
1173 
1174  if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1175  return "generic";
1176 
1177  switch (hostInfo.cpu_subtype) {
1179  return "601";
1181  return "602";
1183  return "603";
1185  return "603e";
1187  return "603ev";
1189  return "604";
1191  return "604e";
1193  return "620";
1195  return "750";
1197  return "7400";
1199  return "7450";
1201  return "970";
1202  default:;
1203  }
1204 
1205  return "generic";
1206 }
1207 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
1209  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1210  StringRef Content = P ? P->getBuffer() : "";
1211  return detail::getHostCPUNameForPowerPC(Content);
1212 }
1213 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1215  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1216  StringRef Content = P ? P->getBuffer() : "";
1217  return detail::getHostCPUNameForARM(Content);
1218 }
1219 #elif defined(__linux__) && defined(__s390x__)
1221  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1222  StringRef Content = P ? P->getBuffer() : "";
1223  return detail::getHostCPUNameForS390x(Content);
1224 }
1225 #else
1226 StringRef sys::getHostCPUName() { return "generic"; }
1227 #endif
1228 
1229 #if defined(__linux__) && defined(__x86_64__)
1230 // On Linux, the number of physical cores can be computed from /proc/cpuinfo,
1231 // using the number of unique physical/core id pairs. The following
1232 // implementation reads the /proc/cpuinfo format on an x86_64 system.
1233 static int computeHostNumPhysicalCores() {
1234  // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
1235  // mmapped because it appears to have 0 size.
1237  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
1238  if (std::error_code EC = Text.getError()) {
1239  llvm::errs() << "Can't read "
1240  << "/proc/cpuinfo: " << EC.message() << "\n";
1241  return -1;
1242  }
1244  (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1,
1245  /*KeepEmpty=*/false);
1246  int CurPhysicalId = -1;
1247  int CurCoreId = -1;
1248  SmallSet<std::pair<int, int>, 32> UniqueItems;
1249  for (auto &Line : strs) {
1250  Line = Line.trim();
1251  if (!Line.startswith("physical id") && !Line.startswith("core id"))
1252  continue;
1253  std::pair<StringRef, StringRef> Data = Line.split(':');
1254  auto Name = Data.first.trim();
1255  auto Val = Data.second.trim();
1256  if (Name == "physical id") {
1257  assert(CurPhysicalId == -1 &&
1258  "Expected a core id before seeing another physical id");
1259  Val.getAsInteger(10, CurPhysicalId);
1260  }
1261  if (Name == "core id") {
1262  assert(CurCoreId == -1 &&
1263  "Expected a physical id before seeing another core id");
1264  Val.getAsInteger(10, CurCoreId);
1265  }
1266  if (CurPhysicalId != -1 && CurCoreId != -1) {
1267  UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId));
1268  CurPhysicalId = -1;
1269  CurCoreId = -1;
1270  }
1271  }
1272  return UniqueItems.size();
1273 }
1274 #elif defined(__APPLE__) && defined(__x86_64__)
1275 #include <sys/param.h>
1276 #include <sys/sysctl.h>
1277 
1278 // Gets the number of *physical cores* on the machine.
1279 static int computeHostNumPhysicalCores() {
1280  uint32_t count;
1281  size_t len = sizeof(count);
1282  sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0);
1283  if (count < 1) {
1284  int nm[2];
1285  nm[0] = CTL_HW;
1286  nm[1] = HW_AVAILCPU;
1287  sysctl(nm, 2, &count, &len, NULL, 0);
1288  if (count < 1)
1289  return -1;
1290  }
1291  return count;
1292 }
1293 #else
1294 // On other systems, return -1 to indicate unknown.
1295 static int computeHostNumPhysicalCores() { return -1; }
1296 #endif
1297 
1299  static int NumCores = computeHostNumPhysicalCores();
1300  return NumCores;
1301 }
1302 
1303 #if defined(__i386__) || defined(_M_IX86) || \
1304  defined(__x86_64__) || defined(_M_X64)
1305 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1306  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1307  unsigned MaxLevel;
1308  union {
1309  unsigned u[3];
1310  char c[12];
1311  } text;
1312 
1313  if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
1314  MaxLevel < 1)
1315  return false;
1316 
1317  getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1318 
1319  Features["cx8"] = (EDX >> 8) & 1;
1320  Features["cmov"] = (EDX >> 15) & 1;
1321  Features["mmx"] = (EDX >> 23) & 1;
1322  Features["fxsr"] = (EDX >> 24) & 1;
1323  Features["sse"] = (EDX >> 25) & 1;
1324  Features["sse2"] = (EDX >> 26) & 1;
1325 
1326  Features["sse3"] = (ECX >> 0) & 1;
1327  Features["pclmul"] = (ECX >> 1) & 1;
1328  Features["ssse3"] = (ECX >> 9) & 1;
1329  Features["cx16"] = (ECX >> 13) & 1;
1330  Features["sse4.1"] = (ECX >> 19) & 1;
1331  Features["sse4.2"] = (ECX >> 20) & 1;
1332  Features["movbe"] = (ECX >> 22) & 1;
1333  Features["popcnt"] = (ECX >> 23) & 1;
1334  Features["aes"] = (ECX >> 25) & 1;
1335  Features["rdrnd"] = (ECX >> 30) & 1;
1336 
1337  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1338  // indicates that the AVX registers will be saved and restored on context
1339  // switch, then we have full AVX support.
1340  bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
1341  !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
1342  // AVX512 requires additional context to be saved by the OS.
1343  bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1344 
1345  Features["avx"] = HasAVXSave;
1346  Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
1347  // Only enable XSAVE if OS has enabled support for saving YMM state.
1348  Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1349  Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
1350 
1351  unsigned MaxExtLevel;
1352  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1353 
1354  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1355  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1356  Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);
1357  Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1358  Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1359  Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1360  Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1361  Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1362  Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1363  Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1364  Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1365 
1366  Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);
1367 
1368  // Miscellaneous memory related features, detected by
1369  // using the 0x80000008 leaf of the CPUID instruction
1370  bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1371  !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1372  Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1373  Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1374 
1375  bool HasLeaf7 =
1376  MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1377 
1378  Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1379  Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1380  Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1381  // AVX2 is only supported if we have the OS save support from AVX.
1382  Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
1383  Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1384  Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
1385  Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1386  // AVX512 is only supported if the OS supports the context save for it.
1387  Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1388  Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1389  Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1390  Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1391  Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1392  Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1393  Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1394  Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1395  Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1396  Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1397  Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1398  Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1399  Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1400 
1401  Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1);
1402  Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1403  Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1404  Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);
1405  Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
1406  Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
1407  Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
1408  Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
1409  Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1410  Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1411  Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1412  Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1413  Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
1414  Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
1415  Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
1416  Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
1417  Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
1418 
1419  // There are two CPUID leafs which information associated with the pconfig
1420  // instruction:
1421  // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1422  // bit of EDX), while the EAX=0x1b leaf returns information on the
1423  // availability of specific pconfig leafs.
1424  // The target feature here only refers to the the first of these two.
1425  // Users might need to check for the availability of specific pconfig
1426  // leaves using cpuid, since that information is ignored while
1427  // detecting features using the "-march=native" flag.
1428  // For more info, see X86 ISA docs.
1429  Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1430  bool HasLeaf7Subleaf1 =
1431  MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1432  Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
1433 
1434  bool HasLeafD = MaxLevel >= 0xd &&
1435  !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1436 
1437  // Only enable XSAVE if OS has enabled support for saving YMM state.
1438  Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1439  Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1440  Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1441 
1442  bool HasLeaf14 = MaxLevel >= 0x14 &&
1443  !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1444 
1445  Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1446 
1447  return true;
1448 }
1449 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1450 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1451  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1452  if (!P)
1453  return false;
1454 
1456  P->getBuffer().split(Lines, "\n");
1457 
1458  SmallVector<StringRef, 32> CPUFeatures;
1459 
1460  // Look for the CPU features.
1461  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1462  if (Lines[I].startswith("Features")) {
1463  Lines[I].split(CPUFeatures, ' ');
1464  break;
1465  }
1466 
1467 #if defined(__aarch64__)
1468  // Keep track of which crypto features we have seen
1469  enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1470  uint32_t crypto = 0;
1471 #endif
1472 
1473  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1474  StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1475 #if defined(__aarch64__)
1476  .Case("asimd", "neon")
1477  .Case("fp", "fp-armv8")
1478  .Case("crc32", "crc")
1479 #else
1480  .Case("half", "fp16")
1481  .Case("neon", "neon")
1482  .Case("vfpv3", "vfp3")
1483  .Case("vfpv3d16", "d16")
1484  .Case("vfpv4", "vfp4")
1485  .Case("idiva", "hwdiv-arm")
1486  .Case("idivt", "hwdiv")
1487 #endif
1488  .Default("");
1489 
1490 #if defined(__aarch64__)
1491  // We need to check crypto separately since we need all of the crypto
1492  // extensions to enable the subtarget feature
1493  if (CPUFeatures[I] == "aes")
1494  crypto |= CAP_AES;
1495  else if (CPUFeatures[I] == "pmull")
1496  crypto |= CAP_PMULL;
1497  else if (CPUFeatures[I] == "sha1")
1498  crypto |= CAP_SHA1;
1499  else if (CPUFeatures[I] == "sha2")
1500  crypto |= CAP_SHA2;
1501 #endif
1502 
1503  if (LLVMFeatureStr != "")
1504  Features[LLVMFeatureStr] = true;
1505  }
1506 
1507 #if defined(__aarch64__)
1508  // If we have all crypto bits we can add the feature
1509  if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1510  Features["crypto"] = true;
1511 #endif
1512 
1513  return true;
1514 }
1515 #else
1516 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1517 #endif
1518 
1519 std::string sys::getProcessTriple() {
1520  std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1521  Triple PT(Triple::normalize(TargetTripleString));
1522 
1523  if (sizeof(void *) == 8 && PT.isArch32Bit())
1524  PT = PT.get64BitArchVariant();
1525  if (sizeof(void *) == 4 && PT.isArch64Bit())
1526  PT = PT.get32BitArchVariant();
1527 
1528  return PT.str();
1529 }
Represents either an error or a value T.
Definition: ErrorOr.h:56
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
Definition: Host.cpp:56
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:281
This class represents lattice values for constants.
Definition: AllocatorList.h:23
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
Definition: Host.cpp:67
F(f)
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
Definition: Host.cpp:282
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
int getHostNumPhysicalCores()
Get the number of physical cores (as opposed to logical cores returned from thread::hardware_concurre...
Definition: Host.cpp:1298
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:29
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1296
const std::string & str() const
Definition: Triple.h:365
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(adl_begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1231
#define P(N)
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
Definition: Triple.cpp:1304
StringRef getHostCPUNameForBPF()
Definition: Host.cpp:337
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
std::error_code getError() const
Definition: ErrorOr.h:159
size_type size() const
Definition: SmallSet.h:159
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:172
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
size_t size() const
Definition: SmallVector.h:52
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
Definition: Host.cpp:1519
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:710
std::string normalize() const
Return the normalized form of this triple&#39;s string.
Definition: Triple.h:289
iterator begin() const
Definition: StringRef.h:115
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
Definition: Host.cpp:1226
static const size_t npos
Definition: StringRef.h:50
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1292
#define I(x, y, z)
Definition: MD5.cpp:58
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
Definition: Host.cpp:146
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:265
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
Definition: Triple.cpp:1368
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool getHostCPUFeatures(StringMap< bool > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
Definition: Host.cpp:1516
iterator end() const
Definition: StringRef.h:117
static int computeHostNumPhysicalCores()
Definition: Host.cpp:1295