18#include "llvm/Config/llvm-config.h"
40#include <mach/host_info.h>
42#include <mach/mach_host.h>
43#include <mach/machine.h>
45#include <sys/sysctl.h>
48#include <sys/systemcfg.h>
50#if defined(__sun__) && defined(__svr4__)
53#if defined(__GNUC__) || defined(__clang__)
54#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
59#define DEBUG_TYPE "host-detection"
69static std::unique_ptr<llvm::MemoryBuffer>
71 const char *CPUInfoFile =
"/proc/cpuinfo";
72 if (
const char *CpuinfoIntercept = std::getenv(
"LLVM_CPUINFO"))
73 CPUInfoFile = CpuinfoIntercept;
77 if (std::error_code EC = Text.getError()) {
78 llvm::errs() <<
"Can't read " << CPUInfoFile <<
": " << EC.message()
82 return std::move(*Text);
89 const char *
generic =
"generic";
103 while (CIP < CPUInfoEnd && CPUStart ==
nullptr) {
104 if (CIP < CPUInfoEnd && *CIP ==
'\n')
107 if (CIP < CPUInfoEnd && *CIP ==
'c') {
109 if (CIP < CPUInfoEnd && *CIP ==
'p') {
111 if (CIP < CPUInfoEnd && *CIP ==
'u') {
113 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
116 if (CIP < CPUInfoEnd && *CIP ==
':') {
118 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
121 if (CIP < CPUInfoEnd) {
123 while (CIP < CPUInfoEnd && (*CIP !=
' ' && *CIP !=
'\t' &&
124 *CIP !=
',' && *CIP !=
'\n'))
126 CPULen = CIP - CPUStart;
133 if (CPUStart ==
nullptr)
134 while (CIP < CPUInfoEnd && *CIP !=
'\n')
138 if (CPUStart ==
nullptr)
142 .
Case(
"604e",
"604e")
144 .
Case(
"7400",
"7400")
145 .
Case(
"7410",
"7400")
146 .
Case(
"7447",
"7400")
147 .
Case(
"7455",
"7450")
149 .
Case(
"POWER4",
"970")
150 .
Case(
"PPC970FX",
"970")
151 .
Case(
"PPC970MP",
"970")
153 .
Case(
"POWER5",
"g5")
155 .
Case(
"POWER6",
"pwr6")
156 .
Case(
"POWER7",
"pwr7")
157 .
Case(
"POWER8",
"pwr8")
158 .
Case(
"POWER8E",
"pwr8")
159 .
Case(
"POWER8NVL",
"pwr8")
160 .
Case(
"POWER9",
"pwr9")
161 .
Case(
"POWER10",
"pwr10")
162 .
Case(
"POWER11",
"pwr11")
176 ProcCpuinfoContent.
split(Lines,
"\n");
182 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
184 Implementer = Lines[
I].substr(15).ltrim(
"\t :");
186 Hardware = Lines[
I].substr(8).ltrim(
"\t :");
188 Part = Lines[
I].substr(8).ltrim(
"\t :");
191 if (Implementer ==
"0x41") {
204 .
Case(
"0x926",
"arm926ej-s")
205 .
Case(
"0xb02",
"mpcore")
206 .
Case(
"0xb36",
"arm1136j-s")
207 .
Case(
"0xb56",
"arm1156t2-s")
208 .
Case(
"0xb76",
"arm1176jz-s")
209 .
Case(
"0xc05",
"cortex-a5")
210 .
Case(
"0xc07",
"cortex-a7")
211 .
Case(
"0xc08",
"cortex-a8")
212 .
Case(
"0xc09",
"cortex-a9")
213 .
Case(
"0xc0f",
"cortex-a15")
214 .
Case(
"0xc0e",
"cortex-a17")
215 .
Case(
"0xc20",
"cortex-m0")
216 .
Case(
"0xc23",
"cortex-m3")
217 .
Case(
"0xc24",
"cortex-m4")
218 .
Case(
"0xc27",
"cortex-m7")
219 .
Case(
"0xd20",
"cortex-m23")
220 .
Case(
"0xd21",
"cortex-m33")
221 .
Case(
"0xd24",
"cortex-m52")
222 .
Case(
"0xd22",
"cortex-m55")
223 .
Case(
"0xd23",
"cortex-m85")
224 .
Case(
"0xc18",
"cortex-r8")
225 .
Case(
"0xd13",
"cortex-r52")
226 .
Case(
"0xd16",
"cortex-r52plus")
227 .
Case(
"0xd15",
"cortex-r82")
228 .
Case(
"0xd14",
"cortex-r82ae")
229 .
Case(
"0xd02",
"cortex-a34")
230 .
Case(
"0xd04",
"cortex-a35")
231 .
Case(
"0xd03",
"cortex-a53")
232 .
Case(
"0xd05",
"cortex-a55")
233 .
Case(
"0xd46",
"cortex-a510")
234 .
Case(
"0xd80",
"cortex-a520")
235 .
Case(
"0xd88",
"cortex-a520ae")
236 .
Case(
"0xd07",
"cortex-a57")
237 .
Case(
"0xd06",
"cortex-a65")
238 .
Case(
"0xd43",
"cortex-a65ae")
239 .
Case(
"0xd08",
"cortex-a72")
240 .
Case(
"0xd09",
"cortex-a73")
241 .
Case(
"0xd0a",
"cortex-a75")
242 .
Case(
"0xd0b",
"cortex-a76")
243 .
Case(
"0xd0e",
"cortex-a76ae")
244 .
Case(
"0xd0d",
"cortex-a77")
245 .
Case(
"0xd41",
"cortex-a78")
246 .
Case(
"0xd42",
"cortex-a78ae")
247 .
Case(
"0xd4b",
"cortex-a78c")
248 .
Case(
"0xd47",
"cortex-a710")
249 .
Case(
"0xd4d",
"cortex-a715")
250 .
Case(
"0xd81",
"cortex-a720")
251 .
Case(
"0xd89",
"cortex-a720ae")
252 .
Case(
"0xd87",
"cortex-a725")
253 .
Case(
"0xd44",
"cortex-x1")
254 .
Case(
"0xd4c",
"cortex-x1c")
255 .
Case(
"0xd48",
"cortex-x2")
256 .
Case(
"0xd4e",
"cortex-x3")
257 .
Case(
"0xd82",
"cortex-x4")
258 .
Case(
"0xd85",
"cortex-x925")
259 .
Case(
"0xd4a",
"neoverse-e1")
260 .
Case(
"0xd0c",
"neoverse-n1")
261 .
Case(
"0xd49",
"neoverse-n2")
262 .
Case(
"0xd8e",
"neoverse-n3")
263 .
Case(
"0xd40",
"neoverse-v1")
264 .
Case(
"0xd4f",
"neoverse-v2")
265 .
Case(
"0xd84",
"neoverse-v3")
266 .
Case(
"0xd83",
"neoverse-v3ae")
270 if (Implementer ==
"0x42" || Implementer ==
"0x43") {
272 .
Case(
"0x516",
"thunderx2t99")
273 .
Case(
"0x0516",
"thunderx2t99")
274 .
Case(
"0xaf",
"thunderx2t99")
275 .
Case(
"0x0af",
"thunderx2t99")
276 .
Case(
"0xa1",
"thunderxt88")
277 .
Case(
"0x0a1",
"thunderxt88")
281 if (Implementer ==
"0x46") {
283 .
Case(
"0x001",
"a64fx")
284 .
Case(
"0x003",
"fujitsu-monaka")
288 if (Implementer ==
"0x4e") {
290 .
Case(
"0x004",
"carmel")
294 if (Implementer ==
"0x48")
299 .
Case(
"0xd01",
"tsv110")
302 if (Implementer ==
"0x51")
307 .
Case(
"0x06f",
"krait")
308 .
Case(
"0x201",
"kryo")
309 .
Case(
"0x205",
"kryo")
310 .
Case(
"0x211",
"kryo")
311 .
Case(
"0x800",
"cortex-a73")
312 .
Case(
"0x801",
"cortex-a73")
313 .
Case(
"0x802",
"cortex-a75")
314 .
Case(
"0x803",
"cortex-a75")
315 .
Case(
"0x804",
"cortex-a76")
316 .
Case(
"0x805",
"cortex-a76")
317 .
Case(
"0xc00",
"falkor")
318 .
Case(
"0xc01",
"saphira")
319 .
Case(
"0x001",
"oryon-1")
321 if (Implementer ==
"0x53") {
324 unsigned Variant = 0, Part = 0;
329 if (
I.consume_front(
"CPU variant"))
330 I.ltrim(
"\t :").getAsInteger(0, Variant);
335 if (
I.consume_front(
"CPU part"))
336 I.ltrim(
"\t :").getAsInteger(0, Part);
338 unsigned Exynos = (Variant << 12) | Part;
350 if (Implementer ==
"0x61") {
352 .
Case(
"0x020",
"apple-m1")
353 .
Case(
"0x021",
"apple-m1")
354 .
Case(
"0x022",
"apple-m1")
355 .
Case(
"0x023",
"apple-m1")
356 .
Case(
"0x024",
"apple-m1")
357 .
Case(
"0x025",
"apple-m1")
358 .
Case(
"0x028",
"apple-m1")
359 .
Case(
"0x029",
"apple-m1")
360 .
Case(
"0x030",
"apple-m2")
361 .
Case(
"0x031",
"apple-m2")
362 .
Case(
"0x032",
"apple-m2")
363 .
Case(
"0x033",
"apple-m2")
364 .
Case(
"0x034",
"apple-m2")
365 .
Case(
"0x035",
"apple-m2")
366 .
Case(
"0x038",
"apple-m2")
367 .
Case(
"0x039",
"apple-m2")
368 .
Case(
"0x049",
"apple-m3")
369 .
Case(
"0x048",
"apple-m3")
373 if (Implementer ==
"0x63") {
375 .
Case(
"0x132",
"star-mc1")
379 if (Implementer ==
"0x6d") {
382 .
Case(
"0xd49",
"neoverse-n2")
386 if (Implementer ==
"0xc0") {
388 .
Case(
"0xac3",
"ampere1")
389 .
Case(
"0xac4",
"ampere1a")
390 .
Case(
"0xac5",
"ampere1b")
398StringRef getCPUNameFromS390Model(
unsigned int Id,
bool HaveVectorSupport) {
418 return HaveVectorSupport?
"z13" :
"zEC12";
421 return HaveVectorSupport?
"z14" :
"zEC12";
424 return HaveVectorSupport?
"z15" :
"zEC12";
428 return HaveVectorSupport?
"z16" :
"zEC12";
439 ProcCpuinfoContent.
split(Lines,
"\n");
443 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I)
445 size_t Pos = Lines[
I].find(
':');
447 Lines[
I].drop_front(Pos + 1).split(CPUFeatures,
' ');
455 bool HaveVectorSupport =
false;
456 for (
unsigned I = 0, E = CPUFeatures.
size();
I != E; ++
I) {
457 if (CPUFeatures[
I] ==
"vx")
458 HaveVectorSupport =
true;
462 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
464 size_t Pos = Lines[
I].find(
"machine = ");
466 Pos +=
sizeof(
"machine = ") - 1;
468 if (!Lines[
I].drop_front(Pos).getAsInteger(10, Id))
469 return getCPUNameFromS390Model(Id, HaveVectorSupport);
481 ProcCpuinfoContent.
split(Lines,
"\n");
485 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
487 UArch = Lines[
I].substr(5).ltrim(
"\t :");
493 .
Case(
"sifive,u74-mc",
"sifive-u74")
494 .
Case(
"sifive,bullet0",
"sifive-u74")
499#if !defined(__linux__) || !defined(__x86_64__)
502 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
504 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
506 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
508 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
510 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
512 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
514 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
516 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
518 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
520 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
522 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
524 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
526 struct bpf_prog_load_attr {
542 int fd = syscall(321 , 5 , &attr,
550 memset(&attr, 0,
sizeof(attr));
555 fd = syscall(321 , 5 , &attr,
sizeof(attr));
564#if defined(__i386__) || defined(_M_IX86) || defined(__x86_64__) || \
569static bool getX86CpuIDAndInfo(
unsigned value,
unsigned *rEAX,
unsigned *rEBX,
570 unsigned *rECX,
unsigned *rEDX) {
571#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
572 return !__get_cpuid(
value, rEAX, rEBX, rECX, rEDX);
573#elif defined(_MSC_VER)
576 __cpuid(registers,
value);
577 *rEAX = registers[0];
578 *rEBX = registers[1];
579 *rECX = registers[2];
580 *rEDX = registers[3];
592VendorSignatures getVendorSignature(
unsigned *MaxLeaf) {
593 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
594 if (MaxLeaf ==
nullptr)
599 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
600 return VendorSignatures::UNKNOWN;
603 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
604 return VendorSignatures::GENUINE_INTEL;
607 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
608 return VendorSignatures::AUTHENTIC_AMD;
610 return VendorSignatures::UNKNOWN;
623static bool getX86CpuIDAndInfoEx(
unsigned value,
unsigned subleaf,
624 unsigned *rEAX,
unsigned *rEBX,
unsigned *rECX,
630#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
631 return !__get_cpuid_count(
value, subleaf, rEAX, rEBX, rECX, rEDX);
632#elif defined(_MSC_VER)
634 __cpuidex(registers,
value, subleaf);
635 *rEAX = registers[0];
636 *rEBX = registers[1];
637 *rECX = registers[2];
638 *rEDX = registers[3];
646static bool getX86XCR0(
unsigned *rEAX,
unsigned *rEDX) {
650#if defined(__GNUC__) || defined(__clang__)
654 __asm__(
".byte 0x0f, 0x01, 0xd0" :
"=a"(*rEAX),
"=d"(*rEDX) :
"c"(0));
656#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
657 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
666static void detectX86FamilyModel(
unsigned EAX,
unsigned *Family,
668 *Family = (
EAX >> 8) & 0xf;
670 if (*Family == 6 || *Family == 0xf) {
673 *Family += (
EAX >> 20) & 0xff;
679#define testFeature(F) (Features[F / 32] & (1 << (F % 32))) != 0
681static StringRef getIntelProcessorTypeAndSubtype(
unsigned Family,
683 const unsigned *Features,
696 if (testFeature(X86::FEATURE_MMX)) {
712 *
Type = X86::INTEL_CORE2;
721 *
Type = X86::INTEL_CORE2;
730 *
Type = X86::INTEL_COREI7;
731 *Subtype = X86::INTEL_COREI7_NEHALEM;
738 *
Type = X86::INTEL_COREI7;
739 *Subtype = X86::INTEL_COREI7_WESTMERE;
745 *
Type = X86::INTEL_COREI7;
746 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
751 *
Type = X86::INTEL_COREI7;
752 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
761 *
Type = X86::INTEL_COREI7;
762 *Subtype = X86::INTEL_COREI7_HASWELL;
771 *
Type = X86::INTEL_COREI7;
772 *Subtype = X86::INTEL_COREI7_BROADWELL;
783 *
Type = X86::INTEL_COREI7;
784 *Subtype = X86::INTEL_COREI7_SKYLAKE;
790 *
Type = X86::INTEL_COREI7;
791 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
796 *
Type = X86::INTEL_COREI7;
797 if (testFeature(X86::FEATURE_AVX512BF16)) {
799 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
800 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
802 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
804 CPU =
"skylake-avx512";
805 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
812 *
Type = X86::INTEL_COREI7;
813 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
819 CPU =
"icelake-client";
820 *
Type = X86::INTEL_COREI7;
821 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
828 *
Type = X86::INTEL_COREI7;
829 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
836 *
Type = X86::INTEL_COREI7;
837 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
843 *
Type = X86::INTEL_COREI7;
844 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
852 *
Type = X86::INTEL_COREI7;
853 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
860 *
Type = X86::INTEL_COREI7;
861 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
869 *
Type = X86::INTEL_COREI7;
870 *Subtype = X86::INTEL_COREI7_ARROWLAKE;
876 *
Type = X86::INTEL_COREI7;
877 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
883 *
Type = X86::INTEL_COREI7;
884 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
890 *
Type = X86::INTEL_COREI7;
891 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;
896 CPU =
"graniterapids";
897 *
Type = X86::INTEL_COREI7;
898 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
903 CPU =
"graniterapids-d";
904 *
Type = X86::INTEL_COREI7;
905 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
911 CPU =
"icelake-server";
912 *
Type = X86::INTEL_COREI7;
913 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
918 CPU =
"emeraldrapids";
919 *
Type = X86::INTEL_COREI7;
920 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
925 CPU =
"sapphirerapids";
926 *
Type = X86::INTEL_COREI7;
927 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
936 *
Type = X86::INTEL_BONNELL;
947 *
Type = X86::INTEL_SILVERMONT;
953 *
Type = X86::INTEL_GOLDMONT;
956 CPU =
"goldmont-plus";
957 *
Type = X86::INTEL_GOLDMONT_PLUS;
964 *
Type = X86::INTEL_TREMONT;
969 CPU =
"sierraforest";
970 *
Type = X86::INTEL_SIERRAFOREST;
976 *
Type = X86::INTEL_GRANDRIDGE;
981 CPU =
"clearwaterforest";
982 *
Type = X86::INTEL_CLEARWATERFOREST;
988 *
Type = X86::INTEL_KNL;
992 *
Type = X86::INTEL_KNM;
999 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
1001 }
else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
1002 CPU =
"icelake-client";
1003 }
else if (testFeature(X86::FEATURE_AVX512VBMI)) {
1005 }
else if (testFeature(X86::FEATURE_AVX512BF16)) {
1007 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
1008 CPU =
"cascadelake";
1009 }
else if (testFeature(X86::FEATURE_AVX512VL)) {
1010 CPU =
"skylake-avx512";
1011 }
else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
1012 if (testFeature(X86::FEATURE_SHA))
1016 }
else if (testFeature(X86::FEATURE_ADX)) {
1018 }
else if (testFeature(X86::FEATURE_AVX2)) {
1020 }
else if (testFeature(X86::FEATURE_AVX)) {
1021 CPU =
"sandybridge";
1022 }
else if (testFeature(X86::FEATURE_SSE4_2)) {
1023 if (testFeature(X86::FEATURE_MOVBE))
1027 }
else if (testFeature(X86::FEATURE_SSE4_1)) {
1029 }
else if (testFeature(X86::FEATURE_SSSE3)) {
1030 if (testFeature(X86::FEATURE_MOVBE))
1034 }
else if (testFeature(X86::FEATURE_64BIT)) {
1036 }
else if (testFeature(X86::FEATURE_SSE3)) {
1038 }
else if (testFeature(X86::FEATURE_SSE2)) {
1040 }
else if (testFeature(X86::FEATURE_SSE)) {
1042 }
else if (testFeature(X86::FEATURE_MMX)) {
1051 if (testFeature(X86::FEATURE_64BIT)) {
1055 if (testFeature(X86::FEATURE_SSE3)) {
1066 CPU =
"diamondrapids";
1067 *
Type = X86::INTEL_COREI7;
1068 *Subtype = X86::INTEL_COREI7_DIAMONDRAPIDS;
1082static const char *getAMDProcessorTypeAndSubtype(
unsigned Family,
1084 const unsigned *Features,
1086 unsigned *Subtype) {
1087 const char *CPU = 0;
1113 if (testFeature(X86::FEATURE_SSE)) {
1120 if (testFeature(X86::FEATURE_SSE3)) {
1129 *
Type = X86::AMDFAM10H;
1132 *Subtype = X86::AMDFAM10H_BARCELONA;
1135 *Subtype = X86::AMDFAM10H_SHANGHAI;
1138 *Subtype = X86::AMDFAM10H_ISTANBUL;
1144 *
Type = X86::AMD_BTVER1;
1148 *
Type = X86::AMDFAM15H;
1149 if (Model >= 0x60 && Model <= 0x7f) {
1151 *Subtype = X86::AMDFAM15H_BDVER4;
1154 if (Model >= 0x30 && Model <= 0x3f) {
1156 *Subtype = X86::AMDFAM15H_BDVER3;
1159 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
1161 *Subtype = X86::AMDFAM15H_BDVER2;
1164 if (Model <= 0x0f) {
1165 *Subtype = X86::AMDFAM15H_BDVER1;
1171 *
Type = X86::AMD_BTVER2;
1175 *
Type = X86::AMDFAM17H;
1176 if ((Model >= 0x30 && Model <= 0x3f) || (Model == 0x47) ||
1177 (Model >= 0x60 && Model <= 0x67) || (Model >= 0x68 && Model <= 0x6f) ||
1178 (Model >= 0x70 && Model <= 0x7f) || (Model >= 0x84 && Model <= 0x87) ||
1179 (Model >= 0x90 && Model <= 0x97) || (Model >= 0x98 && Model <= 0x9f) ||
1180 (Model >= 0xa0 && Model <= 0xaf)) {
1191 *Subtype = X86::AMDFAM17H_ZNVER2;
1194 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x20 && Model <= 0x2f)) {
1198 *Subtype = X86::AMDFAM17H_ZNVER1;
1204 *
Type = X86::AMDFAM19H;
1205 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x2f) ||
1206 (Model >= 0x30 && Model <= 0x3f) || (Model >= 0x40 && Model <= 0x4f) ||
1207 (Model >= 0x50 && Model <= 0x5f)) {
1213 *Subtype = X86::AMDFAM19H_ZNVER3;
1216 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x60 && Model <= 0x6f) ||
1217 (Model >= 0x70 && Model <= 0x77) || (Model >= 0x78 && Model <= 0x7f) ||
1218 (Model >= 0xa0 && Model <= 0xaf)) {
1225 *Subtype = X86::AMDFAM19H_ZNVER4;
1231 *
Type = X86::AMDFAM1AH;
1232 if (Model <= 0x77) {
1243 *Subtype = X86::AMDFAM1AH_ZNVER5;
1257static void getAvailableFeatures(
unsigned ECX,
unsigned EDX,
unsigned MaxLeaf,
1258 unsigned *Features) {
1261 auto setFeature = [&](
unsigned F) {
1262 Features[
F / 32] |= 1U << (
F % 32);
1265 if ((EDX >> 15) & 1)
1266 setFeature(X86::FEATURE_CMOV);
1267 if ((EDX >> 23) & 1)
1268 setFeature(X86::FEATURE_MMX);
1269 if ((EDX >> 25) & 1)
1270 setFeature(X86::FEATURE_SSE);
1271 if ((EDX >> 26) & 1)
1272 setFeature(X86::FEATURE_SSE2);
1275 setFeature(X86::FEATURE_SSE3);
1277 setFeature(X86::FEATURE_PCLMUL);
1279 setFeature(X86::FEATURE_SSSE3);
1280 if ((ECX >> 12) & 1)
1281 setFeature(X86::FEATURE_FMA);
1282 if ((ECX >> 19) & 1)
1283 setFeature(X86::FEATURE_SSE4_1);
1284 if ((ECX >> 20) & 1) {
1285 setFeature(X86::FEATURE_SSE4_2);
1286 setFeature(X86::FEATURE_CRC32);
1288 if ((ECX >> 23) & 1)
1289 setFeature(X86::FEATURE_POPCNT);
1290 if ((ECX >> 25) & 1)
1291 setFeature(X86::FEATURE_AES);
1293 if ((ECX >> 22) & 1)
1294 setFeature(X86::FEATURE_MOVBE);
1299 const unsigned AVXBits = (1 << 27) | (1 << 28);
1300 bool HasAVX = ((
ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1301 ((
EAX & 0x6) == 0x6);
1302#if defined(__APPLE__)
1306 bool HasAVX512Save =
true;
1309 bool HasAVX512Save = HasAVX && ((
EAX & 0xe0) == 0xe0);
1313 setFeature(X86::FEATURE_AVX);
1316 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1318 if (HasLeaf7 && ((EBX >> 3) & 1))
1319 setFeature(X86::FEATURE_BMI);
1320 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1321 setFeature(X86::FEATURE_AVX2);
1322 if (HasLeaf7 && ((EBX >> 8) & 1))
1323 setFeature(X86::FEATURE_BMI2);
1324 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) {
1325 setFeature(X86::FEATURE_AVX512F);
1326 setFeature(X86::FEATURE_EVEX512);
1328 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1329 setFeature(X86::FEATURE_AVX512DQ);
1330 if (HasLeaf7 && ((EBX >> 19) & 1))
1331 setFeature(X86::FEATURE_ADX);
1332 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1333 setFeature(X86::FEATURE_AVX512IFMA);
1334 if (HasLeaf7 && ((EBX >> 23) & 1))
1335 setFeature(X86::FEATURE_CLFLUSHOPT);
1336 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1337 setFeature(X86::FEATURE_AVX512CD);
1338 if (HasLeaf7 && ((EBX >> 29) & 1))
1339 setFeature(X86::FEATURE_SHA);
1340 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1341 setFeature(X86::FEATURE_AVX512BW);
1342 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1343 setFeature(X86::FEATURE_AVX512VL);
1345 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1346 setFeature(X86::FEATURE_AVX512VBMI);
1347 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1348 setFeature(X86::FEATURE_AVX512VBMI2);
1349 if (HasLeaf7 && ((ECX >> 8) & 1))
1350 setFeature(X86::FEATURE_GFNI);
1351 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1352 setFeature(X86::FEATURE_VPCLMULQDQ);
1353 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1354 setFeature(X86::FEATURE_AVX512VNNI);
1355 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1356 setFeature(X86::FEATURE_AVX512BITALG);
1357 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1358 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1360 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1361 setFeature(X86::FEATURE_AVX5124VNNIW);
1362 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1363 setFeature(X86::FEATURE_AVX5124FMAPS);
1364 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1365 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1369 bool HasLeaf7Subleaf1 =
1370 HasLeaf7 &&
EAX >= 1 &&
1371 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1372 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1373 setFeature(X86::FEATURE_AVX512BF16);
1375 unsigned MaxExtLevel;
1376 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1378 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1379 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1380 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1381 setFeature(X86::FEATURE_SSE4_A);
1382 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1383 setFeature(X86::FEATURE_XOP);
1384 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1385 setFeature(X86::FEATURE_FMA4);
1387 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1388 setFeature(X86::FEATURE_64BIT);
1392 unsigned MaxLeaf = 0;
1394 if (Vendor == VendorSignatures::UNKNOWN)
1398 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1400 unsigned Family = 0,
Model = 0;
1402 detectX86FamilyModel(EAX, &Family, &Model);
1403 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1408 unsigned Subtype = 0;
1412 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1413 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1415 }
else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1416 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1426#elif defined(__APPLE__) && defined(__powerpc__)
1428 host_basic_info_data_t hostInfo;
1429 mach_msg_type_number_t infoCount;
1431 infoCount = HOST_BASIC_INFO_COUNT;
1432 mach_port_t hostPort = mach_host_self();
1433 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1435 mach_port_deallocate(mach_task_self(), hostPort);
1437 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1440 switch (hostInfo.cpu_subtype) {
1470#elif defined(__linux__) && defined(__powerpc__)
1474 return detail::getHostCPUNameForPowerPC(
Content);
1476#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1480 return detail::getHostCPUNameForARM(
Content);
1482#elif defined(__linux__) && defined(__s390x__)
1486 return detail::getHostCPUNameForS390x(
Content);
1488#elif defined(__MVS__)
1493 int *StartToCVTOffset =
reinterpret_cast<int *
>(0x10);
1496 int ReadValue = *StartToCVTOffset;
1498 ReadValue = (ReadValue & 0x7FFFFFFF);
1499 char *CVT =
reinterpret_cast<char *
>(ReadValue);
1504 Id = decodePackedBCD<uint16_t>(Id,
false);
1508 bool HaveVectorSupport = CVT[244] & 0x80;
1509 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1511#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1512#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1513#define CPUFAMILY_ARM_CYCLONE 0x37a09642
1514#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1515#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1516#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1517#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1518#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1519#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1520#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1521#define CPUFAMILY_ARM_BLIZZARD_AVALANCHE 0xda33d83d
1522#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea
1526 size_t Length =
sizeof(Family);
1527 sysctlbyname(
"hw.cpufamily", &Family, &
Length, NULL, 0);
1530 case CPUFAMILY_ARM_SWIFT:
1532 case CPUFAMILY_ARM_CYCLONE:
1534 case CPUFAMILY_ARM_TYPHOON:
1536 case CPUFAMILY_ARM_TWISTER:
1538 case CPUFAMILY_ARM_HURRICANE:
1540 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1542 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1544 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1546 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1548 case CPUFAMILY_ARM_BLIZZARD_AVALANCHE:
1550 case CPUFAMILY_ARM_EVEREST_SAWTOOTH:
1559 switch (_system_configuration.implementation) {
1561 if (_system_configuration.version == PV_4_3)
1565 if (_system_configuration.version == PV_5)
1569 if (_system_configuration.version == PV_6_Compat)
1595#elif defined(__loongarch__)
1599 __asm__(
"cpucfg %[prid], $zero\n\t" : [prid]
"=r"(processor_id));
1601 switch (processor_id & 0xf000) {
1612#elif defined(__riscv)
1614#if defined(__linux__)
1621#if __riscv_xlen == 64
1622 return "generic-rv64";
1623#elif __riscv_xlen == 32
1624 return "generic-rv32";
1626#error "Unhandled value of __riscv_xlen"
1629#elif defined(__sparc__)
1630#if defined(__linux__)
1633 ProcCpuinfoContent.
split(Lines,
"\n");
1637 for (
unsigned I = 0, E =
Lines.size();
I != E; ++
I) {
1639 Cpu =
Lines[
I].substr(5).ltrim(
"\t :");
1671#if defined(__linux__)
1674 return detail::getHostCPUNameForSPARC(
Content);
1675#elif defined(__sun__) && defined(__svr4__)
1679 kstat_named_t *brand = NULL;
1683 ksp = kstat_lookup(kc,
const_cast<char *
>(
"cpu_info"), -1, NULL);
1684 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1685 ksp->ks_type == KSTAT_TYPE_NAMED)
1687 (kstat_named_t *)kstat_data_lookup(ksp,
const_cast<char *
>(
"brand"));
1688 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1689 buf = KSTAT_NAMED_STR_PTR(brand);
1694 .
Case(
"TMS390S10",
"supersparc")
1695 .
Case(
"TMS390Z50",
"supersparc")
1698 .
Case(
"MB86904",
"supersparc")
1699 .
Case(
"MB86907",
"supersparc")
1700 .
Case(
"RT623",
"hypersparc")
1701 .
Case(
"RT625",
"hypersparc")
1702 .
Case(
"RT626",
"hypersparc")
1703 .
Case(
"UltraSPARC-I",
"ultrasparc")
1704 .
Case(
"UltraSPARC-II",
"ultrasparc")
1705 .
Case(
"UltraSPARC-IIe",
"ultrasparc")
1706 .
Case(
"UltraSPARC-IIi",
"ultrasparc")
1707 .
Case(
"SPARC64-III",
"ultrasparc")
1708 .
Case(
"SPARC64-IV",
"ultrasparc")
1709 .
Case(
"UltraSPARC-III",
"ultrasparc3")
1710 .
Case(
"UltraSPARC-III+",
"ultrasparc3")
1711 .
Case(
"UltraSPARC-IIIi",
"ultrasparc3")
1712 .
Case(
"UltraSPARC-IIIi+",
"ultrasparc3")
1713 .
Case(
"UltraSPARC-IV",
"ultrasparc3")
1714 .
Case(
"UltraSPARC-IV+",
"ultrasparc3")
1715 .
Case(
"SPARC64-V",
"ultrasparc3")
1716 .
Case(
"SPARC64-VI",
"ultrasparc3")
1717 .
Case(
"SPARC64-VII",
"ultrasparc3")
1718 .
Case(
"UltraSPARC-T1",
"niagara")
1719 .
Case(
"UltraSPARC-T2",
"niagara2")
1720 .
Case(
"UltraSPARC-T2",
"niagara2")
1721 .
Case(
"UltraSPARC-T2+",
"niagara2")
1722 .
Case(
"SPARC-T3",
"niagara3")
1723 .
Case(
"SPARC-T4",
"niagara4")
1724 .
Case(
"SPARC-T5",
"niagara4")
1726 .
Case(
"SPARC-M7",
"niagara4" )
1727 .
Case(
"SPARC-S7",
"niagara4" )
1728 .
Case(
"SPARC-M8",
"niagara4" )
1751#if defined(__i386__) || defined(_M_IX86) || \
1752 defined(__x86_64__) || defined(_M_X64)
1758 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1761 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1763 Features[
"cx8"] = (
EDX >> 8) & 1;
1764 Features[
"cmov"] = (
EDX >> 15) & 1;
1765 Features[
"mmx"] = (
EDX >> 23) & 1;
1766 Features[
"fxsr"] = (
EDX >> 24) & 1;
1767 Features[
"sse"] = (
EDX >> 25) & 1;
1768 Features[
"sse2"] = (
EDX >> 26) & 1;
1770 Features[
"sse3"] = (
ECX >> 0) & 1;
1771 Features[
"pclmul"] = (
ECX >> 1) & 1;
1772 Features[
"ssse3"] = (
ECX >> 9) & 1;
1773 Features[
"cx16"] = (
ECX >> 13) & 1;
1774 Features[
"sse4.1"] = (
ECX >> 19) & 1;
1775 Features[
"sse4.2"] = (
ECX >> 20) & 1;
1776 Features[
"crc32"] = Features[
"sse4.2"];
1777 Features[
"movbe"] = (
ECX >> 22) & 1;
1778 Features[
"popcnt"] = (
ECX >> 23) & 1;
1779 Features[
"aes"] = (
ECX >> 25) & 1;
1780 Features[
"rdrnd"] = (
ECX >> 30) & 1;
1785 bool HasXSave = ((
ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1786 bool HasAVXSave = HasXSave && ((
ECX >> 28) & 1) && ((
EAX & 0x6) == 0x6);
1787#if defined(__APPLE__)
1791 bool HasAVX512Save =
true;
1794 bool HasAVX512Save = HasAVXSave && ((
EAX & 0xe0) == 0xe0);
1797 const unsigned AMXBits = (1 << 17) | (1 << 18);
1798 bool HasAMXSave = HasXSave && ((
EAX & AMXBits) == AMXBits);
1800 Features[
"avx"] = HasAVXSave;
1801 Features[
"fma"] = ((
ECX >> 12) & 1) && HasAVXSave;
1803 Features[
"xsave"] = ((
ECX >> 26) & 1) && HasAVXSave;
1804 Features[
"f16c"] = ((
ECX >> 29) & 1) && HasAVXSave;
1806 unsigned MaxExtLevel;
1807 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1809 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1810 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1811 Features[
"sahf"] = HasExtLeaf1 && ((
ECX >> 0) & 1);
1812 Features[
"lzcnt"] = HasExtLeaf1 && ((
ECX >> 5) & 1);
1813 Features[
"sse4a"] = HasExtLeaf1 && ((
ECX >> 6) & 1);
1814 Features[
"prfchw"] = HasExtLeaf1 && ((
ECX >> 8) & 1);
1815 Features[
"xop"] = HasExtLeaf1 && ((
ECX >> 11) & 1) && HasAVXSave;
1816 Features[
"lwp"] = HasExtLeaf1 && ((
ECX >> 15) & 1);
1817 Features[
"fma4"] = HasExtLeaf1 && ((
ECX >> 16) & 1) && HasAVXSave;
1818 Features[
"tbm"] = HasExtLeaf1 && ((
ECX >> 21) & 1);
1819 Features[
"mwaitx"] = HasExtLeaf1 && ((
ECX >> 29) & 1);
1821 Features[
"64bit"] = HasExtLeaf1 && ((
EDX >> 29) & 1);
1825 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1826 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1827 Features[
"clzero"] = HasExtLeaf8 && ((
EBX >> 0) & 1);
1828 Features[
"rdpru"] = HasExtLeaf8 && ((
EBX >> 4) & 1);
1829 Features[
"wbnoinvd"] = HasExtLeaf8 && ((
EBX >> 9) & 1);
1832 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1834 Features[
"fsgsbase"] = HasLeaf7 && ((
EBX >> 0) & 1);
1835 Features[
"sgx"] = HasLeaf7 && ((
EBX >> 2) & 1);
1836 Features[
"bmi"] = HasLeaf7 && ((
EBX >> 3) & 1);
1838 Features[
"avx2"] = HasLeaf7 && ((
EBX >> 5) & 1) && HasAVXSave;
1839 Features[
"bmi2"] = HasLeaf7 && ((
EBX >> 8) & 1);
1840 Features[
"invpcid"] = HasLeaf7 && ((
EBX >> 10) & 1);
1841 Features[
"rtm"] = HasLeaf7 && ((
EBX >> 11) & 1);
1843 Features[
"avx512f"] = HasLeaf7 && ((
EBX >> 16) & 1) && HasAVX512Save;
1844 if (Features[
"avx512f"])
1845 Features[
"evex512"] =
true;
1846 Features[
"avx512dq"] = HasLeaf7 && ((
EBX >> 17) & 1) && HasAVX512Save;
1847 Features[
"rdseed"] = HasLeaf7 && ((
EBX >> 18) & 1);
1848 Features[
"adx"] = HasLeaf7 && ((
EBX >> 19) & 1);
1849 Features[
"avx512ifma"] = HasLeaf7 && ((
EBX >> 21) & 1) && HasAVX512Save;
1850 Features[
"clflushopt"] = HasLeaf7 && ((
EBX >> 23) & 1);
1851 Features[
"clwb"] = HasLeaf7 && ((
EBX >> 24) & 1);
1852 Features[
"avx512cd"] = HasLeaf7 && ((
EBX >> 28) & 1) && HasAVX512Save;
1853 Features[
"sha"] = HasLeaf7 && ((
EBX >> 29) & 1);
1854 Features[
"avx512bw"] = HasLeaf7 && ((
EBX >> 30) & 1) && HasAVX512Save;
1855 Features[
"avx512vl"] = HasLeaf7 && ((
EBX >> 31) & 1) && HasAVX512Save;
1857 Features[
"avx512vbmi"] = HasLeaf7 && ((
ECX >> 1) & 1) && HasAVX512Save;
1858 Features[
"pku"] = HasLeaf7 && ((
ECX >> 4) & 1);
1859 Features[
"waitpkg"] = HasLeaf7 && ((
ECX >> 5) & 1);
1860 Features[
"avx512vbmi2"] = HasLeaf7 && ((
ECX >> 6) & 1) && HasAVX512Save;
1861 Features[
"shstk"] = HasLeaf7 && ((
ECX >> 7) & 1);
1862 Features[
"gfni"] = HasLeaf7 && ((
ECX >> 8) & 1);
1863 Features[
"vaes"] = HasLeaf7 && ((
ECX >> 9) & 1) && HasAVXSave;
1864 Features[
"vpclmulqdq"] = HasLeaf7 && ((
ECX >> 10) & 1) && HasAVXSave;
1865 Features[
"avx512vnni"] = HasLeaf7 && ((
ECX >> 11) & 1) && HasAVX512Save;
1866 Features[
"avx512bitalg"] = HasLeaf7 && ((
ECX >> 12) & 1) && HasAVX512Save;
1867 Features[
"avx512vpopcntdq"] = HasLeaf7 && ((
ECX >> 14) & 1) && HasAVX512Save;
1868 Features[
"rdpid"] = HasLeaf7 && ((
ECX >> 22) & 1);
1869 Features[
"kl"] = HasLeaf7 && ((
ECX >> 23) & 1);
1870 Features[
"cldemote"] = HasLeaf7 && ((
ECX >> 25) & 1);
1871 Features[
"movdiri"] = HasLeaf7 && ((
ECX >> 27) & 1);
1872 Features[
"movdir64b"] = HasLeaf7 && ((
ECX >> 28) & 1);
1873 Features[
"enqcmd"] = HasLeaf7 && ((
ECX >> 29) & 1);
1875 Features[
"uintr"] = HasLeaf7 && ((
EDX >> 5) & 1);
1876 Features[
"avx512vp2intersect"] =
1877 HasLeaf7 && ((
EDX >> 8) & 1) && HasAVX512Save;
1878 Features[
"serialize"] = HasLeaf7 && ((
EDX >> 14) & 1);
1879 Features[
"tsxldtrk"] = HasLeaf7 && ((
EDX >> 16) & 1);
1890 Features[
"pconfig"] = HasLeaf7 && ((
EDX >> 18) & 1);
1891 Features[
"amx-bf16"] = HasLeaf7 && ((
EDX >> 22) & 1) && HasAMXSave;
1892 Features[
"avx512fp16"] = HasLeaf7 && ((
EDX >> 23) & 1) && HasAVX512Save;
1893 Features[
"amx-tile"] = HasLeaf7 && ((
EDX >> 24) & 1) && HasAMXSave;
1894 Features[
"amx-int8"] = HasLeaf7 && ((
EDX >> 25) & 1) && HasAMXSave;
1897 bool HasLeaf7Subleaf1 =
1898 HasLeaf7 &&
EAX >= 1 &&
1899 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1900 Features[
"sha512"] = HasLeaf7Subleaf1 && ((
EAX >> 0) & 1);
1901 Features[
"sm3"] = HasLeaf7Subleaf1 && ((
EAX >> 1) & 1);
1902 Features[
"sm4"] = HasLeaf7Subleaf1 && ((
EAX >> 2) & 1);
1903 Features[
"raoint"] = HasLeaf7Subleaf1 && ((
EAX >> 3) & 1);
1904 Features[
"avxvnni"] = HasLeaf7Subleaf1 && ((
EAX >> 4) & 1) && HasAVXSave;
1905 Features[
"avx512bf16"] = HasLeaf7Subleaf1 && ((
EAX >> 5) & 1) && HasAVX512Save;
1906 Features[
"amx-fp16"] = HasLeaf7Subleaf1 && ((
EAX >> 21) & 1) && HasAMXSave;
1907 Features[
"cmpccxadd"] = HasLeaf7Subleaf1 && ((
EAX >> 7) & 1);
1908 Features[
"hreset"] = HasLeaf7Subleaf1 && ((
EAX >> 22) & 1);
1909 Features[
"avxifma"] = HasLeaf7Subleaf1 && ((
EAX >> 23) & 1) && HasAVXSave;
1910 Features[
"movrs"] = HasLeaf7Subleaf1 && ((
EAX >> 31) & 1);
1911 Features[
"avxvnniint8"] = HasLeaf7Subleaf1 && ((
EDX >> 4) & 1) && HasAVXSave;
1912 Features[
"avxneconvert"] = HasLeaf7Subleaf1 && ((
EDX >> 5) & 1) && HasAVXSave;
1913 Features[
"amx-complex"] = HasLeaf7Subleaf1 && ((
EDX >> 8) & 1) && HasAMXSave;
1914 Features[
"avxvnniint16"] = HasLeaf7Subleaf1 && ((
EDX >> 10) & 1) && HasAVXSave;
1915 Features[
"prefetchi"] = HasLeaf7Subleaf1 && ((
EDX >> 14) & 1);
1916 Features[
"usermsr"] = HasLeaf7Subleaf1 && ((
EDX >> 15) & 1);
1917 bool HasAVX10 = HasLeaf7Subleaf1 && ((
EDX >> 19) & 1);
1918 bool HasAPXF = HasLeaf7Subleaf1 && ((
EDX >> 21) & 1);
1919 Features[
"egpr"] = HasAPXF;
1920 Features[
"push2pop2"] = HasAPXF;
1921 Features[
"ppx"] = HasAPXF;
1922 Features[
"ndd"] = HasAPXF;
1923 Features[
"ccmp"] = HasAPXF;
1924 Features[
"nf"] = HasAPXF;
1925 Features[
"cf"] = HasAPXF;
1926 Features[
"zu"] = HasAPXF;
1928 bool HasLeafD = MaxLevel >= 0xd &&
1929 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1932 Features[
"xsaveopt"] = HasLeafD && ((
EAX >> 0) & 1) && HasAVXSave;
1933 Features[
"xsavec"] = HasLeafD && ((
EAX >> 1) & 1) && HasAVXSave;
1934 Features[
"xsaves"] = HasLeafD && ((
EAX >> 3) & 1) && HasAVXSave;
1936 bool HasLeaf14 = MaxLevel >= 0x14 &&
1937 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1939 Features[
"ptwrite"] = HasLeaf14 && ((
EBX >> 4) & 1);
1942 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1943 Features[
"widekl"] = HasLeaf7 && HasLeaf19 && ((
EBX >> 2) & 1);
1945 bool HasLeaf1E = MaxLevel >= 0x1e &&
1946 !getX86CpuIDAndInfoEx(0x1e, 0x1, &EAX, &EBX, &ECX, &EDX);
1947 Features[
"amx-fp8"] = HasLeaf1E && ((
EAX >> 4) & 1) && HasAMXSave;
1948 Features[
"amx-transpose"] = HasLeaf1E && ((
EAX >> 5) & 1) && HasAMXSave;
1949 Features[
"amx-tf32"] = HasLeaf1E && ((
EAX >> 6) & 1) && HasAMXSave;
1950 Features[
"amx-avx512"] = HasLeaf1E && ((
EAX >> 7) & 1) && HasAMXSave;
1951 Features[
"amx-movrs"] = HasLeaf1E && ((
EAX >> 8) & 1) && HasAMXSave;
1954 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);
1956 int AVX10Ver = HasLeaf24 && (
EBX & 0xff);
1957 int Has512Len = HasLeaf24 && ((
EBX >> 18) & 1);
1958 Features[
"avx10.1-256"] = HasAVX10 && AVX10Ver >= 1;
1959 Features[
"avx10.1-512"] = HasAVX10 && AVX10Ver >= 1 && Has512Len;
1960 Features[
"avx10.2-256"] = HasAVX10 && AVX10Ver >= 2;
1961 Features[
"avx10.2-512"] = HasAVX10 && AVX10Ver >= 2 && Has512Len;
1965#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1973 P->getBuffer().split(Lines,
"\n");
1978 for (
unsigned I = 0, E =
Lines.size();
I != E; ++
I)
1980 Lines[
I].split(CPUFeatures,
' ');
1984#if defined(__aarch64__)
1987 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1991 for (
unsigned I = 0, E = CPUFeatures.
size();
I != E; ++
I) {
1993#if defined(__aarch64__)
1994 .
Case(
"asimd",
"neon")
1995 .
Case(
"fp",
"fp-armv8")
1996 .
Case(
"crc32",
"crc")
1997 .
Case(
"atomics",
"lse")
1999 .
Case(
"sve2",
"sve2")
2001 .
Case(
"half",
"fp16")
2002 .
Case(
"neon",
"neon")
2003 .
Case(
"vfpv3",
"vfp3")
2004 .
Case(
"vfpv3d16",
"vfp3d16")
2005 .
Case(
"vfpv4",
"vfp4")
2006 .
Case(
"idiva",
"hwdiv-arm")
2007 .
Case(
"idivt",
"hwdiv")
2011#if defined(__aarch64__)
2014 if (CPUFeatures[
I] ==
"aes")
2016 else if (CPUFeatures[
I] ==
"pmull")
2017 crypto |= CAP_PMULL;
2018 else if (CPUFeatures[
I] ==
"sha1")
2020 else if (CPUFeatures[
I] ==
"sha2")
2024 if (LLVMFeatureStr !=
"")
2025 Features[LLVMFeatureStr] =
true;
2028#if defined(__aarch64__)
2032 uint32_t Aes = CAP_AES | CAP_PMULL;
2033 uint32_t Sha2 = CAP_SHA1 | CAP_SHA2;
2034 Features[
"aes"] = (crypto & Aes) == Aes;
2035 Features[
"sha2"] = (crypto & Sha2) == Sha2;
2040#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
2046 IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE);
2048 IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE);
2052 IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE);
2053 Features[
"aes"] = TradCrypto;
2054 Features[
"sha2"] = TradCrypto;
2058#elif defined(__linux__) && defined(__loongarch__)
2059#include <sys/auxv.h>
2061 unsigned long hwcap = getauxval(AT_HWCAP);
2062 bool HasFPU = hwcap & (1UL << 3);
2063 uint32_t cpucfg2 = 0x2, cpucfg3 = 0x3;
2064 __asm__(
"cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2]
"+r"(cpucfg2));
2065 __asm__(
"cpucfg %[cpucfg3], %[cpucfg3]\n\t" : [cpucfg3]
"+r"(cpucfg3));
2069 Features[
"f"] = HasFPU && (cpucfg2 & (1U << 1));
2070 Features[
"d"] = HasFPU && (cpucfg2 & (1U << 2));
2072 Features[
"lsx"] = hwcap & (1UL << 4);
2073 Features[
"lasx"] = hwcap & (1UL << 5);
2074 Features[
"lvz"] = hwcap & (1UL << 9);
2076 Features[
"frecipe"] = cpucfg2 & (1U << 25);
2077 Features[
"div32"] = cpucfg2 & (1U << 26);
2078 Features[
"lam-bh"] = cpucfg2 & (1U << 27);
2079 Features[
"lamcas"] = cpucfg2 & (1U << 28);
2081 Features[
"ld-seq-sa"] = cpucfg3 & (1U << 23);
2088#elif defined(__linux__) && defined(__riscv)
2090struct RISCVHwProbe {
2095 RISCVHwProbe Query[]{{3, 0},
2098 int Ret = syscall(258, Query,
2099 std::size(Query), 0,
2105 uint64_t BaseMask = Query[0].Value;
2108 Features[
"i"] =
true;
2109 Features[
"m"] =
true;
2110 Features[
"a"] =
true;
2114 Features[
"f"] = ExtMask & (1 << 0);
2115 Features[
"d"] = ExtMask & (1 << 0);
2116 Features[
"c"] = ExtMask & (1 << 1);
2117 Features[
"v"] = ExtMask & (1 << 2);
2118 Features[
"zba"] = ExtMask & (1 << 3);
2119 Features[
"zbb"] = ExtMask & (1 << 4);
2120 Features[
"zbs"] = ExtMask & (1 << 5);
2121 Features[
"zicboz"] = ExtMask & (1 << 6);
2122 Features[
"zbc"] = ExtMask & (1 << 7);
2123 Features[
"zbkb"] = ExtMask & (1 << 8);
2124 Features[
"zbkc"] = ExtMask & (1 << 9);
2125 Features[
"zbkx"] = ExtMask & (1 << 10);
2126 Features[
"zknd"] = ExtMask & (1 << 11);
2127 Features[
"zkne"] = ExtMask & (1 << 12);
2128 Features[
"zknh"] = ExtMask & (1 << 13);
2129 Features[
"zksed"] = ExtMask & (1 << 14);
2130 Features[
"zksh"] = ExtMask & (1 << 15);
2131 Features[
"zkt"] = ExtMask & (1 << 16);
2132 Features[
"zvbb"] = ExtMask & (1 << 17);
2133 Features[
"zvbc"] = ExtMask & (1 << 18);
2134 Features[
"zvkb"] = ExtMask & (1 << 19);
2135 Features[
"zvkg"] = ExtMask & (1 << 20);
2136 Features[
"zvkned"] = ExtMask & (1 << 21);
2137 Features[
"zvknha"] = ExtMask & (1 << 22);
2138 Features[
"zvknhb"] = ExtMask & (1 << 23);
2139 Features[
"zvksed"] = ExtMask & (1 << 24);
2140 Features[
"zvksh"] = ExtMask & (1 << 25);
2141 Features[
"zvkt"] = ExtMask & (1 << 26);
2142 Features[
"zfh"] = ExtMask & (1 << 27);
2143 Features[
"zfhmin"] = ExtMask & (1 << 28);
2144 Features[
"zihintntl"] = ExtMask & (1 << 29);
2145 Features[
"zvfh"] = ExtMask & (1 << 30);
2146 Features[
"zvfhmin"] = ExtMask & (1ULL << 31);
2147 Features[
"zfa"] = ExtMask & (1ULL << 32);
2148 Features[
"ztso"] = ExtMask & (1ULL << 33);
2149 Features[
"zacas"] = ExtMask & (1ULL << 34);
2150 Features[
"zicond"] = ExtMask & (1ULL << 35);
2151 Features[
"zihintpause"] =
2152 ExtMask & (1ULL << 36);
2153 Features[
"zve32x"] = ExtMask & (1ULL << 37);
2154 Features[
"zve32f"] = ExtMask & (1ULL << 38);
2155 Features[
"zve64x"] = ExtMask & (1ULL << 39);
2156 Features[
"zve64f"] = ExtMask & (1ULL << 40);
2157 Features[
"zve64d"] = ExtMask & (1ULL << 41);
2158 Features[
"zimop"] = ExtMask & (1ULL << 42);
2159 Features[
"zca"] = ExtMask & (1ULL << 43);
2160 Features[
"zcb"] = ExtMask & (1ULL << 44);
2161 Features[
"zcd"] = ExtMask & (1ULL << 45);
2162 Features[
"zcf"] = ExtMask & (1ULL << 46);
2163 Features[
"zcmop"] = ExtMask & (1ULL << 47);
2164 Features[
"zawrs"] = ExtMask & (1ULL << 48);
2170 if (Query[2].Key != -1 &&
2171 Query[2].
Value == 3)
2172 Features[
"unaligned-scalar-mem"] =
true;
2185 T.setArchName(
"arm");
2186#elif defined(__arm64e__)
2188 T.setArchName(
"arm64e");
2189#elif defined(__aarch64__)
2191 T.setArchName(
"arm64");
2192#elif defined(__x86_64h__)
2194 T.setArchName(
"x86_64h");
2195#elif defined(__x86_64__)
2197 T.setArchName(
"x86_64");
2198#elif defined(__i386__)
2200 T.setArchName(
"i386");
2201#elif defined(__powerpc__)
2203 T.setArchName(
"powerpc");
2205# error "Unimplemented host arch fixup"
2212 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
2218 PT = withHostArch(PT);
2230#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
2232 if (CPU ==
"generic")
2235 <<
" Host CPU: " << CPU <<
'\n';
This file defines the StringMap class.
#define LLVM_ATTRIBUTE_UNUSED
Given that RA is a live value
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Represents either an error or a value T.
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
constexpr bool empty() const
empty - Check if the string is empty.
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
static constexpr size_t npos
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
StringSwitch & StartsWith(StringLiteral S, T Value)
Triple - Helper class for working with autoconf configuration names.
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
std::string normalize() const
Return the normalized form of this triple's string.
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
const std::string & str() const
bool isArch64Bit() const
Test whether the architecture is 64-bit.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
@ CPU_SUBTYPE_POWERPC_970
@ CPU_SUBTYPE_POWERPC_604e
@ CPU_SUBTYPE_POWERPC_603e
@ CPU_SUBTYPE_POWERPC_7400
@ CPU_SUBTYPE_POWERPC_604
@ CPU_SUBTYPE_POWERPC_750
@ CPU_SUBTYPE_POWERPC_601
@ CPU_SUBTYPE_POWERPC_620
@ CPU_SUBTYPE_POWERPC_603ev
@ CPU_SUBTYPE_POWERPC_603
@ CPU_SUBTYPE_POWERPC_7450
@ CPU_SUBTYPE_POWERPC_602
Helper functions to extract CPU details from CPUID on x86.
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
StringRef getHostCPUNameForBPF()
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
const StringMap< bool, MallocAllocator > getHostCPUFeatures()
getHostCPUFeatures - Get the LLVM names for the host CPU features.
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
void printDefaultTargetAndDetectedCPU(raw_ostream &OS)
This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
std::string getDefaultTargetTriple()
getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...
This is an optimization pass for GlobalISel generic memory operations.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.