18#include "llvm/Config/llvm-config.h"
40#include <mach/host_info.h>
42#include <mach/mach_host.h>
43#include <mach/machine.h>
45#include <sys/sysctl.h>
48#include <sys/systemcfg.h>
50#if defined(__sun__) && defined(__svr4__)
54#define DEBUG_TYPE "host-detection"
64static std::unique_ptr<llvm::MemoryBuffer>
68 if (std::error_code EC = Text.getError()) {
70 <<
"/proc/cpuinfo: " << EC.message() <<
"\n";
73 return std::move(*Text);
80 const char *
generic =
"generic";
94 while (CIP < CPUInfoEnd && CPUStart ==
nullptr) {
95 if (CIP < CPUInfoEnd && *CIP ==
'\n')
98 if (CIP < CPUInfoEnd && *CIP ==
'c') {
100 if (CIP < CPUInfoEnd && *CIP ==
'p') {
102 if (CIP < CPUInfoEnd && *CIP ==
'u') {
104 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
107 if (CIP < CPUInfoEnd && *CIP ==
':') {
109 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
112 if (CIP < CPUInfoEnd) {
114 while (CIP < CPUInfoEnd && (*CIP !=
' ' && *CIP !=
'\t' &&
115 *CIP !=
',' && *CIP !=
'\n'))
117 CPULen = CIP - CPUStart;
124 if (CPUStart ==
nullptr)
125 while (CIP < CPUInfoEnd && *CIP !=
'\n')
129 if (CPUStart ==
nullptr)
133 .
Case(
"604e",
"604e")
135 .
Case(
"7400",
"7400")
136 .
Case(
"7410",
"7400")
137 .
Case(
"7447",
"7400")
138 .
Case(
"7455",
"7450")
140 .
Case(
"POWER4",
"970")
141 .
Case(
"PPC970FX",
"970")
142 .
Case(
"PPC970MP",
"970")
144 .
Case(
"POWER5",
"g5")
146 .
Case(
"POWER6",
"pwr6")
147 .
Case(
"POWER7",
"pwr7")
148 .
Case(
"POWER8",
"pwr8")
149 .
Case(
"POWER8E",
"pwr8")
150 .
Case(
"POWER8NVL",
"pwr8")
151 .
Case(
"POWER9",
"pwr9")
152 .
Case(
"POWER10",
"pwr10")
166 ProcCpuinfoContent.
split(Lines,
"\n");
172 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I) {
174 Implementer = Lines[
I].substr(15).ltrim(
"\t :");
176 Hardware = Lines[
I].substr(8).ltrim(
"\t :");
178 Part = Lines[
I].substr(8).ltrim(
"\t :");
181 if (Implementer ==
"0x41") {
194 .
Case(
"0x926",
"arm926ej-s")
195 .
Case(
"0xb02",
"mpcore")
196 .
Case(
"0xb36",
"arm1136j-s")
197 .
Case(
"0xb56",
"arm1156t2-s")
198 .
Case(
"0xb76",
"arm1176jz-s")
199 .
Case(
"0xc08",
"cortex-a8")
200 .
Case(
"0xc09",
"cortex-a9")
201 .
Case(
"0xc0f",
"cortex-a15")
202 .
Case(
"0xc20",
"cortex-m0")
203 .
Case(
"0xc23",
"cortex-m3")
204 .
Case(
"0xc24",
"cortex-m4")
205 .
Case(
"0xd22",
"cortex-m55")
206 .
Case(
"0xd02",
"cortex-a34")
207 .
Case(
"0xd04",
"cortex-a35")
208 .
Case(
"0xd03",
"cortex-a53")
209 .
Case(
"0xd05",
"cortex-a55")
210 .
Case(
"0xd46",
"cortex-a510")
211 .
Case(
"0xd80",
"cortex-a520")
212 .
Case(
"0xd07",
"cortex-a57")
213 .
Case(
"0xd08",
"cortex-a72")
214 .
Case(
"0xd09",
"cortex-a73")
215 .
Case(
"0xd0a",
"cortex-a75")
216 .
Case(
"0xd0b",
"cortex-a76")
217 .
Case(
"0xd0d",
"cortex-a77")
218 .
Case(
"0xd41",
"cortex-a78")
219 .
Case(
"0xd47",
"cortex-a710")
220 .
Case(
"0xd4d",
"cortex-a715")
221 .
Case(
"0xd81",
"cortex-a720")
222 .
Case(
"0xd44",
"cortex-x1")
223 .
Case(
"0xd4c",
"cortex-x1c")
224 .
Case(
"0xd48",
"cortex-x2")
225 .
Case(
"0xd4e",
"cortex-x3")
226 .
Case(
"0xd82",
"cortex-x4")
227 .
Case(
"0xd0c",
"neoverse-n1")
228 .
Case(
"0xd49",
"neoverse-n2")
229 .
Case(
"0xd40",
"neoverse-v1")
230 .
Case(
"0xd4f",
"neoverse-v2")
234 if (Implementer ==
"0x42" || Implementer ==
"0x43") {
236 .
Case(
"0x516",
"thunderx2t99")
237 .
Case(
"0x0516",
"thunderx2t99")
238 .
Case(
"0xaf",
"thunderx2t99")
239 .
Case(
"0x0af",
"thunderx2t99")
240 .
Case(
"0xa1",
"thunderxt88")
241 .
Case(
"0x0a1",
"thunderxt88")
245 if (Implementer ==
"0x46") {
247 .
Case(
"0x001",
"a64fx")
251 if (Implementer ==
"0x4e") {
253 .
Case(
"0x004",
"carmel")
257 if (Implementer ==
"0x48")
262 .
Case(
"0xd01",
"tsv110")
265 if (Implementer ==
"0x51")
270 .
Case(
"0x06f",
"krait")
271 .
Case(
"0x201",
"kryo")
272 .
Case(
"0x205",
"kryo")
273 .
Case(
"0x211",
"kryo")
274 .
Case(
"0x800",
"cortex-a73")
275 .
Case(
"0x801",
"cortex-a73")
276 .
Case(
"0x802",
"cortex-a75")
277 .
Case(
"0x803",
"cortex-a75")
278 .
Case(
"0x804",
"cortex-a76")
279 .
Case(
"0x805",
"cortex-a76")
280 .
Case(
"0xc00",
"falkor")
281 .
Case(
"0xc01",
"saphira")
283 if (Implementer ==
"0x53") {
286 unsigned Variant = 0, Part = 0;
291 if (
I.consume_front(
"CPU variant"))
292 I.ltrim(
"\t :").getAsInteger(0, Variant);
297 if (
I.consume_front(
"CPU part"))
298 I.ltrim(
"\t :").getAsInteger(0, Part);
300 unsigned Exynos = (Variant << 12) | Part;
312 if (Implementer ==
"0xc0") {
314 .
Case(
"0xac3",
"ampere1")
315 .
Case(
"0xac4",
"ampere1a")
323StringRef getCPUNameFromS390Model(
unsigned int Id,
bool HaveVectorSupport) {
343 return HaveVectorSupport?
"z13" :
"zEC12";
346 return HaveVectorSupport?
"z14" :
"zEC12";
349 return HaveVectorSupport?
"z15" :
"zEC12";
353 return HaveVectorSupport?
"z16" :
"zEC12";
364 ProcCpuinfoContent.
split(Lines,
"\n");
368 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I)
370 size_t Pos = Lines[
I].find(
':');
372 Lines[
I].drop_front(Pos + 1).split(CPUFeatures,
' ');
380 bool HaveVectorSupport =
false;
381 for (
unsigned I = 0,
E = CPUFeatures.size();
I !=
E; ++
I) {
382 if (CPUFeatures[
I] ==
"vx")
383 HaveVectorSupport =
true;
387 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I) {
389 size_t Pos = Lines[
I].find(
"machine = ");
391 Pos +=
sizeof(
"machine = ") - 1;
393 if (!Lines[
I].drop_front(Pos).getAsInteger(10, Id))
394 return getCPUNameFromS390Model(Id, HaveVectorSupport);
406 ProcCpuinfoContent.
split(Lines,
"\n");
410 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I) {
412 UArch = Lines[
I].substr(5).ltrim(
"\t :");
418 .
Case(
"sifive,u74-mc",
"sifive-u74")
419 .
Case(
"sifive,bullet0",
"sifive-u74")
424#if !defined(__linux__) || !defined(__x86_64__)
427 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
429 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
431 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
433 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
435 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
437 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
439 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
441 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
443 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
445 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
447 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
449 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
451 struct bpf_prog_load_attr {
467 int fd = syscall(321 , 5 , &attr,
475 memset(&attr, 0,
sizeof(attr));
480 fd = syscall(321 , 5 , &attr,
sizeof(attr));
489#if defined(__i386__) || defined(_M_IX86) || \
490 defined(__x86_64__) || defined(_M_X64)
499static bool isCpuIdSupported() {
500#if defined(__GNUC__) || defined(__clang__)
502 int __cpuid_supported;
505 " movl %%eax,%%ecx\n"
506 " xorl $0x00200000,%%eax\n"
512 " cmpl %%eax,%%ecx\n"
516 :
"=r"(__cpuid_supported)
519 if (!__cpuid_supported)
529static bool getX86CpuIDAndInfo(
unsigned value,
unsigned *rEAX,
unsigned *rEBX,
530 unsigned *rECX,
unsigned *rEDX) {
531#if defined(__GNUC__) || defined(__clang__)
532#if defined(__x86_64__)
535 __asm__(
"movq\t%%rbx, %%rsi\n\t"
537 "xchgq\t%%rbx, %%rsi\n\t"
538 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
541#elif defined(__i386__)
542 __asm__(
"movl\t%%ebx, %%esi\n\t"
544 "xchgl\t%%ebx, %%esi\n\t"
545 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
551#elif defined(_MSC_VER)
554 __cpuid(registers,
value);
555 *rEAX = registers[0];
556 *rEBX = registers[1];
557 *rECX = registers[2];
558 *rEDX = registers[3];
570VendorSignatures getVendorSignature(
unsigned *MaxLeaf) {
571 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
572 if (MaxLeaf ==
nullptr)
577 if (!isCpuIdSupported())
578 return VendorSignatures::UNKNOWN;
580 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
581 return VendorSignatures::UNKNOWN;
584 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
585 return VendorSignatures::GENUINE_INTEL;
588 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
589 return VendorSignatures::AUTHENTIC_AMD;
591 return VendorSignatures::UNKNOWN;
604static bool getX86CpuIDAndInfoEx(
unsigned value,
unsigned subleaf,
605 unsigned *rEAX,
unsigned *rEBX,
unsigned *rECX,
607#if defined(__GNUC__) || defined(__clang__)
608#if defined(__x86_64__)
611 __asm__(
"movq\t%%rbx, %%rsi\n\t"
613 "xchgq\t%%rbx, %%rsi\n\t"
614 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
615 :
"a"(
value),
"c"(subleaf));
617#elif defined(__i386__)
618 __asm__(
"movl\t%%ebx, %%esi\n\t"
620 "xchgl\t%%ebx, %%esi\n\t"
621 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
622 :
"a"(
value),
"c"(subleaf));
627#elif defined(_MSC_VER)
629 __cpuidex(registers,
value, subleaf);
630 *rEAX = registers[0];
631 *rEBX = registers[1];
632 *rECX = registers[2];
633 *rEDX = registers[3];
641static bool getX86XCR0(
unsigned *rEAX,
unsigned *rEDX) {
642#if defined(__GNUC__) || defined(__clang__)
646 __asm__(
".byte 0x0f, 0x01, 0xd0" :
"=a"(*rEAX),
"=d"(*rEDX) :
"c"(0));
648#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
649 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
658static void detectX86FamilyModel(
unsigned EAX,
unsigned *Family,
660 *Family = (
EAX >> 8) & 0xf;
662 if (*Family == 6 || *Family == 0xf) {
665 *Family += (
EAX >> 20) & 0xff;
672getIntelProcessorTypeAndSubtype(
unsigned Family,
unsigned Model,
673 const unsigned *Features,
674 unsigned *
Type,
unsigned *Subtype) {
675 auto testFeature = [&](
unsigned F) {
676 return (Features[
F / 32] & (1U << (
F % 32))) != 0;
689 if (testFeature(X86::FEATURE_MMX)) {
705 *
Type = X86::INTEL_CORE2;
714 *
Type = X86::INTEL_CORE2;
723 *
Type = X86::INTEL_COREI7;
724 *Subtype = X86::INTEL_COREI7_NEHALEM;
731 *
Type = X86::INTEL_COREI7;
732 *Subtype = X86::INTEL_COREI7_WESTMERE;
738 *
Type = X86::INTEL_COREI7;
739 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
744 *
Type = X86::INTEL_COREI7;
745 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
754 *
Type = X86::INTEL_COREI7;
755 *Subtype = X86::INTEL_COREI7_HASWELL;
764 *
Type = X86::INTEL_COREI7;
765 *Subtype = X86::INTEL_COREI7_BROADWELL;
776 *
Type = X86::INTEL_COREI7;
777 *Subtype = X86::INTEL_COREI7_SKYLAKE;
783 *
Type = X86::INTEL_COREI7;
784 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
789 *
Type = X86::INTEL_COREI7;
790 if (testFeature(X86::FEATURE_AVX512BF16)) {
792 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
793 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
795 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
797 CPU =
"skylake-avx512";
798 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
805 *
Type = X86::INTEL_COREI7;
806 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
812 CPU =
"icelake-client";
813 *
Type = X86::INTEL_COREI7;
814 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
821 *
Type = X86::INTEL_COREI7;
822 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
838 *
Type = X86::INTEL_COREI7;
839 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
845 *
Type = X86::INTEL_COREI7;
846 *Subtype = X86::INTEL_COREI7_ARROWLAKE;
854 *
Type = X86::INTEL_COREI7;
855 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
861 *
Type = X86::INTEL_COREI7;
862 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;
867 CPU =
"graniterapids";
868 *
Type = X86::INTEL_COREI7;
869 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
874 CPU =
"graniterapids-d";
875 *
Type = X86::INTEL_COREI7;
876 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
882 CPU =
"icelake-server";
883 *
Type = X86::INTEL_COREI7;
884 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
891 CPU =
"sapphirerapids";
892 *
Type = X86::INTEL_COREI7;
893 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
902 *
Type = X86::INTEL_BONNELL;
913 *
Type = X86::INTEL_SILVERMONT;
919 *
Type = X86::INTEL_GOLDMONT;
922 CPU =
"goldmont-plus";
923 *
Type = X86::INTEL_GOLDMONT_PLUS;
930 *
Type = X86::INTEL_TREMONT;
935 CPU =
"sierraforest";
936 *
Type = X86::INTEL_SIERRAFOREST;
942 *
Type = X86::INTEL_GRANDRIDGE;
947 CPU =
"clearwaterforest";
948 *
Type = X86::INTEL_CLEARWATERFOREST;
954 *
Type = X86::INTEL_KNL;
958 *
Type = X86::INTEL_KNM;
965 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
967 }
else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
968 CPU =
"icelake-client";
969 }
else if (testFeature(X86::FEATURE_AVX512VBMI)) {
971 }
else if (testFeature(X86::FEATURE_AVX512BF16)) {
973 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
975 }
else if (testFeature(X86::FEATURE_AVX512VL)) {
976 CPU =
"skylake-avx512";
977 }
else if (testFeature(X86::FEATURE_AVX512ER)) {
979 }
else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
980 if (testFeature(X86::FEATURE_SHA))
984 }
else if (testFeature(X86::FEATURE_ADX)) {
986 }
else if (testFeature(X86::FEATURE_AVX2)) {
988 }
else if (testFeature(X86::FEATURE_AVX)) {
990 }
else if (testFeature(X86::FEATURE_SSE4_2)) {
991 if (testFeature(X86::FEATURE_MOVBE))
995 }
else if (testFeature(X86::FEATURE_SSE4_1)) {
997 }
else if (testFeature(X86::FEATURE_SSSE3)) {
998 if (testFeature(X86::FEATURE_MOVBE))
1002 }
else if (testFeature(X86::FEATURE_64BIT)) {
1004 }
else if (testFeature(X86::FEATURE_SSE3)) {
1006 }
else if (testFeature(X86::FEATURE_SSE2)) {
1008 }
else if (testFeature(X86::FEATURE_SSE)) {
1010 }
else if (testFeature(X86::FEATURE_MMX)) {
1019 if (testFeature(X86::FEATURE_64BIT)) {
1023 if (testFeature(X86::FEATURE_SSE3)) {
1038getAMDProcessorTypeAndSubtype(
unsigned Family,
unsigned Model,
1039 const unsigned *Features,
1040 unsigned *
Type,
unsigned *Subtype) {
1041 auto testFeature = [&](
unsigned F) {
1042 return (Features[
F / 32] & (1U << (
F % 32))) != 0;
1071 if (testFeature(X86::FEATURE_SSE)) {
1078 if (testFeature(X86::FEATURE_SSE3)) {
1086 *
Type = X86::AMDFAM10H;
1089 *Subtype = X86::AMDFAM10H_BARCELONA;
1092 *Subtype = X86::AMDFAM10H_SHANGHAI;
1095 *Subtype = X86::AMDFAM10H_ISTANBUL;
1101 *
Type = X86::AMD_BTVER1;
1105 *
Type = X86::AMDFAM15H;
1106 if (Model >= 0x60 && Model <= 0x7f) {
1108 *Subtype = X86::AMDFAM15H_BDVER4;
1111 if (Model >= 0x30 && Model <= 0x3f) {
1113 *Subtype = X86::AMDFAM15H_BDVER3;
1116 if ((Model >= 0x10 && Model <= 0x1f) ||
Model == 0x02) {
1118 *Subtype = X86::AMDFAM15H_BDVER2;
1121 if (Model <= 0x0f) {
1122 *Subtype = X86::AMDFAM15H_BDVER1;
1128 *
Type = X86::AMD_BTVER2;
1132 *
Type = X86::AMDFAM17H;
1133 if ((Model >= 0x30 && Model <= 0x3f) ||
Model == 0x71) {
1135 *Subtype = X86::AMDFAM17H_ZNVER2;
1138 if (Model <= 0x0f) {
1139 *Subtype = X86::AMDFAM17H_ZNVER1;
1145 *
Type = X86::AMDFAM19H;
1146 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x5f)) {
1152 *Subtype = X86::AMDFAM19H_ZNVER3;
1155 if ((Model >= 0x10 && Model <= 0x1f) ||
1157 (Model >= 0x78 && Model <= 0x7b) ||
1160 *Subtype = X86::AMDFAM19H_ZNVER4;
1171static void getAvailableFeatures(
unsigned ECX,
unsigned EDX,
unsigned MaxLeaf,
1172 unsigned *Features) {
1175 auto setFeature = [&](
unsigned F) {
1176 Features[
F / 32] |= 1U << (
F % 32);
1179 if ((EDX >> 15) & 1)
1180 setFeature(X86::FEATURE_CMOV);
1181 if ((EDX >> 23) & 1)
1182 setFeature(X86::FEATURE_MMX);
1183 if ((EDX >> 25) & 1)
1184 setFeature(X86::FEATURE_SSE);
1185 if ((EDX >> 26) & 1)
1186 setFeature(X86::FEATURE_SSE2);
1189 setFeature(X86::FEATURE_SSE3);
1191 setFeature(X86::FEATURE_PCLMUL);
1193 setFeature(X86::FEATURE_SSSE3);
1194 if ((ECX >> 12) & 1)
1195 setFeature(X86::FEATURE_FMA);
1196 if ((ECX >> 19) & 1)
1197 setFeature(X86::FEATURE_SSE4_1);
1198 if ((ECX >> 20) & 1) {
1199 setFeature(X86::FEATURE_SSE4_2);
1200 setFeature(X86::FEATURE_CRC32);
1202 if ((ECX >> 23) & 1)
1203 setFeature(X86::FEATURE_POPCNT);
1204 if ((ECX >> 25) & 1)
1205 setFeature(X86::FEATURE_AES);
1207 if ((ECX >> 22) & 1)
1208 setFeature(X86::FEATURE_MOVBE);
1213 const unsigned AVXBits = (1 << 27) | (1 << 28);
1214 bool HasAVX = ((
ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1215 ((
EAX & 0x6) == 0x6);
1216#if defined(__APPLE__)
1220 bool HasAVX512Save =
true;
1223 bool HasAVX512Save = HasAVX && ((
EAX & 0xe0) == 0xe0);
1227 setFeature(X86::FEATURE_AVX);
1230 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1232 if (HasLeaf7 && ((EBX >> 3) & 1))
1233 setFeature(X86::FEATURE_BMI);
1234 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1235 setFeature(X86::FEATURE_AVX2);
1236 if (HasLeaf7 && ((EBX >> 8) & 1))
1237 setFeature(X86::FEATURE_BMI2);
1238 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
1239 setFeature(X86::FEATURE_AVX512F);
1240 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1241 setFeature(X86::FEATURE_AVX512DQ);
1242 if (HasLeaf7 && ((EBX >> 19) & 1))
1243 setFeature(X86::FEATURE_ADX);
1244 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1245 setFeature(X86::FEATURE_AVX512IFMA);
1246 if (HasLeaf7 && ((EBX >> 23) & 1))
1247 setFeature(X86::FEATURE_CLFLUSHOPT);
1248 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1249 setFeature(X86::FEATURE_AVX512PF);
1250 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1251 setFeature(X86::FEATURE_AVX512ER);
1252 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1253 setFeature(X86::FEATURE_AVX512CD);
1254 if (HasLeaf7 && ((EBX >> 29) & 1))
1255 setFeature(X86::FEATURE_SHA);
1256 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1257 setFeature(X86::FEATURE_AVX512BW);
1258 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1259 setFeature(X86::FEATURE_AVX512VL);
1261 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1262 setFeature(X86::FEATURE_AVX512VBMI);
1263 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1264 setFeature(X86::FEATURE_AVX512VBMI2);
1265 if (HasLeaf7 && ((ECX >> 8) & 1))
1266 setFeature(X86::FEATURE_GFNI);
1267 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1268 setFeature(X86::FEATURE_VPCLMULQDQ);
1269 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1270 setFeature(X86::FEATURE_AVX512VNNI);
1271 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1272 setFeature(X86::FEATURE_AVX512BITALG);
1273 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1274 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1276 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1277 setFeature(X86::FEATURE_AVX5124VNNIW);
1278 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1279 setFeature(X86::FEATURE_AVX5124FMAPS);
1280 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1281 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1285 bool HasLeaf7Subleaf1 =
1286 HasLeaf7 &&
EAX >= 1 &&
1287 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1288 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1289 setFeature(X86::FEATURE_AVX512BF16);
1291 unsigned MaxExtLevel;
1292 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1294 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1295 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1296 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1297 setFeature(X86::FEATURE_SSE4_A);
1298 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1299 setFeature(X86::FEATURE_XOP);
1300 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1301 setFeature(X86::FEATURE_FMA4);
1303 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1304 setFeature(X86::FEATURE_64BIT);
1308 unsigned MaxLeaf = 0;
1310 if (Vendor == VendorSignatures::UNKNOWN)
1314 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1316 unsigned Family = 0,
Model = 0;
1318 detectX86FamilyModel(EAX, &Family, &Model);
1319 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1324 unsigned Subtype = 0;
1328 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1329 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1331 }
else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1332 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1342#elif defined(__APPLE__) && defined(__powerpc__)
1344 host_basic_info_data_t hostInfo;
1345 mach_msg_type_number_t infoCount;
1347 infoCount = HOST_BASIC_INFO_COUNT;
1348 mach_port_t hostPort = mach_host_self();
1349 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1351 mach_port_deallocate(mach_task_self(), hostPort);
1353 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1356 switch (hostInfo.cpu_subtype) {
1386#elif defined(__linux__) && defined(__powerpc__)
1392#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1398#elif defined(__linux__) && defined(__s390x__)
1404#elif defined(__MVS__)
1409 int *StartToCVTOffset =
reinterpret_cast<int *
>(0x10);
1412 int ReadValue = *StartToCVTOffset;
1414 ReadValue = (ReadValue & 0x7FFFFFFF);
1415 char *CVT =
reinterpret_cast<char *
>(ReadValue);
1420 Id = decodePackedBCD<uint16_t>(Id,
false);
1424 bool HaveVectorSupport = CVT[244] & 0x80;
1425 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1427#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1428#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1429#define CPUFAMILY_ARM_CYCLONE 0x37a09642
1430#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1431#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1432#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1433#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1434#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1435#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1436#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1440 size_t Length =
sizeof(Family);
1441 sysctlbyname(
"hw.cpufamily", &Family, &
Length, NULL, 0);
1444 case CPUFAMILY_ARM_SWIFT:
1446 case CPUFAMILY_ARM_CYCLONE:
1448 case CPUFAMILY_ARM_TYPHOON:
1450 case CPUFAMILY_ARM_TWISTER:
1452 case CPUFAMILY_ARM_HURRICANE:
1454 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1456 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1458 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1460 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1469 switch (_system_configuration.implementation) {
1471 if (_system_configuration.version == PV_4_3)
1475 if (_system_configuration.version == PV_5)
1479 if (_system_configuration.version == PV_6_Compat)
1499#elif defined(__loongarch__)
1503 __asm__(
"cpucfg %[prid], $zero\n\t" : [prid]
"=r"(processor_id));
1504 switch (processor_id & 0xff00) {
1513#elif defined(__riscv)
1515#if defined(__linux__)
1520#if __riscv_xlen == 64
1521 return "generic-rv64";
1522#elif __riscv_xlen == 32
1523 return "generic-rv32";
1525#error "Unhandled value of __riscv_xlen"
1529#elif defined(__sparc__)
1530#if defined(__linux__)
1533 ProcCpuinfoContent.
split(Lines,
"\n");
1537 for (
unsigned I = 0,
E =
Lines.size();
I !=
E; ++
I) {
1539 Cpu =
Lines[
I].substr(5).ltrim(
"\t :");
1571#if defined(__linux__)
1575#elif defined(__sun__) && defined(__svr4__)
1579 kstat_named_t *brand = NULL;
1583 ksp = kstat_lookup(kc,
const_cast<char *
>(
"cpu_info"), -1, NULL);
1584 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1585 ksp->ks_type == KSTAT_TYPE_NAMED)
1587 (kstat_named_t *)kstat_data_lookup(ksp,
const_cast<char *
>(
"brand"));
1588 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1589 buf = KSTAT_NAMED_STR_PTR(brand);
1594 .
Case(
"TMS390S10",
"supersparc")
1595 .
Case(
"TMS390Z50",
"supersparc")
1598 .
Case(
"MB86904",
"supersparc")
1599 .
Case(
"MB86907",
"supersparc")
1600 .
Case(
"RT623",
"hypersparc")
1601 .
Case(
"RT625",
"hypersparc")
1602 .
Case(
"RT626",
"hypersparc")
1603 .
Case(
"UltraSPARC-I",
"ultrasparc")
1604 .
Case(
"UltraSPARC-II",
"ultrasparc")
1605 .
Case(
"UltraSPARC-IIe",
"ultrasparc")
1606 .
Case(
"UltraSPARC-IIi",
"ultrasparc")
1607 .
Case(
"SPARC64-III",
"ultrasparc")
1608 .
Case(
"SPARC64-IV",
"ultrasparc")
1609 .
Case(
"UltraSPARC-III",
"ultrasparc3")
1610 .
Case(
"UltraSPARC-III+",
"ultrasparc3")
1611 .
Case(
"UltraSPARC-IIIi",
"ultrasparc3")
1612 .
Case(
"UltraSPARC-IIIi+",
"ultrasparc3")
1613 .
Case(
"UltraSPARC-IV",
"ultrasparc3")
1614 .
Case(
"UltraSPARC-IV+",
"ultrasparc3")
1615 .
Case(
"SPARC64-V",
"ultrasparc3")
1616 .
Case(
"SPARC64-VI",
"ultrasparc3")
1617 .
Case(
"SPARC64-VII",
"ultrasparc3")
1618 .
Case(
"UltraSPARC-T1",
"niagara")
1619 .
Case(
"UltraSPARC-T2",
"niagara2")
1620 .
Case(
"UltraSPARC-T2",
"niagara2")
1621 .
Case(
"UltraSPARC-T2+",
"niagara2")
1622 .
Case(
"SPARC-T3",
"niagara3")
1623 .
Case(
"SPARC-T4",
"niagara4")
1624 .
Case(
"SPARC-T5",
"niagara4")
1626 .
Case(
"SPARC-M7",
"niagara4" )
1627 .
Case(
"SPARC-S7",
"niagara4" )
1628 .
Case(
"SPARC-M8",
"niagara4" )
1651#if defined(__i386__) || defined(_M_IX86) || \
1652 defined(__x86_64__) || defined(_M_X64)
1657 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1660 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1662 Features[
"cx8"] = (
EDX >> 8) & 1;
1663 Features[
"cmov"] = (
EDX >> 15) & 1;
1664 Features[
"mmx"] = (
EDX >> 23) & 1;
1665 Features[
"fxsr"] = (
EDX >> 24) & 1;
1666 Features[
"sse"] = (
EDX >> 25) & 1;
1667 Features[
"sse2"] = (
EDX >> 26) & 1;
1669 Features[
"sse3"] = (
ECX >> 0) & 1;
1670 Features[
"pclmul"] = (
ECX >> 1) & 1;
1671 Features[
"ssse3"] = (
ECX >> 9) & 1;
1672 Features[
"cx16"] = (
ECX >> 13) & 1;
1673 Features[
"sse4.1"] = (
ECX >> 19) & 1;
1674 Features[
"sse4.2"] = (
ECX >> 20) & 1;
1675 Features[
"crc32"] = Features[
"sse4.2"];
1676 Features[
"movbe"] = (
ECX >> 22) & 1;
1677 Features[
"popcnt"] = (
ECX >> 23) & 1;
1678 Features[
"aes"] = (
ECX >> 25) & 1;
1679 Features[
"rdrnd"] = (
ECX >> 30) & 1;
1684 bool HasXSave = ((
ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1685 bool HasAVXSave = HasXSave && ((
ECX >> 28) & 1) && ((
EAX & 0x6) == 0x6);
1686#if defined(__APPLE__)
1690 bool HasAVX512Save =
true;
1693 bool HasAVX512Save = HasAVXSave && ((
EAX & 0xe0) == 0xe0);
1696 const unsigned AMXBits = (1 << 17) | (1 << 18);
1697 bool HasAMXSave = HasXSave && ((
EAX & AMXBits) == AMXBits);
1699 Features[
"avx"] = HasAVXSave;
1700 Features[
"fma"] = ((
ECX >> 12) & 1) && HasAVXSave;
1702 Features[
"xsave"] = ((
ECX >> 26) & 1) && HasAVXSave;
1703 Features[
"f16c"] = ((
ECX >> 29) & 1) && HasAVXSave;
1705 unsigned MaxExtLevel;
1706 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1708 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1709 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1710 Features[
"sahf"] = HasExtLeaf1 && ((
ECX >> 0) & 1);
1711 Features[
"lzcnt"] = HasExtLeaf1 && ((
ECX >> 5) & 1);
1712 Features[
"sse4a"] = HasExtLeaf1 && ((
ECX >> 6) & 1);
1713 Features[
"prfchw"] = HasExtLeaf1 && ((
ECX >> 8) & 1);
1714 Features[
"xop"] = HasExtLeaf1 && ((
ECX >> 11) & 1) && HasAVXSave;
1715 Features[
"lwp"] = HasExtLeaf1 && ((
ECX >> 15) & 1);
1716 Features[
"fma4"] = HasExtLeaf1 && ((
ECX >> 16) & 1) && HasAVXSave;
1717 Features[
"tbm"] = HasExtLeaf1 && ((
ECX >> 21) & 1);
1718 Features[
"mwaitx"] = HasExtLeaf1 && ((
ECX >> 29) & 1);
1720 Features[
"64bit"] = HasExtLeaf1 && ((
EDX >> 29) & 1);
1724 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1725 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1726 Features[
"clzero"] = HasExtLeaf8 && ((
EBX >> 0) & 1);
1727 Features[
"rdpru"] = HasExtLeaf8 && ((
EBX >> 4) & 1);
1728 Features[
"wbnoinvd"] = HasExtLeaf8 && ((
EBX >> 9) & 1);
1731 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1733 Features[
"fsgsbase"] = HasLeaf7 && ((
EBX >> 0) & 1);
1734 Features[
"sgx"] = HasLeaf7 && ((
EBX >> 2) & 1);
1735 Features[
"bmi"] = HasLeaf7 && ((
EBX >> 3) & 1);
1737 Features[
"avx2"] = HasLeaf7 && ((
EBX >> 5) & 1) && HasAVXSave;
1738 Features[
"bmi2"] = HasLeaf7 && ((
EBX >> 8) & 1);
1739 Features[
"invpcid"] = HasLeaf7 && ((
EBX >> 10) & 1);
1740 Features[
"rtm"] = HasLeaf7 && ((
EBX >> 11) & 1);
1742 Features[
"avx512f"] = HasLeaf7 && ((
EBX >> 16) & 1) && HasAVX512Save;
1743 Features[
"avx512dq"] = HasLeaf7 && ((
EBX >> 17) & 1) && HasAVX512Save;
1744 Features[
"rdseed"] = HasLeaf7 && ((
EBX >> 18) & 1);
1745 Features[
"adx"] = HasLeaf7 && ((
EBX >> 19) & 1);
1746 Features[
"avx512ifma"] = HasLeaf7 && ((
EBX >> 21) & 1) && HasAVX512Save;
1747 Features[
"clflushopt"] = HasLeaf7 && ((
EBX >> 23) & 1);
1748 Features[
"clwb"] = HasLeaf7 && ((
EBX >> 24) & 1);
1749 Features[
"avx512pf"] = HasLeaf7 && ((
EBX >> 26) & 1) && HasAVX512Save;
1750 Features[
"avx512er"] = HasLeaf7 && ((
EBX >> 27) & 1) && HasAVX512Save;
1751 Features[
"avx512cd"] = HasLeaf7 && ((
EBX >> 28) & 1) && HasAVX512Save;
1752 Features[
"sha"] = HasLeaf7 && ((
EBX >> 29) & 1);
1753 Features[
"avx512bw"] = HasLeaf7 && ((
EBX >> 30) & 1) && HasAVX512Save;
1754 Features[
"avx512vl"] = HasLeaf7 && ((
EBX >> 31) & 1) && HasAVX512Save;
1756 Features[
"prefetchwt1"] = HasLeaf7 && ((
ECX >> 0) & 1);
1757 Features[
"avx512vbmi"] = HasLeaf7 && ((
ECX >> 1) & 1) && HasAVX512Save;
1758 Features[
"pku"] = HasLeaf7 && ((
ECX >> 4) & 1);
1759 Features[
"waitpkg"] = HasLeaf7 && ((
ECX >> 5) & 1);
1760 Features[
"avx512vbmi2"] = HasLeaf7 && ((
ECX >> 6) & 1) && HasAVX512Save;
1761 Features[
"shstk"] = HasLeaf7 && ((
ECX >> 7) & 1);
1762 Features[
"gfni"] = HasLeaf7 && ((
ECX >> 8) & 1);
1763 Features[
"vaes"] = HasLeaf7 && ((
ECX >> 9) & 1) && HasAVXSave;
1764 Features[
"vpclmulqdq"] = HasLeaf7 && ((
ECX >> 10) & 1) && HasAVXSave;
1765 Features[
"avx512vnni"] = HasLeaf7 && ((
ECX >> 11) & 1) && HasAVX512Save;
1766 Features[
"avx512bitalg"] = HasLeaf7 && ((
ECX >> 12) & 1) && HasAVX512Save;
1767 Features[
"avx512vpopcntdq"] = HasLeaf7 && ((
ECX >> 14) & 1) && HasAVX512Save;
1768 Features[
"rdpid"] = HasLeaf7 && ((
ECX >> 22) & 1);
1769 Features[
"kl"] = HasLeaf7 && ((
ECX >> 23) & 1);
1770 Features[
"cldemote"] = HasLeaf7 && ((
ECX >> 25) & 1);
1771 Features[
"movdiri"] = HasLeaf7 && ((
ECX >> 27) & 1);
1772 Features[
"movdir64b"] = HasLeaf7 && ((
ECX >> 28) & 1);
1773 Features[
"enqcmd"] = HasLeaf7 && ((
ECX >> 29) & 1);
1775 Features[
"uintr"] = HasLeaf7 && ((
EDX >> 5) & 1);
1776 Features[
"avx512vp2intersect"] =
1777 HasLeaf7 && ((
EDX >> 8) & 1) && HasAVX512Save;
1778 Features[
"serialize"] = HasLeaf7 && ((
EDX >> 14) & 1);
1779 Features[
"tsxldtrk"] = HasLeaf7 && ((
EDX >> 16) & 1);
1790 Features[
"pconfig"] = HasLeaf7 && ((
EDX >> 18) & 1);
1791 Features[
"amx-bf16"] = HasLeaf7 && ((
EDX >> 22) & 1) && HasAMXSave;
1792 Features[
"avx512fp16"] = HasLeaf7 && ((
EDX >> 23) & 1) && HasAVX512Save;
1793 Features[
"amx-tile"] = HasLeaf7 && ((
EDX >> 24) & 1) && HasAMXSave;
1794 Features[
"amx-int8"] = HasLeaf7 && ((
EDX >> 25) & 1) && HasAMXSave;
1797 bool HasLeaf7Subleaf1 =
1798 HasLeaf7 &&
EAX >= 1 &&
1799 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1800 Features[
"sha512"] = HasLeaf7Subleaf1 && ((
EAX >> 0) & 1);
1801 Features[
"sm3"] = HasLeaf7Subleaf1 && ((
EAX >> 1) & 1);
1802 Features[
"sm4"] = HasLeaf7Subleaf1 && ((
EAX >> 2) & 1);
1803 Features[
"raoint"] = HasLeaf7Subleaf1 && ((
EAX >> 3) & 1);
1804 Features[
"avxvnni"] = HasLeaf7Subleaf1 && ((
EAX >> 4) & 1) && HasAVXSave;
1805 Features[
"avx512bf16"] = HasLeaf7Subleaf1 && ((
EAX >> 5) & 1) && HasAVX512Save;
1806 Features[
"amx-fp16"] = HasLeaf7Subleaf1 && ((
EAX >> 21) & 1) && HasAMXSave;
1807 Features[
"cmpccxadd"] = HasLeaf7Subleaf1 && ((
EAX >> 7) & 1);
1808 Features[
"hreset"] = HasLeaf7Subleaf1 && ((
EAX >> 22) & 1);
1809 Features[
"avxifma"] = HasLeaf7Subleaf1 && ((
EAX >> 23) & 1) && HasAVXSave;
1810 Features[
"avxvnniint8"] = HasLeaf7Subleaf1 && ((
EDX >> 4) & 1) && HasAVXSave;
1811 Features[
"avxneconvert"] = HasLeaf7Subleaf1 && ((
EDX >> 5) & 1) && HasAVXSave;
1812 Features[
"amx-complex"] = HasLeaf7Subleaf1 && ((
EDX >> 8) & 1) && HasAMXSave;
1813 Features[
"avxvnniint16"] = HasLeaf7Subleaf1 && ((
EDX >> 10) & 1) && HasAVXSave;
1814 Features[
"prefetchi"] = HasLeaf7Subleaf1 && ((
EDX >> 14) & 1);
1815 Features[
"usermsr"] = HasLeaf7Subleaf1 && ((
EDX >> 15) & 1);
1816 Features[
"avx10.1-256"] = HasLeaf7Subleaf1 && ((
EDX >> 19) & 1);
1818 bool HasLeafD = MaxLevel >= 0xd &&
1819 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1822 Features[
"xsaveopt"] = HasLeafD && ((
EAX >> 0) & 1) && HasAVXSave;
1823 Features[
"xsavec"] = HasLeafD && ((
EAX >> 1) & 1) && HasAVXSave;
1824 Features[
"xsaves"] = HasLeafD && ((
EAX >> 3) & 1) && HasAVXSave;
1826 bool HasLeaf14 = MaxLevel >= 0x14 &&
1827 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1829 Features[
"ptwrite"] = HasLeaf14 && ((
EBX >> 4) & 1);
1832 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1833 Features[
"widekl"] = HasLeaf7 && HasLeaf19 && ((
EBX >> 2) & 1);
1836 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);
1837 Features[
"avx10.1-512"] =
1838 Features[
"avx10.1-256"] && HasLeaf24 && ((
EBX >> 18) & 1);
1842#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1849 P->getBuffer().split(Lines,
"\n");
1854 for (
unsigned I = 0,
E =
Lines.size();
I !=
E; ++
I)
1856 Lines[
I].split(CPUFeatures,
' ');
1860#if defined(__aarch64__)
1862 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1868#if defined(__aarch64__)
1869 .
Case(
"asimd",
"neon")
1870 .
Case(
"fp",
"fp-armv8")
1871 .
Case(
"crc32",
"crc")
1872 .
Case(
"atomics",
"lse")
1874 .
Case(
"sve2",
"sve2")
1876 .
Case(
"half",
"fp16")
1877 .
Case(
"neon",
"neon")
1878 .
Case(
"vfpv3",
"vfp3")
1879 .
Case(
"vfpv3d16",
"vfp3d16")
1880 .
Case(
"vfpv4",
"vfp4")
1881 .
Case(
"idiva",
"hwdiv-arm")
1882 .
Case(
"idivt",
"hwdiv")
1886#if defined(__aarch64__)
1889 if (CPUFeatures[
I] ==
"aes")
1891 else if (CPUFeatures[
I] ==
"pmull")
1892 crypto |= CAP_PMULL;
1893 else if (CPUFeatures[
I] ==
"sha1")
1895 else if (CPUFeatures[
I] ==
"sha2")
1899 if (LLVMFeatureStr !=
"")
1900 Features[LLVMFeatureStr] =
true;
1903#if defined(__aarch64__)
1905 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1906 Features[
"crypto"] =
true;
1911#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1913 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1914 Features[
"neon"] =
true;
1915 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1916 Features[
"crc"] =
true;
1917 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1918 Features[
"crypto"] =
true;
1922#elif defined(__linux__) && defined(__loongarch__)
1923#include <sys/auxv.h>
1925 unsigned long hwcap = getauxval(AT_HWCAP);
1926 bool HasFPU = hwcap & (1UL << 3);
1928 __asm__(
"cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2]
"+r"(cpucfg2));
1930 Features[
"f"] = HasFPU && (cpucfg2 & (1U << 1));
1931 Features[
"d"] = HasFPU && (cpucfg2 & (1U << 2));
1933 Features[
"lsx"] = hwcap & (1UL << 4);
1934 Features[
"lasx"] = hwcap & (1UL << 5);
1935 Features[
"lvz"] = hwcap & (1UL << 9);
1948 T.setArchName(
"arm");
1949#elif defined(__arm64e__)
1951 T.setArchName(
"arm64e");
1952#elif defined(__aarch64__)
1954 T.setArchName(
"arm64");
1955#elif defined(__x86_64h__)
1957 T.setArchName(
"x86_64h");
1958#elif defined(__x86_64__)
1960 T.setArchName(
"x86_64");
1961#elif defined(__i386__)
1963 T.setArchName(
"i386");
1964#elif defined(__powerpc__)
1966 T.setArchName(
"powerpc");
1968# error "Unimplemented host arch fixup"
1975 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1981 PT = withHostArch(PT);
1993#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
1995 if (CPU ==
"generic")
1998 <<
" Host CPU: " << CPU <<
'\n';
This file defines the StringMap class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
Given that RA is a live value
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
static bool startswith(StringRef Magic, const char(&S)[N])
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Represents either an error or a value T.
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
constexpr bool empty() const
empty - Check if the string is empty.
bool endswith(StringRef Suffix) const
static constexpr size_t npos
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
StringSwitch & StartsWith(StringLiteral S, T Value)
Triple - Helper class for working with autoconf configuration names.
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
std::string normalize() const
Return the normalized form of this triple's string.
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
const std::string & str() const
bool isArch64Bit() const
Test whether the architecture is 64-bit.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
The instances of the Type class are immutable: once they are created, they are never changed.
This class implements an extremely fast bulk output stream that can only output to a stream.
@ CPU_SUBTYPE_POWERPC_970
@ CPU_SUBTYPE_POWERPC_604e
@ CPU_SUBTYPE_POWERPC_603e
@ CPU_SUBTYPE_POWERPC_7400
@ CPU_SUBTYPE_POWERPC_604
@ CPU_SUBTYPE_POWERPC_750
@ CPU_SUBTYPE_POWERPC_601
@ CPU_SUBTYPE_POWERPC_620
@ CPU_SUBTYPE_POWERPC_603ev
@ CPU_SUBTYPE_POWERPC_603
@ CPU_SUBTYPE_POWERPC_7450
@ CPU_SUBTYPE_POWERPC_602
Helper functions to extract CPU details from CPUID on x86.
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
StringRef getHostCPUNameForBPF()
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
void printDefaultTargetAndDetectedCPU(raw_ostream &OS)
This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...
bool getHostCPUFeatures(StringMap< bool, MallocAllocator > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
std::string getDefaultTargetTriple()
getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...
This is an optimization pass for GlobalISel generic memory operations.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.