LLVM  9.0.0svn
Host.cpp
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1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the operating system Host concept.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallSet.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/Config/llvm-config.h"
21 #include "llvm/Support/Debug.h"
25 #include <assert.h>
26 #include <string.h>
27 
28 // Include the platform-specific parts of this class.
29 #ifdef LLVM_ON_UNIX
30 #include "Unix/Host.inc"
31 #endif
32 #ifdef _WIN32
33 #include "Windows/Host.inc"
34 #endif
35 #ifdef _MSC_VER
36 #include <intrin.h>
37 #endif
38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
39 #include <mach/host_info.h>
40 #include <mach/mach.h>
41 #include <mach/mach_host.h>
42 #include <mach/machine.h>
43 #endif
44 
45 #define DEBUG_TYPE "host-detection"
46 
47 //===----------------------------------------------------------------------===//
48 //
49 // Implementations of the CPU detection routines
50 //
51 //===----------------------------------------------------------------------===//
52 
53 using namespace llvm;
54 
55 static std::unique_ptr<llvm::MemoryBuffer>
58  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
59  if (std::error_code EC = Text.getError()) {
60  llvm::errs() << "Can't read "
61  << "/proc/cpuinfo: " << EC.message() << "\n";
62  return nullptr;
63  }
64  return std::move(*Text);
65 }
66 
68  // Access to the Processor Version Register (PVR) on PowerPC is privileged,
69  // and so we must use an operating-system interface to determine the current
70  // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
71  const char *generic = "generic";
72 
73  // The cpu line is second (after the 'processor: 0' line), so if this
74  // buffer is too small then something has changed (or is wrong).
75  StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
76  StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
77 
78  StringRef::const_iterator CIP = CPUInfoStart;
79 
80  StringRef::const_iterator CPUStart = 0;
81  size_t CPULen = 0;
82 
83  // We need to find the first line which starts with cpu, spaces, and a colon.
84  // After the colon, there may be some additional spaces and then the cpu type.
85  while (CIP < CPUInfoEnd && CPUStart == 0) {
86  if (CIP < CPUInfoEnd && *CIP == '\n')
87  ++CIP;
88 
89  if (CIP < CPUInfoEnd && *CIP == 'c') {
90  ++CIP;
91  if (CIP < CPUInfoEnd && *CIP == 'p') {
92  ++CIP;
93  if (CIP < CPUInfoEnd && *CIP == 'u') {
94  ++CIP;
95  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
96  ++CIP;
97 
98  if (CIP < CPUInfoEnd && *CIP == ':') {
99  ++CIP;
100  while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
101  ++CIP;
102 
103  if (CIP < CPUInfoEnd) {
104  CPUStart = CIP;
105  while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
106  *CIP != ',' && *CIP != '\n'))
107  ++CIP;
108  CPULen = CIP - CPUStart;
109  }
110  }
111  }
112  }
113  }
114 
115  if (CPUStart == 0)
116  while (CIP < CPUInfoEnd && *CIP != '\n')
117  ++CIP;
118  }
119 
120  if (CPUStart == 0)
121  return generic;
122 
123  return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
124  .Case("604e", "604e")
125  .Case("604", "604")
126  .Case("7400", "7400")
127  .Case("7410", "7400")
128  .Case("7447", "7400")
129  .Case("7455", "7450")
130  .Case("G4", "g4")
131  .Case("POWER4", "970")
132  .Case("PPC970FX", "970")
133  .Case("PPC970MP", "970")
134  .Case("G5", "g5")
135  .Case("POWER5", "g5")
136  .Case("A2", "a2")
137  .Case("POWER6", "pwr6")
138  .Case("POWER7", "pwr7")
139  .Case("POWER8", "pwr8")
140  .Case("POWER8E", "pwr8")
141  .Case("POWER8NVL", "pwr8")
142  .Case("POWER9", "pwr9")
143  .Default(generic);
144 }
145 
147  // The cpuid register on arm is not accessible from user space. On Linux,
148  // it is exposed through the /proc/cpuinfo file.
149 
150  // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
151  // in all cases.
153  ProcCpuinfoContent.split(Lines, "\n");
154 
155  // Look for the CPU implementer line.
156  StringRef Implementer;
157  StringRef Hardware;
158  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
159  if (Lines[I].startswith("CPU implementer"))
160  Implementer = Lines[I].substr(15).ltrim("\t :");
161  if (Lines[I].startswith("Hardware"))
162  Hardware = Lines[I].substr(8).ltrim("\t :");
163  }
164 
165  if (Implementer == "0x41") { // ARM Ltd.
166  // MSM8992/8994 may give cpu part for the core that the kernel is running on,
167  // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
168  if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
169  return "cortex-a53";
170 
171 
172  // Look for the CPU part line.
173  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
174  if (Lines[I].startswith("CPU part"))
175  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
176  // values correspond to the "Part number" in the CP15/c0 register. The
177  // contents are specified in the various processor manuals.
178  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
179  .Case("0x926", "arm926ej-s")
180  .Case("0xb02", "mpcore")
181  .Case("0xb36", "arm1136j-s")
182  .Case("0xb56", "arm1156t2-s")
183  .Case("0xb76", "arm1176jz-s")
184  .Case("0xc08", "cortex-a8")
185  .Case("0xc09", "cortex-a9")
186  .Case("0xc0f", "cortex-a15")
187  .Case("0xc20", "cortex-m0")
188  .Case("0xc23", "cortex-m3")
189  .Case("0xc24", "cortex-m4")
190  .Case("0xd04", "cortex-a35")
191  .Case("0xd03", "cortex-a53")
192  .Case("0xd07", "cortex-a57")
193  .Case("0xd08", "cortex-a72")
194  .Case("0xd09", "cortex-a73")
195  .Case("0xd0a", "cortex-a75")
196  .Case("0xd0b", "cortex-a76")
197  .Default("generic");
198  }
199 
200  if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
201  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
202  if (Lines[I].startswith("CPU part")) {
203  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
204  .Case("0x516", "thunderx2t99")
205  .Case("0x0516", "thunderx2t99")
206  .Case("0xaf", "thunderx2t99")
207  .Case("0x0af", "thunderx2t99")
208  .Case("0xa1", "thunderxt88")
209  .Case("0x0a1", "thunderxt88")
210  .Default("generic");
211  }
212  }
213  }
214 
215  if (Implementer == "0x48") // HiSilicon Technologies, Inc.
216  // Look for the CPU part line.
217  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
218  if (Lines[I].startswith("CPU part"))
219  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
220  // values correspond to the "Part number" in the CP15/c0 register. The
221  // contents are specified in the various processor manuals.
222  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
223  .Case("0xd01", "tsv110")
224  .Default("generic");
225 
226  if (Implementer == "0x51") // Qualcomm Technologies, Inc.
227  // Look for the CPU part line.
228  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
229  if (Lines[I].startswith("CPU part"))
230  // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
231  // values correspond to the "Part number" in the CP15/c0 register. The
232  // contents are specified in the various processor manuals.
233  return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
234  .Case("0x06f", "krait") // APQ8064
235  .Case("0x201", "kryo")
236  .Case("0x205", "kryo")
237  .Case("0x211", "kryo")
238  .Case("0x800", "cortex-a73")
239  .Case("0x801", "cortex-a73")
240  .Case("0x802", "cortex-a73")
241  .Case("0x803", "cortex-a73")
242  .Case("0x804", "cortex-a73")
243  .Case("0x805", "cortex-a73")
244  .Case("0xc00", "falkor")
245  .Case("0xc01", "saphira")
246  .Default("generic");
247 
248  if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
249  // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
250  // any predictive pattern across variants and parts.
251  unsigned Variant = 0, Part = 0;
252 
253  // Look for the CPU variant line, whose value is a 1 digit hexadecimal
254  // number, corresponding to the Variant bits in the CP15/C0 register.
255  for (auto I : Lines)
256  if (I.consume_front("CPU variant"))
257  I.ltrim("\t :").getAsInteger(0, Variant);
258 
259  // Look for the CPU part line, whose value is a 3 digit hexadecimal
260  // number, corresponding to the PartNum bits in the CP15/C0 register.
261  for (auto I : Lines)
262  if (I.consume_front("CPU part"))
263  I.ltrim("\t :").getAsInteger(0, Part);
264 
265  unsigned Exynos = (Variant << 12) | Part;
266  switch (Exynos) {
267  default:
268  // Default by falling through to Exynos M1.
270 
271  case 0x1001:
272  return "exynos-m1";
273 
274  case 0x4001:
275  return "exynos-m2";
276  }
277  }
278 
279  return "generic";
280 }
281 
283  // STIDP is a privileged operation, so use /proc/cpuinfo instead.
284 
285  // The "processor 0:" line comes after a fair amount of other information,
286  // including a cache breakdown, but this should be plenty.
288  ProcCpuinfoContent.split(Lines, "\n");
289 
290  // Look for the CPU features.
291  SmallVector<StringRef, 32> CPUFeatures;
292  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
293  if (Lines[I].startswith("features")) {
294  size_t Pos = Lines[I].find(":");
295  if (Pos != StringRef::npos) {
296  Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
297  break;
298  }
299  }
300 
301  // We need to check for the presence of vector support independently of
302  // the machine type, since we may only use the vector register set when
303  // supported by the kernel (and hypervisor).
304  bool HaveVectorSupport = false;
305  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
306  if (CPUFeatures[I] == "vx")
307  HaveVectorSupport = true;
308  }
309 
310  // Now check the processor machine type.
311  for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
312  if (Lines[I].startswith("processor ")) {
313  size_t Pos = Lines[I].find("machine = ");
314  if (Pos != StringRef::npos) {
315  Pos += sizeof("machine = ") - 1;
316  unsigned int Id;
317  if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
318  if (Id >= 8561 && HaveVectorSupport)
319  return "arch13";
320  if (Id >= 3906 && HaveVectorSupport)
321  return "z14";
322  if (Id >= 2964 && HaveVectorSupport)
323  return "z13";
324  if (Id >= 2827)
325  return "zEC12";
326  if (Id >= 2817)
327  return "z196";
328  }
329  }
330  break;
331  }
332  }
333 
334  return "generic";
335 }
336 
338 #if !defined(__linux__) || !defined(__x86_64__)
339  return "generic";
340 #else
341  uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
342  /* BPF_MOV64_IMM(BPF_REG_0, 0) */
343  { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
344  /* BPF_MOV64_IMM(BPF_REG_2, 1) */
345  0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
346  /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
347  0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
348  /* BPF_MOV64_IMM(BPF_REG_0, 1) */
349  0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
350  /* BPF_EXIT_INSN() */
351  0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
352 
353  uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
354  /* BPF_MOV64_IMM(BPF_REG_0, 0) */
355  { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
356  /* BPF_MOV64_IMM(BPF_REG_2, 1) */
357  0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
358  /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
359  0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
360  /* BPF_MOV64_IMM(BPF_REG_0, 1) */
361  0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
362  /* BPF_EXIT_INSN() */
363  0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
364 
365  struct bpf_prog_load_attr {
366  uint32_t prog_type;
367  uint32_t insn_cnt;
368  uint64_t insns;
369  uint64_t license;
370  uint32_t log_level;
371  uint32_t log_size;
372  uint64_t log_buf;
373  uint32_t kern_version;
374  uint32_t prog_flags;
375  } attr = {};
376  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
377  attr.insn_cnt = 5;
378  attr.insns = (uint64_t)v3_insns;
379  attr.license = (uint64_t)"DUMMY";
380 
381  int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
382  sizeof(attr));
383  if (fd >= 0) {
384  close(fd);
385  return "v3";
386  }
387 
388  /* Clear the whole attr in case its content changed by syscall. */
389  memset(&attr, 0, sizeof(attr));
390  attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
391  attr.insn_cnt = 5;
392  attr.insns = (uint64_t)v2_insns;
393  attr.license = (uint64_t)"DUMMY";
394  fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
395  if (fd >= 0) {
396  close(fd);
397  return "v2";
398  }
399  return "v1";
400 #endif
401 }
402 
403 #if defined(__i386__) || defined(_M_IX86) || \
404  defined(__x86_64__) || defined(_M_X64)
405 
406 enum VendorSignatures {
407  SIG_INTEL = 0x756e6547 /* Genu */,
408  SIG_AMD = 0x68747541 /* Auth */
409 };
410 
411 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
412 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
413 // support. Consequently, for i386, the presence of CPUID is checked first
414 // via the corresponding eflags bit.
415 // Removal of cpuid.h header motivated by PR30384
416 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
417 // or test-suite, but are used in external projects e.g. libstdcxx
418 static bool isCpuIdSupported() {
419 #if defined(__GNUC__) || defined(__clang__)
420 #if defined(__i386__)
421  int __cpuid_supported;
422  __asm__(" pushfl\n"
423  " popl %%eax\n"
424  " movl %%eax,%%ecx\n"
425  " xorl $0x00200000,%%eax\n"
426  " pushl %%eax\n"
427  " popfl\n"
428  " pushfl\n"
429  " popl %%eax\n"
430  " movl $0,%0\n"
431  " cmpl %%eax,%%ecx\n"
432  " je 1f\n"
433  " movl $1,%0\n"
434  "1:"
435  : "=r"(__cpuid_supported)
436  :
437  : "eax", "ecx");
438  if (!__cpuid_supported)
439  return false;
440 #endif
441  return true;
442 #endif
443  return true;
444 }
445 
446 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
447 /// the specified arguments. If we can't run cpuid on the host, return true.
448 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
449  unsigned *rECX, unsigned *rEDX) {
450 #if defined(__GNUC__) || defined(__clang__)
451 #if defined(__x86_64__)
452  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
453  // FIXME: should we save this for Clang?
454  __asm__("movq\t%%rbx, %%rsi\n\t"
455  "cpuid\n\t"
456  "xchgq\t%%rbx, %%rsi\n\t"
457  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
458  : "a"(value));
459  return false;
460 #elif defined(__i386__)
461  __asm__("movl\t%%ebx, %%esi\n\t"
462  "cpuid\n\t"
463  "xchgl\t%%ebx, %%esi\n\t"
464  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
465  : "a"(value));
466  return false;
467 #else
468  return true;
469 #endif
470 #elif defined(_MSC_VER)
471  // The MSVC intrinsic is portable across x86 and x64.
472  int registers[4];
473  __cpuid(registers, value);
474  *rEAX = registers[0];
475  *rEBX = registers[1];
476  *rECX = registers[2];
477  *rEDX = registers[3];
478  return false;
479 #else
480  return true;
481 #endif
482 }
483 
484 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
485 /// the 4 values in the specified arguments. If we can't run cpuid on the host,
486 /// return true.
487 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
488  unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
489  unsigned *rEDX) {
490 #if defined(__GNUC__) || defined(__clang__)
491 #if defined(__x86_64__)
492  // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
493  // FIXME: should we save this for Clang?
494  __asm__("movq\t%%rbx, %%rsi\n\t"
495  "cpuid\n\t"
496  "xchgq\t%%rbx, %%rsi\n\t"
497  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
498  : "a"(value), "c"(subleaf));
499  return false;
500 #elif defined(__i386__)
501  __asm__("movl\t%%ebx, %%esi\n\t"
502  "cpuid\n\t"
503  "xchgl\t%%ebx, %%esi\n\t"
504  : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
505  : "a"(value), "c"(subleaf));
506  return false;
507 #else
508  return true;
509 #endif
510 #elif defined(_MSC_VER)
511  int registers[4];
512  __cpuidex(registers, value, subleaf);
513  *rEAX = registers[0];
514  *rEBX = registers[1];
515  *rECX = registers[2];
516  *rEDX = registers[3];
517  return false;
518 #else
519  return true;
520 #endif
521 }
522 
523 // Read control register 0 (XCR0). Used to detect features such as AVX.
524 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
525 #if defined(__GNUC__) || defined(__clang__)
526  // Check xgetbv; this uses a .byte sequence instead of the instruction
527  // directly because older assemblers do not include support for xgetbv and
528  // there is no easy way to conditionally compile based on the assembler used.
529  __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
530  return false;
531 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
532  unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
533  *rEAX = Result;
534  *rEDX = Result >> 32;
535  return false;
536 #else
537  return true;
538 #endif
539 }
540 
541 static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
542  unsigned *Model) {
543  *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
544  *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
545  if (*Family == 6 || *Family == 0xf) {
546  if (*Family == 0xf)
547  // Examine extended family ID if family ID is F.
548  *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
549  // Examine extended model ID if family ID is 6 or F.
550  *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
551  }
552 }
553 
554 static void
555 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
556  unsigned Brand_id, unsigned Features,
557  unsigned Features2, unsigned Features3,
558  unsigned *Type, unsigned *Subtype) {
559  if (Brand_id != 0)
560  return;
561  switch (Family) {
562  case 3:
563  *Type = X86::INTEL_i386;
564  break;
565  case 4:
566  *Type = X86::INTEL_i486;
567  break;
568  case 5:
569  if (Features & (1 << X86::FEATURE_MMX)) {
570  *Type = X86::INTEL_PENTIUM_MMX;
571  break;
572  }
573  *Type = X86::INTEL_PENTIUM;
574  break;
575  case 6:
576  switch (Model) {
577  case 0x01: // Pentium Pro processor
578  *Type = X86::INTEL_PENTIUM_PRO;
579  break;
580  case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
581  // model 03
582  case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
583  // model 05, and Intel Celeron processor, model 05
584  case 0x06: // Celeron processor, model 06
585  *Type = X86::INTEL_PENTIUM_II;
586  break;
587  case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
588  // processor, model 07
589  case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
590  // model 08, and Celeron processor, model 08
591  case 0x0a: // Pentium III Xeon processor, model 0Ah
592  case 0x0b: // Pentium III processor, model 0Bh
593  *Type = X86::INTEL_PENTIUM_III;
594  break;
595  case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
596  case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
597  // 0Dh. All processors are manufactured using the 90 nm process.
598  case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
599  // Integrated Processor with Intel QuickAssist Technology
600  *Type = X86::INTEL_PENTIUM_M;
601  break;
602  case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
603  // 0Eh. All processors are manufactured using the 65 nm process.
604  *Type = X86::INTEL_CORE_DUO;
605  break; // yonah
606  case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
607  // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
608  // mobile processor, Intel Core 2 Extreme processor, Intel
609  // Pentium Dual-Core processor, Intel Xeon processor, model
610  // 0Fh. All processors are manufactured using the 65 nm process.
611  case 0x16: // Intel Celeron processor model 16h. All processors are
612  // manufactured using the 65 nm process
613  *Type = X86::INTEL_CORE2; // "core2"
614  *Subtype = X86::INTEL_CORE2_65;
615  break;
616  case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
617  // 17h. All processors are manufactured using the 45 nm process.
618  //
619  // 45nm: Penryn , Wolfdale, Yorkfield (XE)
620  case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
621  // the 45 nm process.
622  *Type = X86::INTEL_CORE2; // "penryn"
623  *Subtype = X86::INTEL_CORE2_45;
624  break;
625  case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
626  // processors are manufactured using the 45 nm process.
627  case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
628  // As found in a Summer 2010 model iMac.
629  case 0x1f:
630  case 0x2e: // Nehalem EX
631  *Type = X86::INTEL_COREI7; // "nehalem"
632  *Subtype = X86::INTEL_COREI7_NEHALEM;
633  break;
634  case 0x25: // Intel Core i7, laptop version.
635  case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
636  // processors are manufactured using the 32 nm process.
637  case 0x2f: // Westmere EX
638  *Type = X86::INTEL_COREI7; // "westmere"
639  *Subtype = X86::INTEL_COREI7_WESTMERE;
640  break;
641  case 0x2a: // Intel Core i7 processor. All processors are manufactured
642  // using the 32 nm process.
643  case 0x2d:
644  *Type = X86::INTEL_COREI7; //"sandybridge"
645  *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
646  break;
647  case 0x3a:
648  case 0x3e: // Ivy Bridge EP
649  *Type = X86::INTEL_COREI7; // "ivybridge"
650  *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
651  break;
652 
653  // Haswell:
654  case 0x3c:
655  case 0x3f:
656  case 0x45:
657  case 0x46:
658  *Type = X86::INTEL_COREI7; // "haswell"
659  *Subtype = X86::INTEL_COREI7_HASWELL;
660  break;
661 
662  // Broadwell:
663  case 0x3d:
664  case 0x47:
665  case 0x4f:
666  case 0x56:
667  *Type = X86::INTEL_COREI7; // "broadwell"
668  *Subtype = X86::INTEL_COREI7_BROADWELL;
669  break;
670 
671  // Skylake:
672  case 0x4e: // Skylake mobile
673  case 0x5e: // Skylake desktop
674  case 0x8e: // Kaby Lake mobile
675  case 0x9e: // Kaby Lake desktop
676  *Type = X86::INTEL_COREI7; // "skylake"
677  *Subtype = X86::INTEL_COREI7_SKYLAKE;
678  break;
679 
680  // Skylake Xeon:
681  case 0x55:
682  *Type = X86::INTEL_COREI7;
683  if (Features3 & (1 << (X86::FEATURE_AVX512BF16 - 64)))
684  *Subtype = X86::INTEL_COREI7_COOPERLAKE; // "cooperlake"
685  else if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32)))
686  *Subtype = X86::INTEL_COREI7_CASCADELAKE; // "cascadelake"
687  else
688  *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
689  break;
690 
691  // Cannonlake:
692  case 0x66:
693  *Type = X86::INTEL_COREI7;
694  *Subtype = X86::INTEL_COREI7_CANNONLAKE; // "cannonlake"
695  break;
696 
697  // Icelake:
698  case 0x7d:
699  case 0x7e:
700  *Type = X86::INTEL_COREI7;
701  *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT; // "icelake-client"
702  break;
703 
704  // Icelake Xeon:
705  case 0x6a:
706  case 0x6c:
707  *Type = X86::INTEL_COREI7;
708  *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER; // "icelake-server"
709  break;
710 
711  case 0x1c: // Most 45 nm Intel Atom processors
712  case 0x26: // 45 nm Atom Lincroft
713  case 0x27: // 32 nm Atom Medfield
714  case 0x35: // 32 nm Atom Midview
715  case 0x36: // 32 nm Atom Midview
716  *Type = X86::INTEL_BONNELL;
717  break; // "bonnell"
718 
719  // Atom Silvermont codes from the Intel software optimization guide.
720  case 0x37:
721  case 0x4a:
722  case 0x4d:
723  case 0x5a:
724  case 0x5d:
725  case 0x4c: // really airmont
726  *Type = X86::INTEL_SILVERMONT;
727  break; // "silvermont"
728  // Goldmont:
729  case 0x5c: // Apollo Lake
730  case 0x5f: // Denverton
731  *Type = X86::INTEL_GOLDMONT;
732  break; // "goldmont"
733  case 0x7a:
734  *Type = X86::INTEL_GOLDMONT_PLUS;
735  break;
736  case 0x86:
737  *Type = X86::INTEL_TREMONT;
738  break;
739 
740  case 0x57:
741  *Type = X86::INTEL_KNL; // knl
742  break;
743 
744  case 0x85:
745  *Type = X86::INTEL_KNM; // knm
746  break;
747 
748  default: // Unknown family 6 CPU, try to guess.
749  if (Features & (1 << X86::FEATURE_AVX512VBMI2)) {
750  *Type = X86::INTEL_COREI7;
751  *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
752  break;
753  }
754 
755  if (Features & (1 << X86::FEATURE_AVX512VBMI)) {
756  *Type = X86::INTEL_COREI7;
757  *Subtype = X86::INTEL_COREI7_CANNONLAKE;
758  break;
759  }
760 
761  if (Features3 & (1 << (X86::FEATURE_AVX512BF16 - 64))) {
762  *Type = X86::INTEL_COREI7;
763  *Subtype = X86::INTEL_COREI7_COOPERLAKE;
764  break;
765  }
766 
767  if (Features2 & (1 << (X86::FEATURE_AVX512VNNI - 32))) {
768  *Type = X86::INTEL_COREI7;
769  *Subtype = X86::INTEL_COREI7_CASCADELAKE;
770  break;
771  }
772 
773  if (Features & (1 << X86::FEATURE_AVX512VL)) {
774  *Type = X86::INTEL_COREI7;
775  *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
776  break;
777  }
778 
779  if (Features & (1 << X86::FEATURE_AVX512ER)) {
780  *Type = X86::INTEL_KNL; // knl
781  break;
782  }
783 
784  if (Features3 & (1 << (X86::FEATURE_CLFLUSHOPT - 64))) {
785  if (Features3 & (1 << (X86::FEATURE_SHA - 64))) {
786  *Type = X86::INTEL_GOLDMONT;
787  } else {
788  *Type = X86::INTEL_COREI7;
789  *Subtype = X86::INTEL_COREI7_SKYLAKE;
790  }
791  break;
792  }
793  if (Features3 & (1 << (X86::FEATURE_ADX - 64))) {
794  *Type = X86::INTEL_COREI7;
795  *Subtype = X86::INTEL_COREI7_BROADWELL;
796  break;
797  }
798  if (Features & (1 << X86::FEATURE_AVX2)) {
799  *Type = X86::INTEL_COREI7;
800  *Subtype = X86::INTEL_COREI7_HASWELL;
801  break;
802  }
803  if (Features & (1 << X86::FEATURE_AVX)) {
804  *Type = X86::INTEL_COREI7;
805  *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
806  break;
807  }
808  if (Features & (1 << X86::FEATURE_SSE4_2)) {
809  if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) {
810  *Type = X86::INTEL_SILVERMONT;
811  } else {
812  *Type = X86::INTEL_COREI7;
813  *Subtype = X86::INTEL_COREI7_NEHALEM;
814  }
815  break;
816  }
817  if (Features & (1 << X86::FEATURE_SSE4_1)) {
818  *Type = X86::INTEL_CORE2; // "penryn"
819  *Subtype = X86::INTEL_CORE2_45;
820  break;
821  }
822  if (Features & (1 << X86::FEATURE_SSSE3)) {
823  if (Features3 & (1 << (X86::FEATURE_MOVBE - 64))) {
824  *Type = X86::INTEL_BONNELL; // "bonnell"
825  } else {
826  *Type = X86::INTEL_CORE2; // "core2"
827  *Subtype = X86::INTEL_CORE2_65;
828  }
829  break;
830  }
831  if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) {
832  *Type = X86::INTEL_CORE2; // "core2"
833  *Subtype = X86::INTEL_CORE2_65;
834  break;
835  }
836  if (Features & (1 << X86::FEATURE_SSE3)) {
837  *Type = X86::INTEL_CORE_DUO;
838  break;
839  }
840  if (Features & (1 << X86::FEATURE_SSE2)) {
841  *Type = X86::INTEL_PENTIUM_M;
842  break;
843  }
844  if (Features & (1 << X86::FEATURE_SSE)) {
845  *Type = X86::INTEL_PENTIUM_III;
846  break;
847  }
848  if (Features & (1 << X86::FEATURE_MMX)) {
849  *Type = X86::INTEL_PENTIUM_II;
850  break;
851  }
852  *Type = X86::INTEL_PENTIUM_PRO;
853  break;
854  }
855  break;
856  case 15: {
857  if (Features3 & (1 << (X86::FEATURE_EM64T - 64))) {
858  *Type = X86::INTEL_NOCONA;
859  break;
860  }
861  if (Features & (1 << X86::FEATURE_SSE3)) {
862  *Type = X86::INTEL_PRESCOTT;
863  break;
864  }
865  *Type = X86::INTEL_PENTIUM_IV;
866  break;
867  }
868  default:
869  break; /*"generic"*/
870  }
871 }
872 
873 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
874  unsigned Features, unsigned *Type,
875  unsigned *Subtype) {
876  // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
877  // appears to be no way to generate the wide variety of AMD-specific targets
878  // from the information returned from CPUID.
879  switch (Family) {
880  case 4:
881  *Type = X86::AMD_i486;
882  break;
883  case 5:
884  *Type = X86::AMDPENTIUM;
885  switch (Model) {
886  case 6:
887  case 7:
888  *Subtype = X86::AMDPENTIUM_K6;
889  break; // "k6"
890  case 8:
891  *Subtype = X86::AMDPENTIUM_K62;
892  break; // "k6-2"
893  case 9:
894  case 13:
895  *Subtype = X86::AMDPENTIUM_K63;
896  break; // "k6-3"
897  case 10:
898  *Subtype = X86::AMDPENTIUM_GEODE;
899  break; // "geode"
900  }
901  break;
902  case 6:
903  if (Features & (1 << X86::FEATURE_SSE)) {
904  *Type = X86::AMD_ATHLON_XP;
905  break; // "athlon-xp"
906  }
907  *Type = X86::AMD_ATHLON;
908  break; // "athlon"
909  case 15:
910  if (Features & (1 << X86::FEATURE_SSE3)) {
911  *Type = X86::AMD_K8SSE3;
912  break; // "k8-sse3"
913  }
914  *Type = X86::AMD_K8;
915  break; // "k8"
916  case 16:
917  *Type = X86::AMDFAM10H; // "amdfam10"
918  switch (Model) {
919  case 2:
920  *Subtype = X86::AMDFAM10H_BARCELONA;
921  break;
922  case 4:
923  *Subtype = X86::AMDFAM10H_SHANGHAI;
924  break;
925  case 8:
926  *Subtype = X86::AMDFAM10H_ISTANBUL;
927  break;
928  }
929  break;
930  case 20:
931  *Type = X86::AMD_BTVER1;
932  break; // "btver1";
933  case 21:
934  *Type = X86::AMDFAM15H;
935  if (Model >= 0x60 && Model <= 0x7f) {
936  *Subtype = X86::AMDFAM15H_BDVER4;
937  break; // "bdver4"; 60h-7Fh: Excavator
938  }
939  if (Model >= 0x30 && Model <= 0x3f) {
940  *Subtype = X86::AMDFAM15H_BDVER3;
941  break; // "bdver3"; 30h-3Fh: Steamroller
942  }
943  if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
944  *Subtype = X86::AMDFAM15H_BDVER2;
945  break; // "bdver2"; 02h, 10h-1Fh: Piledriver
946  }
947  if (Model <= 0x0f) {
948  *Subtype = X86::AMDFAM15H_BDVER1;
949  break; // "bdver1"; 00h-0Fh: Bulldozer
950  }
951  break;
952  case 22:
953  *Type = X86::AMD_BTVER2;
954  break; // "btver2"
955  case 23:
956  *Type = X86::AMDFAM17H;
957  if (Model >= 0x30 && Model <= 0x3f) {
958  *Subtype = X86::AMDFAM17H_ZNVER2;
959  break; // "znver2"; 30h-3fh: Zen2
960  }
961  if (Model <= 0x0f) {
962  *Subtype = X86::AMDFAM17H_ZNVER1;
963  break; // "znver1"; 00h-0Fh: Zen1
964  }
965  break;
966  default:
967  break; // "generic"
968  }
969 }
970 
971 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
972  unsigned *FeaturesOut, unsigned *Features2Out,
973  unsigned *Features3Out) {
974  unsigned Features = 0;
975  unsigned Features2 = 0;
976  unsigned Features3 = 0;
977  unsigned EAX, EBX;
978 
979  auto setFeature = [&](unsigned F) {
980  if (F < 32)
981  Features |= 1U << (F & 0x1f);
982  else if (F < 64)
983  Features2 |= 1U << ((F - 32) & 0x1f);
984  else if (F < 96)
985  Features3 |= 1U << ((F - 64) & 0x1f);
986  else
987  llvm_unreachable("Unexpected FeatureBit");
988  };
989 
990  if ((EDX >> 15) & 1)
991  setFeature(X86::FEATURE_CMOV);
992  if ((EDX >> 23) & 1)
993  setFeature(X86::FEATURE_MMX);
994  if ((EDX >> 25) & 1)
995  setFeature(X86::FEATURE_SSE);
996  if ((EDX >> 26) & 1)
997  setFeature(X86::FEATURE_SSE2);
998 
999  if ((ECX >> 0) & 1)
1000  setFeature(X86::FEATURE_SSE3);
1001  if ((ECX >> 1) & 1)
1002  setFeature(X86::FEATURE_PCLMUL);
1003  if ((ECX >> 9) & 1)
1004  setFeature(X86::FEATURE_SSSE3);
1005  if ((ECX >> 12) & 1)
1006  setFeature(X86::FEATURE_FMA);
1007  if ((ECX >> 19) & 1)
1008  setFeature(X86::FEATURE_SSE4_1);
1009  if ((ECX >> 20) & 1)
1010  setFeature(X86::FEATURE_SSE4_2);
1011  if ((ECX >> 23) & 1)
1012  setFeature(X86::FEATURE_POPCNT);
1013  if ((ECX >> 25) & 1)
1014  setFeature(X86::FEATURE_AES);
1015 
1016  if ((ECX >> 22) & 1)
1017  setFeature(X86::FEATURE_MOVBE);
1018 
1019  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1020  // indicates that the AVX registers will be saved and restored on context
1021  // switch, then we have full AVX support.
1022  const unsigned AVXBits = (1 << 27) | (1 << 28);
1023  bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1024  ((EAX & 0x6) == 0x6);
1025  bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
1026 
1027  if (HasAVX)
1028  setFeature(X86::FEATURE_AVX);
1029 
1030  bool HasLeaf7 =
1031  MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1032 
1033  if (HasLeaf7 && ((EBX >> 3) & 1))
1034  setFeature(X86::FEATURE_BMI);
1035  if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1036  setFeature(X86::FEATURE_AVX2);
1037  if (HasLeaf7 && ((EBX >> 9) & 1))
1038  setFeature(X86::FEATURE_BMI2);
1039  if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
1040  setFeature(X86::FEATURE_AVX512F);
1041  if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1042  setFeature(X86::FEATURE_AVX512DQ);
1043  if (HasLeaf7 && ((EBX >> 19) & 1))
1044  setFeature(X86::FEATURE_ADX);
1045  if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1046  setFeature(X86::FEATURE_AVX512IFMA);
1047  if (HasLeaf7 && ((EBX >> 23) & 1))
1048  setFeature(X86::FEATURE_CLFLUSHOPT);
1049  if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1050  setFeature(X86::FEATURE_AVX512PF);
1051  if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1052  setFeature(X86::FEATURE_AVX512ER);
1053  if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1054  setFeature(X86::FEATURE_AVX512CD);
1055  if (HasLeaf7 && ((EBX >> 29) & 1))
1056  setFeature(X86::FEATURE_SHA);
1057  if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1058  setFeature(X86::FEATURE_AVX512BW);
1059  if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1060  setFeature(X86::FEATURE_AVX512VL);
1061 
1062  if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1063  setFeature(X86::FEATURE_AVX512VBMI);
1064  if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1065  setFeature(X86::FEATURE_AVX512VBMI2);
1066  if (HasLeaf7 && ((ECX >> 8) & 1))
1067  setFeature(X86::FEATURE_GFNI);
1068  if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1069  setFeature(X86::FEATURE_VPCLMULQDQ);
1070  if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1071  setFeature(X86::FEATURE_AVX512VNNI);
1072  if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1073  setFeature(X86::FEATURE_AVX512BITALG);
1074  if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1075  setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1076 
1077  if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1078  setFeature(X86::FEATURE_AVX5124VNNIW);
1079  if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1080  setFeature(X86::FEATURE_AVX5124FMAPS);
1081 
1082  unsigned MaxExtLevel;
1083  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1084 
1085  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1086  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1087  if (HasExtLeaf1 && ((ECX >> 6) & 1))
1088  setFeature(X86::FEATURE_SSE4_A);
1089  if (HasExtLeaf1 && ((ECX >> 11) & 1))
1090  setFeature(X86::FEATURE_XOP);
1091  if (HasExtLeaf1 && ((ECX >> 16) & 1))
1092  setFeature(X86::FEATURE_FMA4);
1093 
1094  if (HasExtLeaf1 && ((EDX >> 29) & 1))
1095  setFeature(X86::FEATURE_EM64T);
1096 
1097  *FeaturesOut = Features;
1098  *Features2Out = Features2;
1099  *Features3Out = Features3;
1100 }
1101 
1103  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1104  unsigned MaxLeaf, Vendor;
1105 
1106 #if defined(__GNUC__) || defined(__clang__)
1107  //FIXME: include cpuid.h from clang or copy __get_cpuid_max here
1108  // and simplify it to not invoke __cpuid (like cpu_model.c in
1109  // compiler-rt/lib/builtins/cpu_model.c?
1110  // Opting for the second option.
1111  if(!isCpuIdSupported())
1112  return "generic";
1113 #endif
1114  if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1)
1115  return "generic";
1116  getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1117 
1118  unsigned Brand_id = EBX & 0xff;
1119  unsigned Family = 0, Model = 0;
1120  unsigned Features = 0, Features2 = 0, Features3 = 0;
1121  detectX86FamilyModel(EAX, &Family, &Model);
1122  getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2, &Features3);
1123 
1124  unsigned Type = 0;
1125  unsigned Subtype = 0;
1126 
1127  if (Vendor == SIG_INTEL) {
1128  getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features,
1129  Features2, Features3, &Type, &Subtype);
1130  } else if (Vendor == SIG_AMD) {
1131  getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
1132  }
1133 
1134  // Check subtypes first since those are more specific.
1135 #define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \
1136  if (Subtype == X86::ENUM) \
1137  return ARCHNAME;
1138 #include "llvm/Support/X86TargetParser.def"
1139 
1140  // Now check types.
1141 #define X86_CPU_TYPE(ARCHNAME, ENUM) \
1142  if (Type == X86::ENUM) \
1143  return ARCHNAME;
1144 #include "llvm/Support/X86TargetParser.def"
1145 
1146  return "generic";
1147 }
1148 
1149 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
1151  host_basic_info_data_t hostInfo;
1152  mach_msg_type_number_t infoCount;
1153 
1154  infoCount = HOST_BASIC_INFO_COUNT;
1155  mach_port_t hostPort = mach_host_self();
1156  host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1157  &infoCount);
1158  mach_port_deallocate(mach_task_self(), hostPort);
1159 
1160  if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1161  return "generic";
1162 
1163  switch (hostInfo.cpu_subtype) {
1165  return "601";
1167  return "602";
1169  return "603";
1171  return "603e";
1173  return "603ev";
1175  return "604";
1177  return "604e";
1179  return "620";
1181  return "750";
1183  return "7400";
1185  return "7450";
1187  return "970";
1188  default:;
1189  }
1190 
1191  return "generic";
1192 }
1193 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
1195  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1196  StringRef Content = P ? P->getBuffer() : "";
1197  return detail::getHostCPUNameForPowerPC(Content);
1198 }
1199 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1201  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1202  StringRef Content = P ? P->getBuffer() : "";
1203  return detail::getHostCPUNameForARM(Content);
1204 }
1205 #elif defined(__linux__) && defined(__s390x__)
1207  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1208  StringRef Content = P ? P->getBuffer() : "";
1209  return detail::getHostCPUNameForS390x(Content);
1210 }
1211 #else
1212 StringRef sys::getHostCPUName() { return "generic"; }
1213 #endif
1214 
1215 #if defined(__linux__) && defined(__x86_64__)
1216 // On Linux, the number of physical cores can be computed from /proc/cpuinfo,
1217 // using the number of unique physical/core id pairs. The following
1218 // implementation reads the /proc/cpuinfo format on an x86_64 system.
1219 static int computeHostNumPhysicalCores() {
1220  // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be
1221  // mmapped because it appears to have 0 size.
1223  llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo");
1224  if (std::error_code EC = Text.getError()) {
1225  llvm::errs() << "Can't read "
1226  << "/proc/cpuinfo: " << EC.message() << "\n";
1227  return -1;
1228  }
1230  (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1,
1231  /*KeepEmpty=*/false);
1232  int CurPhysicalId = -1;
1233  int CurCoreId = -1;
1234  SmallSet<std::pair<int, int>, 32> UniqueItems;
1235  for (auto &Line : strs) {
1236  Line = Line.trim();
1237  if (!Line.startswith("physical id") && !Line.startswith("core id"))
1238  continue;
1239  std::pair<StringRef, StringRef> Data = Line.split(':');
1240  auto Name = Data.first.trim();
1241  auto Val = Data.second.trim();
1242  if (Name == "physical id") {
1243  assert(CurPhysicalId == -1 &&
1244  "Expected a core id before seeing another physical id");
1245  Val.getAsInteger(10, CurPhysicalId);
1246  }
1247  if (Name == "core id") {
1248  assert(CurCoreId == -1 &&
1249  "Expected a physical id before seeing another core id");
1250  Val.getAsInteger(10, CurCoreId);
1251  }
1252  if (CurPhysicalId != -1 && CurCoreId != -1) {
1253  UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId));
1254  CurPhysicalId = -1;
1255  CurCoreId = -1;
1256  }
1257  }
1258  return UniqueItems.size();
1259 }
1260 #elif defined(__APPLE__) && defined(__x86_64__)
1261 #include <sys/param.h>
1262 #include <sys/sysctl.h>
1263 
1264 // Gets the number of *physical cores* on the machine.
1265 static int computeHostNumPhysicalCores() {
1266  uint32_t count;
1267  size_t len = sizeof(count);
1268  sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0);
1269  if (count < 1) {
1270  int nm[2];
1271  nm[0] = CTL_HW;
1272  nm[1] = HW_AVAILCPU;
1273  sysctl(nm, 2, &count, &len, NULL, 0);
1274  if (count < 1)
1275  return -1;
1276  }
1277  return count;
1278 }
1279 #else
1280 // On other systems, return -1 to indicate unknown.
1281 static int computeHostNumPhysicalCores() { return -1; }
1282 #endif
1283 
1285  static int NumCores = computeHostNumPhysicalCores();
1286  return NumCores;
1287 }
1288 
1289 #if defined(__i386__) || defined(_M_IX86) || \
1290  defined(__x86_64__) || defined(_M_X64)
1291 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1292  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1293  unsigned MaxLevel;
1294  union {
1295  unsigned u[3];
1296  char c[12];
1297  } text;
1298 
1299  if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
1300  MaxLevel < 1)
1301  return false;
1302 
1303  getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1304 
1305  Features["cx8"] = (EDX >> 8) & 1;
1306  Features["cmov"] = (EDX >> 15) & 1;
1307  Features["mmx"] = (EDX >> 23) & 1;
1308  Features["fxsr"] = (EDX >> 24) & 1;
1309  Features["sse"] = (EDX >> 25) & 1;
1310  Features["sse2"] = (EDX >> 26) & 1;
1311 
1312  Features["sse3"] = (ECX >> 0) & 1;
1313  Features["pclmul"] = (ECX >> 1) & 1;
1314  Features["ssse3"] = (ECX >> 9) & 1;
1315  Features["cx16"] = (ECX >> 13) & 1;
1316  Features["sse4.1"] = (ECX >> 19) & 1;
1317  Features["sse4.2"] = (ECX >> 20) & 1;
1318  Features["movbe"] = (ECX >> 22) & 1;
1319  Features["popcnt"] = (ECX >> 23) & 1;
1320  Features["aes"] = (ECX >> 25) & 1;
1321  Features["rdrnd"] = (ECX >> 30) & 1;
1322 
1323  // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1324  // indicates that the AVX registers will be saved and restored on context
1325  // switch, then we have full AVX support.
1326  bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
1327  !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
1328  // AVX512 requires additional context to be saved by the OS.
1329  bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1330 
1331  Features["avx"] = HasAVXSave;
1332  Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
1333  // Only enable XSAVE if OS has enabled support for saving YMM state.
1334  Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1335  Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
1336 
1337  unsigned MaxExtLevel;
1338  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1339 
1340  bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1341  !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1342  Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);
1343  Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1344  Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1345  Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1346  Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1347  Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1348  Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1349  Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1350  Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1351 
1352  Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);
1353 
1354  // Miscellaneous memory related features, detected by
1355  // using the 0x80000008 leaf of the CPUID instruction
1356  bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1357  !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1358  Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1359  Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1360 
1361  bool HasLeaf7 =
1362  MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1363 
1364  Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1365  Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1366  Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1367  // AVX2 is only supported if we have the OS save support from AVX.
1368  Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
1369  Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1370  Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
1371  Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1372  Features["mpx"] = HasLeaf7 && ((EBX >> 14) & 1);
1373  // AVX512 is only supported if the OS supports the context save for it.
1374  Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1375  Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1376  Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1377  Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1378  Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1379  Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1380  Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1381  Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1382  Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1383  Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1384  Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1385  Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1386  Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1387 
1388  Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1);
1389  Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1390  Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1391  Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);
1392  Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
1393  Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
1394  Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
1395  Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
1396  Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1397  Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1398  Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1399  Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1400  Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
1401  Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
1402  Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
1403  Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
1404  Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
1405 
1406  // There are two CPUID leafs which information associated with the pconfig
1407  // instruction:
1408  // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1409  // bit of EDX), while the EAX=0x1b leaf returns information on the
1410  // availability of specific pconfig leafs.
1411  // The target feature here only refers to the the first of these two.
1412  // Users might need to check for the availability of specific pconfig
1413  // leaves using cpuid, since that information is ignored while
1414  // detecting features using the "-march=native" flag.
1415  // For more info, see X86 ISA docs.
1416  Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1417  bool HasLeaf7Subleaf1 =
1418  MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1419  Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
1420 
1421  bool HasLeafD = MaxLevel >= 0xd &&
1422  !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1423 
1424  // Only enable XSAVE if OS has enabled support for saving YMM state.
1425  Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1426  Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1427  Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1428 
1429  bool HasLeaf14 = MaxLevel >= 0x14 &&
1430  !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1431 
1432  Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1433 
1434  return true;
1435 }
1436 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1437 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
1438  std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1439  if (!P)
1440  return false;
1441 
1443  P->getBuffer().split(Lines, "\n");
1444 
1445  SmallVector<StringRef, 32> CPUFeatures;
1446 
1447  // Look for the CPU features.
1448  for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1449  if (Lines[I].startswith("Features")) {
1450  Lines[I].split(CPUFeatures, ' ');
1451  break;
1452  }
1453 
1454 #if defined(__aarch64__)
1455  // Keep track of which crypto features we have seen
1456  enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1457  uint32_t crypto = 0;
1458 #endif
1459 
1460  for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1461  StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1462 #if defined(__aarch64__)
1463  .Case("asimd", "neon")
1464  .Case("fp", "fp-armv8")
1465  .Case("crc32", "crc")
1466 #else
1467  .Case("half", "fp16")
1468  .Case("neon", "neon")
1469  .Case("vfpv3", "vfp3")
1470  .Case("vfpv3d16", "d16")
1471  .Case("vfpv4", "vfp4")
1472  .Case("idiva", "hwdiv-arm")
1473  .Case("idivt", "hwdiv")
1474 #endif
1475  .Default("");
1476 
1477 #if defined(__aarch64__)
1478  // We need to check crypto separately since we need all of the crypto
1479  // extensions to enable the subtarget feature
1480  if (CPUFeatures[I] == "aes")
1481  crypto |= CAP_AES;
1482  else if (CPUFeatures[I] == "pmull")
1483  crypto |= CAP_PMULL;
1484  else if (CPUFeatures[I] == "sha1")
1485  crypto |= CAP_SHA1;
1486  else if (CPUFeatures[I] == "sha2")
1487  crypto |= CAP_SHA2;
1488 #endif
1489 
1490  if (LLVMFeatureStr != "")
1491  Features[LLVMFeatureStr] = true;
1492  }
1493 
1494 #if defined(__aarch64__)
1495  // If we have all crypto bits we can add the feature
1496  if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1497  Features["crypto"] = true;
1498 #endif
1499 
1500  return true;
1501 }
1502 #else
1503 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1504 #endif
1505 
1506 std::string sys::getProcessTriple() {
1507  std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1508  Triple PT(Triple::normalize(TargetTripleString));
1509 
1510  if (sizeof(void *) == 8 && PT.isArch32Bit())
1511  PT = PT.get64BitArchVariant();
1512  if (sizeof(void *) == 4 && PT.isArch64Bit())
1513  PT = PT.get32BitArchVariant();
1514 
1515  return PT.str();
1516 }
Represents either an error or a value T.
Definition: ErrorOr.h:56
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
Definition: Host.cpp:56
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:267
This class represents lattice values for constants.
Definition: AllocatorList.h:23
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
Definition: Host.cpp:67
F(f)
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
Definition: Host.cpp:282
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
int getHostNumPhysicalCores()
Get the number of physical cores (as opposed to logical cores returned from thread::hardware_concurre...
Definition: Host.cpp:1284
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:29
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1296
const std::string & str() const
Definition: Triple.h:365
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(adl_begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1258
#define P(N)
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
Definition: Triple.cpp:1304
StringRef getHostCPUNameForBPF()
Definition: Host.cpp:337
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
std::error_code getError() const
Definition: ErrorOr.h:159
size_type size() const
Definition: SmallSet.h:159
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:159
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
size_t size() const
Definition: SmallVector.h:52
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
Definition: Host.cpp:1506
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
std::string normalize() const
Return the normalized form of this triple&#39;s string.
Definition: Triple.h:289
iterator begin() const
Definition: StringRef.h:101
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
Definition: Host.cpp:1212
static const size_t npos
Definition: StringRef.h:50
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1292
#define I(x, y, z)
Definition: MD5.cpp:58
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
Definition: Host.cpp:146
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
Definition: Triple.cpp:1368
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool getHostCPUFeatures(StringMap< bool > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
Definition: Host.cpp:1503
iterator end() const
Definition: StringRef.h:103
static int computeHostNumPhysicalCores()
Definition: Host.cpp:1281