LLVM 20.0.0git
Host.cpp
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1//===-- Host.cpp - Implement OS Host Detection ------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the operating system Host detection.
10//
11//===----------------------------------------------------------------------===//
12
15#include "llvm/ADT/StringMap.h"
16#include "llvm/ADT/StringRef.h"
18#include "llvm/Config/llvm-config.h"
23#include <string.h>
24
25// Include the platform-specific parts of this class.
26#ifdef LLVM_ON_UNIX
27#include "Unix/Host.inc"
28#include <sched.h>
29#endif
30#ifdef _WIN32
31#include "Windows/Host.inc"
32#endif
33#ifdef _MSC_VER
34#include <intrin.h>
35#endif
36#ifdef __MVS__
37#include "llvm/Support/BCD.h"
38#endif
39#if defined(__APPLE__)
40#include <mach/host_info.h>
41#include <mach/mach.h>
42#include <mach/mach_host.h>
43#include <mach/machine.h>
44#include <sys/param.h>
45#include <sys/sysctl.h>
46#endif
47#ifdef _AIX
48#include <sys/systemcfg.h>
49#endif
50#if defined(__sun__) && defined(__svr4__)
51#include <kstat.h>
52#endif
53#if defined(__GNUC__) || defined(__clang__)
54#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
55#include <cpuid.h>
56#endif
57#endif
58
59#define DEBUG_TYPE "host-detection"
60
61//===----------------------------------------------------------------------===//
62//
63// Implementations of the CPU detection routines
64//
65//===----------------------------------------------------------------------===//
66
67using namespace llvm;
68
69static std::unique_ptr<llvm::MemoryBuffer>
73 if (std::error_code EC = Text.getError()) {
74 llvm::errs() << "Can't read "
75 << "/proc/cpuinfo: " << EC.message() << "\n";
76 return nullptr;
77 }
78 return std::move(*Text);
79}
80
82 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
83 // and so we must use an operating-system interface to determine the current
84 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
85 const char *generic = "generic";
86
87 // The cpu line is second (after the 'processor: 0' line), so if this
88 // buffer is too small then something has changed (or is wrong).
89 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
90 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
91
92 StringRef::const_iterator CIP = CPUInfoStart;
93
94 StringRef::const_iterator CPUStart = nullptr;
95 size_t CPULen = 0;
96
97 // We need to find the first line which starts with cpu, spaces, and a colon.
98 // After the colon, there may be some additional spaces and then the cpu type.
99 while (CIP < CPUInfoEnd && CPUStart == nullptr) {
100 if (CIP < CPUInfoEnd && *CIP == '\n')
101 ++CIP;
102
103 if (CIP < CPUInfoEnd && *CIP == 'c') {
104 ++CIP;
105 if (CIP < CPUInfoEnd && *CIP == 'p') {
106 ++CIP;
107 if (CIP < CPUInfoEnd && *CIP == 'u') {
108 ++CIP;
109 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
110 ++CIP;
111
112 if (CIP < CPUInfoEnd && *CIP == ':') {
113 ++CIP;
114 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
115 ++CIP;
116
117 if (CIP < CPUInfoEnd) {
118 CPUStart = CIP;
119 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
120 *CIP != ',' && *CIP != '\n'))
121 ++CIP;
122 CPULen = CIP - CPUStart;
123 }
124 }
125 }
126 }
127 }
128
129 if (CPUStart == nullptr)
130 while (CIP < CPUInfoEnd && *CIP != '\n')
131 ++CIP;
132 }
133
134 if (CPUStart == nullptr)
135 return generic;
136
137 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
138 .Case("604e", "604e")
139 .Case("604", "604")
140 .Case("7400", "7400")
141 .Case("7410", "7400")
142 .Case("7447", "7400")
143 .Case("7455", "7450")
144 .Case("G4", "g4")
145 .Case("POWER4", "970")
146 .Case("PPC970FX", "970")
147 .Case("PPC970MP", "970")
148 .Case("G5", "g5")
149 .Case("POWER5", "g5")
150 .Case("A2", "a2")
151 .Case("POWER6", "pwr6")
152 .Case("POWER7", "pwr7")
153 .Case("POWER8", "pwr8")
154 .Case("POWER8E", "pwr8")
155 .Case("POWER8NVL", "pwr8")
156 .Case("POWER9", "pwr9")
157 .Case("POWER10", "pwr10")
158 .Case("POWER11", "pwr11")
159 // FIXME: If we get a simulator or machine with the capabilities of
160 // mcpu=future, we should revisit this and add the name reported by the
161 // simulator/machine.
162 .Default(generic);
163}
164
166 // The cpuid register on arm is not accessible from user space. On Linux,
167 // it is exposed through the /proc/cpuinfo file.
168
169 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
170 // in all cases.
172 ProcCpuinfoContent.split(Lines, "\n");
173
174 // Look for the CPU implementer line.
175 StringRef Implementer;
176 StringRef Hardware;
177 StringRef Part;
178 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
179 if (Lines[I].starts_with("CPU implementer"))
180 Implementer = Lines[I].substr(15).ltrim("\t :");
181 if (Lines[I].starts_with("Hardware"))
182 Hardware = Lines[I].substr(8).ltrim("\t :");
183 if (Lines[I].starts_with("CPU part"))
184 Part = Lines[I].substr(8).ltrim("\t :");
185 }
186
187 if (Implementer == "0x41") { // ARM Ltd.
188 // MSM8992/8994 may give cpu part for the core that the kernel is running on,
189 // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
190 if (Hardware.ends_with("MSM8994") || Hardware.ends_with("MSM8996"))
191 return "cortex-a53";
192
193
194 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
195 // values correspond to the "Part number" in the CP15/c0 register. The
196 // contents are specified in the various processor manuals.
197 // This corresponds to the Main ID Register in Technical Reference Manuals.
198 // and is used in programs like sys-utils
199 return StringSwitch<const char *>(Part)
200 .Case("0x926", "arm926ej-s")
201 .Case("0xb02", "mpcore")
202 .Case("0xb36", "arm1136j-s")
203 .Case("0xb56", "arm1156t2-s")
204 .Case("0xb76", "arm1176jz-s")
205 .Case("0xc05", "cortex-a5")
206 .Case("0xc07", "cortex-a7")
207 .Case("0xc08", "cortex-a8")
208 .Case("0xc09", "cortex-a9")
209 .Case("0xc0f", "cortex-a15")
210 .Case("0xc0e", "cortex-a17")
211 .Case("0xc20", "cortex-m0")
212 .Case("0xc23", "cortex-m3")
213 .Case("0xc24", "cortex-m4")
214 .Case("0xc27", "cortex-m7")
215 .Case("0xd20", "cortex-m23")
216 .Case("0xd21", "cortex-m33")
217 .Case("0xd24", "cortex-m52")
218 .Case("0xd22", "cortex-m55")
219 .Case("0xd23", "cortex-m85")
220 .Case("0xc18", "cortex-r8")
221 .Case("0xd13", "cortex-r52")
222 .Case("0xd16", "cortex-r52plus")
223 .Case("0xd15", "cortex-r82")
224 .Case("0xd14", "cortex-r82ae")
225 .Case("0xd02", "cortex-a34")
226 .Case("0xd04", "cortex-a35")
227 .Case("0xd03", "cortex-a53")
228 .Case("0xd05", "cortex-a55")
229 .Case("0xd46", "cortex-a510")
230 .Case("0xd80", "cortex-a520")
231 .Case("0xd88", "cortex-a520ae")
232 .Case("0xd07", "cortex-a57")
233 .Case("0xd06", "cortex-a65")
234 .Case("0xd43", "cortex-a65ae")
235 .Case("0xd08", "cortex-a72")
236 .Case("0xd09", "cortex-a73")
237 .Case("0xd0a", "cortex-a75")
238 .Case("0xd0b", "cortex-a76")
239 .Case("0xd0e", "cortex-a76ae")
240 .Case("0xd0d", "cortex-a77")
241 .Case("0xd41", "cortex-a78")
242 .Case("0xd42", "cortex-a78ae")
243 .Case("0xd4b", "cortex-a78c")
244 .Case("0xd47", "cortex-a710")
245 .Case("0xd4d", "cortex-a715")
246 .Case("0xd81", "cortex-a720")
247 .Case("0xd89", "cortex-a720ae")
248 .Case("0xd87", "cortex-a725")
249 .Case("0xd44", "cortex-x1")
250 .Case("0xd4c", "cortex-x1c")
251 .Case("0xd48", "cortex-x2")
252 .Case("0xd4e", "cortex-x3")
253 .Case("0xd82", "cortex-x4")
254 .Case("0xd85", "cortex-x925")
255 .Case("0xd4a", "neoverse-e1")
256 .Case("0xd0c", "neoverse-n1")
257 .Case("0xd49", "neoverse-n2")
258 .Case("0xd8e", "neoverse-n3")
259 .Case("0xd40", "neoverse-v1")
260 .Case("0xd4f", "neoverse-v2")
261 .Case("0xd84", "neoverse-v3")
262 .Case("0xd83", "neoverse-v3ae")
263 .Default("generic");
264 }
265
266 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
267 return StringSwitch<const char *>(Part)
268 .Case("0x516", "thunderx2t99")
269 .Case("0x0516", "thunderx2t99")
270 .Case("0xaf", "thunderx2t99")
271 .Case("0x0af", "thunderx2t99")
272 .Case("0xa1", "thunderxt88")
273 .Case("0x0a1", "thunderxt88")
274 .Default("generic");
275 }
276
277 if (Implementer == "0x46") { // Fujitsu Ltd.
278 return StringSwitch<const char *>(Part)
279 .Case("0x001", "a64fx")
280 .Default("generic");
281 }
282
283 if (Implementer == "0x4e") { // NVIDIA Corporation
284 return StringSwitch<const char *>(Part)
285 .Case("0x004", "carmel")
286 .Default("generic");
287 }
288
289 if (Implementer == "0x48") // HiSilicon Technologies, Inc.
290 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
291 // values correspond to the "Part number" in the CP15/c0 register. The
292 // contents are specified in the various processor manuals.
293 return StringSwitch<const char *>(Part)
294 .Case("0xd01", "tsv110")
295 .Default("generic");
296
297 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
298 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
299 // values correspond to the "Part number" in the CP15/c0 register. The
300 // contents are specified in the various processor manuals.
301 return StringSwitch<const char *>(Part)
302 .Case("0x06f", "krait") // APQ8064
303 .Case("0x201", "kryo")
304 .Case("0x205", "kryo")
305 .Case("0x211", "kryo")
306 .Case("0x800", "cortex-a73") // Kryo 2xx Gold
307 .Case("0x801", "cortex-a73") // Kryo 2xx Silver
308 .Case("0x802", "cortex-a75") // Kryo 3xx Gold
309 .Case("0x803", "cortex-a75") // Kryo 3xx Silver
310 .Case("0x804", "cortex-a76") // Kryo 4xx Gold
311 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver
312 .Case("0xc00", "falkor")
313 .Case("0xc01", "saphira")
314 .Case("0x001", "oryon-1")
315 .Default("generic");
316 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
317 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
318 // any predictive pattern across variants and parts.
319 unsigned Variant = 0, Part = 0;
320
321 // Look for the CPU variant line, whose value is a 1 digit hexadecimal
322 // number, corresponding to the Variant bits in the CP15/C0 register.
323 for (auto I : Lines)
324 if (I.consume_front("CPU variant"))
325 I.ltrim("\t :").getAsInteger(0, Variant);
326
327 // Look for the CPU part line, whose value is a 3 digit hexadecimal
328 // number, corresponding to the PartNum bits in the CP15/C0 register.
329 for (auto I : Lines)
330 if (I.consume_front("CPU part"))
331 I.ltrim("\t :").getAsInteger(0, Part);
332
333 unsigned Exynos = (Variant << 12) | Part;
334 switch (Exynos) {
335 default:
336 // Default by falling through to Exynos M3.
337 [[fallthrough]];
338 case 0x1002:
339 return "exynos-m3";
340 case 0x1003:
341 return "exynos-m4";
342 }
343 }
344
345 if (Implementer == "0x6d") { // Microsoft Corporation.
346 // The Microsoft Azure Cobalt 100 CPU is handled as a Neoverse N2.
347 return StringSwitch<const char *>(Part)
348 .Case("0xd49", "neoverse-n2")
349 .Default("generic");
350 }
351
352 if (Implementer == "0xc0") { // Ampere Computing
353 return StringSwitch<const char *>(Part)
354 .Case("0xac3", "ampere1")
355 .Case("0xac4", "ampere1a")
356 .Case("0xac5", "ampere1b")
357 .Default("generic");
358 }
359
360 return "generic";
361}
362
363namespace {
364StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) {
365 switch (Id) {
366 case 2064: // z900 not supported by LLVM
367 case 2066:
368 case 2084: // z990 not supported by LLVM
369 case 2086:
370 case 2094: // z9-109 not supported by LLVM
371 case 2096:
372 return "generic";
373 case 2097:
374 case 2098:
375 return "z10";
376 case 2817:
377 case 2818:
378 return "z196";
379 case 2827:
380 case 2828:
381 return "zEC12";
382 case 2964:
383 case 2965:
384 return HaveVectorSupport? "z13" : "zEC12";
385 case 3906:
386 case 3907:
387 return HaveVectorSupport? "z14" : "zEC12";
388 case 8561:
389 case 8562:
390 return HaveVectorSupport? "z15" : "zEC12";
391 case 3931:
392 case 3932:
393 default:
394 return HaveVectorSupport? "z16" : "zEC12";
395 }
396}
397} // end anonymous namespace
398
400 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
401
402 // The "processor 0:" line comes after a fair amount of other information,
403 // including a cache breakdown, but this should be plenty.
405 ProcCpuinfoContent.split(Lines, "\n");
406
407 // Look for the CPU features.
408 SmallVector<StringRef, 32> CPUFeatures;
409 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
410 if (Lines[I].starts_with("features")) {
411 size_t Pos = Lines[I].find(':');
412 if (Pos != StringRef::npos) {
413 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
414 break;
415 }
416 }
417
418 // We need to check for the presence of vector support independently of
419 // the machine type, since we may only use the vector register set when
420 // supported by the kernel (and hypervisor).
421 bool HaveVectorSupport = false;
422 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
423 if (CPUFeatures[I] == "vx")
424 HaveVectorSupport = true;
425 }
426
427 // Now check the processor machine type.
428 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
429 if (Lines[I].starts_with("processor ")) {
430 size_t Pos = Lines[I].find("machine = ");
431 if (Pos != StringRef::npos) {
432 Pos += sizeof("machine = ") - 1;
433 unsigned int Id;
434 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id))
435 return getCPUNameFromS390Model(Id, HaveVectorSupport);
436 }
437 break;
438 }
439 }
440
441 return "generic";
442}
443
445 // There are 24 lines in /proc/cpuinfo
447 ProcCpuinfoContent.split(Lines, "\n");
448
449 // Look for uarch line to determine cpu name
450 StringRef UArch;
451 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
452 if (Lines[I].starts_with("uarch")) {
453 UArch = Lines[I].substr(5).ltrim("\t :");
454 break;
455 }
456 }
457
458 return StringSwitch<const char *>(UArch)
459 .Case("sifive,u74-mc", "sifive-u74")
460 .Case("sifive,bullet0", "sifive-u74")
461 .Default("");
462}
463
465#if !defined(__linux__) || !defined(__x86_64__)
466 return "generic";
467#else
468 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
469 /* BPF_MOV64_IMM(BPF_REG_0, 0) */
470 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
471 /* BPF_MOV64_IMM(BPF_REG_2, 1) */
472 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
473 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
474 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
475 /* BPF_MOV64_IMM(BPF_REG_0, 1) */
476 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
477 /* BPF_EXIT_INSN() */
478 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
479
480 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
481 /* BPF_MOV64_IMM(BPF_REG_0, 0) */
482 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
483 /* BPF_MOV64_IMM(BPF_REG_2, 1) */
484 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
485 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
486 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
487 /* BPF_MOV64_IMM(BPF_REG_0, 1) */
488 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
489 /* BPF_EXIT_INSN() */
490 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
491
492 struct bpf_prog_load_attr {
493 uint32_t prog_type;
494 uint32_t insn_cnt;
495 uint64_t insns;
496 uint64_t license;
497 uint32_t log_level;
498 uint32_t log_size;
499 uint64_t log_buf;
500 uint32_t kern_version;
501 uint32_t prog_flags;
502 } attr = {};
503 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
504 attr.insn_cnt = 5;
505 attr.insns = (uint64_t)v3_insns;
506 attr.license = (uint64_t)"DUMMY";
507
508 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
509 sizeof(attr));
510 if (fd >= 0) {
511 close(fd);
512 return "v3";
513 }
514
515 /* Clear the whole attr in case its content changed by syscall. */
516 memset(&attr, 0, sizeof(attr));
517 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
518 attr.insn_cnt = 5;
519 attr.insns = (uint64_t)v2_insns;
520 attr.license = (uint64_t)"DUMMY";
521 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
522 if (fd >= 0) {
523 close(fd);
524 return "v2";
525 }
526 return "v1";
527#endif
528}
529
530#if defined(__i386__) || defined(_M_IX86) || defined(__x86_64__) || \
531 defined(_M_X64)
532
533/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
534/// the specified arguments. If we can't run cpuid on the host, return true.
535static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
536 unsigned *rECX, unsigned *rEDX) {
537#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
538 return !__get_cpuid(value, rEAX, rEBX, rECX, rEDX);
539#elif defined(_MSC_VER)
540 // The MSVC intrinsic is portable across x86 and x64.
541 int registers[4];
542 __cpuid(registers, value);
543 *rEAX = registers[0];
544 *rEBX = registers[1];
545 *rECX = registers[2];
546 *rEDX = registers[3];
547 return false;
548#else
549 return true;
550#endif
551}
552
553namespace llvm {
554namespace sys {
555namespace detail {
556namespace x86 {
557
558VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
559 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
560 if (MaxLeaf == nullptr)
561 MaxLeaf = &EAX;
562 else
563 *MaxLeaf = 0;
564
565 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
566 return VendorSignatures::UNKNOWN;
567
568 // "Genu ineI ntel"
569 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
570 return VendorSignatures::GENUINE_INTEL;
571
572 // "Auth enti cAMD"
573 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
574 return VendorSignatures::AUTHENTIC_AMD;
575
576 return VendorSignatures::UNKNOWN;
577}
578
579} // namespace x86
580} // namespace detail
581} // namespace sys
582} // namespace llvm
583
584using namespace llvm::sys::detail::x86;
585
586/// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
587/// the 4 values in the specified arguments. If we can't run cpuid on the host,
588/// return true.
589static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
590 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
591 unsigned *rEDX) {
592 // TODO(boomanaiden154): When the minimum toolchain versions for gcc and clang
593 // are such that __cpuidex is defined within cpuid.h for both, we can remove
594 // the __get_cpuid_count function and share the MSVC implementation between
595 // all three.
596#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
597 return !__get_cpuid_count(value, subleaf, rEAX, rEBX, rECX, rEDX);
598#elif defined(_MSC_VER)
599 int registers[4];
600 __cpuidex(registers, value, subleaf);
601 *rEAX = registers[0];
602 *rEBX = registers[1];
603 *rECX = registers[2];
604 *rEDX = registers[3];
605 return false;
606#else
607 return true;
608#endif
609}
610
611// Read control register 0 (XCR0). Used to detect features such as AVX.
612static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
613 // TODO(boomanaiden154): When the minimum toolchain versions for gcc and clang
614 // are such that _xgetbv is supported by both, we can unify the implementation
615 // with MSVC and remove all inline assembly.
616#if defined(__GNUC__) || defined(__clang__)
617 // Check xgetbv; this uses a .byte sequence instead of the instruction
618 // directly because older assemblers do not include support for xgetbv and
619 // there is no easy way to conditionally compile based on the assembler used.
620 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
621 return false;
622#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
623 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
624 *rEAX = Result;
625 *rEDX = Result >> 32;
626 return false;
627#else
628 return true;
629#endif
630}
631
632static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
633 unsigned *Model) {
634 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
635 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
636 if (*Family == 6 || *Family == 0xf) {
637 if (*Family == 0xf)
638 // Examine extended family ID if family ID is F.
639 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
640 // Examine extended model ID if family ID is 6 or F.
641 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
642 }
643}
644
645#define testFeature(F) (Features[F / 32] & (1 << (F % 32))) != 0
646
647static StringRef getIntelProcessorTypeAndSubtype(unsigned Family,
648 unsigned Model,
649 const unsigned *Features,
650 unsigned *Type,
651 unsigned *Subtype) {
652 StringRef CPU;
653
654 switch (Family) {
655 case 3:
656 CPU = "i386";
657 break;
658 case 4:
659 CPU = "i486";
660 break;
661 case 5:
662 if (testFeature(X86::FEATURE_MMX)) {
663 CPU = "pentium-mmx";
664 break;
665 }
666 CPU = "pentium";
667 break;
668 case 6:
669 switch (Model) {
670 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
671 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
672 // mobile processor, Intel Core 2 Extreme processor, Intel
673 // Pentium Dual-Core processor, Intel Xeon processor, model
674 // 0Fh. All processors are manufactured using the 65 nm process.
675 case 0x16: // Intel Celeron processor model 16h. All processors are
676 // manufactured using the 65 nm process
677 CPU = "core2";
678 *Type = X86::INTEL_CORE2;
679 break;
680 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
681 // 17h. All processors are manufactured using the 45 nm process.
682 //
683 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
684 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
685 // the 45 nm process.
686 CPU = "penryn";
687 *Type = X86::INTEL_CORE2;
688 break;
689 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
690 // processors are manufactured using the 45 nm process.
691 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
692 // As found in a Summer 2010 model iMac.
693 case 0x1f:
694 case 0x2e: // Nehalem EX
695 CPU = "nehalem";
696 *Type = X86::INTEL_COREI7;
697 *Subtype = X86::INTEL_COREI7_NEHALEM;
698 break;
699 case 0x25: // Intel Core i7, laptop version.
700 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
701 // processors are manufactured using the 32 nm process.
702 case 0x2f: // Westmere EX
703 CPU = "westmere";
704 *Type = X86::INTEL_COREI7;
705 *Subtype = X86::INTEL_COREI7_WESTMERE;
706 break;
707 case 0x2a: // Intel Core i7 processor. All processors are manufactured
708 // using the 32 nm process.
709 case 0x2d:
710 CPU = "sandybridge";
711 *Type = X86::INTEL_COREI7;
712 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
713 break;
714 case 0x3a:
715 case 0x3e: // Ivy Bridge EP
716 CPU = "ivybridge";
717 *Type = X86::INTEL_COREI7;
718 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
719 break;
720
721 // Haswell:
722 case 0x3c:
723 case 0x3f:
724 case 0x45:
725 case 0x46:
726 CPU = "haswell";
727 *Type = X86::INTEL_COREI7;
728 *Subtype = X86::INTEL_COREI7_HASWELL;
729 break;
730
731 // Broadwell:
732 case 0x3d:
733 case 0x47:
734 case 0x4f:
735 case 0x56:
736 CPU = "broadwell";
737 *Type = X86::INTEL_COREI7;
738 *Subtype = X86::INTEL_COREI7_BROADWELL;
739 break;
740
741 // Skylake:
742 case 0x4e: // Skylake mobile
743 case 0x5e: // Skylake desktop
744 case 0x8e: // Kaby Lake mobile
745 case 0x9e: // Kaby Lake desktop
746 case 0xa5: // Comet Lake-H/S
747 case 0xa6: // Comet Lake-U
748 CPU = "skylake";
749 *Type = X86::INTEL_COREI7;
750 *Subtype = X86::INTEL_COREI7_SKYLAKE;
751 break;
752
753 // Rocketlake:
754 case 0xa7:
755 CPU = "rocketlake";
756 *Type = X86::INTEL_COREI7;
757 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
758 break;
759
760 // Skylake Xeon:
761 case 0x55:
762 *Type = X86::INTEL_COREI7;
763 if (testFeature(X86::FEATURE_AVX512BF16)) {
764 CPU = "cooperlake";
765 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
766 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
767 CPU = "cascadelake";
768 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
769 } else {
770 CPU = "skylake-avx512";
771 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
772 }
773 break;
774
775 // Cannonlake:
776 case 0x66:
777 CPU = "cannonlake";
778 *Type = X86::INTEL_COREI7;
779 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
780 break;
781
782 // Icelake:
783 case 0x7d:
784 case 0x7e:
785 CPU = "icelake-client";
786 *Type = X86::INTEL_COREI7;
787 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
788 break;
789
790 // Tigerlake:
791 case 0x8c:
792 case 0x8d:
793 CPU = "tigerlake";
794 *Type = X86::INTEL_COREI7;
795 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
796 break;
797
798 // Alderlake:
799 case 0x97:
800 case 0x9a:
801 // Gracemont
802 case 0xbe:
803 // Raptorlake:
804 case 0xb7:
805 case 0xba:
806 case 0xbf:
807 // Meteorlake:
808 case 0xaa:
809 case 0xac:
810 CPU = "alderlake";
811 *Type = X86::INTEL_COREI7;
812 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
813 break;
814
815 // Arrowlake:
816 case 0xc5:
817 CPU = "arrowlake";
818 *Type = X86::INTEL_COREI7;
819 *Subtype = X86::INTEL_COREI7_ARROWLAKE;
820 break;
821
822 // Arrowlake S:
823 case 0xc6:
824 // Lunarlake:
825 case 0xbd:
826 CPU = "arrowlake-s";
827 *Type = X86::INTEL_COREI7;
828 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
829 break;
830
831 // Pantherlake:
832 case 0xcc:
833 CPU = "pantherlake";
834 *Type = X86::INTEL_COREI7;
835 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;
836 break;
837
838 // Graniterapids:
839 case 0xad:
840 CPU = "graniterapids";
841 *Type = X86::INTEL_COREI7;
842 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
843 break;
844
845 // Granite Rapids D:
846 case 0xae:
847 CPU = "graniterapids-d";
848 *Type = X86::INTEL_COREI7;
849 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
850 break;
851
852 // Icelake Xeon:
853 case 0x6a:
854 case 0x6c:
855 CPU = "icelake-server";
856 *Type = X86::INTEL_COREI7;
857 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
858 break;
859
860 // Emerald Rapids:
861 case 0xcf:
862 // Sapphire Rapids:
863 case 0x8f:
864 CPU = "sapphirerapids";
865 *Type = X86::INTEL_COREI7;
866 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
867 break;
868
869 case 0x1c: // Most 45 nm Intel Atom processors
870 case 0x26: // 45 nm Atom Lincroft
871 case 0x27: // 32 nm Atom Medfield
872 case 0x35: // 32 nm Atom Midview
873 case 0x36: // 32 nm Atom Midview
874 CPU = "bonnell";
875 *Type = X86::INTEL_BONNELL;
876 break;
877
878 // Atom Silvermont codes from the Intel software optimization guide.
879 case 0x37:
880 case 0x4a:
881 case 0x4d:
882 case 0x5a:
883 case 0x5d:
884 case 0x4c: // really airmont
885 CPU = "silvermont";
886 *Type = X86::INTEL_SILVERMONT;
887 break;
888 // Goldmont:
889 case 0x5c: // Apollo Lake
890 case 0x5f: // Denverton
891 CPU = "goldmont";
892 *Type = X86::INTEL_GOLDMONT;
893 break;
894 case 0x7a:
895 CPU = "goldmont-plus";
896 *Type = X86::INTEL_GOLDMONT_PLUS;
897 break;
898 case 0x86:
899 case 0x8a: // Lakefield
900 case 0x96: // Elkhart Lake
901 case 0x9c: // Jasper Lake
902 CPU = "tremont";
903 *Type = X86::INTEL_TREMONT;
904 break;
905
906 // Sierraforest:
907 case 0xaf:
908 CPU = "sierraforest";
909 *Type = X86::INTEL_SIERRAFOREST;
910 break;
911
912 // Grandridge:
913 case 0xb6:
914 CPU = "grandridge";
915 *Type = X86::INTEL_GRANDRIDGE;
916 break;
917
918 // Clearwaterforest:
919 case 0xdd:
920 CPU = "clearwaterforest";
921 *Type = X86::INTEL_CLEARWATERFOREST;
922 break;
923
924 // Xeon Phi (Knights Landing + Knights Mill):
925 case 0x57:
926 CPU = "knl";
927 *Type = X86::INTEL_KNL;
928 break;
929 case 0x85:
930 CPU = "knm";
931 *Type = X86::INTEL_KNM;
932 break;
933
934 default: // Unknown family 6 CPU, try to guess.
935 // Don't both with Type/Subtype here, they aren't used by the caller.
936 // They're used above to keep the code in sync with compiler-rt.
937 // TODO detect tigerlake host from model
938 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
939 CPU = "tigerlake";
940 } else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
941 CPU = "icelake-client";
942 } else if (testFeature(X86::FEATURE_AVX512VBMI)) {
943 CPU = "cannonlake";
944 } else if (testFeature(X86::FEATURE_AVX512BF16)) {
945 CPU = "cooperlake";
946 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
947 CPU = "cascadelake";
948 } else if (testFeature(X86::FEATURE_AVX512VL)) {
949 CPU = "skylake-avx512";
950 } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
951 if (testFeature(X86::FEATURE_SHA))
952 CPU = "goldmont";
953 else
954 CPU = "skylake";
955 } else if (testFeature(X86::FEATURE_ADX)) {
956 CPU = "broadwell";
957 } else if (testFeature(X86::FEATURE_AVX2)) {
958 CPU = "haswell";
959 } else if (testFeature(X86::FEATURE_AVX)) {
960 CPU = "sandybridge";
961 } else if (testFeature(X86::FEATURE_SSE4_2)) {
962 if (testFeature(X86::FEATURE_MOVBE))
963 CPU = "silvermont";
964 else
965 CPU = "nehalem";
966 } else if (testFeature(X86::FEATURE_SSE4_1)) {
967 CPU = "penryn";
968 } else if (testFeature(X86::FEATURE_SSSE3)) {
969 if (testFeature(X86::FEATURE_MOVBE))
970 CPU = "bonnell";
971 else
972 CPU = "core2";
973 } else if (testFeature(X86::FEATURE_64BIT)) {
974 CPU = "core2";
975 } else if (testFeature(X86::FEATURE_SSE3)) {
976 CPU = "yonah";
977 } else if (testFeature(X86::FEATURE_SSE2)) {
978 CPU = "pentium-m";
979 } else if (testFeature(X86::FEATURE_SSE)) {
980 CPU = "pentium3";
981 } else if (testFeature(X86::FEATURE_MMX)) {
982 CPU = "pentium2";
983 } else {
984 CPU = "pentiumpro";
985 }
986 break;
987 }
988 break;
989 case 15: {
990 if (testFeature(X86::FEATURE_64BIT)) {
991 CPU = "nocona";
992 break;
993 }
994 if (testFeature(X86::FEATURE_SSE3)) {
995 CPU = "prescott";
996 break;
997 }
998 CPU = "pentium4";
999 break;
1000 }
1001 default:
1002 break; // Unknown.
1003 }
1004
1005 return CPU;
1006}
1007
1008static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
1009 unsigned Model,
1010 const unsigned *Features,
1011 unsigned *Type,
1012 unsigned *Subtype) {
1013 const char *CPU = 0;
1014
1015 switch (Family) {
1016 case 4:
1017 CPU = "i486";
1018 break;
1019 case 5:
1020 CPU = "pentium";
1021 switch (Model) {
1022 case 6:
1023 case 7:
1024 CPU = "k6";
1025 break;
1026 case 8:
1027 CPU = "k6-2";
1028 break;
1029 case 9:
1030 case 13:
1031 CPU = "k6-3";
1032 break;
1033 case 10:
1034 CPU = "geode";
1035 break;
1036 }
1037 break;
1038 case 6:
1039 if (testFeature(X86::FEATURE_SSE)) {
1040 CPU = "athlon-xp";
1041 break;
1042 }
1043 CPU = "athlon";
1044 break;
1045 case 15:
1046 if (testFeature(X86::FEATURE_SSE3)) {
1047 CPU = "k8-sse3";
1048 break;
1049 }
1050 CPU = "k8";
1051 break;
1052 case 16:
1053 CPU = "amdfam10";
1054 *Type = X86::AMDFAM10H; // "amdfam10"
1055 switch (Model) {
1056 case 2:
1057 *Subtype = X86::AMDFAM10H_BARCELONA;
1058 break;
1059 case 4:
1060 *Subtype = X86::AMDFAM10H_SHANGHAI;
1061 break;
1062 case 8:
1063 *Subtype = X86::AMDFAM10H_ISTANBUL;
1064 break;
1065 }
1066 break;
1067 case 20:
1068 CPU = "btver1";
1069 *Type = X86::AMD_BTVER1;
1070 break;
1071 case 21:
1072 CPU = "bdver1";
1073 *Type = X86::AMDFAM15H;
1074 if (Model >= 0x60 && Model <= 0x7f) {
1075 CPU = "bdver4";
1076 *Subtype = X86::AMDFAM15H_BDVER4;
1077 break; // 60h-7Fh: Excavator
1078 }
1079 if (Model >= 0x30 && Model <= 0x3f) {
1080 CPU = "bdver3";
1081 *Subtype = X86::AMDFAM15H_BDVER3;
1082 break; // 30h-3Fh: Steamroller
1083 }
1084 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
1085 CPU = "bdver2";
1086 *Subtype = X86::AMDFAM15H_BDVER2;
1087 break; // 02h, 10h-1Fh: Piledriver
1088 }
1089 if (Model <= 0x0f) {
1090 *Subtype = X86::AMDFAM15H_BDVER1;
1091 break; // 00h-0Fh: Bulldozer
1092 }
1093 break;
1094 case 22:
1095 CPU = "btver2";
1096 *Type = X86::AMD_BTVER2;
1097 break;
1098 case 23:
1099 CPU = "znver1";
1100 *Type = X86::AMDFAM17H;
1101 if ((Model >= 0x30 && Model <= 0x3f) || (Model == 0x47) ||
1102 (Model >= 0x60 && Model <= 0x67) || (Model >= 0x68 && Model <= 0x6f) ||
1103 (Model >= 0x70 && Model <= 0x7f) || (Model >= 0x84 && Model <= 0x87) ||
1104 (Model >= 0x90 && Model <= 0x97) || (Model >= 0x98 && Model <= 0x9f) ||
1105 (Model >= 0xa0 && Model <= 0xaf)) {
1106 // Family 17h Models 30h-3Fh (Starship) Zen 2
1107 // Family 17h Models 47h (Cardinal) Zen 2
1108 // Family 17h Models 60h-67h (Renoir) Zen 2
1109 // Family 17h Models 68h-6Fh (Lucienne) Zen 2
1110 // Family 17h Models 70h-7Fh (Matisse) Zen 2
1111 // Family 17h Models 84h-87h (ProjectX) Zen 2
1112 // Family 17h Models 90h-97h (VanGogh) Zen 2
1113 // Family 17h Models 98h-9Fh (Mero) Zen 2
1114 // Family 17h Models A0h-AFh (Mendocino) Zen 2
1115 CPU = "znver2";
1116 *Subtype = X86::AMDFAM17H_ZNVER2;
1117 break;
1118 }
1119 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x20 && Model <= 0x2f)) {
1120 // Family 17h Models 10h-1Fh (Raven1) Zen
1121 // Family 17h Models 10h-1Fh (Picasso) Zen+
1122 // Family 17h Models 20h-2Fh (Raven2 x86) Zen
1123 *Subtype = X86::AMDFAM17H_ZNVER1;
1124 break;
1125 }
1126 break;
1127 case 25:
1128 CPU = "znver3";
1129 *Type = X86::AMDFAM19H;
1130 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x2f) ||
1131 (Model >= 0x30 && Model <= 0x3f) || (Model >= 0x40 && Model <= 0x4f) ||
1132 (Model >= 0x50 && Model <= 0x5f)) {
1133 // Family 19h Models 00h-0Fh (Genesis, Chagall) Zen 3
1134 // Family 19h Models 20h-2Fh (Vermeer) Zen 3
1135 // Family 19h Models 30h-3Fh (Badami) Zen 3
1136 // Family 19h Models 40h-4Fh (Rembrandt) Zen 3+
1137 // Family 19h Models 50h-5Fh (Cezanne) Zen 3
1138 *Subtype = X86::AMDFAM19H_ZNVER3;
1139 break;
1140 }
1141 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x60 && Model <= 0x6f) ||
1142 (Model >= 0x70 && Model <= 0x77) || (Model >= 0x78 && Model <= 0x7f) ||
1143 (Model >= 0xa0 && Model <= 0xaf)) {
1144 // Family 19h Models 10h-1Fh (Stones; Storm Peak) Zen 4
1145 // Family 19h Models 60h-6Fh (Raphael) Zen 4
1146 // Family 19h Models 70h-77h (Phoenix, Hawkpoint1) Zen 4
1147 // Family 19h Models 78h-7Fh (Phoenix 2, Hawkpoint2) Zen 4
1148 // Family 19h Models A0h-AFh (Stones-Dense) Zen 4
1149 CPU = "znver4";
1150 *Subtype = X86::AMDFAM19H_ZNVER4;
1151 break; // "znver4"
1152 }
1153 break; // family 19h
1154 default:
1155 break; // Unknown AMD CPU.
1156 }
1157
1158 return CPU;
1159}
1160
1161#undef testFeature
1162
1163static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
1164 unsigned *Features) {
1165 unsigned EAX, EBX;
1166
1167 auto setFeature = [&](unsigned F) {
1168 Features[F / 32] |= 1U << (F % 32);
1169 };
1170
1171 if ((EDX >> 15) & 1)
1172 setFeature(X86::FEATURE_CMOV);
1173 if ((EDX >> 23) & 1)
1174 setFeature(X86::FEATURE_MMX);
1175 if ((EDX >> 25) & 1)
1176 setFeature(X86::FEATURE_SSE);
1177 if ((EDX >> 26) & 1)
1178 setFeature(X86::FEATURE_SSE2);
1179
1180 if ((ECX >> 0) & 1)
1181 setFeature(X86::FEATURE_SSE3);
1182 if ((ECX >> 1) & 1)
1183 setFeature(X86::FEATURE_PCLMUL);
1184 if ((ECX >> 9) & 1)
1185 setFeature(X86::FEATURE_SSSE3);
1186 if ((ECX >> 12) & 1)
1187 setFeature(X86::FEATURE_FMA);
1188 if ((ECX >> 19) & 1)
1189 setFeature(X86::FEATURE_SSE4_1);
1190 if ((ECX >> 20) & 1) {
1191 setFeature(X86::FEATURE_SSE4_2);
1192 setFeature(X86::FEATURE_CRC32);
1193 }
1194 if ((ECX >> 23) & 1)
1195 setFeature(X86::FEATURE_POPCNT);
1196 if ((ECX >> 25) & 1)
1197 setFeature(X86::FEATURE_AES);
1198
1199 if ((ECX >> 22) & 1)
1200 setFeature(X86::FEATURE_MOVBE);
1201
1202 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1203 // indicates that the AVX registers will be saved and restored on context
1204 // switch, then we have full AVX support.
1205 const unsigned AVXBits = (1 << 27) | (1 << 28);
1206 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1207 ((EAX & 0x6) == 0x6);
1208#if defined(__APPLE__)
1209 // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1210 // save the AVX512 context if we use AVX512 instructions, even the bit is not
1211 // set right now.
1212 bool HasAVX512Save = true;
1213#else
1214 // AVX512 requires additional context to be saved by the OS.
1215 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
1216#endif
1217
1218 if (HasAVX)
1219 setFeature(X86::FEATURE_AVX);
1220
1221 bool HasLeaf7 =
1222 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1223
1224 if (HasLeaf7 && ((EBX >> 3) & 1))
1225 setFeature(X86::FEATURE_BMI);
1226 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1227 setFeature(X86::FEATURE_AVX2);
1228 if (HasLeaf7 && ((EBX >> 8) & 1))
1229 setFeature(X86::FEATURE_BMI2);
1230 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) {
1231 setFeature(X86::FEATURE_AVX512F);
1232 setFeature(X86::FEATURE_EVEX512);
1233 }
1234 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1235 setFeature(X86::FEATURE_AVX512DQ);
1236 if (HasLeaf7 && ((EBX >> 19) & 1))
1237 setFeature(X86::FEATURE_ADX);
1238 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1239 setFeature(X86::FEATURE_AVX512IFMA);
1240 if (HasLeaf7 && ((EBX >> 23) & 1))
1241 setFeature(X86::FEATURE_CLFLUSHOPT);
1242 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1243 setFeature(X86::FEATURE_AVX512CD);
1244 if (HasLeaf7 && ((EBX >> 29) & 1))
1245 setFeature(X86::FEATURE_SHA);
1246 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1247 setFeature(X86::FEATURE_AVX512BW);
1248 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1249 setFeature(X86::FEATURE_AVX512VL);
1250
1251 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1252 setFeature(X86::FEATURE_AVX512VBMI);
1253 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1254 setFeature(X86::FEATURE_AVX512VBMI2);
1255 if (HasLeaf7 && ((ECX >> 8) & 1))
1256 setFeature(X86::FEATURE_GFNI);
1257 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1258 setFeature(X86::FEATURE_VPCLMULQDQ);
1259 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1260 setFeature(X86::FEATURE_AVX512VNNI);
1261 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1262 setFeature(X86::FEATURE_AVX512BITALG);
1263 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1264 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1265
1266 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1267 setFeature(X86::FEATURE_AVX5124VNNIW);
1268 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1269 setFeature(X86::FEATURE_AVX5124FMAPS);
1270 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1271 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1272
1273 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
1274 // return all 0s for invalid subleaves so check the limit.
1275 bool HasLeaf7Subleaf1 =
1276 HasLeaf7 && EAX >= 1 &&
1277 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1278 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1279 setFeature(X86::FEATURE_AVX512BF16);
1280
1281 unsigned MaxExtLevel;
1282 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1283
1284 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1285 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1286 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1287 setFeature(X86::FEATURE_SSE4_A);
1288 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1289 setFeature(X86::FEATURE_XOP);
1290 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1291 setFeature(X86::FEATURE_FMA4);
1292
1293 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1294 setFeature(X86::FEATURE_64BIT);
1295}
1296
1298 unsigned MaxLeaf = 0;
1299 const VendorSignatures Vendor = getVendorSignature(&MaxLeaf);
1300 if (Vendor == VendorSignatures::UNKNOWN)
1301 return "generic";
1302
1303 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1304 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1305
1306 unsigned Family = 0, Model = 0;
1307 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0};
1308 detectX86FamilyModel(EAX, &Family, &Model);
1309 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1310
1311 // These aren't consumed in this file, but we try to keep some source code the
1312 // same or similar to compiler-rt.
1313 unsigned Type = 0;
1314 unsigned Subtype = 0;
1315
1316 StringRef CPU;
1317
1318 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1319 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type,
1320 &Subtype);
1321 } else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1322 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type,
1323 &Subtype);
1324 }
1325
1326 if (!CPU.empty())
1327 return CPU;
1328
1329 return "generic";
1330}
1331
1332#elif defined(__APPLE__) && defined(__powerpc__)
1334 host_basic_info_data_t hostInfo;
1335 mach_msg_type_number_t infoCount;
1336
1337 infoCount = HOST_BASIC_INFO_COUNT;
1338 mach_port_t hostPort = mach_host_self();
1339 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1340 &infoCount);
1341 mach_port_deallocate(mach_task_self(), hostPort);
1342
1343 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1344 return "generic";
1345
1346 switch (hostInfo.cpu_subtype) {
1348 return "601";
1350 return "602";
1352 return "603";
1354 return "603e";
1356 return "603ev";
1358 return "604";
1360 return "604e";
1362 return "620";
1364 return "750";
1366 return "7400";
1368 return "7450";
1370 return "970";
1371 default:;
1372 }
1373
1374 return "generic";
1375}
1376#elif defined(__linux__) && defined(__powerpc__)
1378 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1379 StringRef Content = P ? P->getBuffer() : "";
1380 return detail::getHostCPUNameForPowerPC(Content);
1381}
1382#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1384 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1385 StringRef Content = P ? P->getBuffer() : "";
1386 return detail::getHostCPUNameForARM(Content);
1387}
1388#elif defined(__linux__) && defined(__s390x__)
1390 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1391 StringRef Content = P ? P->getBuffer() : "";
1392 return detail::getHostCPUNameForS390x(Content);
1393}
1394#elif defined(__MVS__)
1396 // Get pointer to Communications Vector Table (CVT).
1397 // The pointer is located at offset 16 of the Prefixed Save Area (PSA).
1398 // It is stored as 31 bit pointer and will be zero-extended to 64 bit.
1399 int *StartToCVTOffset = reinterpret_cast<int *>(0x10);
1400 // Since its stored as a 31-bit pointer, get the 4 bytes from the start
1401 // of address.
1402 int ReadValue = *StartToCVTOffset;
1403 // Explicitly clear the high order bit.
1404 ReadValue = (ReadValue & 0x7FFFFFFF);
1405 char *CVT = reinterpret_cast<char *>(ReadValue);
1406 // The model number is located in the CVT prefix at offset -6 and stored as
1407 // signless packed decimal.
1408 uint16_t Id = *(uint16_t *)&CVT[-6];
1409 // Convert number to integer.
1410 Id = decodePackedBCD<uint16_t>(Id, false);
1411 // Check for vector support. It's stored in field CVTFLAG5 (offset 244),
1412 // bit CVTVEF (X'80'). The facilities list is part of the PSA but the vector
1413 // extension can only be used if bit CVTVEF is on.
1414 bool HaveVectorSupport = CVT[244] & 0x80;
1415 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1416}
1417#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1418#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1419#define CPUFAMILY_ARM_CYCLONE 0x37a09642
1420#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1421#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1422#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1423#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1424#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1425#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1426#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1427#define CPUFAMILY_ARM_BLIZZARD_AVALANCHE 0xda33d83d
1428#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea
1429
1431 uint32_t Family;
1432 size_t Length = sizeof(Family);
1433 sysctlbyname("hw.cpufamily", &Family, &Length, NULL, 0);
1434
1435 switch (Family) {
1436 case CPUFAMILY_ARM_SWIFT:
1437 return "swift";
1438 case CPUFAMILY_ARM_CYCLONE:
1439 return "apple-a7";
1440 case CPUFAMILY_ARM_TYPHOON:
1441 return "apple-a8";
1442 case CPUFAMILY_ARM_TWISTER:
1443 return "apple-a9";
1444 case CPUFAMILY_ARM_HURRICANE:
1445 return "apple-a10";
1446 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1447 return "apple-a11";
1448 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1449 return "apple-a12";
1450 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1451 return "apple-a13";
1452 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1453 return "apple-m1";
1454 case CPUFAMILY_ARM_BLIZZARD_AVALANCHE:
1455 return "apple-m2";
1456 case CPUFAMILY_ARM_EVEREST_SAWTOOTH:
1457 return "apple-m3";
1458 default:
1459 // Default to the newest CPU we know about.
1460 return "apple-m3";
1461 }
1462}
1463#elif defined(_AIX)
1465 switch (_system_configuration.implementation) {
1466 case POWER_4:
1467 if (_system_configuration.version == PV_4_3)
1468 return "970";
1469 return "pwr4";
1470 case POWER_5:
1471 if (_system_configuration.version == PV_5)
1472 return "pwr5";
1473 return "pwr5x";
1474 case POWER_6:
1475 if (_system_configuration.version == PV_6_Compat)
1476 return "pwr6";
1477 return "pwr6x";
1478 case POWER_7:
1479 return "pwr7";
1480 case POWER_8:
1481 return "pwr8";
1482 case POWER_9:
1483 return "pwr9";
1484// TODO: simplify this once the macro is available in all OS levels.
1485#ifdef POWER_10
1486 case POWER_10:
1487#else
1488 case 0x40000:
1489#endif
1490 return "pwr10";
1491#ifdef POWER_11
1492 case POWER_11:
1493#else
1494 case 0x80000:
1495#endif
1496 return "pwr11";
1497 default:
1498 return "generic";
1499 }
1500}
1501#elif defined(__loongarch__)
1503 // Use processor id to detect cpu name.
1504 uint32_t processor_id;
1505 __asm__("cpucfg %[prid], $zero\n\t" : [prid] "=r"(processor_id));
1506 // Refer PRID_SERIES_MASK in linux kernel: arch/loongarch/include/asm/cpu.h.
1507 switch (processor_id & 0xf000) {
1508 case 0xc000: // Loongson 64bit, 4-issue
1509 return "la464";
1510 case 0xd000: // Loongson 64bit, 6-issue
1511 return "la664";
1512 // TODO: Others.
1513 default:
1514 break;
1515 }
1516 return "generic";
1517}
1518#elif defined(__riscv)
1520#if defined(__linux__)
1521 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1522 StringRef Content = P ? P->getBuffer() : "";
1523 StringRef Name = detail::getHostCPUNameForRISCV(Content);
1524 if (!Name.empty())
1525 return Name;
1526#endif
1527#if __riscv_xlen == 64
1528 return "generic-rv64";
1529#elif __riscv_xlen == 32
1530 return "generic-rv32";
1531#else
1532#error "Unhandled value of __riscv_xlen"
1533#endif
1534}
1535#elif defined(__sparc__)
1536#if defined(__linux__)
1539 ProcCpuinfoContent.split(Lines, "\n");
1540
1541 // Look for cpu line to determine cpu name
1542 StringRef Cpu;
1543 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
1544 if (Lines[I].starts_with("cpu")) {
1545 Cpu = Lines[I].substr(5).ltrim("\t :");
1546 break;
1547 }
1548 }
1549
1550 return StringSwitch<const char *>(Cpu)
1551 .StartsWith("SuperSparc", "supersparc")
1552 .StartsWith("HyperSparc", "hypersparc")
1553 .StartsWith("SpitFire", "ultrasparc")
1554 .StartsWith("BlackBird", "ultrasparc")
1555 .StartsWith("Sabre", " ultrasparc")
1556 .StartsWith("Hummingbird", "ultrasparc")
1557 .StartsWith("Cheetah", "ultrasparc3")
1558 .StartsWith("Jalapeno", "ultrasparc3")
1559 .StartsWith("Jaguar", "ultrasparc3")
1560 .StartsWith("Panther", "ultrasparc3")
1561 .StartsWith("Serrano", "ultrasparc3")
1562 .StartsWith("UltraSparc T1", "niagara")
1563 .StartsWith("UltraSparc T2", "niagara2")
1564 .StartsWith("UltraSparc T3", "niagara3")
1565 .StartsWith("UltraSparc T4", "niagara4")
1566 .StartsWith("UltraSparc T5", "niagara4")
1567 .StartsWith("LEON", "leon3")
1568 // niagara7/m8 not supported by LLVM yet.
1569 .StartsWith("SPARC-M7", "niagara4" /* "niagara7" */)
1570 .StartsWith("SPARC-S7", "niagara4" /* "niagara7" */)
1571 .StartsWith("SPARC-M8", "niagara4" /* "m8" */)
1572 .Default("generic");
1573}
1574#endif
1575
1577#if defined(__linux__)
1578 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1579 StringRef Content = P ? P->getBuffer() : "";
1580 return detail::getHostCPUNameForSPARC(Content);
1581#elif defined(__sun__) && defined(__svr4__)
1582 char *buf = NULL;
1583 kstat_ctl_t *kc;
1584 kstat_t *ksp;
1585 kstat_named_t *brand = NULL;
1586
1587 kc = kstat_open();
1588 if (kc != NULL) {
1589 ksp = kstat_lookup(kc, const_cast<char *>("cpu_info"), -1, NULL);
1590 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1591 ksp->ks_type == KSTAT_TYPE_NAMED)
1592 brand =
1593 (kstat_named_t *)kstat_data_lookup(ksp, const_cast<char *>("brand"));
1594 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1595 buf = KSTAT_NAMED_STR_PTR(brand);
1596 }
1597 kstat_close(kc);
1598
1599 return StringSwitch<const char *>(buf)
1600 .Case("TMS390S10", "supersparc") // Texas Instruments microSPARC I
1601 .Case("TMS390Z50", "supersparc") // Texas Instruments SuperSPARC I
1602 .Case("TMS390Z55",
1603 "supersparc") // Texas Instruments SuperSPARC I with SuperCache
1604 .Case("MB86904", "supersparc") // Fujitsu microSPARC II
1605 .Case("MB86907", "supersparc") // Fujitsu TurboSPARC
1606 .Case("RT623", "hypersparc") // Ross hyperSPARC
1607 .Case("RT625", "hypersparc")
1608 .Case("RT626", "hypersparc")
1609 .Case("UltraSPARC-I", "ultrasparc")
1610 .Case("UltraSPARC-II", "ultrasparc")
1611 .Case("UltraSPARC-IIe", "ultrasparc")
1612 .Case("UltraSPARC-IIi", "ultrasparc")
1613 .Case("SPARC64-III", "ultrasparc")
1614 .Case("SPARC64-IV", "ultrasparc")
1615 .Case("UltraSPARC-III", "ultrasparc3")
1616 .Case("UltraSPARC-III+", "ultrasparc3")
1617 .Case("UltraSPARC-IIIi", "ultrasparc3")
1618 .Case("UltraSPARC-IIIi+", "ultrasparc3")
1619 .Case("UltraSPARC-IV", "ultrasparc3")
1620 .Case("UltraSPARC-IV+", "ultrasparc3")
1621 .Case("SPARC64-V", "ultrasparc3")
1622 .Case("SPARC64-VI", "ultrasparc3")
1623 .Case("SPARC64-VII", "ultrasparc3")
1624 .Case("UltraSPARC-T1", "niagara")
1625 .Case("UltraSPARC-T2", "niagara2")
1626 .Case("UltraSPARC-T2", "niagara2")
1627 .Case("UltraSPARC-T2+", "niagara2")
1628 .Case("SPARC-T3", "niagara3")
1629 .Case("SPARC-T4", "niagara4")
1630 .Case("SPARC-T5", "niagara4")
1631 // niagara7/m8 not supported by LLVM yet.
1632 .Case("SPARC-M7", "niagara4" /* "niagara7" */)
1633 .Case("SPARC-S7", "niagara4" /* "niagara7" */)
1634 .Case("SPARC-M8", "niagara4" /* "m8" */)
1635 .Default("generic");
1636#else
1637 return "generic";
1638#endif
1639}
1640#else
1641StringRef sys::getHostCPUName() { return "generic"; }
1642namespace llvm {
1643namespace sys {
1644namespace detail {
1645namespace x86 {
1646
1649}
1650
1651} // namespace x86
1652} // namespace detail
1653} // namespace sys
1654} // namespace llvm
1655#endif
1656
1657#if defined(__i386__) || defined(_M_IX86) || \
1658 defined(__x86_64__) || defined(_M_X64)
1660 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1661 unsigned MaxLevel;
1662 StringMap<bool> Features;
1663
1664 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1665 return Features;
1666
1667 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1668
1669 Features["cx8"] = (EDX >> 8) & 1;
1670 Features["cmov"] = (EDX >> 15) & 1;
1671 Features["mmx"] = (EDX >> 23) & 1;
1672 Features["fxsr"] = (EDX >> 24) & 1;
1673 Features["sse"] = (EDX >> 25) & 1;
1674 Features["sse2"] = (EDX >> 26) & 1;
1675
1676 Features["sse3"] = (ECX >> 0) & 1;
1677 Features["pclmul"] = (ECX >> 1) & 1;
1678 Features["ssse3"] = (ECX >> 9) & 1;
1679 Features["cx16"] = (ECX >> 13) & 1;
1680 Features["sse4.1"] = (ECX >> 19) & 1;
1681 Features["sse4.2"] = (ECX >> 20) & 1;
1682 Features["crc32"] = Features["sse4.2"];
1683 Features["movbe"] = (ECX >> 22) & 1;
1684 Features["popcnt"] = (ECX >> 23) & 1;
1685 Features["aes"] = (ECX >> 25) & 1;
1686 Features["rdrnd"] = (ECX >> 30) & 1;
1687
1688 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1689 // indicates that the AVX registers will be saved and restored on context
1690 // switch, then we have full AVX support.
1691 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1692 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6);
1693#if defined(__APPLE__)
1694 // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1695 // save the AVX512 context if we use AVX512 instructions, even the bit is not
1696 // set right now.
1697 bool HasAVX512Save = true;
1698#else
1699 // AVX512 requires additional context to be saved by the OS.
1700 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1701#endif
1702 // AMX requires additional context to be saved by the OS.
1703 const unsigned AMXBits = (1 << 17) | (1 << 18);
1704 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits);
1705
1706 Features["avx"] = HasAVXSave;
1707 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
1708 // Only enable XSAVE if OS has enabled support for saving YMM state.
1709 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1710 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
1711
1712 unsigned MaxExtLevel;
1713 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1714
1715 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1716 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1717 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);
1718 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1719 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1720 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1721 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1722 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1723 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1724 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1725 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1726
1727 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);
1728
1729 // Miscellaneous memory related features, detected by
1730 // using the 0x80000008 leaf of the CPUID instruction
1731 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1732 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1733 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1734 Features["rdpru"] = HasExtLeaf8 && ((EBX >> 4) & 1);
1735 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1736
1737 bool HasLeaf7 =
1738 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1739
1740 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1741 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1742 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1743 // AVX2 is only supported if we have the OS save support from AVX.
1744 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
1745 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1746 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
1747 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1748 // AVX512 is only supported if the OS supports the context save for it.
1749 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1750 if (Features["avx512f"])
1751 Features["evex512"] = true;
1752 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1753 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1754 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1755 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1756 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1757 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1758 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1759 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1760 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1761 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1762
1763 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1764 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1765 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);
1766 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
1767 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
1768 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
1769 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
1770 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1771 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1772 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1773 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1774 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
1775 Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker
1776 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
1777 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
1778 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
1779 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
1780
1781 Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1);
1782 Features["avx512vp2intersect"] =
1783 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save;
1784 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1);
1785 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1);
1786 // There are two CPUID leafs which information associated with the pconfig
1787 // instruction:
1788 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1789 // bit of EDX), while the EAX=0x1b leaf returns information on the
1790 // availability of specific pconfig leafs.
1791 // The target feature here only refers to the the first of these two.
1792 // Users might need to check for the availability of specific pconfig
1793 // leaves using cpuid, since that information is ignored while
1794 // detecting features using the "-march=native" flag.
1795 // For more info, see X86 ISA docs.
1796 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1797 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
1798 Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save;
1799 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
1800 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
1801 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
1802 // return all 0s for invalid subleaves so check the limit.
1803 bool HasLeaf7Subleaf1 =
1804 HasLeaf7 && EAX >= 1 &&
1805 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1806 Features["sha512"] = HasLeaf7Subleaf1 && ((EAX >> 0) & 1);
1807 Features["sm3"] = HasLeaf7Subleaf1 && ((EAX >> 1) & 1);
1808 Features["sm4"] = HasLeaf7Subleaf1 && ((EAX >> 2) & 1);
1809 Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
1810 Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
1811 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
1812 Features["amx-fp16"] = HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave;
1813 Features["cmpccxadd"] = HasLeaf7Subleaf1 && ((EAX >> 7) & 1);
1814 Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
1815 Features["avxifma"] = HasLeaf7Subleaf1 && ((EAX >> 23) & 1) && HasAVXSave;
1816 Features["avxvnniint8"] = HasLeaf7Subleaf1 && ((EDX >> 4) & 1) && HasAVXSave;
1817 Features["avxneconvert"] = HasLeaf7Subleaf1 && ((EDX >> 5) & 1) && HasAVXSave;
1818 Features["amx-complex"] = HasLeaf7Subleaf1 && ((EDX >> 8) & 1) && HasAMXSave;
1819 Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && HasAVXSave;
1820 Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
1821 Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
1822 bool HasAVX10 = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
1823 bool HasAPXF = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);
1824 Features["egpr"] = HasAPXF;
1825 Features["push2pop2"] = HasAPXF;
1826 Features["ppx"] = HasAPXF;
1827 Features["ndd"] = HasAPXF;
1828 Features["ccmp"] = HasAPXF;
1829 Features["nf"] = HasAPXF;
1830 Features["cf"] = HasAPXF;
1831 Features["zu"] = HasAPXF;
1832
1833 bool HasLeafD = MaxLevel >= 0xd &&
1834 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1835
1836 // Only enable XSAVE if OS has enabled support for saving YMM state.
1837 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1838 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1839 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1840
1841 bool HasLeaf14 = MaxLevel >= 0x14 &&
1842 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1843
1844 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1845
1846 bool HasLeaf19 =
1847 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1848 Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1);
1849
1850 bool HasLeaf24 =
1851 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);
1852
1853 int AVX10Ver = HasLeaf24 && (EBX & 0xff);
1854 int Has512Len = HasLeaf24 && ((EBX >> 18) & 1);
1855 Features["avx10.1-256"] = HasAVX10 && AVX10Ver >= 1;
1856 Features["avx10.1-512"] = HasAVX10 && AVX10Ver >= 1 && Has512Len;
1857 Features["avx10.2-256"] = HasAVX10 && AVX10Ver >= 2;
1858 Features["avx10.2-512"] = HasAVX10 && AVX10Ver >= 2 && Has512Len;
1859
1860 return Features;
1861}
1862#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1864 StringMap<bool> Features;
1865 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1866 if (!P)
1867 return Features;
1868
1870 P->getBuffer().split(Lines, "\n");
1871
1872 SmallVector<StringRef, 32> CPUFeatures;
1873
1874 // Look for the CPU features.
1875 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1876 if (Lines[I].starts_with("Features")) {
1877 Lines[I].split(CPUFeatures, ' ');
1878 break;
1879 }
1880
1881#if defined(__aarch64__)
1882 // Keep track of which crypto features we have seen
1883 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1884 uint32_t crypto = 0;
1885#endif
1886
1887 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1888 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1889#if defined(__aarch64__)
1890 .Case("asimd", "neon")
1891 .Case("fp", "fp-armv8")
1892 .Case("crc32", "crc")
1893 .Case("atomics", "lse")
1894 .Case("sve", "sve")
1895 .Case("sve2", "sve2")
1896#else
1897 .Case("half", "fp16")
1898 .Case("neon", "neon")
1899 .Case("vfpv3", "vfp3")
1900 .Case("vfpv3d16", "vfp3d16")
1901 .Case("vfpv4", "vfp4")
1902 .Case("idiva", "hwdiv-arm")
1903 .Case("idivt", "hwdiv")
1904#endif
1905 .Default("");
1906
1907#if defined(__aarch64__)
1908 // We need to check crypto separately since we need all of the crypto
1909 // extensions to enable the subtarget feature
1910 if (CPUFeatures[I] == "aes")
1911 crypto |= CAP_AES;
1912 else if (CPUFeatures[I] == "pmull")
1913 crypto |= CAP_PMULL;
1914 else if (CPUFeatures[I] == "sha1")
1915 crypto |= CAP_SHA1;
1916 else if (CPUFeatures[I] == "sha2")
1917 crypto |= CAP_SHA2;
1918#endif
1919
1920 if (LLVMFeatureStr != "")
1921 Features[LLVMFeatureStr] = true;
1922 }
1923
1924#if defined(__aarch64__)
1925 // If we have all crypto bits we can add the feature
1926 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1927 Features["crypto"] = true;
1928#endif
1929
1930 return Features;
1931}
1932#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1934 StringMap<bool> Features;
1935
1936 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1937 Features["neon"] = true;
1938 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1939 Features["crc"] = true;
1940 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1941 Features["crypto"] = true;
1942
1943 return Features;
1944}
1945#elif defined(__linux__) && defined(__loongarch__)
1946#include <sys/auxv.h>
1948 unsigned long hwcap = getauxval(AT_HWCAP);
1949 bool HasFPU = hwcap & (1UL << 3); // HWCAP_LOONGARCH_FPU
1950 uint32_t cpucfg2 = 0x2;
1951 __asm__("cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2] "+r"(cpucfg2));
1952
1953 StringMap<bool> Features;
1954
1955 Features["f"] = HasFPU && (cpucfg2 & (1U << 1)); // CPUCFG.2.FP_SP
1956 Features["d"] = HasFPU && (cpucfg2 & (1U << 2)); // CPUCFG.2.FP_DP
1957
1958 Features["lsx"] = hwcap & (1UL << 4); // HWCAP_LOONGARCH_LSX
1959 Features["lasx"] = hwcap & (1UL << 5); // HWCAP_LOONGARCH_LASX
1960 Features["lvz"] = hwcap & (1UL << 9); // HWCAP_LOONGARCH_LVZ
1961
1962 return Features;
1963}
1964#elif defined(__linux__) && defined(__riscv)
1965// struct riscv_hwprobe
1966struct RISCVHwProbe {
1967 int64_t Key;
1969};
1971 RISCVHwProbe Query[]{{/*RISCV_HWPROBE_KEY_BASE_BEHAVIOR=*/3, 0},
1972 {/*RISCV_HWPROBE_KEY_IMA_EXT_0=*/4, 0}};
1973 int Ret = syscall(/*__NR_riscv_hwprobe=*/258, /*pairs=*/Query,
1974 /*pair_count=*/std::size(Query), /*cpu_count=*/0,
1975 /*cpus=*/0, /*flags=*/0);
1976 if (Ret != 0)
1977 return {};
1978
1979 StringMap<bool> Features;
1980 uint64_t BaseMask = Query[0].Value;
1981 // Check whether RISCV_HWPROBE_BASE_BEHAVIOR_IMA is set.
1982 if (BaseMask & 1) {
1983 Features["i"] = true;
1984 Features["m"] = true;
1985 Features["a"] = true;
1986 }
1987
1988 uint64_t ExtMask = Query[1].Value;
1989 Features["f"] = ExtMask & (1 << 0); // RISCV_HWPROBE_IMA_FD
1990 Features["d"] = ExtMask & (1 << 0); // RISCV_HWPROBE_IMA_FD
1991 Features["c"] = ExtMask & (1 << 1); // RISCV_HWPROBE_IMA_C
1992 Features["v"] = ExtMask & (1 << 2); // RISCV_HWPROBE_IMA_V
1993 Features["zba"] = ExtMask & (1 << 3); // RISCV_HWPROBE_EXT_ZBA
1994 Features["zbb"] = ExtMask & (1 << 4); // RISCV_HWPROBE_EXT_ZBB
1995 Features["zbs"] = ExtMask & (1 << 5); // RISCV_HWPROBE_EXT_ZBS
1996 Features["zicboz"] = ExtMask & (1 << 6); // RISCV_HWPROBE_EXT_ZICBOZ
1997 Features["zbc"] = ExtMask & (1 << 7); // RISCV_HWPROBE_EXT_ZBC
1998 Features["zbkb"] = ExtMask & (1 << 8); // RISCV_HWPROBE_EXT_ZBKB
1999 Features["zbkc"] = ExtMask & (1 << 9); // RISCV_HWPROBE_EXT_ZBKC
2000 Features["zbkx"] = ExtMask & (1 << 10); // RISCV_HWPROBE_EXT_ZBKX
2001 Features["zknd"] = ExtMask & (1 << 11); // RISCV_HWPROBE_EXT_ZKND
2002 Features["zkne"] = ExtMask & (1 << 12); // RISCV_HWPROBE_EXT_ZKNE
2003 Features["zknh"] = ExtMask & (1 << 13); // RISCV_HWPROBE_EXT_ZKNH
2004 Features["zksed"] = ExtMask & (1 << 14); // RISCV_HWPROBE_EXT_ZKSED
2005 Features["zksh"] = ExtMask & (1 << 15); // RISCV_HWPROBE_EXT_ZKSH
2006 Features["zkt"] = ExtMask & (1 << 16); // RISCV_HWPROBE_EXT_ZKT
2007 Features["zvbb"] = ExtMask & (1 << 17); // RISCV_HWPROBE_EXT_ZVBB
2008 Features["zvbc"] = ExtMask & (1 << 18); // RISCV_HWPROBE_EXT_ZVBC
2009 Features["zvkb"] = ExtMask & (1 << 19); // RISCV_HWPROBE_EXT_ZVKB
2010 Features["zvkg"] = ExtMask & (1 << 20); // RISCV_HWPROBE_EXT_ZVKG
2011 Features["zvkned"] = ExtMask & (1 << 21); // RISCV_HWPROBE_EXT_ZVKNED
2012 Features["zvknha"] = ExtMask & (1 << 22); // RISCV_HWPROBE_EXT_ZVKNHA
2013 Features["zvknhb"] = ExtMask & (1 << 23); // RISCV_HWPROBE_EXT_ZVKNHB
2014 Features["zvksed"] = ExtMask & (1 << 24); // RISCV_HWPROBE_EXT_ZVKSED
2015 Features["zvksh"] = ExtMask & (1 << 25); // RISCV_HWPROBE_EXT_ZVKSH
2016 Features["zvkt"] = ExtMask & (1 << 26); // RISCV_HWPROBE_EXT_ZVKT
2017 Features["zfh"] = ExtMask & (1 << 27); // RISCV_HWPROBE_EXT_ZFH
2018 Features["zfhmin"] = ExtMask & (1 << 28); // RISCV_HWPROBE_EXT_ZFHMIN
2019 Features["zihintntl"] = ExtMask & (1 << 29); // RISCV_HWPROBE_EXT_ZIHINTNTL
2020 Features["zvfh"] = ExtMask & (1 << 30); // RISCV_HWPROBE_EXT_ZVFH
2021 Features["zvfhmin"] = ExtMask & (1ULL << 31); // RISCV_HWPROBE_EXT_ZVFHMIN
2022 Features["zfa"] = ExtMask & (1ULL << 32); // RISCV_HWPROBE_EXT_ZFA
2023 Features["ztso"] = ExtMask & (1ULL << 33); // RISCV_HWPROBE_EXT_ZTSO
2024 // TODO: Re-enable zacas when it is marked non-experimental again.
2025 // Features["zacas"] = ExtMask & (1ULL << 34); // RISCV_HWPROBE_EXT_ZACAS
2026 Features["zicond"] = ExtMask & (1ULL << 35); // RISCV_HWPROBE_EXT_ZICOND
2027 Features["zihintpause"] =
2028 ExtMask & (1ULL << 36); // RISCV_HWPROBE_EXT_ZIHINTPAUSE
2029
2030 // TODO: set unaligned-scalar-mem if RISCV_HWPROBE_KEY_MISALIGNED_PERF returns
2031 // RISCV_HWPROBE_MISALIGNED_FAST.
2032
2033 return Features;
2034}
2035#else
2037#endif
2038
2039#if __APPLE__
2040/// \returns the \p triple, but with the Host's arch spliced in.
2041static Triple withHostArch(Triple T) {
2042#if defined(__arm__)
2043 T.setArch(Triple::arm);
2044 T.setArchName("arm");
2045#elif defined(__arm64e__)
2047 T.setArchName("arm64e");
2048#elif defined(__aarch64__)
2049 T.setArch(Triple::aarch64);
2050 T.setArchName("arm64");
2051#elif defined(__x86_64h__)
2052 T.setArch(Triple::x86_64);
2053 T.setArchName("x86_64h");
2054#elif defined(__x86_64__)
2055 T.setArch(Triple::x86_64);
2056 T.setArchName("x86_64");
2057#elif defined(__i386__)
2058 T.setArch(Triple::x86);
2059 T.setArchName("i386");
2060#elif defined(__powerpc__)
2061 T.setArch(Triple::ppc);
2062 T.setArchName("powerpc");
2063#else
2064# error "Unimplemented host arch fixup"
2065#endif
2066 return T;
2067}
2068#endif
2069
2071 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
2072 Triple PT(Triple::normalize(TargetTripleString));
2073
2074#if __APPLE__
2075 /// In Universal builds, LLVM_HOST_TRIPLE will have the wrong arch in one of
2076 /// the slices. This fixes that up.
2077 PT = withHostArch(PT);
2078#endif
2079
2080 if (sizeof(void *) == 8 && PT.isArch32Bit())
2081 PT = PT.get64BitArchVariant();
2082 if (sizeof(void *) == 4 && PT.isArch64Bit())
2083 PT = PT.get32BitArchVariant();
2084
2085 return PT.str();
2086}
2087
2089#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
2090 std::string CPU = std::string(sys::getHostCPUName());
2091 if (CPU == "generic")
2092 CPU = "(unknown)";
2093 OS << " Default target: " << sys::getDefaultTargetTriple() << '\n'
2094 << " Host CPU: " << CPU << '\n';
2095#endif
2096}
This file defines the StringMap class.
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:203
Given that RA is a live value
T Content
std::string Name
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
Definition: Host.cpp:70
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define P(N)
raw_pwrite_stream & OS
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
DEMANGLE_NAMESPACE_BEGIN bool starts_with(std::string_view self, char C) noexcept
Represents either an error or a value T.
Definition: ErrorOr.h:56
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
size_t size() const
Definition: SmallVector.h:92
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1210
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
Definition: StringMap.h:128
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:685
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
iterator begin() const
Definition: StringRef.h:111
iterator end() const
Definition: StringRef.h:113
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:262
static constexpr size_t npos
Definition: StringRef.h:52
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
StringSwitch & StartsWith(StringLiteral S, T Value)
Definition: StringSwitch.h:83
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
Definition: Triple.cpp:1663
std::string normalize() const
Return the normalized form of this triple's string.
Definition: Triple.h:366
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
Definition: Triple.cpp:1742
const std::string & str() const
Definition: Triple.h:440
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1651
@ AArch64SubArch_arm64e
Definition: Triple.h:147
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1655
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
Key
PAL metadata keys.
@ CPU_SUBTYPE_POWERPC_970
Definition: MachO.h:1663
@ CPU_SUBTYPE_POWERPC_604e
Definition: MachO.h:1658
@ CPU_SUBTYPE_POWERPC_603e
Definition: MachO.h:1655
@ CPU_SUBTYPE_POWERPC_7400
Definition: MachO.h:1661
@ CPU_SUBTYPE_POWERPC_604
Definition: MachO.h:1657
@ CPU_SUBTYPE_POWERPC_750
Definition: MachO.h:1660
@ CPU_SUBTYPE_POWERPC_601
Definition: MachO.h:1652
@ CPU_SUBTYPE_POWERPC_620
Definition: MachO.h:1659
@ CPU_SUBTYPE_POWERPC_603ev
Definition: MachO.h:1656
@ CPU_SUBTYPE_POWERPC_603
Definition: MachO.h:1654
@ CPU_SUBTYPE_POWERPC_7450
Definition: MachO.h:1662
@ CPU_SUBTYPE_POWERPC_602
Definition: MachO.h:1653
Helper functions to extract CPU details from CPUID on x86.
Definition: Host.h:71
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
Definition: Host.cpp:1647
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
Definition: Host.cpp:399
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
Definition: Host.cpp:81
StringRef getHostCPUNameForBPF()
Definition: Host.cpp:464
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
Definition: Host.cpp:165
StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
Definition: Host.cpp:444
StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
const StringMap< bool, MallocAllocator > getHostCPUFeatures()
getHostCPUFeatures - Get the LLVM names for the host CPU features.
Definition: Host.cpp:2036
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
Definition: Host.cpp:1641
void printDefaultTargetAndDetectedCPU(raw_ostream &OS)
This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...
Definition: Host.cpp:2088
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
Definition: Host.cpp:2070
std::string getDefaultTargetTriple()
getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Length
Definition: DWP.cpp:480
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.