18#include "llvm/Config/llvm-config.h"
40#include <mach/host_info.h>
42#include <mach/mach_host.h>
43#include <mach/machine.h>
45#include <sys/sysctl.h>
48#include <sys/systemcfg.h>
50#if defined(__sun__) && defined(__svr4__)
53#if defined(__GNUC__) || defined(__clang__)
54#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
59#define DEBUG_TYPE "host-detection"
69static std::unique_ptr<llvm::MemoryBuffer>
71 const char *CPUInfoFile =
"/proc/cpuinfo";
72 if (
const char *CpuinfoIntercept = std::getenv(
"LLVM_CPUINFO"))
73 CPUInfoFile = CpuinfoIntercept;
77 if (std::error_code EC = Text.getError()) {
78 llvm::errs() <<
"Can't read " << CPUInfoFile <<
": " << EC.message()
82 return std::move(*Text);
89 const char *
generic =
"generic";
103 while (CIP < CPUInfoEnd && CPUStart ==
nullptr) {
104 if (CIP < CPUInfoEnd && *CIP ==
'\n')
107 if (CIP < CPUInfoEnd && *CIP ==
'c') {
109 if (CIP < CPUInfoEnd && *CIP ==
'p') {
111 if (CIP < CPUInfoEnd && *CIP ==
'u') {
113 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
116 if (CIP < CPUInfoEnd && *CIP ==
':') {
118 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
121 if (CIP < CPUInfoEnd) {
123 while (CIP < CPUInfoEnd && (*CIP !=
' ' && *CIP !=
'\t' &&
124 *CIP !=
',' && *CIP !=
'\n'))
126 CPULen = CIP - CPUStart;
133 if (CPUStart ==
nullptr)
134 while (CIP < CPUInfoEnd && *CIP !=
'\n')
138 if (CPUStart ==
nullptr)
142 .
Case(
"604e",
"604e")
144 .
Case(
"7400",
"7400")
145 .
Case(
"7410",
"7400")
146 .
Case(
"7447",
"7400")
147 .
Case(
"7455",
"7450")
149 .
Case(
"POWER4",
"970")
150 .
Case(
"PPC970FX",
"970")
151 .
Case(
"PPC970MP",
"970")
153 .
Case(
"POWER5",
"g5")
155 .
Case(
"POWER6",
"pwr6")
156 .
Case(
"POWER7",
"pwr7")
157 .
Case(
"POWER8",
"pwr8")
158 .
Case(
"POWER8E",
"pwr8")
159 .
Case(
"POWER8NVL",
"pwr8")
160 .
Case(
"POWER9",
"pwr9")
161 .
Case(
"POWER10",
"pwr10")
162 .
Case(
"POWER11",
"pwr11")
176 ProcCpuinfoContent.
split(Lines,
'\n');
182 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
184 Implementer = Lines[
I].substr(15).ltrim(
"\t :");
186 Hardware = Lines[
I].substr(8).ltrim(
"\t :");
188 Part = Lines[
I].substr(8).ltrim(
"\t :");
191 if (Implementer ==
"0x41") {
204 .
Case(
"0x926",
"arm926ej-s")
205 .
Case(
"0xb02",
"mpcore")
206 .
Case(
"0xb36",
"arm1136j-s")
207 .
Case(
"0xb56",
"arm1156t2-s")
208 .
Case(
"0xb76",
"arm1176jz-s")
209 .
Case(
"0xc05",
"cortex-a5")
210 .
Case(
"0xc07",
"cortex-a7")
211 .
Case(
"0xc08",
"cortex-a8")
212 .
Case(
"0xc09",
"cortex-a9")
213 .
Case(
"0xc0f",
"cortex-a15")
214 .
Case(
"0xc0e",
"cortex-a17")
215 .
Case(
"0xc20",
"cortex-m0")
216 .
Case(
"0xc23",
"cortex-m3")
217 .
Case(
"0xc24",
"cortex-m4")
218 .
Case(
"0xc27",
"cortex-m7")
219 .
Case(
"0xd20",
"cortex-m23")
220 .
Case(
"0xd21",
"cortex-m33")
221 .
Case(
"0xd24",
"cortex-m52")
222 .
Case(
"0xd22",
"cortex-m55")
223 .
Case(
"0xd23",
"cortex-m85")
224 .
Case(
"0xc18",
"cortex-r8")
225 .
Case(
"0xd13",
"cortex-r52")
226 .
Case(
"0xd16",
"cortex-r52plus")
227 .
Case(
"0xd15",
"cortex-r82")
228 .
Case(
"0xd14",
"cortex-r82ae")
229 .
Case(
"0xd02",
"cortex-a34")
230 .
Case(
"0xd04",
"cortex-a35")
231 .
Case(
"0xd03",
"cortex-a53")
232 .
Case(
"0xd05",
"cortex-a55")
233 .
Case(
"0xd46",
"cortex-a510")
234 .
Case(
"0xd80",
"cortex-a520")
235 .
Case(
"0xd88",
"cortex-a520ae")
236 .
Case(
"0xd07",
"cortex-a57")
237 .
Case(
"0xd06",
"cortex-a65")
238 .
Case(
"0xd43",
"cortex-a65ae")
239 .
Case(
"0xd08",
"cortex-a72")
240 .
Case(
"0xd09",
"cortex-a73")
241 .
Case(
"0xd0a",
"cortex-a75")
242 .
Case(
"0xd0b",
"cortex-a76")
243 .
Case(
"0xd0e",
"cortex-a76ae")
244 .
Case(
"0xd0d",
"cortex-a77")
245 .
Case(
"0xd41",
"cortex-a78")
246 .
Case(
"0xd42",
"cortex-a78ae")
247 .
Case(
"0xd4b",
"cortex-a78c")
248 .
Case(
"0xd47",
"cortex-a710")
249 .
Case(
"0xd4d",
"cortex-a715")
250 .
Case(
"0xd81",
"cortex-a720")
251 .
Case(
"0xd89",
"cortex-a720ae")
252 .
Case(
"0xd87",
"cortex-a725")
253 .
Case(
"0xd44",
"cortex-x1")
254 .
Case(
"0xd4c",
"cortex-x1c")
255 .
Case(
"0xd48",
"cortex-x2")
256 .
Case(
"0xd4e",
"cortex-x3")
257 .
Case(
"0xd82",
"cortex-x4")
258 .
Case(
"0xd85",
"cortex-x925")
259 .
Case(
"0xd4a",
"neoverse-e1")
260 .
Case(
"0xd0c",
"neoverse-n1")
261 .
Case(
"0xd49",
"neoverse-n2")
262 .
Case(
"0xd8e",
"neoverse-n3")
263 .
Case(
"0xd40",
"neoverse-v1")
264 .
Case(
"0xd4f",
"neoverse-v2")
265 .
Case(
"0xd84",
"neoverse-v3")
266 .
Case(
"0xd83",
"neoverse-v3ae")
270 if (Implementer ==
"0x42" || Implementer ==
"0x43") {
272 .
Case(
"0x516",
"thunderx2t99")
273 .
Case(
"0x0516",
"thunderx2t99")
274 .
Case(
"0xaf",
"thunderx2t99")
275 .
Case(
"0x0af",
"thunderx2t99")
276 .
Case(
"0xa1",
"thunderxt88")
277 .
Case(
"0x0a1",
"thunderxt88")
281 if (Implementer ==
"0x46") {
283 .
Case(
"0x001",
"a64fx")
284 .
Case(
"0x003",
"fujitsu-monaka")
288 if (Implementer ==
"0x4e") {
290 .
Case(
"0x004",
"carmel")
294 if (Implementer ==
"0x48")
299 .
Case(
"0xd01",
"tsv110")
302 if (Implementer ==
"0x51")
307 .
Case(
"0x06f",
"krait")
308 .
Case(
"0x201",
"kryo")
309 .
Case(
"0x205",
"kryo")
310 .
Case(
"0x211",
"kryo")
311 .
Case(
"0x800",
"cortex-a73")
312 .
Case(
"0x801",
"cortex-a73")
313 .
Case(
"0x802",
"cortex-a75")
314 .
Case(
"0x803",
"cortex-a75")
315 .
Case(
"0x804",
"cortex-a76")
316 .
Case(
"0x805",
"cortex-a76")
317 .
Case(
"0xc00",
"falkor")
318 .
Case(
"0xc01",
"saphira")
319 .
Case(
"0x001",
"oryon-1")
321 if (Implementer ==
"0x53") {
324 unsigned Variant = 0, Part = 0;
329 if (
I.consume_front(
"CPU variant"))
330 I.ltrim(
"\t :").getAsInteger(0, Variant);
335 if (
I.consume_front(
"CPU part"))
336 I.ltrim(
"\t :").getAsInteger(0, Part);
338 unsigned Exynos = (Variant << 12) | Part;
350 if (Implementer ==
"0x61") {
352 .
Case(
"0x020",
"apple-m1")
353 .
Case(
"0x021",
"apple-m1")
354 .
Case(
"0x022",
"apple-m1")
355 .
Case(
"0x023",
"apple-m1")
356 .
Case(
"0x024",
"apple-m1")
357 .
Case(
"0x025",
"apple-m1")
358 .
Case(
"0x028",
"apple-m1")
359 .
Case(
"0x029",
"apple-m1")
360 .
Case(
"0x030",
"apple-m2")
361 .
Case(
"0x031",
"apple-m2")
362 .
Case(
"0x032",
"apple-m2")
363 .
Case(
"0x033",
"apple-m2")
364 .
Case(
"0x034",
"apple-m2")
365 .
Case(
"0x035",
"apple-m2")
366 .
Case(
"0x038",
"apple-m2")
367 .
Case(
"0x039",
"apple-m2")
368 .
Case(
"0x049",
"apple-m3")
369 .
Case(
"0x048",
"apple-m3")
373 if (Implementer ==
"0x63") {
375 .
Case(
"0x132",
"star-mc1")
379 if (Implementer ==
"0x6d") {
382 .
Case(
"0xd49",
"neoverse-n2")
386 if (Implementer ==
"0xc0") {
388 .
Case(
"0xac3",
"ampere1")
389 .
Case(
"0xac4",
"ampere1a")
390 .
Case(
"0xac5",
"ampere1b")
398StringRef getCPUNameFromS390Model(
unsigned int Id,
bool HaveVectorSupport) {
418 return HaveVectorSupport?
"z13" :
"zEC12";
421 return HaveVectorSupport?
"z14" :
"zEC12";
424 return HaveVectorSupport?
"z15" :
"zEC12";
427 return HaveVectorSupport?
"z16" :
"zEC12";
431 return HaveVectorSupport?
"arch15" :
"zEC12";
442 ProcCpuinfoContent.
split(Lines,
'\n');
446 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I)
448 size_t Pos = Lines[
I].find(
':');
450 Lines[
I].drop_front(Pos + 1).split(CPUFeatures,
' ');
458 bool HaveVectorSupport =
false;
459 for (
unsigned I = 0, E = CPUFeatures.
size();
I != E; ++
I) {
460 if (CPUFeatures[
I] ==
"vx")
461 HaveVectorSupport =
true;
465 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
467 size_t Pos = Lines[
I].find(
"machine = ");
469 Pos +=
sizeof(
"machine = ") - 1;
471 if (!Lines[
I].drop_front(Pos).getAsInteger(10, Id))
472 return getCPUNameFromS390Model(Id, HaveVectorSupport);
484 ProcCpuinfoContent.
split(Lines,
'\n');
488 for (
unsigned I = 0, E = Lines.size();
I != E; ++
I) {
490 UArch = Lines[
I].substr(5).ltrim(
"\t :");
496 .
Case(
"eswin,eic770x",
"sifive-p550")
497 .
Case(
"sifive,u74-mc",
"sifive-u74")
498 .
Case(
"sifive,bullet0",
"sifive-u74")
503#if !defined(__linux__) || !defined(__x86_64__)
506 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
508 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
510 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
512 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
514 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
516 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
518 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
520 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
522 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
524 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
526 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
528 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
530 struct bpf_prog_load_attr {
546 int fd = syscall(321 , 5 , &attr,
554 memset(&attr, 0,
sizeof(attr));
559 fd = syscall(321 , 5 , &attr,
sizeof(attr));
568#if defined(__i386__) || defined(_M_IX86) || defined(__x86_64__) || \
573static bool getX86CpuIDAndInfo(
unsigned value,
unsigned *rEAX,
unsigned *rEBX,
574 unsigned *rECX,
unsigned *rEDX) {
575#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
576 return !__get_cpuid(
value, rEAX, rEBX, rECX, rEDX);
577#elif defined(_MSC_VER)
580 __cpuid(registers,
value);
581 *rEAX = registers[0];
582 *rEBX = registers[1];
583 *rECX = registers[2];
584 *rEDX = registers[3];
596VendorSignatures getVendorSignature(
unsigned *MaxLeaf) {
597 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
598 if (MaxLeaf ==
nullptr)
603 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
604 return VendorSignatures::UNKNOWN;
607 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
608 return VendorSignatures::GENUINE_INTEL;
611 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
612 return VendorSignatures::AUTHENTIC_AMD;
614 return VendorSignatures::UNKNOWN;
627static bool getX86CpuIDAndInfoEx(
unsigned value,
unsigned subleaf,
628 unsigned *rEAX,
unsigned *rEBX,
unsigned *rECX,
634#if (defined(__i386__) || defined(__x86_64__)) && !defined(_MSC_VER)
635 return !__get_cpuid_count(
value, subleaf, rEAX, rEBX, rECX, rEDX);
636#elif defined(_MSC_VER)
638 __cpuidex(registers,
value, subleaf);
639 *rEAX = registers[0];
640 *rEBX = registers[1];
641 *rECX = registers[2];
642 *rEDX = registers[3];
650static bool getX86XCR0(
unsigned *rEAX,
unsigned *rEDX) {
654#if defined(__GNUC__) || defined(__clang__)
658 __asm__(
".byte 0x0f, 0x01, 0xd0" :
"=a"(*rEAX),
"=d"(*rEDX) :
"c"(0));
660#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
661 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
670static void detectX86FamilyModel(
unsigned EAX,
unsigned *Family,
672 *Family = (
EAX >> 8) & 0xf;
674 if (*Family == 6 || *Family == 0xf) {
677 *Family += (
EAX >> 20) & 0xff;
683#define testFeature(F) (Features[F / 32] & (1 << (F % 32))) != 0
685static StringRef getIntelProcessorTypeAndSubtype(
unsigned Family,
687 const unsigned *Features,
700 if (testFeature(X86::FEATURE_MMX)) {
716 *
Type = X86::INTEL_CORE2;
725 *
Type = X86::INTEL_CORE2;
734 *
Type = X86::INTEL_COREI7;
735 *Subtype = X86::INTEL_COREI7_NEHALEM;
742 *
Type = X86::INTEL_COREI7;
743 *Subtype = X86::INTEL_COREI7_WESTMERE;
749 *
Type = X86::INTEL_COREI7;
750 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
755 *
Type = X86::INTEL_COREI7;
756 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
765 *
Type = X86::INTEL_COREI7;
766 *Subtype = X86::INTEL_COREI7_HASWELL;
775 *
Type = X86::INTEL_COREI7;
776 *Subtype = X86::INTEL_COREI7_BROADWELL;
787 *
Type = X86::INTEL_COREI7;
788 *Subtype = X86::INTEL_COREI7_SKYLAKE;
794 *
Type = X86::INTEL_COREI7;
795 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
800 *
Type = X86::INTEL_COREI7;
801 if (testFeature(X86::FEATURE_AVX512BF16)) {
803 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
804 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
806 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
808 CPU =
"skylake-avx512";
809 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
816 *
Type = X86::INTEL_COREI7;
817 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
823 CPU =
"icelake-client";
824 *
Type = X86::INTEL_COREI7;
825 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
832 *
Type = X86::INTEL_COREI7;
833 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
840 *
Type = X86::INTEL_COREI7;
841 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
847 *
Type = X86::INTEL_COREI7;
848 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
856 *
Type = X86::INTEL_COREI7;
857 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
864 *
Type = X86::INTEL_COREI7;
865 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
873 *
Type = X86::INTEL_COREI7;
874 *Subtype = X86::INTEL_COREI7_ARROWLAKE;
880 *
Type = X86::INTEL_COREI7;
881 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
887 *
Type = X86::INTEL_COREI7;
888 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
894 *
Type = X86::INTEL_COREI7;
895 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;
900 CPU =
"graniterapids";
901 *
Type = X86::INTEL_COREI7;
902 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
907 CPU =
"graniterapids-d";
908 *
Type = X86::INTEL_COREI7;
909 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
915 CPU =
"icelake-server";
916 *
Type = X86::INTEL_COREI7;
917 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
922 CPU =
"emeraldrapids";
923 *
Type = X86::INTEL_COREI7;
924 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
929 CPU =
"sapphirerapids";
930 *
Type = X86::INTEL_COREI7;
931 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
940 *
Type = X86::INTEL_BONNELL;
951 *
Type = X86::INTEL_SILVERMONT;
957 *
Type = X86::INTEL_GOLDMONT;
960 CPU =
"goldmont-plus";
961 *
Type = X86::INTEL_GOLDMONT_PLUS;
968 *
Type = X86::INTEL_TREMONT;
973 CPU =
"sierraforest";
974 *
Type = X86::INTEL_SIERRAFOREST;
980 *
Type = X86::INTEL_GRANDRIDGE;
985 CPU =
"clearwaterforest";
986 *
Type = X86::INTEL_CLEARWATERFOREST;
992 *
Type = X86::INTEL_KNL;
996 *
Type = X86::INTEL_KNM;
1003 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
1005 }
else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
1006 CPU =
"icelake-client";
1007 }
else if (testFeature(X86::FEATURE_AVX512VBMI)) {
1009 }
else if (testFeature(X86::FEATURE_AVX512BF16)) {
1011 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
1012 CPU =
"cascadelake";
1013 }
else if (testFeature(X86::FEATURE_AVX512VL)) {
1014 CPU =
"skylake-avx512";
1015 }
else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
1016 if (testFeature(X86::FEATURE_SHA))
1020 }
else if (testFeature(X86::FEATURE_ADX)) {
1022 }
else if (testFeature(X86::FEATURE_AVX2)) {
1024 }
else if (testFeature(X86::FEATURE_AVX)) {
1025 CPU =
"sandybridge";
1026 }
else if (testFeature(X86::FEATURE_SSE4_2)) {
1027 if (testFeature(X86::FEATURE_MOVBE))
1031 }
else if (testFeature(X86::FEATURE_SSE4_1)) {
1033 }
else if (testFeature(X86::FEATURE_SSSE3)) {
1034 if (testFeature(X86::FEATURE_MOVBE))
1038 }
else if (testFeature(X86::FEATURE_64BIT)) {
1040 }
else if (testFeature(X86::FEATURE_SSE3)) {
1042 }
else if (testFeature(X86::FEATURE_SSE2)) {
1044 }
else if (testFeature(X86::FEATURE_SSE)) {
1046 }
else if (testFeature(X86::FEATURE_MMX)) {
1055 if (testFeature(X86::FEATURE_64BIT)) {
1059 if (testFeature(X86::FEATURE_SSE3)) {
1070 CPU =
"diamondrapids";
1071 *
Type = X86::INTEL_COREI7;
1072 *Subtype = X86::INTEL_COREI7_DIAMONDRAPIDS;
1086static const char *getAMDProcessorTypeAndSubtype(
unsigned Family,
1088 const unsigned *Features,
1090 unsigned *Subtype) {
1091 const char *CPU = 0;
1117 if (testFeature(X86::FEATURE_SSE)) {
1124 if (testFeature(X86::FEATURE_SSE3)) {
1133 *
Type = X86::AMDFAM10H;
1136 *Subtype = X86::AMDFAM10H_BARCELONA;
1139 *Subtype = X86::AMDFAM10H_SHANGHAI;
1142 *Subtype = X86::AMDFAM10H_ISTANBUL;
1148 *
Type = X86::AMD_BTVER1;
1152 *
Type = X86::AMDFAM15H;
1153 if (Model >= 0x60 && Model <= 0x7f) {
1155 *Subtype = X86::AMDFAM15H_BDVER4;
1158 if (Model >= 0x30 && Model <= 0x3f) {
1160 *Subtype = X86::AMDFAM15H_BDVER3;
1163 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
1165 *Subtype = X86::AMDFAM15H_BDVER2;
1168 if (Model <= 0x0f) {
1169 *Subtype = X86::AMDFAM15H_BDVER1;
1175 *
Type = X86::AMD_BTVER2;
1179 *
Type = X86::AMDFAM17H;
1180 if ((Model >= 0x30 && Model <= 0x3f) || (Model == 0x47) ||
1181 (Model >= 0x60 && Model <= 0x67) || (Model >= 0x68 && Model <= 0x6f) ||
1182 (Model >= 0x70 && Model <= 0x7f) || (Model >= 0x84 && Model <= 0x87) ||
1183 (Model >= 0x90 && Model <= 0x97) || (Model >= 0x98 && Model <= 0x9f) ||
1184 (Model >= 0xa0 && Model <= 0xaf)) {
1195 *Subtype = X86::AMDFAM17H_ZNVER2;
1198 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x20 && Model <= 0x2f)) {
1202 *Subtype = X86::AMDFAM17H_ZNVER1;
1208 *
Type = X86::AMDFAM19H;
1209 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x2f) ||
1210 (Model >= 0x30 && Model <= 0x3f) || (Model >= 0x40 && Model <= 0x4f) ||
1211 (Model >= 0x50 && Model <= 0x5f)) {
1217 *Subtype = X86::AMDFAM19H_ZNVER3;
1220 if ((Model >= 0x10 && Model <= 0x1f) || (Model >= 0x60 && Model <= 0x6f) ||
1221 (Model >= 0x70 && Model <= 0x77) || (Model >= 0x78 && Model <= 0x7f) ||
1222 (Model >= 0xa0 && Model <= 0xaf)) {
1229 *Subtype = X86::AMDFAM19H_ZNVER4;
1235 *
Type = X86::AMDFAM1AH;
1236 if (Model <= 0x77) {
1247 *Subtype = X86::AMDFAM1AH_ZNVER5;
1261static void getAvailableFeatures(
unsigned ECX,
unsigned EDX,
unsigned MaxLeaf,
1262 unsigned *Features) {
1265 auto setFeature = [&](
unsigned F) {
1266 Features[
F / 32] |= 1U << (
F % 32);
1269 if ((EDX >> 15) & 1)
1270 setFeature(X86::FEATURE_CMOV);
1271 if ((EDX >> 23) & 1)
1272 setFeature(X86::FEATURE_MMX);
1273 if ((EDX >> 25) & 1)
1274 setFeature(X86::FEATURE_SSE);
1275 if ((EDX >> 26) & 1)
1276 setFeature(X86::FEATURE_SSE2);
1279 setFeature(X86::FEATURE_SSE3);
1281 setFeature(X86::FEATURE_PCLMUL);
1283 setFeature(X86::FEATURE_SSSE3);
1284 if ((ECX >> 12) & 1)
1285 setFeature(X86::FEATURE_FMA);
1286 if ((ECX >> 19) & 1)
1287 setFeature(X86::FEATURE_SSE4_1);
1288 if ((ECX >> 20) & 1) {
1289 setFeature(X86::FEATURE_SSE4_2);
1290 setFeature(X86::FEATURE_CRC32);
1292 if ((ECX >> 23) & 1)
1293 setFeature(X86::FEATURE_POPCNT);
1294 if ((ECX >> 25) & 1)
1295 setFeature(X86::FEATURE_AES);
1297 if ((ECX >> 22) & 1)
1298 setFeature(X86::FEATURE_MOVBE);
1303 const unsigned AVXBits = (1 << 27) | (1 << 28);
1304 bool HasAVX = ((
ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1305 ((
EAX & 0x6) == 0x6);
1306#if defined(__APPLE__)
1310 bool HasAVX512Save =
true;
1313 bool HasAVX512Save = HasAVX && ((
EAX & 0xe0) == 0xe0);
1317 setFeature(X86::FEATURE_AVX);
1320 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1322 if (HasLeaf7 && ((EBX >> 3) & 1))
1323 setFeature(X86::FEATURE_BMI);
1324 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1325 setFeature(X86::FEATURE_AVX2);
1326 if (HasLeaf7 && ((EBX >> 8) & 1))
1327 setFeature(X86::FEATURE_BMI2);
1328 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) {
1329 setFeature(X86::FEATURE_AVX512F);
1330 setFeature(X86::FEATURE_EVEX512);
1332 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1333 setFeature(X86::FEATURE_AVX512DQ);
1334 if (HasLeaf7 && ((EBX >> 19) & 1))
1335 setFeature(X86::FEATURE_ADX);
1336 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1337 setFeature(X86::FEATURE_AVX512IFMA);
1338 if (HasLeaf7 && ((EBX >> 23) & 1))
1339 setFeature(X86::FEATURE_CLFLUSHOPT);
1340 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1341 setFeature(X86::FEATURE_AVX512CD);
1342 if (HasLeaf7 && ((EBX >> 29) & 1))
1343 setFeature(X86::FEATURE_SHA);
1344 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1345 setFeature(X86::FEATURE_AVX512BW);
1346 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1347 setFeature(X86::FEATURE_AVX512VL);
1349 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1350 setFeature(X86::FEATURE_AVX512VBMI);
1351 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1352 setFeature(X86::FEATURE_AVX512VBMI2);
1353 if (HasLeaf7 && ((ECX >> 8) & 1))
1354 setFeature(X86::FEATURE_GFNI);
1355 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1356 setFeature(X86::FEATURE_VPCLMULQDQ);
1357 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1358 setFeature(X86::FEATURE_AVX512VNNI);
1359 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1360 setFeature(X86::FEATURE_AVX512BITALG);
1361 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1362 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1364 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1365 setFeature(X86::FEATURE_AVX5124VNNIW);
1366 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1367 setFeature(X86::FEATURE_AVX5124FMAPS);
1368 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1369 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1373 bool HasLeaf7Subleaf1 =
1374 HasLeaf7 &&
EAX >= 1 &&
1375 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1376 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1377 setFeature(X86::FEATURE_AVX512BF16);
1379 unsigned MaxExtLevel;
1380 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1382 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1383 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1384 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1385 setFeature(X86::FEATURE_SSE4_A);
1386 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1387 setFeature(X86::FEATURE_XOP);
1388 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1389 setFeature(X86::FEATURE_FMA4);
1391 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1392 setFeature(X86::FEATURE_64BIT);
1396 unsigned MaxLeaf = 0;
1398 if (Vendor == VendorSignatures::UNKNOWN)
1402 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1404 unsigned Family = 0,
Model = 0;
1406 detectX86FamilyModel(EAX, &Family, &Model);
1407 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1412 unsigned Subtype = 0;
1416 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1417 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1419 }
else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1420 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1430#elif defined(__APPLE__) && defined(__powerpc__)
1432 host_basic_info_data_t hostInfo;
1433 mach_msg_type_number_t infoCount;
1435 infoCount = HOST_BASIC_INFO_COUNT;
1436 mach_port_t hostPort = mach_host_self();
1437 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1439 mach_port_deallocate(mach_task_self(), hostPort);
1441 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1444 switch (hostInfo.cpu_subtype) {
1474#elif defined(__linux__) && defined(__powerpc__)
1478 return detail::getHostCPUNameForPowerPC(
Content);
1480#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1484 return detail::getHostCPUNameForARM(
Content);
1486#elif defined(__linux__) && defined(__s390x__)
1490 return detail::getHostCPUNameForS390x(
Content);
1492#elif defined(__MVS__)
1497 int *StartToCVTOffset =
reinterpret_cast<int *
>(0x10);
1500 int ReadValue = *StartToCVTOffset;
1502 ReadValue = (ReadValue & 0x7FFFFFFF);
1503 char *CVT =
reinterpret_cast<char *
>(ReadValue);
1508 Id = decodePackedBCD<uint16_t>(Id,
false);
1512 bool HaveVectorSupport = CVT[244] & 0x80;
1513 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1515#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1520#define CPUFAMILY_UNKNOWN 0
1521#define CPUFAMILY_ARM_9 0xe73283ae
1522#define CPUFAMILY_ARM_11 0x8ff620d8
1523#define CPUFAMILY_ARM_XSCALE 0x53b005f5
1524#define CPUFAMILY_ARM_12 0xbd1b0ae9
1525#define CPUFAMILY_ARM_13 0x0cc90e64
1526#define CPUFAMILY_ARM_14 0x96077ef1
1527#define CPUFAMILY_ARM_15 0xa8511bca
1528#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1529#define CPUFAMILY_ARM_CYCLONE 0x37a09642
1530#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1531#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1532#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1533#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1534#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1535#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1536#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1537#define CPUFAMILY_ARM_BLIZZARD_AVALANCHE 0xda33d83d
1538#define CPUFAMILY_ARM_EVEREST_SAWTOOTH 0x8765edea
1539#define CPUFAMILY_ARM_IBIZA 0xfa33415e
1540#define CPUFAMILY_ARM_PALMA 0x72015832
1541#define CPUFAMILY_ARM_COLL 0x2876f5b5
1542#define CPUFAMILY_ARM_LOBOS 0x5f4dea93
1543#define CPUFAMILY_ARM_DONAN 0x6f5129ac
1544#define CPUFAMILY_ARM_BRAVA 0x17d5b93a
1545#define CPUFAMILY_ARM_TAHITI 0x75d4acb9
1546#define CPUFAMILY_ARM_TUPAI 0x204526d0
1550 size_t Length =
sizeof(Family);
1551 sysctlbyname(
"hw.cpufamily", &Family, &
Length, NULL, 0);
1563 case CPUFAMILY_UNKNOWN:
1565 case CPUFAMILY_ARM_9:
1567 case CPUFAMILY_ARM_11:
1568 return "arm1136jf-s";
1569 case CPUFAMILY_ARM_XSCALE:
1571 case CPUFAMILY_ARM_12:
1573 case CPUFAMILY_ARM_13:
1575 case CPUFAMILY_ARM_14:
1577 case CPUFAMILY_ARM_15:
1579 case CPUFAMILY_ARM_SWIFT:
1581 case CPUFAMILY_ARM_CYCLONE:
1583 case CPUFAMILY_ARM_TYPHOON:
1585 case CPUFAMILY_ARM_TWISTER:
1587 case CPUFAMILY_ARM_HURRICANE:
1589 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1591 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1593 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1595 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1597 case CPUFAMILY_ARM_BLIZZARD_AVALANCHE:
1599 case CPUFAMILY_ARM_EVEREST_SAWTOOTH:
1600 case CPUFAMILY_ARM_IBIZA:
1601 case CPUFAMILY_ARM_PALMA:
1602 case CPUFAMILY_ARM_LOBOS:
1604 case CPUFAMILY_ARM_COLL:
1606 case CPUFAMILY_ARM_DONAN:
1607 case CPUFAMILY_ARM_BRAVA:
1608 case CPUFAMILY_ARM_TAHITI:
1609 case CPUFAMILY_ARM_TUPAI:
1618 switch (_system_configuration.implementation) {
1620 if (_system_configuration.version == PV_4_3)
1624 if (_system_configuration.version == PV_5)
1628 if (_system_configuration.version == PV_6_Compat)
1654#elif defined(__loongarch__)
1658 __asm__(
"cpucfg %[prid], $zero\n\t" : [prid]
"=r"(processor_id));
1660 switch (processor_id & 0xf000) {
1671#elif defined(__riscv)
1673#if defined(__linux__)
1680#if __riscv_xlen == 64
1681 return "generic-rv64";
1682#elif __riscv_xlen == 32
1683 return "generic-rv32";
1685#error "Unhandled value of __riscv_xlen"
1688#elif defined(__sparc__)
1689#if defined(__linux__)
1692 ProcCpuinfoContent.
split(Lines,
'\n');
1696 for (
unsigned I = 0, E =
Lines.size();
I != E; ++
I) {
1698 Cpu =
Lines[
I].substr(5).ltrim(
"\t :");
1730#if defined(__linux__)
1733 return detail::getHostCPUNameForSPARC(
Content);
1734#elif defined(__sun__) && defined(__svr4__)
1738 kstat_named_t *brand = NULL;
1742 ksp = kstat_lookup(kc,
const_cast<char *
>(
"cpu_info"), -1, NULL);
1743 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1744 ksp->ks_type == KSTAT_TYPE_NAMED)
1746 (kstat_named_t *)kstat_data_lookup(ksp,
const_cast<char *
>(
"brand"));
1747 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1748 buf = KSTAT_NAMED_STR_PTR(brand);
1753 .
Case(
"TMS390S10",
"supersparc")
1754 .
Case(
"TMS390Z50",
"supersparc")
1757 .
Case(
"MB86904",
"supersparc")
1758 .
Case(
"MB86907",
"supersparc")
1759 .
Case(
"RT623",
"hypersparc")
1760 .
Case(
"RT625",
"hypersparc")
1761 .
Case(
"RT626",
"hypersparc")
1762 .
Case(
"UltraSPARC-I",
"ultrasparc")
1763 .
Case(
"UltraSPARC-II",
"ultrasparc")
1764 .
Case(
"UltraSPARC-IIe",
"ultrasparc")
1765 .
Case(
"UltraSPARC-IIi",
"ultrasparc")
1766 .
Case(
"SPARC64-III",
"ultrasparc")
1767 .
Case(
"SPARC64-IV",
"ultrasparc")
1768 .
Case(
"UltraSPARC-III",
"ultrasparc3")
1769 .
Case(
"UltraSPARC-III+",
"ultrasparc3")
1770 .
Case(
"UltraSPARC-IIIi",
"ultrasparc3")
1771 .
Case(
"UltraSPARC-IIIi+",
"ultrasparc3")
1772 .
Case(
"UltraSPARC-IV",
"ultrasparc3")
1773 .
Case(
"UltraSPARC-IV+",
"ultrasparc3")
1774 .
Case(
"SPARC64-V",
"ultrasparc3")
1775 .
Case(
"SPARC64-VI",
"ultrasparc3")
1776 .
Case(
"SPARC64-VII",
"ultrasparc3")
1777 .
Case(
"UltraSPARC-T1",
"niagara")
1778 .
Case(
"UltraSPARC-T2",
"niagara2")
1779 .
Case(
"UltraSPARC-T2",
"niagara2")
1780 .
Case(
"UltraSPARC-T2+",
"niagara2")
1781 .
Case(
"SPARC-T3",
"niagara3")
1782 .
Case(
"SPARC-T4",
"niagara4")
1783 .
Case(
"SPARC-T5",
"niagara4")
1785 .
Case(
"SPARC-M7",
"niagara4" )
1786 .
Case(
"SPARC-S7",
"niagara4" )
1787 .
Case(
"SPARC-M8",
"niagara4" )
1810#if defined(__i386__) || defined(_M_IX86) || \
1811 defined(__x86_64__) || defined(_M_X64)
1817 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1820 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1822 Features[
"cx8"] = (
EDX >> 8) & 1;
1823 Features[
"cmov"] = (
EDX >> 15) & 1;
1824 Features[
"mmx"] = (
EDX >> 23) & 1;
1825 Features[
"fxsr"] = (
EDX >> 24) & 1;
1826 Features[
"sse"] = (
EDX >> 25) & 1;
1827 Features[
"sse2"] = (
EDX >> 26) & 1;
1829 Features[
"sse3"] = (
ECX >> 0) & 1;
1830 Features[
"pclmul"] = (
ECX >> 1) & 1;
1831 Features[
"ssse3"] = (
ECX >> 9) & 1;
1832 Features[
"cx16"] = (
ECX >> 13) & 1;
1833 Features[
"sse4.1"] = (
ECX >> 19) & 1;
1834 Features[
"sse4.2"] = (
ECX >> 20) & 1;
1835 Features[
"crc32"] = Features[
"sse4.2"];
1836 Features[
"movbe"] = (
ECX >> 22) & 1;
1837 Features[
"popcnt"] = (
ECX >> 23) & 1;
1838 Features[
"aes"] = (
ECX >> 25) & 1;
1839 Features[
"rdrnd"] = (
ECX >> 30) & 1;
1844 bool HasXSave = ((
ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1845 bool HasAVXSave = HasXSave && ((
ECX >> 28) & 1) && ((
EAX & 0x6) == 0x6);
1846#if defined(__APPLE__)
1850 bool HasAVX512Save =
true;
1853 bool HasAVX512Save = HasAVXSave && ((
EAX & 0xe0) == 0xe0);
1856 const unsigned AMXBits = (1 << 17) | (1 << 18);
1857 bool HasAMXSave = HasXSave && ((
EAX & AMXBits) == AMXBits);
1859 Features[
"avx"] = HasAVXSave;
1860 Features[
"fma"] = ((
ECX >> 12) & 1) && HasAVXSave;
1862 Features[
"xsave"] = ((
ECX >> 26) & 1) && HasAVXSave;
1863 Features[
"f16c"] = ((
ECX >> 29) & 1) && HasAVXSave;
1865 unsigned MaxExtLevel;
1866 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1868 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1869 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1870 Features[
"sahf"] = HasExtLeaf1 && ((
ECX >> 0) & 1);
1871 Features[
"lzcnt"] = HasExtLeaf1 && ((
ECX >> 5) & 1);
1872 Features[
"sse4a"] = HasExtLeaf1 && ((
ECX >> 6) & 1);
1873 Features[
"prfchw"] = HasExtLeaf1 && ((
ECX >> 8) & 1);
1874 Features[
"xop"] = HasExtLeaf1 && ((
ECX >> 11) & 1) && HasAVXSave;
1875 Features[
"lwp"] = HasExtLeaf1 && ((
ECX >> 15) & 1);
1876 Features[
"fma4"] = HasExtLeaf1 && ((
ECX >> 16) & 1) && HasAVXSave;
1877 Features[
"tbm"] = HasExtLeaf1 && ((
ECX >> 21) & 1);
1878 Features[
"mwaitx"] = HasExtLeaf1 && ((
ECX >> 29) & 1);
1880 Features[
"64bit"] = HasExtLeaf1 && ((
EDX >> 29) & 1);
1884 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1885 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1886 Features[
"clzero"] = HasExtLeaf8 && ((
EBX >> 0) & 1);
1887 Features[
"rdpru"] = HasExtLeaf8 && ((
EBX >> 4) & 1);
1888 Features[
"wbnoinvd"] = HasExtLeaf8 && ((
EBX >> 9) & 1);
1891 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1893 Features[
"fsgsbase"] = HasLeaf7 && ((
EBX >> 0) & 1);
1894 Features[
"sgx"] = HasLeaf7 && ((
EBX >> 2) & 1);
1895 Features[
"bmi"] = HasLeaf7 && ((
EBX >> 3) & 1);
1897 Features[
"avx2"] = HasLeaf7 && ((
EBX >> 5) & 1) && HasAVXSave;
1898 Features[
"bmi2"] = HasLeaf7 && ((
EBX >> 8) & 1);
1899 Features[
"invpcid"] = HasLeaf7 && ((
EBX >> 10) & 1);
1900 Features[
"rtm"] = HasLeaf7 && ((
EBX >> 11) & 1);
1902 Features[
"avx512f"] = HasLeaf7 && ((
EBX >> 16) & 1) && HasAVX512Save;
1903 if (Features[
"avx512f"])
1904 Features[
"evex512"] =
true;
1905 Features[
"avx512dq"] = HasLeaf7 && ((
EBX >> 17) & 1) && HasAVX512Save;
1906 Features[
"rdseed"] = HasLeaf7 && ((
EBX >> 18) & 1);
1907 Features[
"adx"] = HasLeaf7 && ((
EBX >> 19) & 1);
1908 Features[
"avx512ifma"] = HasLeaf7 && ((
EBX >> 21) & 1) && HasAVX512Save;
1909 Features[
"clflushopt"] = HasLeaf7 && ((
EBX >> 23) & 1);
1910 Features[
"clwb"] = HasLeaf7 && ((
EBX >> 24) & 1);
1911 Features[
"avx512cd"] = HasLeaf7 && ((
EBX >> 28) & 1) && HasAVX512Save;
1912 Features[
"sha"] = HasLeaf7 && ((
EBX >> 29) & 1);
1913 Features[
"avx512bw"] = HasLeaf7 && ((
EBX >> 30) & 1) && HasAVX512Save;
1914 Features[
"avx512vl"] = HasLeaf7 && ((
EBX >> 31) & 1) && HasAVX512Save;
1916 Features[
"avx512vbmi"] = HasLeaf7 && ((
ECX >> 1) & 1) && HasAVX512Save;
1917 Features[
"pku"] = HasLeaf7 && ((
ECX >> 4) & 1);
1918 Features[
"waitpkg"] = HasLeaf7 && ((
ECX >> 5) & 1);
1919 Features[
"avx512vbmi2"] = HasLeaf7 && ((
ECX >> 6) & 1) && HasAVX512Save;
1920 Features[
"shstk"] = HasLeaf7 && ((
ECX >> 7) & 1);
1921 Features[
"gfni"] = HasLeaf7 && ((
ECX >> 8) & 1);
1922 Features[
"vaes"] = HasLeaf7 && ((
ECX >> 9) & 1) && HasAVXSave;
1923 Features[
"vpclmulqdq"] = HasLeaf7 && ((
ECX >> 10) & 1) && HasAVXSave;
1924 Features[
"avx512vnni"] = HasLeaf7 && ((
ECX >> 11) & 1) && HasAVX512Save;
1925 Features[
"avx512bitalg"] = HasLeaf7 && ((
ECX >> 12) & 1) && HasAVX512Save;
1926 Features[
"avx512vpopcntdq"] = HasLeaf7 && ((
ECX >> 14) & 1) && HasAVX512Save;
1927 Features[
"rdpid"] = HasLeaf7 && ((
ECX >> 22) & 1);
1928 Features[
"kl"] = HasLeaf7 && ((
ECX >> 23) & 1);
1929 Features[
"cldemote"] = HasLeaf7 && ((
ECX >> 25) & 1);
1930 Features[
"movdiri"] = HasLeaf7 && ((
ECX >> 27) & 1);
1931 Features[
"movdir64b"] = HasLeaf7 && ((
ECX >> 28) & 1);
1932 Features[
"enqcmd"] = HasLeaf7 && ((
ECX >> 29) & 1);
1934 Features[
"uintr"] = HasLeaf7 && ((
EDX >> 5) & 1);
1935 Features[
"avx512vp2intersect"] =
1936 HasLeaf7 && ((
EDX >> 8) & 1) && HasAVX512Save;
1937 Features[
"serialize"] = HasLeaf7 && ((
EDX >> 14) & 1);
1938 Features[
"tsxldtrk"] = HasLeaf7 && ((
EDX >> 16) & 1);
1949 Features[
"pconfig"] = HasLeaf7 && ((
EDX >> 18) & 1);
1950 Features[
"amx-bf16"] = HasLeaf7 && ((
EDX >> 22) & 1) && HasAMXSave;
1951 Features[
"avx512fp16"] = HasLeaf7 && ((
EDX >> 23) & 1) && HasAVX512Save;
1952 Features[
"amx-tile"] = HasLeaf7 && ((
EDX >> 24) & 1) && HasAMXSave;
1953 Features[
"amx-int8"] = HasLeaf7 && ((
EDX >> 25) & 1) && HasAMXSave;
1956 bool HasLeaf7Subleaf1 =
1957 HasLeaf7 &&
EAX >= 1 &&
1958 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1959 Features[
"sha512"] = HasLeaf7Subleaf1 && ((
EAX >> 0) & 1);
1960 Features[
"sm3"] = HasLeaf7Subleaf1 && ((
EAX >> 1) & 1);
1961 Features[
"sm4"] = HasLeaf7Subleaf1 && ((
EAX >> 2) & 1);
1962 Features[
"raoint"] = HasLeaf7Subleaf1 && ((
EAX >> 3) & 1);
1963 Features[
"avxvnni"] = HasLeaf7Subleaf1 && ((
EAX >> 4) & 1) && HasAVXSave;
1964 Features[
"avx512bf16"] = HasLeaf7Subleaf1 && ((
EAX >> 5) & 1) && HasAVX512Save;
1965 Features[
"amx-fp16"] = HasLeaf7Subleaf1 && ((
EAX >> 21) & 1) && HasAMXSave;
1966 Features[
"cmpccxadd"] = HasLeaf7Subleaf1 && ((
EAX >> 7) & 1);
1967 Features[
"hreset"] = HasLeaf7Subleaf1 && ((
EAX >> 22) & 1);
1968 Features[
"avxifma"] = HasLeaf7Subleaf1 && ((
EAX >> 23) & 1) && HasAVXSave;
1969 Features[
"movrs"] = HasLeaf7Subleaf1 && ((
EAX >> 31) & 1);
1970 Features[
"avxvnniint8"] = HasLeaf7Subleaf1 && ((
EDX >> 4) & 1) && HasAVXSave;
1971 Features[
"avxneconvert"] = HasLeaf7Subleaf1 && ((
EDX >> 5) & 1) && HasAVXSave;
1972 Features[
"amx-complex"] = HasLeaf7Subleaf1 && ((
EDX >> 8) & 1) && HasAMXSave;
1973 Features[
"avxvnniint16"] = HasLeaf7Subleaf1 && ((
EDX >> 10) & 1) && HasAVXSave;
1974 Features[
"prefetchi"] = HasLeaf7Subleaf1 && ((
EDX >> 14) & 1);
1975 Features[
"usermsr"] = HasLeaf7Subleaf1 && ((
EDX >> 15) & 1);
1976 bool HasAVX10 = HasLeaf7Subleaf1 && ((
EDX >> 19) & 1);
1977 bool HasAPXF = HasLeaf7Subleaf1 && ((
EDX >> 21) & 1);
1978 Features[
"egpr"] = HasAPXF;
1979 Features[
"push2pop2"] = HasAPXF;
1980 Features[
"ppx"] = HasAPXF;
1981 Features[
"ndd"] = HasAPXF;
1982 Features[
"ccmp"] = HasAPXF;
1983 Features[
"nf"] = HasAPXF;
1984 Features[
"cf"] = HasAPXF;
1985 Features[
"zu"] = HasAPXF;
1987 bool HasLeafD = MaxLevel >= 0xd &&
1988 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1991 Features[
"xsaveopt"] = HasLeafD && ((
EAX >> 0) & 1) && HasAVXSave;
1992 Features[
"xsavec"] = HasLeafD && ((
EAX >> 1) & 1) && HasAVXSave;
1993 Features[
"xsaves"] = HasLeafD && ((
EAX >> 3) & 1) && HasAVXSave;
1995 bool HasLeaf14 = MaxLevel >= 0x14 &&
1996 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1998 Features[
"ptwrite"] = HasLeaf14 && ((
EBX >> 4) & 1);
2001 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
2002 Features[
"widekl"] = HasLeaf7 && HasLeaf19 && ((
EBX >> 2) & 1);
2004 bool HasLeaf1E = MaxLevel >= 0x1e &&
2005 !getX86CpuIDAndInfoEx(0x1e, 0x1, &EAX, &EBX, &ECX, &EDX);
2006 Features[
"amx-fp8"] = HasLeaf1E && ((
EAX >> 4) & 1) && HasAMXSave;
2007 Features[
"amx-transpose"] = HasLeaf1E && ((
EAX >> 5) & 1) && HasAMXSave;
2008 Features[
"amx-tf32"] = HasLeaf1E && ((
EAX >> 6) & 1) && HasAMXSave;
2009 Features[
"amx-avx512"] = HasLeaf1E && ((
EAX >> 7) & 1) && HasAMXSave;
2010 Features[
"amx-movrs"] = HasLeaf1E && ((
EAX >> 8) & 1) && HasAMXSave;
2013 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);
2015 int AVX10Ver = HasLeaf24 && (
EBX & 0xff);
2016 int Has512Len = HasLeaf24 && ((
EBX >> 18) & 1);
2017 Features[
"avx10.1-256"] = HasAVX10 && AVX10Ver >= 1;
2018 Features[
"avx10.1-512"] = HasAVX10 && AVX10Ver >= 1 && Has512Len;
2019 Features[
"avx10.2-256"] = HasAVX10 && AVX10Ver >= 2;
2020 Features[
"avx10.2-512"] = HasAVX10 && AVX10Ver >= 2 && Has512Len;
2024#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
2032 P->getBuffer().split(Lines,
'\n');
2037 for (
unsigned I = 0, E =
Lines.size();
I != E; ++
I)
2039 Lines[
I].split(CPUFeatures,
' ');
2043#if defined(__aarch64__)
2046 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
2050 for (
unsigned I = 0, E = CPUFeatures.
size();
I != E; ++
I) {
2052#if defined(__aarch64__)
2053 .
Case(
"asimd",
"neon")
2054 .
Case(
"fp",
"fp-armv8")
2055 .
Case(
"crc32",
"crc")
2056 .
Case(
"atomics",
"lse")
2058 .
Case(
"sve2",
"sve2")
2060 .
Case(
"half",
"fp16")
2061 .
Case(
"neon",
"neon")
2062 .
Case(
"vfpv3",
"vfp3")
2063 .
Case(
"vfpv3d16",
"vfp3d16")
2064 .
Case(
"vfpv4",
"vfp4")
2065 .
Case(
"idiva",
"hwdiv-arm")
2066 .
Case(
"idivt",
"hwdiv")
2070#if defined(__aarch64__)
2073 if (CPUFeatures[
I] ==
"aes")
2075 else if (CPUFeatures[
I] ==
"pmull")
2076 crypto |= CAP_PMULL;
2077 else if (CPUFeatures[
I] ==
"sha1")
2079 else if (CPUFeatures[
I] ==
"sha2")
2083 if (LLVMFeatureStr !=
"")
2084 Features[LLVMFeatureStr] =
true;
2087#if defined(__aarch64__)
2091 uint32_t Aes = CAP_AES | CAP_PMULL;
2092 uint32_t Sha2 = CAP_SHA1 | CAP_SHA2;
2093 Features[
"aes"] = (crypto & Aes) == Aes;
2094 Features[
"sha2"] = (crypto & Sha2) == Sha2;
2099#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
2105 IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE);
2107 IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE);
2111 IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE);
2112 Features[
"aes"] = TradCrypto;
2113 Features[
"sha2"] = TradCrypto;
2117#elif defined(__linux__) && defined(__loongarch__)
2118#include <sys/auxv.h>
2120 unsigned long hwcap = getauxval(AT_HWCAP);
2121 bool HasFPU = hwcap & (1UL << 3);
2122 uint32_t cpucfg2 = 0x2, cpucfg3 = 0x3;
2123 __asm__(
"cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2]
"+r"(cpucfg2));
2124 __asm__(
"cpucfg %[cpucfg3], %[cpucfg3]\n\t" : [cpucfg3]
"+r"(cpucfg3));
2128 Features[
"f"] = HasFPU && (cpucfg2 & (1U << 1));
2129 Features[
"d"] = HasFPU && (cpucfg2 & (1U << 2));
2131 Features[
"lsx"] = hwcap & (1UL << 4);
2132 Features[
"lasx"] = hwcap & (1UL << 5);
2133 Features[
"lvz"] = hwcap & (1UL << 9);
2135 Features[
"frecipe"] = cpucfg2 & (1U << 25);
2136 Features[
"div32"] = cpucfg2 & (1U << 26);
2137 Features[
"lam-bh"] = cpucfg2 & (1U << 27);
2138 Features[
"lamcas"] = cpucfg2 & (1U << 28);
2139 Features[
"scq"] = cpucfg2 & (1U << 30);
2141 Features[
"ld-seq-sa"] = cpucfg3 & (1U << 23);
2147#elif defined(__linux__) && defined(__riscv)
2149struct RISCVHwProbe {
2154 RISCVHwProbe Query[]{{3, 0},
2157 int Ret = syscall(258, Query,
2158 std::size(Query), 0,
2164 uint64_t BaseMask = Query[0].Value;
2167 Features[
"i"] =
true;
2168 Features[
"m"] =
true;
2169 Features[
"a"] =
true;
2173 Features[
"f"] = ExtMask & (1 << 0);
2174 Features[
"d"] = ExtMask & (1 << 0);
2175 Features[
"c"] = ExtMask & (1 << 1);
2176 Features[
"v"] = ExtMask & (1 << 2);
2177 Features[
"zba"] = ExtMask & (1 << 3);
2178 Features[
"zbb"] = ExtMask & (1 << 4);
2179 Features[
"zbs"] = ExtMask & (1 << 5);
2180 Features[
"zicboz"] = ExtMask & (1 << 6);
2181 Features[
"zbc"] = ExtMask & (1 << 7);
2182 Features[
"zbkb"] = ExtMask & (1 << 8);
2183 Features[
"zbkc"] = ExtMask & (1 << 9);
2184 Features[
"zbkx"] = ExtMask & (1 << 10);
2185 Features[
"zknd"] = ExtMask & (1 << 11);
2186 Features[
"zkne"] = ExtMask & (1 << 12);
2187 Features[
"zknh"] = ExtMask & (1 << 13);
2188 Features[
"zksed"] = ExtMask & (1 << 14);
2189 Features[
"zksh"] = ExtMask & (1 << 15);
2190 Features[
"zkt"] = ExtMask & (1 << 16);
2191 Features[
"zvbb"] = ExtMask & (1 << 17);
2192 Features[
"zvbc"] = ExtMask & (1 << 18);
2193 Features[
"zvkb"] = ExtMask & (1 << 19);
2194 Features[
"zvkg"] = ExtMask & (1 << 20);
2195 Features[
"zvkned"] = ExtMask & (1 << 21);
2196 Features[
"zvknha"] = ExtMask & (1 << 22);
2197 Features[
"zvknhb"] = ExtMask & (1 << 23);
2198 Features[
"zvksed"] = ExtMask & (1 << 24);
2199 Features[
"zvksh"] = ExtMask & (1 << 25);
2200 Features[
"zvkt"] = ExtMask & (1 << 26);
2201 Features[
"zfh"] = ExtMask & (1 << 27);
2202 Features[
"zfhmin"] = ExtMask & (1 << 28);
2203 Features[
"zihintntl"] = ExtMask & (1 << 29);
2204 Features[
"zvfh"] = ExtMask & (1 << 30);
2205 Features[
"zvfhmin"] = ExtMask & (1ULL << 31);
2206 Features[
"zfa"] = ExtMask & (1ULL << 32);
2207 Features[
"ztso"] = ExtMask & (1ULL << 33);
2208 Features[
"zacas"] = ExtMask & (1ULL << 34);
2209 Features[
"zicond"] = ExtMask & (1ULL << 35);
2210 Features[
"zihintpause"] =
2211 ExtMask & (1ULL << 36);
2212 Features[
"zve32x"] = ExtMask & (1ULL << 37);
2213 Features[
"zve32f"] = ExtMask & (1ULL << 38);
2214 Features[
"zve64x"] = ExtMask & (1ULL << 39);
2215 Features[
"zve64f"] = ExtMask & (1ULL << 40);
2216 Features[
"zve64d"] = ExtMask & (1ULL << 41);
2217 Features[
"zimop"] = ExtMask & (1ULL << 42);
2218 Features[
"zca"] = ExtMask & (1ULL << 43);
2219 Features[
"zcb"] = ExtMask & (1ULL << 44);
2220 Features[
"zcd"] = ExtMask & (1ULL << 45);
2221 Features[
"zcf"] = ExtMask & (1ULL << 46);
2222 Features[
"zcmop"] = ExtMask & (1ULL << 47);
2223 Features[
"zawrs"] = ExtMask & (1ULL << 48);
2229 if (Query[2].Key != -1 &&
2230 Query[2].
Value == 3)
2231 Features[
"unaligned-scalar-mem"] =
true;
2244 T.setArchName(
"arm");
2245#elif defined(__arm64e__)
2247 T.setArchName(
"arm64e");
2248#elif defined(__aarch64__)
2250 T.setArchName(
"arm64");
2251#elif defined(__x86_64h__)
2253 T.setArchName(
"x86_64h");
2254#elif defined(__x86_64__)
2256 T.setArchName(
"x86_64");
2257#elif defined(__i386__)
2259 T.setArchName(
"i386");
2260#elif defined(__powerpc__)
2262 T.setArchName(
"powerpc");
2264# error "Unimplemented host arch fixup"
2271 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
2277 PT = withHostArch(PT);
2289#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
2291 if (CPU ==
"generic")
2294 <<
" Host CPU: " << CPU <<
'\n';
This file defines the StringMap class.
#define LLVM_ATTRIBUTE_UNUSED
Given that RA is a live value
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Represents either an error or a value T.
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
constexpr bool empty() const
empty - Check if the string is empty.
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
static constexpr size_t npos
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
StringSwitch & StartsWith(StringLiteral S, T Value)
Triple - Helper class for working with autoconf configuration names.
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
static std::string normalize(StringRef Str, CanonicalForm Form=CanonicalForm::ANY)
Turn an arbitrary machine specification into the canonical triple form (or something sensible that th...
const std::string & str() const
bool isArch64Bit() const
Test whether the architecture is 64-bit.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
@ CPU_SUBTYPE_POWERPC_970
@ CPU_SUBTYPE_POWERPC_604e
@ CPU_SUBTYPE_POWERPC_603e
@ CPU_SUBTYPE_POWERPC_7400
@ CPU_SUBTYPE_POWERPC_604
@ CPU_SUBTYPE_POWERPC_750
@ CPU_SUBTYPE_POWERPC_601
@ CPU_SUBTYPE_POWERPC_620
@ CPU_SUBTYPE_POWERPC_603ev
@ CPU_SUBTYPE_POWERPC_603
@ CPU_SUBTYPE_POWERPC_7450
@ CPU_SUBTYPE_POWERPC_602
Helper functions to extract CPU details from CPUID on x86.
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
StringRef getHostCPUNameForBPF()
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
const StringMap< bool, MallocAllocator > getHostCPUFeatures()
getHostCPUFeatures - Get the LLVM names for the host CPU features.
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
void printDefaultTargetAndDetectedCPU(raw_ostream &OS)
This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
std::string getDefaultTargetTriple()
getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...
This is an optimization pass for GlobalISel generic memory operations.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.