19 #include "llvm/Config/llvm-config.h"
39 #if defined(__APPLE__)
40 #include <mach/host_info.h>
41 #include <mach/mach.h>
42 #include <mach/mach_host.h>
43 #include <mach/machine.h>
44 #include <sys/param.h>
45 #include <sys/sysctl.h>
48 #include <sys/systemcfg.h>
50 #if defined(__sun__) && defined(__svr4__)
54 #define DEBUG_TYPE "host-detection"
64 static std::unique_ptr<llvm::MemoryBuffer>
68 if (std::error_code EC = Text.
getError()) {
70 <<
"/proc/cpuinfo: " << EC.message() <<
"\n";
80 const char *
generic =
"generic";
94 while (CIP < CPUInfoEnd && CPUStart ==
nullptr) {
95 if (CIP < CPUInfoEnd && *CIP ==
'\n')
98 if (CIP < CPUInfoEnd && *CIP ==
'c') {
100 if (CIP < CPUInfoEnd && *CIP ==
'p') {
102 if (CIP < CPUInfoEnd && *CIP ==
'u') {
104 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
107 if (CIP < CPUInfoEnd && *CIP ==
':') {
109 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
112 if (CIP < CPUInfoEnd) {
114 while (CIP < CPUInfoEnd && (*CIP !=
' ' && *CIP !=
'\t' &&
115 *CIP !=
',' && *CIP !=
'\n'))
117 CPULen = CIP - CPUStart;
124 if (CPUStart ==
nullptr)
125 while (CIP < CPUInfoEnd && *CIP !=
'\n')
129 if (CPUStart ==
nullptr)
133 .
Case(
"604e",
"604e")
135 .
Case(
"7400",
"7400")
136 .
Case(
"7410",
"7400")
137 .
Case(
"7447",
"7400")
138 .
Case(
"7455",
"7450")
140 .
Case(
"POWER4",
"970")
141 .
Case(
"PPC970FX",
"970")
142 .
Case(
"PPC970MP",
"970")
144 .
Case(
"POWER5",
"g5")
146 .
Case(
"POWER6",
"pwr6")
147 .
Case(
"POWER7",
"pwr7")
148 .
Case(
"POWER8",
"pwr8")
149 .
Case(
"POWER8E",
"pwr8")
150 .
Case(
"POWER8NVL",
"pwr8")
151 .
Case(
"POWER9",
"pwr9")
152 .
Case(
"POWER10",
"pwr10")
166 ProcCpuinfoContent.
split(Lines,
"\n");
172 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I) {
174 Implementer = Lines[
I].substr(15).ltrim(
"\t :");
176 Hardware = Lines[
I].substr(8).ltrim(
"\t :");
178 Part = Lines[
I].substr(8).ltrim(
"\t :");
181 if (Implementer ==
"0x41") {
194 .
Case(
"0x926",
"arm926ej-s")
195 .
Case(
"0xb02",
"mpcore")
196 .
Case(
"0xb36",
"arm1136j-s")
197 .
Case(
"0xb56",
"arm1156t2-s")
198 .
Case(
"0xb76",
"arm1176jz-s")
199 .
Case(
"0xc08",
"cortex-a8")
200 .
Case(
"0xc09",
"cortex-a9")
201 .
Case(
"0xc0f",
"cortex-a15")
202 .
Case(
"0xc20",
"cortex-m0")
203 .
Case(
"0xc23",
"cortex-m3")
204 .
Case(
"0xc24",
"cortex-m4")
205 .
Case(
"0xd22",
"cortex-m55")
206 .
Case(
"0xd02",
"cortex-a34")
207 .
Case(
"0xd04",
"cortex-a35")
208 .
Case(
"0xd03",
"cortex-a53")
209 .
Case(
"0xd07",
"cortex-a57")
210 .
Case(
"0xd08",
"cortex-a72")
211 .
Case(
"0xd09",
"cortex-a73")
212 .
Case(
"0xd0a",
"cortex-a75")
213 .
Case(
"0xd0b",
"cortex-a76")
214 .
Case(
"0xd0d",
"cortex-a77")
215 .
Case(
"0xd41",
"cortex-a78")
216 .
Case(
"0xd44",
"cortex-x1")
217 .
Case(
"0xd4c",
"cortex-x1c")
218 .
Case(
"0xd0c",
"neoverse-n1")
219 .
Case(
"0xd49",
"neoverse-n2")
220 .
Case(
"0xd40",
"neoverse-v1")
224 if (Implementer ==
"0x42" || Implementer ==
"0x43") {
226 .
Case(
"0x516",
"thunderx2t99")
227 .
Case(
"0x0516",
"thunderx2t99")
228 .
Case(
"0xaf",
"thunderx2t99")
229 .
Case(
"0x0af",
"thunderx2t99")
230 .
Case(
"0xa1",
"thunderxt88")
231 .
Case(
"0x0a1",
"thunderxt88")
235 if (Implementer ==
"0x46") {
237 .
Case(
"0x001",
"a64fx")
241 if (Implementer ==
"0x4e") {
243 .
Case(
"0x004",
"carmel")
247 if (Implementer ==
"0x48")
252 .
Case(
"0xd01",
"tsv110")
255 if (Implementer ==
"0x51")
260 .
Case(
"0x06f",
"krait")
261 .
Case(
"0x201",
"kryo")
262 .
Case(
"0x205",
"kryo")
263 .
Case(
"0x211",
"kryo")
264 .
Case(
"0x800",
"cortex-a73")
265 .
Case(
"0x801",
"cortex-a73")
266 .
Case(
"0x802",
"cortex-a75")
267 .
Case(
"0x803",
"cortex-a75")
268 .
Case(
"0x804",
"cortex-a76")
269 .
Case(
"0x805",
"cortex-a76")
270 .
Case(
"0xc00",
"falkor")
271 .
Case(
"0xc01",
"saphira")
273 if (Implementer ==
"0x53") {
276 unsigned Variant = 0, Part = 0;
281 if (
I.consume_front(
"CPU variant"))
282 I.ltrim(
"\t :").getAsInteger(0, Variant);
287 if (
I.consume_front(
"CPU part"))
288 I.ltrim(
"\t :").getAsInteger(0, Part);
290 unsigned Exynos = (Variant << 12) | Part;
302 if (Implementer ==
"0xc0") {
304 .
Case(
"0xac3",
"ampere1")
312 StringRef getCPUNameFromS390Model(
unsigned int Id,
bool HaveVectorSupport) {
332 return HaveVectorSupport?
"z13" :
"zEC12";
335 return HaveVectorSupport?
"z14" :
"zEC12";
338 return HaveVectorSupport?
"z15" :
"zEC12";
342 return HaveVectorSupport?
"z16" :
"zEC12";
353 ProcCpuinfoContent.
split(Lines,
"\n");
357 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I)
359 size_t Pos = Lines[
I].find(
':');
361 Lines[
I].drop_front(Pos + 1).split(CPUFeatures,
' ');
369 bool HaveVectorSupport =
false;
370 for (
unsigned I = 0,
E = CPUFeatures.size();
I !=
E; ++
I) {
371 if (CPUFeatures[
I] ==
"vx")
372 HaveVectorSupport =
true;
376 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I) {
378 size_t Pos = Lines[
I].find(
"machine = ");
380 Pos +=
sizeof(
"machine = ") - 1;
382 if (!Lines[
I].drop_front(Pos).getAsInteger(10,
Id))
383 return getCPUNameFromS390Model(
Id, HaveVectorSupport);
395 ProcCpuinfoContent.
split(Lines,
"\n");
399 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I) {
401 UArch = Lines[
I].substr(5).ltrim(
"\t :");
407 .
Case(
"sifive,u74-mc",
"sifive-u74")
408 .
Case(
"sifive,bullet0",
"sifive-u74")
413 #if !defined(__linux__) || !defined(__x86_64__)
416 uint8_t v3_insns[40] __attribute__ ((
aligned (8))) =
418 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
420 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
422 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
424 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
426 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
428 uint8_t v2_insns[40] __attribute__ ((
aligned (8))) =
430 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
432 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
434 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
436 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
438 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
440 struct bpf_prog_load_attr {
456 int fd = syscall(321 , 5 , &attr,
464 memset(&attr, 0,
sizeof(attr));
469 fd = syscall(321 , 5 , &attr,
sizeof(attr));
478 #if defined(__i386__) || defined(_M_IX86) || \
479 defined(__x86_64__) || defined(_M_X64)
488 static bool isCpuIdSupported() {
489 #if defined(__GNUC__) || defined(__clang__)
490 #if defined(__i386__)
491 int __cpuid_supported;
494 " movl %%eax,%%ecx\n"
495 " xorl $0x00200000,%%eax\n"
501 " cmpl %%eax,%%ecx\n"
505 :
"=r"(__cpuid_supported)
508 if (!__cpuid_supported)
518 static bool getX86CpuIDAndInfo(
unsigned value,
unsigned *rEAX,
unsigned *rEBX,
519 unsigned *rECX,
unsigned *rEDX) {
520 #if defined(__GNUC__) || defined(__clang__)
521 #if defined(__x86_64__)
524 __asm__(
"movq\t%%rbx, %%rsi\n\t"
526 "xchgq\t%%rbx, %%rsi\n\t"
527 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
530 #elif defined(__i386__)
531 __asm__(
"movl\t%%ebx, %%esi\n\t"
533 "xchgl\t%%ebx, %%esi\n\t"
534 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
540 #elif defined(_MSC_VER)
561 if (MaxLeaf ==
nullptr)
566 if (!isCpuIdSupported())
569 if (getX86CpuIDAndInfo(0, MaxLeaf, &
EBX, &
ECX, &
EDX) || *MaxLeaf < 1)
573 if (
EBX == 0x756e6547 &&
EDX == 0x49656e69 &&
ECX == 0x6c65746e)
574 return VendorSignatures::GENUINE_INTEL;
577 if (
EBX == 0x68747541 &&
EDX == 0x69746e65 &&
ECX == 0x444d4163)
578 return VendorSignatures::AUTHENTIC_AMD;
593 static bool getX86CpuIDAndInfoEx(
unsigned value,
unsigned subleaf,
594 unsigned *rEAX,
unsigned *rEBX,
unsigned *rECX,
596 #if defined(__GNUC__) || defined(__clang__)
597 #if defined(__x86_64__)
600 __asm__(
"movq\t%%rbx, %%rsi\n\t"
602 "xchgq\t%%rbx, %%rsi\n\t"
603 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
604 :
"a"(value),
"c"(subleaf));
606 #elif defined(__i386__)
607 __asm__(
"movl\t%%ebx, %%esi\n\t"
609 "xchgl\t%%ebx, %%esi\n\t"
610 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
611 :
"a"(value),
"c"(subleaf));
616 #elif defined(_MSC_VER)
630 static bool getX86XCR0(
unsigned *rEAX,
unsigned *rEDX) {
631 #if defined(__GNUC__) || defined(__clang__)
635 __asm__(
".byte 0x0f, 0x01, 0xd0" :
"=a"(*rEAX),
"=d"(*rEDX) :
"c"(0));
637 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
638 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
647 static void detectX86FamilyModel(
unsigned EAX,
unsigned *Family,
649 *Family = (
EAX >> 8) & 0xf;
651 if (*Family == 6 || *Family == 0xf) {
654 *Family += (
EAX >> 20) & 0xff;
661 getIntelProcessorTypeAndSubtype(
unsigned Family,
unsigned Model,
662 const unsigned *Features,
663 unsigned *
Type,
unsigned *Subtype) {
664 auto testFeature = [&](
unsigned F) {
665 return (Features[
F / 32] & (1U << (
F % 32))) != 0;
678 if (testFeature(X86::FEATURE_MMX)) {
694 *
Type = X86::INTEL_CORE2;
703 *
Type = X86::INTEL_CORE2;
712 *
Type = X86::INTEL_COREI7;
713 *Subtype = X86::INTEL_COREI7_NEHALEM;
720 *
Type = X86::INTEL_COREI7;
721 *Subtype = X86::INTEL_COREI7_WESTMERE;
727 *
Type = X86::INTEL_COREI7;
728 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
733 *
Type = X86::INTEL_COREI7;
734 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
743 *
Type = X86::INTEL_COREI7;
744 *Subtype = X86::INTEL_COREI7_HASWELL;
753 *
Type = X86::INTEL_COREI7;
754 *Subtype = X86::INTEL_COREI7_BROADWELL;
765 *
Type = X86::INTEL_COREI7;
766 *Subtype = X86::INTEL_COREI7_SKYLAKE;
772 *
Type = X86::INTEL_COREI7;
773 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
778 *
Type = X86::INTEL_COREI7;
779 if (testFeature(X86::FEATURE_AVX512BF16)) {
781 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
782 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
784 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
786 CPU =
"skylake-avx512";
787 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
794 *
Type = X86::INTEL_COREI7;
795 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
801 CPU =
"icelake-client";
802 *
Type = X86::INTEL_COREI7;
803 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
810 *
Type = X86::INTEL_COREI7;
811 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
818 *
Type = X86::INTEL_COREI7;
819 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
825 CPU =
"icelake-server";
826 *
Type = X86::INTEL_COREI7;
827 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
832 CPU =
"sapphirerapids";
833 *
Type = X86::INTEL_COREI7;
834 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
843 *
Type = X86::INTEL_BONNELL;
854 *
Type = X86::INTEL_SILVERMONT;
860 *
Type = X86::INTEL_GOLDMONT;
863 CPU =
"goldmont-plus";
864 *
Type = X86::INTEL_GOLDMONT_PLUS;
868 *
Type = X86::INTEL_TREMONT;
874 *
Type = X86::INTEL_KNL;
878 *
Type = X86::INTEL_KNM;
885 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
887 }
else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
888 CPU =
"icelake-client";
889 }
else if (testFeature(X86::FEATURE_AVX512VBMI)) {
891 }
else if (testFeature(X86::FEATURE_AVX512BF16)) {
893 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
895 }
else if (testFeature(X86::FEATURE_AVX512VL)) {
896 CPU =
"skylake-avx512";
897 }
else if (testFeature(X86::FEATURE_AVX512ER)) {
899 }
else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
900 if (testFeature(X86::FEATURE_SHA))
904 }
else if (testFeature(X86::FEATURE_ADX)) {
906 }
else if (testFeature(X86::FEATURE_AVX2)) {
908 }
else if (testFeature(X86::FEATURE_AVX)) {
910 }
else if (testFeature(X86::FEATURE_SSE4_2)) {
911 if (testFeature(X86::FEATURE_MOVBE))
915 }
else if (testFeature(X86::FEATURE_SSE4_1)) {
917 }
else if (testFeature(X86::FEATURE_SSSE3)) {
918 if (testFeature(X86::FEATURE_MOVBE))
922 }
else if (testFeature(X86::FEATURE_64BIT)) {
924 }
else if (testFeature(X86::FEATURE_SSE3)) {
926 }
else if (testFeature(X86::FEATURE_SSE2)) {
928 }
else if (testFeature(X86::FEATURE_SSE)) {
930 }
else if (testFeature(X86::FEATURE_MMX)) {
939 if (testFeature(X86::FEATURE_64BIT)) {
943 if (testFeature(X86::FEATURE_SSE3)) {
958 getAMDProcessorTypeAndSubtype(
unsigned Family,
unsigned Model,
959 const unsigned *Features,
960 unsigned *
Type,
unsigned *Subtype) {
961 auto testFeature = [&](
unsigned F) {
962 return (Features[
F / 32] & (1U << (
F % 32))) != 0;
991 if (testFeature(X86::FEATURE_SSE)) {
998 if (testFeature(X86::FEATURE_SSE3)) {
1006 *
Type = X86::AMDFAM10H;
1009 *Subtype = X86::AMDFAM10H_BARCELONA;
1012 *Subtype = X86::AMDFAM10H_SHANGHAI;
1015 *Subtype = X86::AMDFAM10H_ISTANBUL;
1021 *
Type = X86::AMD_BTVER1;
1025 *
Type = X86::AMDFAM15H;
1028 *Subtype = X86::AMDFAM15H_BDVER4;
1033 *Subtype = X86::AMDFAM15H_BDVER3;
1038 *Subtype = X86::AMDFAM15H_BDVER2;
1041 if (
Model <= 0x0f) {
1042 *Subtype = X86::AMDFAM15H_BDVER1;
1048 *
Type = X86::AMD_BTVER2;
1052 *
Type = X86::AMDFAM17H;
1055 *Subtype = X86::AMDFAM17H_ZNVER2;
1058 if (
Model <= 0x0f) {
1059 *Subtype = X86::AMDFAM17H_ZNVER1;
1065 *
Type = X86::AMDFAM19H;
1067 *Subtype = X86::AMDFAM19H_ZNVER3;
1078 static void getAvailableFeatures(
unsigned ECX,
unsigned EDX,
unsigned MaxLeaf,
1079 unsigned *Features) {
1082 auto setFeature = [&](
unsigned F) {
1083 Features[
F / 32] |= 1U << (
F % 32);
1086 if ((
EDX >> 15) & 1)
1087 setFeature(X86::FEATURE_CMOV);
1088 if ((
EDX >> 23) & 1)
1089 setFeature(X86::FEATURE_MMX);
1090 if ((
EDX >> 25) & 1)
1091 setFeature(X86::FEATURE_SSE);
1092 if ((
EDX >> 26) & 1)
1093 setFeature(X86::FEATURE_SSE2);
1096 setFeature(X86::FEATURE_SSE3);
1098 setFeature(X86::FEATURE_PCLMUL);
1100 setFeature(X86::FEATURE_SSSE3);
1101 if ((
ECX >> 12) & 1)
1103 if ((
ECX >> 19) & 1)
1104 setFeature(X86::FEATURE_SSE4_1);
1105 if ((
ECX >> 20) & 1) {
1106 setFeature(X86::FEATURE_SSE4_2);
1107 setFeature(X86::FEATURE_CRC32);
1109 if ((
ECX >> 23) & 1)
1110 setFeature(X86::FEATURE_POPCNT);
1111 if ((
ECX >> 25) & 1)
1112 setFeature(X86::FEATURE_AES);
1114 if ((
ECX >> 22) & 1)
1115 setFeature(X86::FEATURE_MOVBE);
1120 const unsigned AVXBits = (1 << 27) | (1 << 28);
1121 bool HasAVX = ((
ECX & AVXBits) == AVXBits) && !getX86XCR0(&
EAX, &
EDX) &&
1122 ((
EAX & 0x6) == 0x6);
1123 #if defined(__APPLE__)
1127 bool HasAVX512Save =
true;
1130 bool HasAVX512Save = HasAVX && ((
EAX & 0xe0) == 0xe0);
1134 setFeature(X86::FEATURE_AVX);
1137 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &
EAX, &
EBX, &
ECX, &
EDX);
1139 if (HasLeaf7 && ((
EBX >> 3) & 1))
1140 setFeature(X86::FEATURE_BMI);
1141 if (HasLeaf7 && ((
EBX >> 5) & 1) && HasAVX)
1142 setFeature(X86::FEATURE_AVX2);
1143 if (HasLeaf7 && ((
EBX >> 8) & 1))
1144 setFeature(X86::FEATURE_BMI2);
1145 if (HasLeaf7 && ((
EBX >> 16) & 1) && HasAVX512Save)
1146 setFeature(X86::FEATURE_AVX512F);
1147 if (HasLeaf7 && ((
EBX >> 17) & 1) && HasAVX512Save)
1148 setFeature(X86::FEATURE_AVX512DQ);
1149 if (HasLeaf7 && ((
EBX >> 19) & 1))
1150 setFeature(X86::FEATURE_ADX);
1151 if (HasLeaf7 && ((
EBX >> 21) & 1) && HasAVX512Save)
1152 setFeature(X86::FEATURE_AVX512IFMA);
1153 if (HasLeaf7 && ((
EBX >> 23) & 1))
1154 setFeature(X86::FEATURE_CLFLUSHOPT);
1155 if (HasLeaf7 && ((
EBX >> 26) & 1) && HasAVX512Save)
1156 setFeature(X86::FEATURE_AVX512PF);
1157 if (HasLeaf7 && ((
EBX >> 27) & 1) && HasAVX512Save)
1158 setFeature(X86::FEATURE_AVX512ER);
1159 if (HasLeaf7 && ((
EBX >> 28) & 1) && HasAVX512Save)
1160 setFeature(X86::FEATURE_AVX512CD);
1161 if (HasLeaf7 && ((
EBX >> 29) & 1))
1162 setFeature(X86::FEATURE_SHA);
1163 if (HasLeaf7 && ((
EBX >> 30) & 1) && HasAVX512Save)
1164 setFeature(X86::FEATURE_AVX512BW);
1165 if (HasLeaf7 && ((
EBX >> 31) & 1) && HasAVX512Save)
1166 setFeature(X86::FEATURE_AVX512VL);
1168 if (HasLeaf7 && ((
ECX >> 1) & 1) && HasAVX512Save)
1169 setFeature(X86::FEATURE_AVX512VBMI);
1170 if (HasLeaf7 && ((
ECX >> 6) & 1) && HasAVX512Save)
1171 setFeature(X86::FEATURE_AVX512VBMI2);
1172 if (HasLeaf7 && ((
ECX >> 8) & 1))
1173 setFeature(X86::FEATURE_GFNI);
1174 if (HasLeaf7 && ((
ECX >> 10) & 1) && HasAVX)
1175 setFeature(X86::FEATURE_VPCLMULQDQ);
1176 if (HasLeaf7 && ((
ECX >> 11) & 1) && HasAVX512Save)
1177 setFeature(X86::FEATURE_AVX512VNNI);
1178 if (HasLeaf7 && ((
ECX >> 12) & 1) && HasAVX512Save)
1179 setFeature(X86::FEATURE_AVX512BITALG);
1180 if (HasLeaf7 && ((
ECX >> 14) & 1) && HasAVX512Save)
1181 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1183 if (HasLeaf7 && ((
EDX >> 2) & 1) && HasAVX512Save)
1184 setFeature(X86::FEATURE_AVX5124VNNIW);
1185 if (HasLeaf7 && ((
EDX >> 3) & 1) && HasAVX512Save)
1186 setFeature(X86::FEATURE_AVX5124FMAPS);
1187 if (HasLeaf7 && ((
EDX >> 8) & 1) && HasAVX512Save)
1188 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1190 bool HasLeaf7Subleaf1 =
1191 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &
EAX, &
EBX, &
ECX, &
EDX);
1192 if (HasLeaf7Subleaf1 && ((
EAX >> 5) & 1) && HasAVX512Save)
1193 setFeature(X86::FEATURE_AVX512BF16);
1195 unsigned MaxExtLevel;
1196 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &
EBX, &
ECX, &
EDX);
1198 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1199 !getX86CpuIDAndInfo(0x80000001, &
EAX, &
EBX, &
ECX, &
EDX);
1200 if (HasExtLeaf1 && ((
ECX >> 6) & 1))
1201 setFeature(X86::FEATURE_SSE4_A);
1202 if (HasExtLeaf1 && ((
ECX >> 11) & 1))
1203 setFeature(X86::FEATURE_XOP);
1204 if (HasExtLeaf1 && ((
ECX >> 16) & 1))
1205 setFeature(X86::FEATURE_FMA4);
1207 if (HasExtLeaf1 && ((
EDX >> 29) & 1))
1208 setFeature(X86::FEATURE_64BIT);
1212 unsigned MaxLeaf = 0;
1220 unsigned Family = 0,
Model = 0;
1222 detectX86FamilyModel(
EAX, &Family, &
Model);
1223 getAvailableFeatures(
ECX,
EDX, MaxLeaf, Features);
1228 unsigned Subtype = 0;
1233 CPU = getIntelProcessorTypeAndSubtype(Family,
Model, Features, &
Type,
1236 CPU = getAMDProcessorTypeAndSubtype(Family,
Model, Features, &
Type,
1246 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
1248 host_basic_info_data_t hostInfo;
1249 mach_msg_type_number_t infoCount;
1251 infoCount = HOST_BASIC_INFO_COUNT;
1252 mach_port_t hostPort = mach_host_self();
1253 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1255 mach_port_deallocate(mach_task_self(), hostPort);
1260 switch (hostInfo.cpu_subtype) {
1290 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
1296 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1302 #elif defined(__linux__) && defined(__s390x__)
1308 #elif defined(__MVS__)
1313 int *StartToCVTOffset =
reinterpret_cast<int *
>(0x10);
1316 int ReadValue = *StartToCVTOffset;
1318 ReadValue = (ReadValue & 0x7FFFFFFF);
1319 char *CVT =
reinterpret_cast<char *
>(ReadValue);
1324 Id = decodePackedBCD<uint16_t>(
Id,
false);
1328 bool HaveVectorSupport = CVT[244] & 0x80;
1329 return getCPUNameFromS390Model(
Id, HaveVectorSupport);
1331 #elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1332 #define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1333 #define CPUFAMILY_ARM_CYCLONE 0x37a09642
1334 #define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1335 #define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1336 #define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1337 #define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1338 #define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1339 #define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1340 #define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1344 size_t Length =
sizeof(Family);
1345 sysctlbyname(
"hw.cpufamily", &Family, &Length, NULL, 0);
1348 case CPUFAMILY_ARM_SWIFT:
1350 case CPUFAMILY_ARM_CYCLONE:
1352 case CPUFAMILY_ARM_TYPHOON:
1354 case CPUFAMILY_ARM_TWISTER:
1356 case CPUFAMILY_ARM_HURRICANE:
1358 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1360 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1362 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1364 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1373 switch (_system_configuration.implementation) {
1375 if (_system_configuration.version == PV_4_3)
1379 if (_system_configuration.version == PV_5)
1383 if (_system_configuration.version == PV_6_Compat)
1403 #elif defined(__riscv)
1405 #if defined(__linux__)
1410 #if __riscv_xlen == 64
1411 return "generic-rv64";
1412 #elif __riscv_xlen == 32
1413 return "generic-rv32";
1415 #error "Unhandled value of __riscv_xlen"
1419 #elif defined(__sparc__)
1420 #if defined(__linux__)
1423 ProcCpuinfoContent.
split(Lines,
"\n");
1427 for (
unsigned I = 0,
E =
Lines.size();
I !=
E; ++
I) {
1429 Cpu =
Lines[
I].substr(5).ltrim(
"\t :");
1461 #if defined(__linux__)
1465 #elif defined(__sun__) && defined(__svr4__)
1469 kstat_named_t *brand = NULL;
1473 ksp = kstat_lookup(kc,
const_cast<char *
>(
"cpu_info"), -1, NULL);
1474 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1475 ksp->ks_type == KSTAT_TYPE_NAMED)
1477 (kstat_named_t *)kstat_data_lookup(ksp,
const_cast<char *
>(
"brand"));
1478 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1479 buf = KSTAT_NAMED_STR_PTR(brand);
1484 .
Case(
"TMS390S10",
"supersparc")
1485 .
Case(
"TMS390Z50",
"supersparc")
1488 .
Case(
"MB86904",
"supersparc")
1489 .
Case(
"MB86907",
"supersparc")
1490 .
Case(
"RT623",
"hypersparc")
1491 .
Case(
"RT625",
"hypersparc")
1492 .
Case(
"RT626",
"hypersparc")
1493 .
Case(
"UltraSPARC-I",
"ultrasparc")
1494 .
Case(
"UltraSPARC-II",
"ultrasparc")
1495 .
Case(
"UltraSPARC-IIe",
"ultrasparc")
1496 .
Case(
"UltraSPARC-IIi",
"ultrasparc")
1497 .
Case(
"SPARC64-III",
"ultrasparc")
1498 .
Case(
"SPARC64-IV",
"ultrasparc")
1499 .
Case(
"UltraSPARC-III",
"ultrasparc3")
1500 .
Case(
"UltraSPARC-III+",
"ultrasparc3")
1501 .
Case(
"UltraSPARC-IIIi",
"ultrasparc3")
1502 .
Case(
"UltraSPARC-IIIi+",
"ultrasparc3")
1503 .
Case(
"UltraSPARC-IV",
"ultrasparc3")
1504 .
Case(
"UltraSPARC-IV+",
"ultrasparc3")
1505 .
Case(
"SPARC64-V",
"ultrasparc3")
1506 .
Case(
"SPARC64-VI",
"ultrasparc3")
1507 .
Case(
"SPARC64-VII",
"ultrasparc3")
1508 .
Case(
"UltraSPARC-T1",
"niagara")
1509 .
Case(
"UltraSPARC-T2",
"niagara2")
1510 .
Case(
"UltraSPARC-T2",
"niagara2")
1511 .
Case(
"UltraSPARC-T2+",
"niagara2")
1512 .
Case(
"SPARC-T3",
"niagara3")
1513 .
Case(
"SPARC-T4",
"niagara4")
1514 .
Case(
"SPARC-T5",
"niagara4")
1516 .
Case(
"SPARC-M7",
"niagara4" )
1517 .
Case(
"SPARC-S7",
"niagara4" )
1518 .
Case(
"SPARC-M8",
"niagara4" )
1541 #if defined(__linux__) && (defined(__i386__) || defined(__x86_64__))
1549 if (sched_getaffinity(0,
sizeof(Affinity), &Affinity) != 0)
1557 if (std::error_code EC = Text.
getError()) {
1559 <<
"/proc/cpuinfo: " <<
EC.message() <<
"\n";
1563 (*Text)->getBuffer().split(strs,
"\n", -1,
1565 int CurProcessor = -1;
1566 int CurPhysicalId = -1;
1567 int CurSiblings = -1;
1570 std::pair<StringRef, StringRef>
Data = Line.split(
':');
1572 auto Val =
Data.second.trim();
1574 if (
Name ==
"processor")
1575 Val.getAsInteger(10, CurProcessor);
1576 else if (
Name ==
"physical id")
1577 Val.getAsInteger(10, CurPhysicalId);
1578 else if (
Name ==
"siblings")
1579 Val.getAsInteger(10, CurSiblings);
1580 else if (
Name ==
"core id") {
1581 Val.getAsInteger(10, CurCoreId);
1583 if (CPU_ISSET(CurProcessor, &Affinity))
1584 CPU_SET(CurPhysicalId * CurSiblings + CurCoreId, &
Enabled);
1589 #elif defined(__linux__) && defined(__s390x__)
1591 #elif defined(__linux__) && !defined(__ANDROID__)
1594 if (sched_getaffinity(0,
sizeof(Affinity), &Affinity) == 0)
1595 return CPU_COUNT(&Affinity);
1601 cpu_set_t *DynAffinity;
1602 DynAffinity = CPU_ALLOC(2048);
1603 if (sched_getaffinity(0, CPU_ALLOC_SIZE(2048), DynAffinity) == 0) {
1604 int NumCPUs = CPU_COUNT(DynAffinity);
1605 CPU_FREE(DynAffinity);
1610 #elif defined(__APPLE__)
1614 size_t len =
sizeof(
count);
1615 sysctlbyname(
"hw.physicalcpu", &
count, &len, NULL, 0);
1619 nm[1] = HW_AVAILCPU;
1620 sysctl(nm, 2, &
count, &len, NULL, 0);
1626 #elif defined(__MVS__)
1639 CSD_NUMBER_ONLINE_STANDARD_CPS = 264,
1642 char *CVT =
reinterpret_cast<char *
>(
1643 static_cast<uintptr_t
>(
reinterpret_cast<unsigned int &
>(PSA[FLCCVT])));
1644 char *CSD =
reinterpret_cast<char *
>(
1645 static_cast<uintptr_t
>(
reinterpret_cast<unsigned int &
>(CVT[CVTCSD])));
1646 return reinterpret_cast<int &
>(CSD[CSD_NUMBER_ONLINE_STANDARD_CPS]);
1648 #elif defined(_WIN32) && LLVM_ENABLE_THREADS != 0
1661 #if defined(__i386__) || defined(_M_IX86) || \
1662 defined(__x86_64__) || defined(_M_X64)
1667 if (getX86CpuIDAndInfo(0, &MaxLevel, &
EBX, &
ECX, &
EDX) || MaxLevel < 1)
1672 Features[
"cx8"] = (
EDX >> 8) & 1;
1673 Features[
"cmov"] = (
EDX >> 15) & 1;
1674 Features[
"mmx"] = (
EDX >> 23) & 1;
1675 Features[
"fxsr"] = (
EDX >> 24) & 1;
1676 Features[
"sse"] = (
EDX >> 25) & 1;
1677 Features[
"sse2"] = (
EDX >> 26) & 1;
1679 Features[
"sse3"] = (
ECX >> 0) & 1;
1680 Features[
"pclmul"] = (
ECX >> 1) & 1;
1681 Features[
"ssse3"] = (
ECX >> 9) & 1;
1682 Features[
"cx16"] = (
ECX >> 13) & 1;
1683 Features[
"sse4.1"] = (
ECX >> 19) & 1;
1684 Features[
"sse4.2"] = (
ECX >> 20) & 1;
1685 Features[
"crc32"] = Features[
"sse4.2"];
1686 Features[
"movbe"] = (
ECX >> 22) & 1;
1687 Features[
"popcnt"] = (
ECX >> 23) & 1;
1688 Features[
"aes"] = (
ECX >> 25) & 1;
1689 Features[
"rdrnd"] = (
ECX >> 30) & 1;
1694 bool HasXSave = ((
ECX >> 27) & 1) && !getX86XCR0(&
EAX, &
EDX);
1695 bool HasAVXSave = HasXSave && ((
ECX >> 28) & 1) && ((
EAX & 0x6) == 0x6);
1696 #if defined(__APPLE__)
1700 bool HasAVX512Save =
true;
1703 bool HasAVX512Save = HasAVXSave && ((
EAX & 0xe0) == 0xe0);
1706 const unsigned AMXBits = (1 << 17) | (1 << 18);
1707 bool HasAMXSave = HasXSave && ((
EAX & AMXBits) == AMXBits);
1709 Features[
"avx"] = HasAVXSave;
1710 Features[
"fma"] = ((
ECX >> 12) & 1) && HasAVXSave;
1712 Features[
"xsave"] = ((
ECX >> 26) & 1) && HasAVXSave;
1713 Features[
"f16c"] = ((
ECX >> 29) & 1) && HasAVXSave;
1715 unsigned MaxExtLevel;
1716 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &
EBX, &
ECX, &
EDX);
1718 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1719 !getX86CpuIDAndInfo(0x80000001, &
EAX, &
EBX, &
ECX, &
EDX);
1720 Features[
"sahf"] = HasExtLeaf1 && ((
ECX >> 0) & 1);
1721 Features[
"lzcnt"] = HasExtLeaf1 && ((
ECX >> 5) & 1);
1722 Features[
"sse4a"] = HasExtLeaf1 && ((
ECX >> 6) & 1);
1723 Features[
"prfchw"] = HasExtLeaf1 && ((
ECX >> 8) & 1);
1724 Features[
"xop"] = HasExtLeaf1 && ((
ECX >> 11) & 1) && HasAVXSave;
1725 Features[
"lwp"] = HasExtLeaf1 && ((
ECX >> 15) & 1);
1726 Features[
"fma4"] = HasExtLeaf1 && ((
ECX >> 16) & 1) && HasAVXSave;
1727 Features[
"tbm"] = HasExtLeaf1 && ((
ECX >> 21) & 1);
1728 Features[
"mwaitx"] = HasExtLeaf1 && ((
ECX >> 29) & 1);
1730 Features[
"64bit"] = HasExtLeaf1 && ((
EDX >> 29) & 1);
1734 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1735 !getX86CpuIDAndInfo(0x80000008, &
EAX, &
EBX, &
ECX, &
EDX);
1736 Features[
"clzero"] = HasExtLeaf8 && ((
EBX >> 0) & 1);
1737 Features[
"rdpru"] = HasExtLeaf8 && ((
EBX >> 4) & 1);
1738 Features[
"wbnoinvd"] = HasExtLeaf8 && ((
EBX >> 9) & 1);
1741 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &
EAX, &
EBX, &
ECX, &
EDX);
1743 Features[
"fsgsbase"] = HasLeaf7 && ((
EBX >> 0) & 1);
1744 Features[
"sgx"] = HasLeaf7 && ((
EBX >> 2) & 1);
1745 Features[
"bmi"] = HasLeaf7 && ((
EBX >> 3) & 1);
1747 Features[
"avx2"] = HasLeaf7 && ((
EBX >> 5) & 1) && HasAVXSave;
1748 Features[
"bmi2"] = HasLeaf7 && ((
EBX >> 8) & 1);
1749 Features[
"invpcid"] = HasLeaf7 && ((
EBX >> 10) & 1);
1750 Features[
"rtm"] = HasLeaf7 && ((
EBX >> 11) & 1);
1752 Features[
"avx512f"] = HasLeaf7 && ((
EBX >> 16) & 1) && HasAVX512Save;
1753 Features[
"avx512dq"] = HasLeaf7 && ((
EBX >> 17) & 1) && HasAVX512Save;
1754 Features[
"rdseed"] = HasLeaf7 && ((
EBX >> 18) & 1);
1755 Features[
"adx"] = HasLeaf7 && ((
EBX >> 19) & 1);
1756 Features[
"avx512ifma"] = HasLeaf7 && ((
EBX >> 21) & 1) && HasAVX512Save;
1757 Features[
"clflushopt"] = HasLeaf7 && ((
EBX >> 23) & 1);
1758 Features[
"clwb"] = HasLeaf7 && ((
EBX >> 24) & 1);
1759 Features[
"avx512pf"] = HasLeaf7 && ((
EBX >> 26) & 1) && HasAVX512Save;
1760 Features[
"avx512er"] = HasLeaf7 && ((
EBX >> 27) & 1) && HasAVX512Save;
1761 Features[
"avx512cd"] = HasLeaf7 && ((
EBX >> 28) & 1) && HasAVX512Save;
1762 Features[
"sha"] = HasLeaf7 && ((
EBX >> 29) & 1);
1763 Features[
"avx512bw"] = HasLeaf7 && ((
EBX >> 30) & 1) && HasAVX512Save;
1764 Features[
"avx512vl"] = HasLeaf7 && ((
EBX >> 31) & 1) && HasAVX512Save;
1766 Features[
"prefetchwt1"] = HasLeaf7 && ((
ECX >> 0) & 1);
1767 Features[
"avx512vbmi"] = HasLeaf7 && ((
ECX >> 1) & 1) && HasAVX512Save;
1768 Features[
"pku"] = HasLeaf7 && ((
ECX >> 4) & 1);
1769 Features[
"waitpkg"] = HasLeaf7 && ((
ECX >> 5) & 1);
1770 Features[
"avx512vbmi2"] = HasLeaf7 && ((
ECX >> 6) & 1) && HasAVX512Save;
1771 Features[
"shstk"] = HasLeaf7 && ((
ECX >> 7) & 1);
1772 Features[
"gfni"] = HasLeaf7 && ((
ECX >> 8) & 1);
1773 Features[
"vaes"] = HasLeaf7 && ((
ECX >> 9) & 1) && HasAVXSave;
1774 Features[
"vpclmulqdq"] = HasLeaf7 && ((
ECX >> 10) & 1) && HasAVXSave;
1775 Features[
"avx512vnni"] = HasLeaf7 && ((
ECX >> 11) & 1) && HasAVX512Save;
1776 Features[
"avx512bitalg"] = HasLeaf7 && ((
ECX >> 12) & 1) && HasAVX512Save;
1777 Features[
"avx512vpopcntdq"] = HasLeaf7 && ((
ECX >> 14) & 1) && HasAVX512Save;
1778 Features[
"rdpid"] = HasLeaf7 && ((
ECX >> 22) & 1);
1779 Features[
"kl"] = HasLeaf7 && ((
ECX >> 23) & 1);
1780 Features[
"cldemote"] = HasLeaf7 && ((
ECX >> 25) & 1);
1781 Features[
"movdiri"] = HasLeaf7 && ((
ECX >> 27) & 1);
1782 Features[
"movdir64b"] = HasLeaf7 && ((
ECX >> 28) & 1);
1783 Features[
"enqcmd"] = HasLeaf7 && ((
ECX >> 29) & 1);
1785 Features[
"uintr"] = HasLeaf7 && ((
EDX >> 5) & 1);
1786 Features[
"avx512vp2intersect"] =
1787 HasLeaf7 && ((
EDX >> 8) & 1) && HasAVX512Save;
1788 Features[
"serialize"] = HasLeaf7 && ((
EDX >> 14) & 1);
1789 Features[
"tsxldtrk"] = HasLeaf7 && ((
EDX >> 16) & 1);
1800 Features[
"pconfig"] = HasLeaf7 && ((
EDX >> 18) & 1);
1801 Features[
"amx-bf16"] = HasLeaf7 && ((
EDX >> 22) & 1) && HasAMXSave;
1802 Features[
"avx512fp16"] = HasLeaf7 && ((
EDX >> 23) & 1) && HasAVX512Save;
1803 Features[
"amx-tile"] = HasLeaf7 && ((
EDX >> 24) & 1) && HasAMXSave;
1804 Features[
"amx-int8"] = HasLeaf7 && ((
EDX >> 25) & 1) && HasAMXSave;
1805 bool HasLeaf7Subleaf1 =
1806 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &
EAX, &
EBX, &
ECX, &
EDX);
1807 Features[
"avxvnni"] = HasLeaf7Subleaf1 && ((
EAX >> 4) & 1) && HasAVXSave;
1808 Features[
"avx512bf16"] = HasLeaf7Subleaf1 && ((
EAX >> 5) & 1) && HasAVX512Save;
1809 Features[
"hreset"] = HasLeaf7Subleaf1 && ((
EAX >> 22) & 1);
1811 bool HasLeafD = MaxLevel >= 0xd &&
1812 !getX86CpuIDAndInfoEx(0xd, 0x1, &
EAX, &
EBX, &
ECX, &
EDX);
1815 Features[
"xsaveopt"] = HasLeafD && ((
EAX >> 0) & 1) && HasAVXSave;
1816 Features[
"xsavec"] = HasLeafD && ((
EAX >> 1) & 1) && HasAVXSave;
1817 Features[
"xsaves"] = HasLeafD && ((
EAX >> 3) & 1) && HasAVXSave;
1819 bool HasLeaf14 = MaxLevel >= 0x14 &&
1820 !getX86CpuIDAndInfoEx(0x14, 0x0, &
EAX, &
EBX, &
ECX, &
EDX);
1822 Features[
"ptwrite"] = HasLeaf14 && ((
EBX >> 4) & 1);
1825 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &
EAX, &
EBX, &
ECX, &
EDX);
1826 Features[
"widekl"] = HasLeaf7 && HasLeaf19 && ((
EBX >> 2) & 1);
1830 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1837 P->getBuffer().split(Lines,
"\n");
1842 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I)
1844 Lines[
I].split(CPUFeatures,
' ');
1848 #if defined(__aarch64__)
1850 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1854 for (
unsigned I = 0,
E = CPUFeatures.size();
I !=
E; ++
I) {
1856 #if defined(__aarch64__)
1857 .
Case(
"asimd",
"neon")
1858 .
Case(
"fp",
"fp-armv8")
1859 .
Case(
"crc32",
"crc")
1860 .
Case(
"atomics",
"lse")
1862 .
Case(
"sve2",
"sve2")
1864 .
Case(
"half",
"fp16")
1865 .
Case(
"neon",
"neon")
1866 .
Case(
"vfpv3",
"vfp3")
1867 .
Case(
"vfpv3d16",
"d16")
1868 .
Case(
"vfpv4",
"vfp4")
1869 .
Case(
"idiva",
"hwdiv-arm")
1870 .
Case(
"idivt",
"hwdiv")
1874 #if defined(__aarch64__)
1877 if (CPUFeatures[
I] ==
"aes")
1879 else if (CPUFeatures[
I] ==
"pmull")
1880 crypto |= CAP_PMULL;
1881 else if (CPUFeatures[
I] ==
"sha1")
1883 else if (CPUFeatures[
I] ==
"sha2")
1887 if (LLVMFeatureStr !=
"")
1888 Features[LLVMFeatureStr] =
true;
1891 #if defined(__aarch64__)
1893 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1894 Features[
"crypto"] =
true;
1899 #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1901 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1902 Features[
"neon"] =
true;
1903 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1904 Features[
"crc"] =
true;
1905 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1906 Features[
"crypto"] =
true;
1915 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);