18#include "llvm/Config/llvm-config.h"
40#include <mach/host_info.h>
42#include <mach/mach_host.h>
43#include <mach/machine.h>
45#include <sys/sysctl.h>
48#include <sys/systemcfg.h>
50#if defined(__sun__) && defined(__svr4__)
54#define DEBUG_TYPE "host-detection"
64static std::unique_ptr<llvm::MemoryBuffer>
68 if (std::error_code EC =
Text.getError()) {
70 <<
"/proc/cpuinfo: " << EC.message() <<
"\n";
73 return std::move(*
Text);
80 const char *
generic =
"generic";
94 while (CIP < CPUInfoEnd && CPUStart ==
nullptr) {
95 if (CIP < CPUInfoEnd && *CIP ==
'\n')
98 if (CIP < CPUInfoEnd && *CIP ==
'c') {
100 if (CIP < CPUInfoEnd && *CIP ==
'p') {
102 if (CIP < CPUInfoEnd && *CIP ==
'u') {
104 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
107 if (CIP < CPUInfoEnd && *CIP ==
':') {
109 while (CIP < CPUInfoEnd && (*CIP ==
' ' || *CIP ==
'\t'))
112 if (CIP < CPUInfoEnd) {
114 while (CIP < CPUInfoEnd && (*CIP !=
' ' && *CIP !=
'\t' &&
115 *CIP !=
',' && *CIP !=
'\n'))
117 CPULen = CIP - CPUStart;
124 if (CPUStart ==
nullptr)
125 while (CIP < CPUInfoEnd && *CIP !=
'\n')
129 if (CPUStart ==
nullptr)
133 .
Case(
"604e",
"604e")
135 .
Case(
"7400",
"7400")
136 .
Case(
"7410",
"7400")
137 .
Case(
"7447",
"7400")
138 .
Case(
"7455",
"7450")
140 .
Case(
"POWER4",
"970")
141 .
Case(
"PPC970FX",
"970")
142 .
Case(
"PPC970MP",
"970")
144 .
Case(
"POWER5",
"g5")
146 .
Case(
"POWER6",
"pwr6")
147 .
Case(
"POWER7",
"pwr7")
148 .
Case(
"POWER8",
"pwr8")
149 .
Case(
"POWER8E",
"pwr8")
150 .
Case(
"POWER8NVL",
"pwr8")
151 .
Case(
"POWER9",
"pwr9")
152 .
Case(
"POWER10",
"pwr10")
166 ProcCpuinfoContent.
split(Lines,
"\n");
172 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I) {
174 Implementer = Lines[
I].substr(15).ltrim(
"\t :");
176 Hardware = Lines[
I].substr(8).ltrim(
"\t :");
178 Part = Lines[
I].substr(8).ltrim(
"\t :");
181 if (Implementer ==
"0x41") {
194 .
Case(
"0x926",
"arm926ej-s")
195 .
Case(
"0xb02",
"mpcore")
196 .
Case(
"0xb36",
"arm1136j-s")
197 .
Case(
"0xb56",
"arm1156t2-s")
198 .
Case(
"0xb76",
"arm1176jz-s")
199 .
Case(
"0xc08",
"cortex-a8")
200 .
Case(
"0xc09",
"cortex-a9")
201 .
Case(
"0xc0f",
"cortex-a15")
202 .
Case(
"0xc20",
"cortex-m0")
203 .
Case(
"0xc23",
"cortex-m3")
204 .
Case(
"0xc24",
"cortex-m4")
205 .
Case(
"0xd22",
"cortex-m55")
206 .
Case(
"0xd02",
"cortex-a34")
207 .
Case(
"0xd04",
"cortex-a35")
208 .
Case(
"0xd03",
"cortex-a53")
209 .
Case(
"0xd05",
"cortex-a55")
210 .
Case(
"0xd46",
"cortex-a510")
211 .
Case(
"0xd07",
"cortex-a57")
212 .
Case(
"0xd08",
"cortex-a72")
213 .
Case(
"0xd09",
"cortex-a73")
214 .
Case(
"0xd0a",
"cortex-a75")
215 .
Case(
"0xd0b",
"cortex-a76")
216 .
Case(
"0xd0d",
"cortex-a77")
217 .
Case(
"0xd41",
"cortex-a78")
218 .
Case(
"0xd47",
"cortex-a710")
219 .
Case(
"0xd4d",
"cortex-a715")
220 .
Case(
"0xd44",
"cortex-x1")
221 .
Case(
"0xd4c",
"cortex-x1c")
222 .
Case(
"0xd48",
"cortex-x2")
223 .
Case(
"0xd4e",
"cortex-x3")
224 .
Case(
"0xd0c",
"neoverse-n1")
225 .
Case(
"0xd49",
"neoverse-n2")
226 .
Case(
"0xd40",
"neoverse-v1")
227 .
Case(
"0xd4f",
"neoverse-v2")
231 if (Implementer ==
"0x42" || Implementer ==
"0x43") {
233 .
Case(
"0x516",
"thunderx2t99")
234 .
Case(
"0x0516",
"thunderx2t99")
235 .
Case(
"0xaf",
"thunderx2t99")
236 .
Case(
"0x0af",
"thunderx2t99")
237 .
Case(
"0xa1",
"thunderxt88")
238 .
Case(
"0x0a1",
"thunderxt88")
242 if (Implementer ==
"0x46") {
244 .
Case(
"0x001",
"a64fx")
248 if (Implementer ==
"0x4e") {
250 .
Case(
"0x004",
"carmel")
254 if (Implementer ==
"0x48")
259 .
Case(
"0xd01",
"tsv110")
262 if (Implementer ==
"0x51")
267 .
Case(
"0x06f",
"krait")
268 .
Case(
"0x201",
"kryo")
269 .
Case(
"0x205",
"kryo")
270 .
Case(
"0x211",
"kryo")
271 .
Case(
"0x800",
"cortex-a73")
272 .
Case(
"0x801",
"cortex-a73")
273 .
Case(
"0x802",
"cortex-a75")
274 .
Case(
"0x803",
"cortex-a75")
275 .
Case(
"0x804",
"cortex-a76")
276 .
Case(
"0x805",
"cortex-a76")
277 .
Case(
"0xc00",
"falkor")
278 .
Case(
"0xc01",
"saphira")
280 if (Implementer ==
"0x53") {
283 unsigned Variant = 0, Part = 0;
288 if (
I.consume_front(
"CPU variant"))
289 I.ltrim(
"\t :").getAsInteger(0, Variant);
294 if (
I.consume_front(
"CPU part"))
295 I.ltrim(
"\t :").getAsInteger(0, Part);
297 unsigned Exynos = (Variant << 12) | Part;
309 if (Implementer ==
"0xc0") {
311 .
Case(
"0xac3",
"ampere1")
312 .
Case(
"0xac4",
"ampere1a")
320StringRef getCPUNameFromS390Model(
unsigned int Id,
bool HaveVectorSupport) {
340 return HaveVectorSupport?
"z13" :
"zEC12";
343 return HaveVectorSupport?
"z14" :
"zEC12";
346 return HaveVectorSupport?
"z15" :
"zEC12";
350 return HaveVectorSupport?
"z16" :
"zEC12";
361 ProcCpuinfoContent.
split(Lines,
"\n");
365 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I)
367 size_t Pos = Lines[
I].find(
':');
369 Lines[
I].drop_front(Pos + 1).split(CPUFeatures,
' ');
377 bool HaveVectorSupport =
false;
378 for (
unsigned I = 0,
E = CPUFeatures.size();
I !=
E; ++
I) {
379 if (CPUFeatures[
I] ==
"vx")
380 HaveVectorSupport =
true;
384 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I) {
386 size_t Pos = Lines[
I].find(
"machine = ");
388 Pos +=
sizeof(
"machine = ") - 1;
390 if (!Lines[
I].drop_front(Pos).getAsInteger(10, Id))
391 return getCPUNameFromS390Model(Id, HaveVectorSupport);
403 ProcCpuinfoContent.
split(Lines,
"\n");
407 for (
unsigned I = 0,
E = Lines.size();
I !=
E; ++
I) {
409 UArch = Lines[
I].substr(5).ltrim(
"\t :");
415 .
Case(
"sifive,u74-mc",
"sifive-u74")
416 .
Case(
"sifive,bullet0",
"sifive-u74")
421#if !defined(__linux__) || !defined(__x86_64__)
424 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
426 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
428 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
430 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
432 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
434 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
436 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
438 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
440 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
442 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
444 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
446 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
448 struct bpf_prog_load_attr {
464 int fd = syscall(321 , 5 , &attr,
472 memset(&attr, 0,
sizeof(attr));
477 fd = syscall(321 , 5 , &attr,
sizeof(attr));
486#if defined(__i386__) || defined(_M_IX86) || \
487 defined(__x86_64__) || defined(_M_X64)
496static bool isCpuIdSupported() {
497#if defined(__GNUC__) || defined(__clang__)
499 int __cpuid_supported;
502 " movl %%eax,%%ecx\n"
503 " xorl $0x00200000,%%eax\n"
509 " cmpl %%eax,%%ecx\n"
513 :
"=r"(__cpuid_supported)
516 if (!__cpuid_supported)
526static bool getX86CpuIDAndInfo(
unsigned value,
unsigned *rEAX,
unsigned *rEBX,
527 unsigned *rECX,
unsigned *rEDX) {
528#if defined(__GNUC__) || defined(__clang__)
529#if defined(__x86_64__)
532 __asm__(
"movq\t%%rbx, %%rsi\n\t"
534 "xchgq\t%%rbx, %%rsi\n\t"
535 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
538#elif defined(__i386__)
539 __asm__(
"movl\t%%ebx, %%esi\n\t"
541 "xchgl\t%%ebx, %%esi\n\t"
542 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
548#elif defined(_MSC_VER)
551 __cpuid(registers,
value);
552 *rEAX = registers[0];
553 *rEBX = registers[1];
554 *rECX = registers[2];
555 *rEDX = registers[3];
567VendorSignatures getVendorSignature(
unsigned *MaxLeaf) {
568 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
569 if (MaxLeaf ==
nullptr)
574 if (!isCpuIdSupported())
575 return VendorSignatures::UNKNOWN;
577 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
578 return VendorSignatures::UNKNOWN;
581 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
582 return VendorSignatures::GENUINE_INTEL;
585 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
586 return VendorSignatures::AUTHENTIC_AMD;
588 return VendorSignatures::UNKNOWN;
601static bool getX86CpuIDAndInfoEx(
unsigned value,
unsigned subleaf,
602 unsigned *rEAX,
unsigned *rEBX,
unsigned *rECX,
604#if defined(__GNUC__) || defined(__clang__)
605#if defined(__x86_64__)
608 __asm__(
"movq\t%%rbx, %%rsi\n\t"
610 "xchgq\t%%rbx, %%rsi\n\t"
611 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
612 :
"a"(
value),
"c"(subleaf));
614#elif defined(__i386__)
615 __asm__(
"movl\t%%ebx, %%esi\n\t"
617 "xchgl\t%%ebx, %%esi\n\t"
618 :
"=a"(*rEAX),
"=S"(*rEBX),
"=c"(*rECX),
"=d"(*rEDX)
619 :
"a"(
value),
"c"(subleaf));
624#elif defined(_MSC_VER)
626 __cpuidex(registers,
value, subleaf);
627 *rEAX = registers[0];
628 *rEBX = registers[1];
629 *rECX = registers[2];
630 *rEDX = registers[3];
638static bool getX86XCR0(
unsigned *rEAX,
unsigned *rEDX) {
639#if defined(__GNUC__) || defined(__clang__)
643 __asm__(
".byte 0x0f, 0x01, 0xd0" :
"=a"(*rEAX),
"=d"(*rEDX) :
"c"(0));
645#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
646 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
655static void detectX86FamilyModel(
unsigned EAX,
unsigned *Family,
657 *Family = (
EAX >> 8) & 0xf;
659 if (*Family == 6 || *Family == 0xf) {
662 *Family += (
EAX >> 20) & 0xff;
669getIntelProcessorTypeAndSubtype(
unsigned Family,
unsigned Model,
670 const unsigned *Features,
671 unsigned *
Type,
unsigned *Subtype) {
672 auto testFeature = [&](
unsigned F) {
673 return (Features[
F / 32] & (1U << (
F % 32))) != 0;
686 if (testFeature(X86::FEATURE_MMX)) {
702 *
Type = X86::INTEL_CORE2;
711 *
Type = X86::INTEL_CORE2;
720 *
Type = X86::INTEL_COREI7;
721 *Subtype = X86::INTEL_COREI7_NEHALEM;
728 *
Type = X86::INTEL_COREI7;
729 *Subtype = X86::INTEL_COREI7_WESTMERE;
735 *
Type = X86::INTEL_COREI7;
736 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
741 *
Type = X86::INTEL_COREI7;
742 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
751 *
Type = X86::INTEL_COREI7;
752 *Subtype = X86::INTEL_COREI7_HASWELL;
761 *
Type = X86::INTEL_COREI7;
762 *Subtype = X86::INTEL_COREI7_BROADWELL;
773 *
Type = X86::INTEL_COREI7;
774 *Subtype = X86::INTEL_COREI7_SKYLAKE;
780 *
Type = X86::INTEL_COREI7;
781 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
786 *
Type = X86::INTEL_COREI7;
787 if (testFeature(X86::FEATURE_AVX512BF16)) {
789 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
790 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
792 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
794 CPU =
"skylake-avx512";
795 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
802 *
Type = X86::INTEL_COREI7;
803 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
809 CPU =
"icelake-client";
810 *
Type = X86::INTEL_COREI7;
811 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
818 *
Type = X86::INTEL_COREI7;
819 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
831 *
Type = X86::INTEL_COREI7;
832 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
838 CPU =
"graniterapids";
839 *
Type = X86::INTEL_COREI7;
840 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
846 CPU =
"icelake-server";
847 *
Type = X86::INTEL_COREI7;
848 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
855 CPU =
"sapphirerapids";
856 *
Type = X86::INTEL_COREI7;
857 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
866 *
Type = X86::INTEL_BONNELL;
877 *
Type = X86::INTEL_SILVERMONT;
883 *
Type = X86::INTEL_GOLDMONT;
886 CPU =
"goldmont-plus";
887 *
Type = X86::INTEL_GOLDMONT_PLUS;
891 *
Type = X86::INTEL_TREMONT;
896 CPU =
"sierraforest";
897 *
Type = X86::INTEL_SIERRAFOREST;
903 *
Type = X86::INTEL_GRANDRIDGE;
909 *
Type = X86::INTEL_KNL;
913 *
Type = X86::INTEL_KNM;
920 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
922 }
else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
923 CPU =
"icelake-client";
924 }
else if (testFeature(X86::FEATURE_AVX512VBMI)) {
926 }
else if (testFeature(X86::FEATURE_AVX512BF16)) {
928 }
else if (testFeature(X86::FEATURE_AVX512VNNI)) {
930 }
else if (testFeature(X86::FEATURE_AVX512VL)) {
931 CPU =
"skylake-avx512";
932 }
else if (testFeature(X86::FEATURE_AVX512ER)) {
934 }
else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
935 if (testFeature(X86::FEATURE_SHA))
939 }
else if (testFeature(X86::FEATURE_ADX)) {
941 }
else if (testFeature(X86::FEATURE_AVX2)) {
943 }
else if (testFeature(X86::FEATURE_AVX)) {
945 }
else if (testFeature(X86::FEATURE_SSE4_2)) {
946 if (testFeature(X86::FEATURE_MOVBE))
950 }
else if (testFeature(X86::FEATURE_SSE4_1)) {
952 }
else if (testFeature(X86::FEATURE_SSSE3)) {
953 if (testFeature(X86::FEATURE_MOVBE))
957 }
else if (testFeature(X86::FEATURE_64BIT)) {
959 }
else if (testFeature(X86::FEATURE_SSE3)) {
961 }
else if (testFeature(X86::FEATURE_SSE2)) {
963 }
else if (testFeature(X86::FEATURE_SSE)) {
965 }
else if (testFeature(X86::FEATURE_MMX)) {
974 if (testFeature(X86::FEATURE_64BIT)) {
978 if (testFeature(X86::FEATURE_SSE3)) {
993getAMDProcessorTypeAndSubtype(
unsigned Family,
unsigned Model,
994 const unsigned *Features,
995 unsigned *
Type,
unsigned *Subtype) {
996 auto testFeature = [&](
unsigned F) {
997 return (Features[
F / 32] & (1U << (
F % 32))) != 0;
1026 if (testFeature(X86::FEATURE_SSE)) {
1033 if (testFeature(X86::FEATURE_SSE3)) {
1041 *
Type = X86::AMDFAM10H;
1044 *Subtype = X86::AMDFAM10H_BARCELONA;
1047 *Subtype = X86::AMDFAM10H_SHANGHAI;
1050 *Subtype = X86::AMDFAM10H_ISTANBUL;
1056 *
Type = X86::AMD_BTVER1;
1060 *
Type = X86::AMDFAM15H;
1061 if (Model >= 0x60 && Model <= 0x7f) {
1063 *Subtype = X86::AMDFAM15H_BDVER4;
1066 if (Model >= 0x30 && Model <= 0x3f) {
1068 *Subtype = X86::AMDFAM15H_BDVER3;
1071 if ((Model >= 0x10 && Model <= 0x1f) ||
Model == 0x02) {
1073 *Subtype = X86::AMDFAM15H_BDVER2;
1076 if (Model <= 0x0f) {
1077 *Subtype = X86::AMDFAM15H_BDVER1;
1083 *
Type = X86::AMD_BTVER2;
1087 *
Type = X86::AMDFAM17H;
1088 if ((Model >= 0x30 && Model <= 0x3f) ||
Model == 0x71) {
1090 *Subtype = X86::AMDFAM17H_ZNVER2;
1093 if (Model <= 0x0f) {
1094 *Subtype = X86::AMDFAM17H_ZNVER1;
1100 *
Type = X86::AMDFAM19H;
1101 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x5f)) {
1107 *Subtype = X86::AMDFAM19H_ZNVER3;
1110 if ((Model >= 0x10 && Model <= 0x1f) ||
1112 (Model >= 0x78 && Model <= 0x7b) ||
1115 *Subtype = X86::AMDFAM19H_ZNVER4;
1126static void getAvailableFeatures(
unsigned ECX,
unsigned EDX,
unsigned MaxLeaf,
1127 unsigned *Features) {
1130 auto setFeature = [&](
unsigned F) {
1131 Features[
F / 32] |= 1U << (
F % 32);
1134 if ((EDX >> 15) & 1)
1135 setFeature(X86::FEATURE_CMOV);
1136 if ((EDX >> 23) & 1)
1137 setFeature(X86::FEATURE_MMX);
1138 if ((EDX >> 25) & 1)
1139 setFeature(X86::FEATURE_SSE);
1140 if ((EDX >> 26) & 1)
1141 setFeature(X86::FEATURE_SSE2);
1144 setFeature(X86::FEATURE_SSE3);
1146 setFeature(X86::FEATURE_PCLMUL);
1148 setFeature(X86::FEATURE_SSSE3);
1149 if ((ECX >> 12) & 1)
1150 setFeature(X86::FEATURE_FMA);
1151 if ((ECX >> 19) & 1)
1152 setFeature(X86::FEATURE_SSE4_1);
1153 if ((ECX >> 20) & 1) {
1154 setFeature(X86::FEATURE_SSE4_2);
1155 setFeature(X86::FEATURE_CRC32);
1157 if ((ECX >> 23) & 1)
1158 setFeature(X86::FEATURE_POPCNT);
1159 if ((ECX >> 25) & 1)
1160 setFeature(X86::FEATURE_AES);
1162 if ((ECX >> 22) & 1)
1163 setFeature(X86::FEATURE_MOVBE);
1168 const unsigned AVXBits = (1 << 27) | (1 << 28);
1169 bool HasAVX = ((
ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1170 ((
EAX & 0x6) == 0x6);
1171#if defined(__APPLE__)
1175 bool HasAVX512Save =
true;
1178 bool HasAVX512Save = HasAVX && ((
EAX & 0xe0) == 0xe0);
1182 setFeature(X86::FEATURE_AVX);
1185 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1187 if (HasLeaf7 && ((EBX >> 3) & 1))
1188 setFeature(X86::FEATURE_BMI);
1189 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1190 setFeature(X86::FEATURE_AVX2);
1191 if (HasLeaf7 && ((EBX >> 8) & 1))
1192 setFeature(X86::FEATURE_BMI2);
1193 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
1194 setFeature(X86::FEATURE_AVX512F);
1195 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1196 setFeature(X86::FEATURE_AVX512DQ);
1197 if (HasLeaf7 && ((EBX >> 19) & 1))
1198 setFeature(X86::FEATURE_ADX);
1199 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1200 setFeature(X86::FEATURE_AVX512IFMA);
1201 if (HasLeaf7 && ((EBX >> 23) & 1))
1202 setFeature(X86::FEATURE_CLFLUSHOPT);
1203 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1204 setFeature(X86::FEATURE_AVX512PF);
1205 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1206 setFeature(X86::FEATURE_AVX512ER);
1207 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1208 setFeature(X86::FEATURE_AVX512CD);
1209 if (HasLeaf7 && ((EBX >> 29) & 1))
1210 setFeature(X86::FEATURE_SHA);
1211 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1212 setFeature(X86::FEATURE_AVX512BW);
1213 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1214 setFeature(X86::FEATURE_AVX512VL);
1216 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1217 setFeature(X86::FEATURE_AVX512VBMI);
1218 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1219 setFeature(X86::FEATURE_AVX512VBMI2);
1220 if (HasLeaf7 && ((ECX >> 8) & 1))
1221 setFeature(X86::FEATURE_GFNI);
1222 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1223 setFeature(X86::FEATURE_VPCLMULQDQ);
1224 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1225 setFeature(X86::FEATURE_AVX512VNNI);
1226 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1227 setFeature(X86::FEATURE_AVX512BITALG);
1228 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1229 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1231 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1232 setFeature(X86::FEATURE_AVX5124VNNIW);
1233 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1234 setFeature(X86::FEATURE_AVX5124FMAPS);
1235 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1236 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1238 bool HasLeaf7Subleaf1 =
1239 MaxLeaf >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1240 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1241 setFeature(X86::FEATURE_AVX512BF16);
1243 unsigned MaxExtLevel;
1244 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1246 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1247 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1248 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1249 setFeature(X86::FEATURE_SSE4_A);
1250 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1251 setFeature(X86::FEATURE_XOP);
1252 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1253 setFeature(X86::FEATURE_FMA4);
1255 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1256 setFeature(X86::FEATURE_64BIT);
1260 unsigned MaxLeaf = 0;
1262 if (Vendor == VendorSignatures::UNKNOWN)
1266 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1268 unsigned Family = 0,
Model = 0;
1270 detectX86FamilyModel(EAX, &Family, &Model);
1271 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1276 unsigned Subtype = 0;
1280 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1281 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1283 }
else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1284 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &
Type,
1294#elif defined(__APPLE__) && defined(__powerpc__)
1296 host_basic_info_data_t hostInfo;
1297 mach_msg_type_number_t infoCount;
1299 infoCount = HOST_BASIC_INFO_COUNT;
1300 mach_port_t hostPort = mach_host_self();
1301 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1303 mach_port_deallocate(mach_task_self(), hostPort);
1305 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1308 switch (hostInfo.cpu_subtype) {
1338#elif defined(__linux__) && defined(__powerpc__)
1344#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1350#elif defined(__linux__) && defined(__s390x__)
1356#elif defined(__MVS__)
1361 int *StartToCVTOffset =
reinterpret_cast<int *
>(0x10);
1364 int ReadValue = *StartToCVTOffset;
1366 ReadValue = (ReadValue & 0x7FFFFFFF);
1367 char *CVT =
reinterpret_cast<char *
>(ReadValue);
1372 Id = decodePackedBCD<uint16_t>(Id,
false);
1376 bool HaveVectorSupport = CVT[244] & 0x80;
1377 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1379#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1380#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1381#define CPUFAMILY_ARM_CYCLONE 0x37a09642
1382#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1383#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1384#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1385#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1386#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1387#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1388#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1392 size_t Length =
sizeof(Family);
1393 sysctlbyname(
"hw.cpufamily", &Family, &
Length, NULL, 0);
1396 case CPUFAMILY_ARM_SWIFT:
1398 case CPUFAMILY_ARM_CYCLONE:
1400 case CPUFAMILY_ARM_TYPHOON:
1402 case CPUFAMILY_ARM_TWISTER:
1404 case CPUFAMILY_ARM_HURRICANE:
1406 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1408 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1410 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1412 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1421 switch (_system_configuration.implementation) {
1423 if (_system_configuration.version == PV_4_3)
1427 if (_system_configuration.version == PV_5)
1431 if (_system_configuration.version == PV_6_Compat)
1451#elif defined(__loongarch__)
1455 __asm__(
"cpucfg %[prid], $zero\n\t" : [prid]
"=r"(processor_id));
1456 switch (processor_id & 0xff00) {
1465#elif defined(__riscv)
1467#if defined(__linux__)
1472#if __riscv_xlen == 64
1473 return "generic-rv64";
1474#elif __riscv_xlen == 32
1475 return "generic-rv32";
1477#error "Unhandled value of __riscv_xlen"
1481#elif defined(__sparc__)
1482#if defined(__linux__)
1485 ProcCpuinfoContent.
split(Lines,
"\n");
1489 for (
unsigned I = 0,
E =
Lines.size();
I !=
E; ++
I) {
1491 Cpu =
Lines[
I].substr(5).ltrim(
"\t :");
1523#if defined(__linux__)
1527#elif defined(__sun__) && defined(__svr4__)
1531 kstat_named_t *brand = NULL;
1535 ksp = kstat_lookup(kc,
const_cast<char *
>(
"cpu_info"), -1, NULL);
1536 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1537 ksp->ks_type == KSTAT_TYPE_NAMED)
1539 (kstat_named_t *)kstat_data_lookup(ksp,
const_cast<char *
>(
"brand"));
1540 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1541 buf = KSTAT_NAMED_STR_PTR(brand);
1546 .
Case(
"TMS390S10",
"supersparc")
1547 .
Case(
"TMS390Z50",
"supersparc")
1550 .
Case(
"MB86904",
"supersparc")
1551 .
Case(
"MB86907",
"supersparc")
1552 .
Case(
"RT623",
"hypersparc")
1553 .
Case(
"RT625",
"hypersparc")
1554 .
Case(
"RT626",
"hypersparc")
1555 .
Case(
"UltraSPARC-I",
"ultrasparc")
1556 .
Case(
"UltraSPARC-II",
"ultrasparc")
1557 .
Case(
"UltraSPARC-IIe",
"ultrasparc")
1558 .
Case(
"UltraSPARC-IIi",
"ultrasparc")
1559 .
Case(
"SPARC64-III",
"ultrasparc")
1560 .
Case(
"SPARC64-IV",
"ultrasparc")
1561 .
Case(
"UltraSPARC-III",
"ultrasparc3")
1562 .
Case(
"UltraSPARC-III+",
"ultrasparc3")
1563 .
Case(
"UltraSPARC-IIIi",
"ultrasparc3")
1564 .
Case(
"UltraSPARC-IIIi+",
"ultrasparc3")
1565 .
Case(
"UltraSPARC-IV",
"ultrasparc3")
1566 .
Case(
"UltraSPARC-IV+",
"ultrasparc3")
1567 .
Case(
"SPARC64-V",
"ultrasparc3")
1568 .
Case(
"SPARC64-VI",
"ultrasparc3")
1569 .
Case(
"SPARC64-VII",
"ultrasparc3")
1570 .
Case(
"UltraSPARC-T1",
"niagara")
1571 .
Case(
"UltraSPARC-T2",
"niagara2")
1572 .
Case(
"UltraSPARC-T2",
"niagara2")
1573 .
Case(
"UltraSPARC-T2+",
"niagara2")
1574 .
Case(
"SPARC-T3",
"niagara3")
1575 .
Case(
"SPARC-T4",
"niagara4")
1576 .
Case(
"SPARC-T5",
"niagara4")
1578 .
Case(
"SPARC-M7",
"niagara4" )
1579 .
Case(
"SPARC-S7",
"niagara4" )
1580 .
Case(
"SPARC-M8",
"niagara4" )
1603#if defined(__i386__) || defined(_M_IX86) || \
1604 defined(__x86_64__) || defined(_M_X64)
1609 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1612 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1614 Features[
"cx8"] = (
EDX >> 8) & 1;
1615 Features[
"cmov"] = (
EDX >> 15) & 1;
1616 Features[
"mmx"] = (
EDX >> 23) & 1;
1617 Features[
"fxsr"] = (
EDX >> 24) & 1;
1618 Features[
"sse"] = (
EDX >> 25) & 1;
1619 Features[
"sse2"] = (
EDX >> 26) & 1;
1621 Features[
"sse3"] = (
ECX >> 0) & 1;
1622 Features[
"pclmul"] = (
ECX >> 1) & 1;
1623 Features[
"ssse3"] = (
ECX >> 9) & 1;
1624 Features[
"cx16"] = (
ECX >> 13) & 1;
1625 Features[
"sse4.1"] = (
ECX >> 19) & 1;
1626 Features[
"sse4.2"] = (
ECX >> 20) & 1;
1627 Features[
"crc32"] = Features[
"sse4.2"];
1628 Features[
"movbe"] = (
ECX >> 22) & 1;
1629 Features[
"popcnt"] = (
ECX >> 23) & 1;
1630 Features[
"aes"] = (
ECX >> 25) & 1;
1631 Features[
"rdrnd"] = (
ECX >> 30) & 1;
1636 bool HasXSave = ((
ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1637 bool HasAVXSave = HasXSave && ((
ECX >> 28) & 1) && ((
EAX & 0x6) == 0x6);
1638#if defined(__APPLE__)
1642 bool HasAVX512Save =
true;
1645 bool HasAVX512Save = HasAVXSave && ((
EAX & 0xe0) == 0xe0);
1648 const unsigned AMXBits = (1 << 17) | (1 << 18);
1649 bool HasAMXSave = HasXSave && ((
EAX & AMXBits) == AMXBits);
1651 Features[
"avx"] = HasAVXSave;
1652 Features[
"fma"] = ((
ECX >> 12) & 1) && HasAVXSave;
1654 Features[
"xsave"] = ((
ECX >> 26) & 1) && HasAVXSave;
1655 Features[
"f16c"] = ((
ECX >> 29) & 1) && HasAVXSave;
1657 unsigned MaxExtLevel;
1658 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1660 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1661 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1662 Features[
"sahf"] = HasExtLeaf1 && ((
ECX >> 0) & 1);
1663 Features[
"lzcnt"] = HasExtLeaf1 && ((
ECX >> 5) & 1);
1664 Features[
"sse4a"] = HasExtLeaf1 && ((
ECX >> 6) & 1);
1665 Features[
"prfchw"] = HasExtLeaf1 && ((
ECX >> 8) & 1);
1666 Features[
"xop"] = HasExtLeaf1 && ((
ECX >> 11) & 1) && HasAVXSave;
1667 Features[
"lwp"] = HasExtLeaf1 && ((
ECX >> 15) & 1);
1668 Features[
"fma4"] = HasExtLeaf1 && ((
ECX >> 16) & 1) && HasAVXSave;
1669 Features[
"tbm"] = HasExtLeaf1 && ((
ECX >> 21) & 1);
1670 Features[
"mwaitx"] = HasExtLeaf1 && ((
ECX >> 29) & 1);
1672 Features[
"64bit"] = HasExtLeaf1 && ((
EDX >> 29) & 1);
1676 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1677 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1678 Features[
"clzero"] = HasExtLeaf8 && ((
EBX >> 0) & 1);
1679 Features[
"rdpru"] = HasExtLeaf8 && ((
EBX >> 4) & 1);
1680 Features[
"wbnoinvd"] = HasExtLeaf8 && ((
EBX >> 9) & 1);
1683 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1685 Features[
"fsgsbase"] = HasLeaf7 && ((
EBX >> 0) & 1);
1686 Features[
"sgx"] = HasLeaf7 && ((
EBX >> 2) & 1);
1687 Features[
"bmi"] = HasLeaf7 && ((
EBX >> 3) & 1);
1689 Features[
"avx2"] = HasLeaf7 && ((
EBX >> 5) & 1) && HasAVXSave;
1690 Features[
"bmi2"] = HasLeaf7 && ((
EBX >> 8) & 1);
1691 Features[
"invpcid"] = HasLeaf7 && ((
EBX >> 10) & 1);
1692 Features[
"rtm"] = HasLeaf7 && ((
EBX >> 11) & 1);
1694 Features[
"avx512f"] = HasLeaf7 && ((
EBX >> 16) & 1) && HasAVX512Save;
1695 Features[
"avx512dq"] = HasLeaf7 && ((
EBX >> 17) & 1) && HasAVX512Save;
1696 Features[
"rdseed"] = HasLeaf7 && ((
EBX >> 18) & 1);
1697 Features[
"adx"] = HasLeaf7 && ((
EBX >> 19) & 1);
1698 Features[
"avx512ifma"] = HasLeaf7 && ((
EBX >> 21) & 1) && HasAVX512Save;
1699 Features[
"clflushopt"] = HasLeaf7 && ((
EBX >> 23) & 1);
1700 Features[
"clwb"] = HasLeaf7 && ((
EBX >> 24) & 1);
1701 Features[
"avx512pf"] = HasLeaf7 && ((
EBX >> 26) & 1) && HasAVX512Save;
1702 Features[
"avx512er"] = HasLeaf7 && ((
EBX >> 27) & 1) && HasAVX512Save;
1703 Features[
"avx512cd"] = HasLeaf7 && ((
EBX >> 28) & 1) && HasAVX512Save;
1704 Features[
"sha"] = HasLeaf7 && ((
EBX >> 29) & 1);
1705 Features[
"avx512bw"] = HasLeaf7 && ((
EBX >> 30) & 1) && HasAVX512Save;
1706 Features[
"avx512vl"] = HasLeaf7 && ((
EBX >> 31) & 1) && HasAVX512Save;
1708 Features[
"prefetchwt1"] = HasLeaf7 && ((
ECX >> 0) & 1);
1709 Features[
"avx512vbmi"] = HasLeaf7 && ((
ECX >> 1) & 1) && HasAVX512Save;
1710 Features[
"pku"] = HasLeaf7 && ((
ECX >> 4) & 1);
1711 Features[
"waitpkg"] = HasLeaf7 && ((
ECX >> 5) & 1);
1712 Features[
"avx512vbmi2"] = HasLeaf7 && ((
ECX >> 6) & 1) && HasAVX512Save;
1713 Features[
"shstk"] = HasLeaf7 && ((
ECX >> 7) & 1);
1714 Features[
"gfni"] = HasLeaf7 && ((
ECX >> 8) & 1);
1715 Features[
"vaes"] = HasLeaf7 && ((
ECX >> 9) & 1) && HasAVXSave;
1716 Features[
"vpclmulqdq"] = HasLeaf7 && ((
ECX >> 10) & 1) && HasAVXSave;
1717 Features[
"avx512vnni"] = HasLeaf7 && ((
ECX >> 11) & 1) && HasAVX512Save;
1718 Features[
"avx512bitalg"] = HasLeaf7 && ((
ECX >> 12) & 1) && HasAVX512Save;
1719 Features[
"avx512vpopcntdq"] = HasLeaf7 && ((
ECX >> 14) & 1) && HasAVX512Save;
1720 Features[
"rdpid"] = HasLeaf7 && ((
ECX >> 22) & 1);
1721 Features[
"kl"] = HasLeaf7 && ((
ECX >> 23) & 1);
1722 Features[
"cldemote"] = HasLeaf7 && ((
ECX >> 25) & 1);
1723 Features[
"movdiri"] = HasLeaf7 && ((
ECX >> 27) & 1);
1724 Features[
"movdir64b"] = HasLeaf7 && ((
ECX >> 28) & 1);
1725 Features[
"enqcmd"] = HasLeaf7 && ((
ECX >> 29) & 1);
1727 Features[
"uintr"] = HasLeaf7 && ((
EDX >> 5) & 1);
1728 Features[
"avx512vp2intersect"] =
1729 HasLeaf7 && ((
EDX >> 8) & 1) && HasAVX512Save;
1730 Features[
"serialize"] = HasLeaf7 && ((
EDX >> 14) & 1);
1731 Features[
"tsxldtrk"] = HasLeaf7 && ((
EDX >> 16) & 1);
1742 Features[
"pconfig"] = HasLeaf7 && ((
EDX >> 18) & 1);
1743 Features[
"amx-bf16"] = HasLeaf7 && ((
EDX >> 22) & 1) && HasAMXSave;
1744 Features[
"avx512fp16"] = HasLeaf7 && ((
EDX >> 23) & 1) && HasAVX512Save;
1745 Features[
"amx-tile"] = HasLeaf7 && ((
EDX >> 24) & 1) && HasAMXSave;
1746 Features[
"amx-int8"] = HasLeaf7 && ((
EDX >> 25) & 1) && HasAMXSave;
1747 bool HasLeaf7Subleaf1 =
1748 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1749 Features[
"raoint"] = HasLeaf7Subleaf1 && ((
EAX >> 3) & 1);
1750 Features[
"avxvnni"] = HasLeaf7Subleaf1 && ((
EAX >> 4) & 1) && HasAVXSave;
1751 Features[
"avx512bf16"] = HasLeaf7Subleaf1 && ((
EAX >> 5) & 1) && HasAVX512Save;
1752 Features[
"amx-fp16"] = HasLeaf7Subleaf1 && ((
EAX >> 21) & 1) && HasAMXSave;
1753 Features[
"cmpccxadd"] = HasLeaf7Subleaf1 && ((
EAX >> 7) & 1);
1754 Features[
"hreset"] = HasLeaf7Subleaf1 && ((
EAX >> 22) & 1);
1755 Features[
"avxifma"] = HasLeaf7Subleaf1 && ((
EAX >> 23) & 1) && HasAVXSave;
1756 Features[
"avxvnniint8"] = HasLeaf7Subleaf1 && ((
EDX >> 4) & 1) && HasAVXSave;
1757 Features[
"avxneconvert"] = HasLeaf7Subleaf1 && ((
EDX >> 5) & 1) && HasAVXSave;
1758 Features[
"prefetchi"] = HasLeaf7Subleaf1 && ((
EDX >> 14) & 1);
1760 bool HasLeafD = MaxLevel >= 0xd &&
1761 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1764 Features[
"xsaveopt"] = HasLeafD && ((
EAX >> 0) & 1) && HasAVXSave;
1765 Features[
"xsavec"] = HasLeafD && ((
EAX >> 1) & 1) && HasAVXSave;
1766 Features[
"xsaves"] = HasLeafD && ((
EAX >> 3) & 1) && HasAVXSave;
1768 bool HasLeaf14 = MaxLevel >= 0x14 &&
1769 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1771 Features[
"ptwrite"] = HasLeaf14 && ((
EBX >> 4) & 1);
1774 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1775 Features[
"widekl"] = HasLeaf7 && HasLeaf19 && ((
EBX >> 2) & 1);
1779#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1786 P->getBuffer().split(Lines,
"\n");
1791 for (
unsigned I = 0,
E =
Lines.size();
I !=
E; ++
I)
1793 Lines[
I].split(CPUFeatures,
' ');
1797#if defined(__aarch64__)
1799 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1805#if defined(__aarch64__)
1806 .
Case(
"asimd",
"neon")
1807 .
Case(
"fp",
"fp-armv8")
1808 .
Case(
"crc32",
"crc")
1809 .
Case(
"atomics",
"lse")
1811 .
Case(
"sve2",
"sve2")
1813 .
Case(
"half",
"fp16")
1814 .
Case(
"neon",
"neon")
1815 .
Case(
"vfpv3",
"vfp3")
1816 .
Case(
"vfpv3d16",
"vfp3d16")
1817 .
Case(
"vfpv4",
"vfp4")
1818 .
Case(
"idiva",
"hwdiv-arm")
1819 .
Case(
"idivt",
"hwdiv")
1823#if defined(__aarch64__)
1826 if (CPUFeatures[
I] ==
"aes")
1828 else if (CPUFeatures[
I] ==
"pmull")
1829 crypto |= CAP_PMULL;
1830 else if (CPUFeatures[
I] ==
"sha1")
1832 else if (CPUFeatures[
I] ==
"sha2")
1836 if (LLVMFeatureStr !=
"")
1837 Features[LLVMFeatureStr] =
true;
1840#if defined(__aarch64__)
1842 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1843 Features[
"crypto"] =
true;
1848#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1850 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1851 Features[
"neon"] =
true;
1852 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1853 Features[
"crc"] =
true;
1854 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1855 Features[
"crypto"] =
true;
1859#elif defined(__linux__) && defined(__loongarch__)
1860#include <sys/auxv.h>
1862 unsigned long hwcap = getauxval(AT_HWCAP);
1863 bool HasFPU = hwcap & (1UL << 3);
1865 __asm__(
"cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2]
"+r"(cpucfg2));
1867 Features[
"f"] = HasFPU && (cpucfg2 & (1U << 1));
1868 Features[
"d"] = HasFPU && (cpucfg2 & (1U << 2));
1870 Features[
"lsx"] = hwcap & (1UL << 4);
1871 Features[
"lasx"] = hwcap & (1UL << 5);
1872 Features[
"lvz"] = hwcap & (1UL << 9);
1881 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1893#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
1895 if (CPU ==
"generic")
1898 <<
" Host CPU: " << CPU <<
'\n';
This file defines the StringMap class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
Given that RA is a live value
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
static bool startswith(StringRef Magic, const char(&S)[N])
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Represents either an error or a value T.
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
constexpr bool empty() const
empty - Check if the string is empty.
bool endswith(StringRef Suffix) const
static constexpr size_t npos
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
StringSwitch & StartsWith(StringLiteral S, T Value)
Triple - Helper class for working with autoconf configuration names.
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
std::string normalize() const
Return the normalized form of this triple's string.
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
const std::string & str() const
bool isArch64Bit() const
Test whether the architecture is 64-bit.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
The instances of the Type class are immutable: once they are created, they are never changed.
This class implements an extremely fast bulk output stream that can only output to a stream.
@ CPU_SUBTYPE_POWERPC_970
@ CPU_SUBTYPE_POWERPC_604e
@ CPU_SUBTYPE_POWERPC_603e
@ CPU_SUBTYPE_POWERPC_7400
@ CPU_SUBTYPE_POWERPC_604
@ CPU_SUBTYPE_POWERPC_750
@ CPU_SUBTYPE_POWERPC_601
@ CPU_SUBTYPE_POWERPC_620
@ CPU_SUBTYPE_POWERPC_603ev
@ CPU_SUBTYPE_POWERPC_603
@ CPU_SUBTYPE_POWERPC_7450
@ CPU_SUBTYPE_POWERPC_602
Helper functions to extract CPU details from CPUID on x86.
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
StringRef getHostCPUNameForBPF()
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
void printDefaultTargetAndDetectedCPU(raw_ostream &OS)
This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...
bool getHostCPUFeatures(StringMap< bool, MallocAllocator > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
std::string getDefaultTargetTriple()
getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...
This is an optimization pass for GlobalISel generic memory operations.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.