LLVM 18.0.0git
Host.cpp
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1//===-- Host.cpp - Implement OS Host Detection ------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the operating system Host detection.
10//
11//===----------------------------------------------------------------------===//
12
15#include "llvm/ADT/StringMap.h"
16#include "llvm/ADT/StringRef.h"
18#include "llvm/Config/llvm-config.h"
23#include <string.h>
24
25// Include the platform-specific parts of this class.
26#ifdef LLVM_ON_UNIX
27#include "Unix/Host.inc"
28#include <sched.h>
29#endif
30#ifdef _WIN32
31#include "Windows/Host.inc"
32#endif
33#ifdef _MSC_VER
34#include <intrin.h>
35#endif
36#ifdef __MVS__
37#include "llvm/Support/BCD.h"
38#endif
39#if defined(__APPLE__)
40#include <mach/host_info.h>
41#include <mach/mach.h>
42#include <mach/mach_host.h>
43#include <mach/machine.h>
44#include <sys/param.h>
45#include <sys/sysctl.h>
46#endif
47#ifdef _AIX
48#include <sys/systemcfg.h>
49#endif
50#if defined(__sun__) && defined(__svr4__)
51#include <kstat.h>
52#endif
53
54#define DEBUG_TYPE "host-detection"
55
56//===----------------------------------------------------------------------===//
57//
58// Implementations of the CPU detection routines
59//
60//===----------------------------------------------------------------------===//
61
62using namespace llvm;
63
64static std::unique_ptr<llvm::MemoryBuffer>
68 if (std::error_code EC = Text.getError()) {
69 llvm::errs() << "Can't read "
70 << "/proc/cpuinfo: " << EC.message() << "\n";
71 return nullptr;
72 }
73 return std::move(*Text);
74}
75
77 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
78 // and so we must use an operating-system interface to determine the current
79 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
80 const char *generic = "generic";
81
82 // The cpu line is second (after the 'processor: 0' line), so if this
83 // buffer is too small then something has changed (or is wrong).
84 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin();
85 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end();
86
87 StringRef::const_iterator CIP = CPUInfoStart;
88
89 StringRef::const_iterator CPUStart = nullptr;
90 size_t CPULen = 0;
91
92 // We need to find the first line which starts with cpu, spaces, and a colon.
93 // After the colon, there may be some additional spaces and then the cpu type.
94 while (CIP < CPUInfoEnd && CPUStart == nullptr) {
95 if (CIP < CPUInfoEnd && *CIP == '\n')
96 ++CIP;
97
98 if (CIP < CPUInfoEnd && *CIP == 'c') {
99 ++CIP;
100 if (CIP < CPUInfoEnd && *CIP == 'p') {
101 ++CIP;
102 if (CIP < CPUInfoEnd && *CIP == 'u') {
103 ++CIP;
104 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
105 ++CIP;
106
107 if (CIP < CPUInfoEnd && *CIP == ':') {
108 ++CIP;
109 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
110 ++CIP;
111
112 if (CIP < CPUInfoEnd) {
113 CPUStart = CIP;
114 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
115 *CIP != ',' && *CIP != '\n'))
116 ++CIP;
117 CPULen = CIP - CPUStart;
118 }
119 }
120 }
121 }
122 }
123
124 if (CPUStart == nullptr)
125 while (CIP < CPUInfoEnd && *CIP != '\n')
126 ++CIP;
127 }
128
129 if (CPUStart == nullptr)
130 return generic;
131
132 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
133 .Case("604e", "604e")
134 .Case("604", "604")
135 .Case("7400", "7400")
136 .Case("7410", "7400")
137 .Case("7447", "7400")
138 .Case("7455", "7450")
139 .Case("G4", "g4")
140 .Case("POWER4", "970")
141 .Case("PPC970FX", "970")
142 .Case("PPC970MP", "970")
143 .Case("G5", "g5")
144 .Case("POWER5", "g5")
145 .Case("A2", "a2")
146 .Case("POWER6", "pwr6")
147 .Case("POWER7", "pwr7")
148 .Case("POWER8", "pwr8")
149 .Case("POWER8E", "pwr8")
150 .Case("POWER8NVL", "pwr8")
151 .Case("POWER9", "pwr9")
152 .Case("POWER10", "pwr10")
153 // FIXME: If we get a simulator or machine with the capabilities of
154 // mcpu=future, we should revisit this and add the name reported by the
155 // simulator/machine.
156 .Default(generic);
157}
158
160 // The cpuid register on arm is not accessible from user space. On Linux,
161 // it is exposed through the /proc/cpuinfo file.
162
163 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line
164 // in all cases.
166 ProcCpuinfoContent.split(Lines, "\n");
167
168 // Look for the CPU implementer line.
169 StringRef Implementer;
170 StringRef Hardware;
171 StringRef Part;
172 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
173 if (Lines[I].startswith("CPU implementer"))
174 Implementer = Lines[I].substr(15).ltrim("\t :");
175 if (Lines[I].startswith("Hardware"))
176 Hardware = Lines[I].substr(8).ltrim("\t :");
177 if (Lines[I].startswith("CPU part"))
178 Part = Lines[I].substr(8).ltrim("\t :");
179 }
180
181 if (Implementer == "0x41") { // ARM Ltd.
182 // MSM8992/8994 may give cpu part for the core that the kernel is running on,
183 // which is undeterministic and wrong. Always return cortex-a53 for these SoC.
184 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996"))
185 return "cortex-a53";
186
187
188 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
189 // values correspond to the "Part number" in the CP15/c0 register. The
190 // contents are specified in the various processor manuals.
191 // This corresponds to the Main ID Register in Technical Reference Manuals.
192 // and is used in programs like sys-utils
193 return StringSwitch<const char *>(Part)
194 .Case("0x926", "arm926ej-s")
195 .Case("0xb02", "mpcore")
196 .Case("0xb36", "arm1136j-s")
197 .Case("0xb56", "arm1156t2-s")
198 .Case("0xb76", "arm1176jz-s")
199 .Case("0xc08", "cortex-a8")
200 .Case("0xc09", "cortex-a9")
201 .Case("0xc0f", "cortex-a15")
202 .Case("0xc20", "cortex-m0")
203 .Case("0xc23", "cortex-m3")
204 .Case("0xc24", "cortex-m4")
205 .Case("0xd22", "cortex-m55")
206 .Case("0xd02", "cortex-a34")
207 .Case("0xd04", "cortex-a35")
208 .Case("0xd03", "cortex-a53")
209 .Case("0xd05", "cortex-a55")
210 .Case("0xd46", "cortex-a510")
211 .Case("0xd80", "cortex-a520")
212 .Case("0xd07", "cortex-a57")
213 .Case("0xd08", "cortex-a72")
214 .Case("0xd09", "cortex-a73")
215 .Case("0xd0a", "cortex-a75")
216 .Case("0xd0b", "cortex-a76")
217 .Case("0xd0d", "cortex-a77")
218 .Case("0xd41", "cortex-a78")
219 .Case("0xd47", "cortex-a710")
220 .Case("0xd4d", "cortex-a715")
221 .Case("0xd81", "cortex-a720")
222 .Case("0xd44", "cortex-x1")
223 .Case("0xd4c", "cortex-x1c")
224 .Case("0xd48", "cortex-x2")
225 .Case("0xd4e", "cortex-x3")
226 .Case("0xd82", "cortex-x4")
227 .Case("0xd0c", "neoverse-n1")
228 .Case("0xd49", "neoverse-n2")
229 .Case("0xd40", "neoverse-v1")
230 .Case("0xd4f", "neoverse-v2")
231 .Default("generic");
232 }
233
234 if (Implementer == "0x42" || Implementer == "0x43") { // Broadcom | Cavium.
235 return StringSwitch<const char *>(Part)
236 .Case("0x516", "thunderx2t99")
237 .Case("0x0516", "thunderx2t99")
238 .Case("0xaf", "thunderx2t99")
239 .Case("0x0af", "thunderx2t99")
240 .Case("0xa1", "thunderxt88")
241 .Case("0x0a1", "thunderxt88")
242 .Default("generic");
243 }
244
245 if (Implementer == "0x46") { // Fujitsu Ltd.
246 return StringSwitch<const char *>(Part)
247 .Case("0x001", "a64fx")
248 .Default("generic");
249 }
250
251 if (Implementer == "0x4e") { // NVIDIA Corporation
252 return StringSwitch<const char *>(Part)
253 .Case("0x004", "carmel")
254 .Default("generic");
255 }
256
257 if (Implementer == "0x48") // HiSilicon Technologies, Inc.
258 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
259 // values correspond to the "Part number" in the CP15/c0 register. The
260 // contents are specified in the various processor manuals.
261 return StringSwitch<const char *>(Part)
262 .Case("0xd01", "tsv110")
263 .Default("generic");
264
265 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
266 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
267 // values correspond to the "Part number" in the CP15/c0 register. The
268 // contents are specified in the various processor manuals.
269 return StringSwitch<const char *>(Part)
270 .Case("0x06f", "krait") // APQ8064
271 .Case("0x201", "kryo")
272 .Case("0x205", "kryo")
273 .Case("0x211", "kryo")
274 .Case("0x800", "cortex-a73") // Kryo 2xx Gold
275 .Case("0x801", "cortex-a73") // Kryo 2xx Silver
276 .Case("0x802", "cortex-a75") // Kryo 3xx Gold
277 .Case("0x803", "cortex-a75") // Kryo 3xx Silver
278 .Case("0x804", "cortex-a76") // Kryo 4xx Gold
279 .Case("0x805", "cortex-a76") // Kryo 4xx/5xx Silver
280 .Case("0xc00", "falkor")
281 .Case("0xc01", "saphira")
282 .Default("generic");
283 if (Implementer == "0x53") { // Samsung Electronics Co., Ltd.
284 // The Exynos chips have a convoluted ID scheme that doesn't seem to follow
285 // any predictive pattern across variants and parts.
286 unsigned Variant = 0, Part = 0;
287
288 // Look for the CPU variant line, whose value is a 1 digit hexadecimal
289 // number, corresponding to the Variant bits in the CP15/C0 register.
290 for (auto I : Lines)
291 if (I.consume_front("CPU variant"))
292 I.ltrim("\t :").getAsInteger(0, Variant);
293
294 // Look for the CPU part line, whose value is a 3 digit hexadecimal
295 // number, corresponding to the PartNum bits in the CP15/C0 register.
296 for (auto I : Lines)
297 if (I.consume_front("CPU part"))
298 I.ltrim("\t :").getAsInteger(0, Part);
299
300 unsigned Exynos = (Variant << 12) | Part;
301 switch (Exynos) {
302 default:
303 // Default by falling through to Exynos M3.
304 [[fallthrough]];
305 case 0x1002:
306 return "exynos-m3";
307 case 0x1003:
308 return "exynos-m4";
309 }
310 }
311
312 if (Implementer == "0xc0") { // Ampere Computing
313 return StringSwitch<const char *>(Part)
314 .Case("0xac3", "ampere1")
315 .Case("0xac4", "ampere1a")
316 .Default("generic");
317 }
318
319 return "generic";
320}
321
322namespace {
323StringRef getCPUNameFromS390Model(unsigned int Id, bool HaveVectorSupport) {
324 switch (Id) {
325 case 2064: // z900 not supported by LLVM
326 case 2066:
327 case 2084: // z990 not supported by LLVM
328 case 2086:
329 case 2094: // z9-109 not supported by LLVM
330 case 2096:
331 return "generic";
332 case 2097:
333 case 2098:
334 return "z10";
335 case 2817:
336 case 2818:
337 return "z196";
338 case 2827:
339 case 2828:
340 return "zEC12";
341 case 2964:
342 case 2965:
343 return HaveVectorSupport? "z13" : "zEC12";
344 case 3906:
345 case 3907:
346 return HaveVectorSupport? "z14" : "zEC12";
347 case 8561:
348 case 8562:
349 return HaveVectorSupport? "z15" : "zEC12";
350 case 3931:
351 case 3932:
352 default:
353 return HaveVectorSupport? "z16" : "zEC12";
354 }
355}
356} // end anonymous namespace
357
359 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
360
361 // The "processor 0:" line comes after a fair amount of other information,
362 // including a cache breakdown, but this should be plenty.
364 ProcCpuinfoContent.split(Lines, "\n");
365
366 // Look for the CPU features.
367 SmallVector<StringRef, 32> CPUFeatures;
368 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
369 if (Lines[I].startswith("features")) {
370 size_t Pos = Lines[I].find(':');
371 if (Pos != StringRef::npos) {
372 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' ');
373 break;
374 }
375 }
376
377 // We need to check for the presence of vector support independently of
378 // the machine type, since we may only use the vector register set when
379 // supported by the kernel (and hypervisor).
380 bool HaveVectorSupport = false;
381 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
382 if (CPUFeatures[I] == "vx")
383 HaveVectorSupport = true;
384 }
385
386 // Now check the processor machine type.
387 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
388 if (Lines[I].startswith("processor ")) {
389 size_t Pos = Lines[I].find("machine = ");
390 if (Pos != StringRef::npos) {
391 Pos += sizeof("machine = ") - 1;
392 unsigned int Id;
393 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id))
394 return getCPUNameFromS390Model(Id, HaveVectorSupport);
395 }
396 break;
397 }
398 }
399
400 return "generic";
401}
402
404 // There are 24 lines in /proc/cpuinfo
406 ProcCpuinfoContent.split(Lines, "\n");
407
408 // Look for uarch line to determine cpu name
409 StringRef UArch;
410 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
411 if (Lines[I].startswith("uarch")) {
412 UArch = Lines[I].substr(5).ltrim("\t :");
413 break;
414 }
415 }
416
417 return StringSwitch<const char *>(UArch)
418 .Case("sifive,u74-mc", "sifive-u74")
419 .Case("sifive,bullet0", "sifive-u74")
420 .Default("generic");
421}
422
424#if !defined(__linux__) || !defined(__x86_64__)
425 return "generic";
426#else
427 uint8_t v3_insns[40] __attribute__ ((aligned (8))) =
428 /* BPF_MOV64_IMM(BPF_REG_0, 0) */
429 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
430 /* BPF_MOV64_IMM(BPF_REG_2, 1) */
431 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
432 /* BPF_JMP32_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
433 0xae, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
434 /* BPF_MOV64_IMM(BPF_REG_0, 1) */
435 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
436 /* BPF_EXIT_INSN() */
437 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
438
439 uint8_t v2_insns[40] __attribute__ ((aligned (8))) =
440 /* BPF_MOV64_IMM(BPF_REG_0, 0) */
441 { 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
442 /* BPF_MOV64_IMM(BPF_REG_2, 1) */
443 0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
444 /* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
445 0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
446 /* BPF_MOV64_IMM(BPF_REG_0, 1) */
447 0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
448 /* BPF_EXIT_INSN() */
449 0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
450
451 struct bpf_prog_load_attr {
452 uint32_t prog_type;
453 uint32_t insn_cnt;
454 uint64_t insns;
455 uint64_t license;
456 uint32_t log_level;
457 uint32_t log_size;
458 uint64_t log_buf;
459 uint32_t kern_version;
460 uint32_t prog_flags;
461 } attr = {};
462 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
463 attr.insn_cnt = 5;
464 attr.insns = (uint64_t)v3_insns;
465 attr.license = (uint64_t)"DUMMY";
466
467 int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr,
468 sizeof(attr));
469 if (fd >= 0) {
470 close(fd);
471 return "v3";
472 }
473
474 /* Clear the whole attr in case its content changed by syscall. */
475 memset(&attr, 0, sizeof(attr));
476 attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
477 attr.insn_cnt = 5;
478 attr.insns = (uint64_t)v2_insns;
479 attr.license = (uint64_t)"DUMMY";
480 fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
481 if (fd >= 0) {
482 close(fd);
483 return "v2";
484 }
485 return "v1";
486#endif
487}
488
489#if defined(__i386__) || defined(_M_IX86) || \
490 defined(__x86_64__) || defined(_M_X64)
491
492// The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
493// Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
494// support. Consequently, for i386, the presence of CPUID is checked first
495// via the corresponding eflags bit.
496// Removal of cpuid.h header motivated by PR30384
497// Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
498// or test-suite, but are used in external projects e.g. libstdcxx
499static bool isCpuIdSupported() {
500#if defined(__GNUC__) || defined(__clang__)
501#if defined(__i386__)
502 int __cpuid_supported;
503 __asm__(" pushfl\n"
504 " popl %%eax\n"
505 " movl %%eax,%%ecx\n"
506 " xorl $0x00200000,%%eax\n"
507 " pushl %%eax\n"
508 " popfl\n"
509 " pushfl\n"
510 " popl %%eax\n"
511 " movl $0,%0\n"
512 " cmpl %%eax,%%ecx\n"
513 " je 1f\n"
514 " movl $1,%0\n"
515 "1:"
516 : "=r"(__cpuid_supported)
517 :
518 : "eax", "ecx");
519 if (!__cpuid_supported)
520 return false;
521#endif
522 return true;
523#endif
524 return true;
525}
526
527/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
528/// the specified arguments. If we can't run cpuid on the host, return true.
529static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
530 unsigned *rECX, unsigned *rEDX) {
531#if defined(__GNUC__) || defined(__clang__)
532#if defined(__x86_64__)
533 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
534 // FIXME: should we save this for Clang?
535 __asm__("movq\t%%rbx, %%rsi\n\t"
536 "cpuid\n\t"
537 "xchgq\t%%rbx, %%rsi\n\t"
538 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
539 : "a"(value));
540 return false;
541#elif defined(__i386__)
542 __asm__("movl\t%%ebx, %%esi\n\t"
543 "cpuid\n\t"
544 "xchgl\t%%ebx, %%esi\n\t"
545 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
546 : "a"(value));
547 return false;
548#else
549 return true;
550#endif
551#elif defined(_MSC_VER)
552 // The MSVC intrinsic is portable across x86 and x64.
553 int registers[4];
554 __cpuid(registers, value);
555 *rEAX = registers[0];
556 *rEBX = registers[1];
557 *rECX = registers[2];
558 *rEDX = registers[3];
559 return false;
560#else
561 return true;
562#endif
563}
564
565namespace llvm {
566namespace sys {
567namespace detail {
568namespace x86 {
569
570VendorSignatures getVendorSignature(unsigned *MaxLeaf) {
571 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
572 if (MaxLeaf == nullptr)
573 MaxLeaf = &EAX;
574 else
575 *MaxLeaf = 0;
576
577 if (!isCpuIdSupported())
578 return VendorSignatures::UNKNOWN;
579
580 if (getX86CpuIDAndInfo(0, MaxLeaf, &EBX, &ECX, &EDX) || *MaxLeaf < 1)
581 return VendorSignatures::UNKNOWN;
582
583 // "Genu ineI ntel"
584 if (EBX == 0x756e6547 && EDX == 0x49656e69 && ECX == 0x6c65746e)
585 return VendorSignatures::GENUINE_INTEL;
586
587 // "Auth enti cAMD"
588 if (EBX == 0x68747541 && EDX == 0x69746e65 && ECX == 0x444d4163)
589 return VendorSignatures::AUTHENTIC_AMD;
590
591 return VendorSignatures::UNKNOWN;
592}
593
594} // namespace x86
595} // namespace detail
596} // namespace sys
597} // namespace llvm
598
599using namespace llvm::sys::detail::x86;
600
601/// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
602/// the 4 values in the specified arguments. If we can't run cpuid on the host,
603/// return true.
604static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
605 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
606 unsigned *rEDX) {
607#if defined(__GNUC__) || defined(__clang__)
608#if defined(__x86_64__)
609 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually.
610 // FIXME: should we save this for Clang?
611 __asm__("movq\t%%rbx, %%rsi\n\t"
612 "cpuid\n\t"
613 "xchgq\t%%rbx, %%rsi\n\t"
614 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
615 : "a"(value), "c"(subleaf));
616 return false;
617#elif defined(__i386__)
618 __asm__("movl\t%%ebx, %%esi\n\t"
619 "cpuid\n\t"
620 "xchgl\t%%ebx, %%esi\n\t"
621 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
622 : "a"(value), "c"(subleaf));
623 return false;
624#else
625 return true;
626#endif
627#elif defined(_MSC_VER)
628 int registers[4];
629 __cpuidex(registers, value, subleaf);
630 *rEAX = registers[0];
631 *rEBX = registers[1];
632 *rECX = registers[2];
633 *rEDX = registers[3];
634 return false;
635#else
636 return true;
637#endif
638}
639
640// Read control register 0 (XCR0). Used to detect features such as AVX.
641static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
642#if defined(__GNUC__) || defined(__clang__)
643 // Check xgetbv; this uses a .byte sequence instead of the instruction
644 // directly because older assemblers do not include support for xgetbv and
645 // there is no easy way to conditionally compile based on the assembler used.
646 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
647 return false;
648#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
649 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
650 *rEAX = Result;
651 *rEDX = Result >> 32;
652 return false;
653#else
654 return true;
655#endif
656}
657
658static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
659 unsigned *Model) {
660 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
661 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7
662 if (*Family == 6 || *Family == 0xf) {
663 if (*Family == 0xf)
664 // Examine extended family ID if family ID is F.
665 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
666 // Examine extended model ID if family ID is 6 or F.
667 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
668 }
669}
670
671static StringRef
672getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
673 const unsigned *Features,
674 unsigned *Type, unsigned *Subtype) {
675 auto testFeature = [&](unsigned F) {
676 return (Features[F / 32] & (1U << (F % 32))) != 0;
677 };
678
679 StringRef CPU;
680
681 switch (Family) {
682 case 3:
683 CPU = "i386";
684 break;
685 case 4:
686 CPU = "i486";
687 break;
688 case 5:
689 if (testFeature(X86::FEATURE_MMX)) {
690 CPU = "pentium-mmx";
691 break;
692 }
693 CPU = "pentium";
694 break;
695 case 6:
696 switch (Model) {
697 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
698 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
699 // mobile processor, Intel Core 2 Extreme processor, Intel
700 // Pentium Dual-Core processor, Intel Xeon processor, model
701 // 0Fh. All processors are manufactured using the 65 nm process.
702 case 0x16: // Intel Celeron processor model 16h. All processors are
703 // manufactured using the 65 nm process
704 CPU = "core2";
705 *Type = X86::INTEL_CORE2;
706 break;
707 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
708 // 17h. All processors are manufactured using the 45 nm process.
709 //
710 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
711 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
712 // the 45 nm process.
713 CPU = "penryn";
714 *Type = X86::INTEL_CORE2;
715 break;
716 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
717 // processors are manufactured using the 45 nm process.
718 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
719 // As found in a Summer 2010 model iMac.
720 case 0x1f:
721 case 0x2e: // Nehalem EX
722 CPU = "nehalem";
723 *Type = X86::INTEL_COREI7;
724 *Subtype = X86::INTEL_COREI7_NEHALEM;
725 break;
726 case 0x25: // Intel Core i7, laptop version.
727 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
728 // processors are manufactured using the 32 nm process.
729 case 0x2f: // Westmere EX
730 CPU = "westmere";
731 *Type = X86::INTEL_COREI7;
732 *Subtype = X86::INTEL_COREI7_WESTMERE;
733 break;
734 case 0x2a: // Intel Core i7 processor. All processors are manufactured
735 // using the 32 nm process.
736 case 0x2d:
737 CPU = "sandybridge";
738 *Type = X86::INTEL_COREI7;
739 *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
740 break;
741 case 0x3a:
742 case 0x3e: // Ivy Bridge EP
743 CPU = "ivybridge";
744 *Type = X86::INTEL_COREI7;
745 *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
746 break;
747
748 // Haswell:
749 case 0x3c:
750 case 0x3f:
751 case 0x45:
752 case 0x46:
753 CPU = "haswell";
754 *Type = X86::INTEL_COREI7;
755 *Subtype = X86::INTEL_COREI7_HASWELL;
756 break;
757
758 // Broadwell:
759 case 0x3d:
760 case 0x47:
761 case 0x4f:
762 case 0x56:
763 CPU = "broadwell";
764 *Type = X86::INTEL_COREI7;
765 *Subtype = X86::INTEL_COREI7_BROADWELL;
766 break;
767
768 // Skylake:
769 case 0x4e: // Skylake mobile
770 case 0x5e: // Skylake desktop
771 case 0x8e: // Kaby Lake mobile
772 case 0x9e: // Kaby Lake desktop
773 case 0xa5: // Comet Lake-H/S
774 case 0xa6: // Comet Lake-U
775 CPU = "skylake";
776 *Type = X86::INTEL_COREI7;
777 *Subtype = X86::INTEL_COREI7_SKYLAKE;
778 break;
779
780 // Rocketlake:
781 case 0xa7:
782 CPU = "rocketlake";
783 *Type = X86::INTEL_COREI7;
784 *Subtype = X86::INTEL_COREI7_ROCKETLAKE;
785 break;
786
787 // Skylake Xeon:
788 case 0x55:
789 *Type = X86::INTEL_COREI7;
790 if (testFeature(X86::FEATURE_AVX512BF16)) {
791 CPU = "cooperlake";
792 *Subtype = X86::INTEL_COREI7_COOPERLAKE;
793 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
794 CPU = "cascadelake";
795 *Subtype = X86::INTEL_COREI7_CASCADELAKE;
796 } else {
797 CPU = "skylake-avx512";
798 *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
799 }
800 break;
801
802 // Cannonlake:
803 case 0x66:
804 CPU = "cannonlake";
805 *Type = X86::INTEL_COREI7;
806 *Subtype = X86::INTEL_COREI7_CANNONLAKE;
807 break;
808
809 // Icelake:
810 case 0x7d:
811 case 0x7e:
812 CPU = "icelake-client";
813 *Type = X86::INTEL_COREI7;
814 *Subtype = X86::INTEL_COREI7_ICELAKE_CLIENT;
815 break;
816
817 // Tigerlake:
818 case 0x8c:
819 case 0x8d:
820 CPU = "tigerlake";
821 *Type = X86::INTEL_COREI7;
822 *Subtype = X86::INTEL_COREI7_TIGERLAKE;
823 break;
824
825 // Alderlake:
826 case 0x97:
827 case 0x9a:
828 // Gracemont
829 case 0xbe:
830 // Raptorlake:
831 case 0xb7:
832 case 0xba:
833 case 0xbf:
834 // Meteorlake:
835 case 0xaa:
836 case 0xac:
837 CPU = "alderlake";
838 *Type = X86::INTEL_COREI7;
839 *Subtype = X86::INTEL_COREI7_ALDERLAKE;
840 break;
841
842 // Arrowlake:
843 case 0xc5:
844 CPU = "arrowlake";
845 *Type = X86::INTEL_COREI7;
846 *Subtype = X86::INTEL_COREI7_ARROWLAKE;
847 break;
848
849 // Arrowlake S:
850 case 0xc6:
851 // Lunarlake:
852 case 0xbd:
853 CPU = "arrowlake-s";
854 *Type = X86::INTEL_COREI7;
855 *Subtype = X86::INTEL_COREI7_ARROWLAKE_S;
856 break;
857
858 // Pantherlake:
859 case 0xcc:
860 CPU = "pantherlake";
861 *Type = X86::INTEL_COREI7;
862 *Subtype = X86::INTEL_COREI7_PANTHERLAKE;
863 break;
864
865 // Graniterapids:
866 case 0xad:
867 CPU = "graniterapids";
868 *Type = X86::INTEL_COREI7;
869 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
870 break;
871
872 // Granite Rapids D:
873 case 0xae:
874 CPU = "graniterapids-d";
875 *Type = X86::INTEL_COREI7;
876 *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
877 break;
878
879 // Icelake Xeon:
880 case 0x6a:
881 case 0x6c:
882 CPU = "icelake-server";
883 *Type = X86::INTEL_COREI7;
884 *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
885 break;
886
887 // Emerald Rapids:
888 case 0xcf:
889 // Sapphire Rapids:
890 case 0x8f:
891 CPU = "sapphirerapids";
892 *Type = X86::INTEL_COREI7;
893 *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
894 break;
895
896 case 0x1c: // Most 45 nm Intel Atom processors
897 case 0x26: // 45 nm Atom Lincroft
898 case 0x27: // 32 nm Atom Medfield
899 case 0x35: // 32 nm Atom Midview
900 case 0x36: // 32 nm Atom Midview
901 CPU = "bonnell";
902 *Type = X86::INTEL_BONNELL;
903 break;
904
905 // Atom Silvermont codes from the Intel software optimization guide.
906 case 0x37:
907 case 0x4a:
908 case 0x4d:
909 case 0x5a:
910 case 0x5d:
911 case 0x4c: // really airmont
912 CPU = "silvermont";
913 *Type = X86::INTEL_SILVERMONT;
914 break;
915 // Goldmont:
916 case 0x5c: // Apollo Lake
917 case 0x5f: // Denverton
918 CPU = "goldmont";
919 *Type = X86::INTEL_GOLDMONT;
920 break;
921 case 0x7a:
922 CPU = "goldmont-plus";
923 *Type = X86::INTEL_GOLDMONT_PLUS;
924 break;
925 case 0x86:
926 case 0x8a: // Lakefield
927 case 0x96: // Elkhart Lake
928 case 0x9c: // Jasper Lake
929 CPU = "tremont";
930 *Type = X86::INTEL_TREMONT;
931 break;
932
933 // Sierraforest:
934 case 0xaf:
935 CPU = "sierraforest";
936 *Type = X86::INTEL_SIERRAFOREST;
937 break;
938
939 // Grandridge:
940 case 0xb6:
941 CPU = "grandridge";
942 *Type = X86::INTEL_GRANDRIDGE;
943 break;
944
945 // Clearwaterforest:
946 case 0xdd:
947 CPU = "clearwaterforest";
948 *Type = X86::INTEL_CLEARWATERFOREST;
949 break;
950
951 // Xeon Phi (Knights Landing + Knights Mill):
952 case 0x57:
953 CPU = "knl";
954 *Type = X86::INTEL_KNL;
955 break;
956 case 0x85:
957 CPU = "knm";
958 *Type = X86::INTEL_KNM;
959 break;
960
961 default: // Unknown family 6 CPU, try to guess.
962 // Don't both with Type/Subtype here, they aren't used by the caller.
963 // They're used above to keep the code in sync with compiler-rt.
964 // TODO detect tigerlake host from model
965 if (testFeature(X86::FEATURE_AVX512VP2INTERSECT)) {
966 CPU = "tigerlake";
967 } else if (testFeature(X86::FEATURE_AVX512VBMI2)) {
968 CPU = "icelake-client";
969 } else if (testFeature(X86::FEATURE_AVX512VBMI)) {
970 CPU = "cannonlake";
971 } else if (testFeature(X86::FEATURE_AVX512BF16)) {
972 CPU = "cooperlake";
973 } else if (testFeature(X86::FEATURE_AVX512VNNI)) {
974 CPU = "cascadelake";
975 } else if (testFeature(X86::FEATURE_AVX512VL)) {
976 CPU = "skylake-avx512";
977 } else if (testFeature(X86::FEATURE_AVX512ER)) {
978 CPU = "knl";
979 } else if (testFeature(X86::FEATURE_CLFLUSHOPT)) {
980 if (testFeature(X86::FEATURE_SHA))
981 CPU = "goldmont";
982 else
983 CPU = "skylake";
984 } else if (testFeature(X86::FEATURE_ADX)) {
985 CPU = "broadwell";
986 } else if (testFeature(X86::FEATURE_AVX2)) {
987 CPU = "haswell";
988 } else if (testFeature(X86::FEATURE_AVX)) {
989 CPU = "sandybridge";
990 } else if (testFeature(X86::FEATURE_SSE4_2)) {
991 if (testFeature(X86::FEATURE_MOVBE))
992 CPU = "silvermont";
993 else
994 CPU = "nehalem";
995 } else if (testFeature(X86::FEATURE_SSE4_1)) {
996 CPU = "penryn";
997 } else if (testFeature(X86::FEATURE_SSSE3)) {
998 if (testFeature(X86::FEATURE_MOVBE))
999 CPU = "bonnell";
1000 else
1001 CPU = "core2";
1002 } else if (testFeature(X86::FEATURE_64BIT)) {
1003 CPU = "core2";
1004 } else if (testFeature(X86::FEATURE_SSE3)) {
1005 CPU = "yonah";
1006 } else if (testFeature(X86::FEATURE_SSE2)) {
1007 CPU = "pentium-m";
1008 } else if (testFeature(X86::FEATURE_SSE)) {
1009 CPU = "pentium3";
1010 } else if (testFeature(X86::FEATURE_MMX)) {
1011 CPU = "pentium2";
1012 } else {
1013 CPU = "pentiumpro";
1014 }
1015 break;
1016 }
1017 break;
1018 case 15: {
1019 if (testFeature(X86::FEATURE_64BIT)) {
1020 CPU = "nocona";
1021 break;
1022 }
1023 if (testFeature(X86::FEATURE_SSE3)) {
1024 CPU = "prescott";
1025 break;
1026 }
1027 CPU = "pentium4";
1028 break;
1029 }
1030 default:
1031 break; // Unknown.
1032 }
1033
1034 return CPU;
1035}
1036
1037static StringRef
1038getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
1039 const unsigned *Features,
1040 unsigned *Type, unsigned *Subtype) {
1041 auto testFeature = [&](unsigned F) {
1042 return (Features[F / 32] & (1U << (F % 32))) != 0;
1043 };
1044
1045 StringRef CPU;
1046
1047 switch (Family) {
1048 case 4:
1049 CPU = "i486";
1050 break;
1051 case 5:
1052 CPU = "pentium";
1053 switch (Model) {
1054 case 6:
1055 case 7:
1056 CPU = "k6";
1057 break;
1058 case 8:
1059 CPU = "k6-2";
1060 break;
1061 case 9:
1062 case 13:
1063 CPU = "k6-3";
1064 break;
1065 case 10:
1066 CPU = "geode";
1067 break;
1068 }
1069 break;
1070 case 6:
1071 if (testFeature(X86::FEATURE_SSE)) {
1072 CPU = "athlon-xp";
1073 break;
1074 }
1075 CPU = "athlon";
1076 break;
1077 case 15:
1078 if (testFeature(X86::FEATURE_SSE3)) {
1079 CPU = "k8-sse3";
1080 break;
1081 }
1082 CPU = "k8";
1083 break;
1084 case 16:
1085 CPU = "amdfam10";
1086 *Type = X86::AMDFAM10H; // "amdfam10"
1087 switch (Model) {
1088 case 2:
1089 *Subtype = X86::AMDFAM10H_BARCELONA;
1090 break;
1091 case 4:
1092 *Subtype = X86::AMDFAM10H_SHANGHAI;
1093 break;
1094 case 8:
1095 *Subtype = X86::AMDFAM10H_ISTANBUL;
1096 break;
1097 }
1098 break;
1099 case 20:
1100 CPU = "btver1";
1101 *Type = X86::AMD_BTVER1;
1102 break;
1103 case 21:
1104 CPU = "bdver1";
1105 *Type = X86::AMDFAM15H;
1106 if (Model >= 0x60 && Model <= 0x7f) {
1107 CPU = "bdver4";
1108 *Subtype = X86::AMDFAM15H_BDVER4;
1109 break; // 60h-7Fh: Excavator
1110 }
1111 if (Model >= 0x30 && Model <= 0x3f) {
1112 CPU = "bdver3";
1113 *Subtype = X86::AMDFAM15H_BDVER3;
1114 break; // 30h-3Fh: Steamroller
1115 }
1116 if ((Model >= 0x10 && Model <= 0x1f) || Model == 0x02) {
1117 CPU = "bdver2";
1118 *Subtype = X86::AMDFAM15H_BDVER2;
1119 break; // 02h, 10h-1Fh: Piledriver
1120 }
1121 if (Model <= 0x0f) {
1122 *Subtype = X86::AMDFAM15H_BDVER1;
1123 break; // 00h-0Fh: Bulldozer
1124 }
1125 break;
1126 case 22:
1127 CPU = "btver2";
1128 *Type = X86::AMD_BTVER2;
1129 break;
1130 case 23:
1131 CPU = "znver1";
1132 *Type = X86::AMDFAM17H;
1133 if ((Model >= 0x30 && Model <= 0x3f) || Model == 0x71) {
1134 CPU = "znver2";
1135 *Subtype = X86::AMDFAM17H_ZNVER2;
1136 break; // 30h-3fh, 71h: Zen2
1137 }
1138 if (Model <= 0x0f) {
1139 *Subtype = X86::AMDFAM17H_ZNVER1;
1140 break; // 00h-0Fh: Zen1
1141 }
1142 break;
1143 case 25:
1144 CPU = "znver3";
1145 *Type = X86::AMDFAM19H;
1146 if (Model <= 0x0f || (Model >= 0x20 && Model <= 0x5f)) {
1147 // Family 19h Models 00h-0Fh - Zen3
1148 // Family 19h Models 20h-2Fh - Zen3
1149 // Family 19h Models 30h-3Fh - Zen3
1150 // Family 19h Models 40h-4Fh - Zen3+
1151 // Family 19h Models 50h-5Fh - Zen3+
1152 *Subtype = X86::AMDFAM19H_ZNVER3;
1153 break;
1154 }
1155 if ((Model >= 0x10 && Model <= 0x1f) ||
1156 (Model >= 0x60 && Model <= 0x74) ||
1157 (Model >= 0x78 && Model <= 0x7b) ||
1158 (Model >= 0xA0 && Model <= 0xAf)) {
1159 CPU = "znver4";
1160 *Subtype = X86::AMDFAM19H_ZNVER4;
1161 break; // "znver4"
1162 }
1163 break; // family 19h
1164 default:
1165 break; // Unknown AMD CPU.
1166 }
1167
1168 return CPU;
1169}
1170
1171static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
1172 unsigned *Features) {
1173 unsigned EAX, EBX;
1174
1175 auto setFeature = [&](unsigned F) {
1176 Features[F / 32] |= 1U << (F % 32);
1177 };
1178
1179 if ((EDX >> 15) & 1)
1180 setFeature(X86::FEATURE_CMOV);
1181 if ((EDX >> 23) & 1)
1182 setFeature(X86::FEATURE_MMX);
1183 if ((EDX >> 25) & 1)
1184 setFeature(X86::FEATURE_SSE);
1185 if ((EDX >> 26) & 1)
1186 setFeature(X86::FEATURE_SSE2);
1187
1188 if ((ECX >> 0) & 1)
1189 setFeature(X86::FEATURE_SSE3);
1190 if ((ECX >> 1) & 1)
1191 setFeature(X86::FEATURE_PCLMUL);
1192 if ((ECX >> 9) & 1)
1193 setFeature(X86::FEATURE_SSSE3);
1194 if ((ECX >> 12) & 1)
1195 setFeature(X86::FEATURE_FMA);
1196 if ((ECX >> 19) & 1)
1197 setFeature(X86::FEATURE_SSE4_1);
1198 if ((ECX >> 20) & 1) {
1199 setFeature(X86::FEATURE_SSE4_2);
1200 setFeature(X86::FEATURE_CRC32);
1201 }
1202 if ((ECX >> 23) & 1)
1203 setFeature(X86::FEATURE_POPCNT);
1204 if ((ECX >> 25) & 1)
1205 setFeature(X86::FEATURE_AES);
1206
1207 if ((ECX >> 22) & 1)
1208 setFeature(X86::FEATURE_MOVBE);
1209
1210 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1211 // indicates that the AVX registers will be saved and restored on context
1212 // switch, then we have full AVX support.
1213 const unsigned AVXBits = (1 << 27) | (1 << 28);
1214 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
1215 ((EAX & 0x6) == 0x6);
1216#if defined(__APPLE__)
1217 // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1218 // save the AVX512 context if we use AVX512 instructions, even the bit is not
1219 // set right now.
1220 bool HasAVX512Save = true;
1221#else
1222 // AVX512 requires additional context to be saved by the OS.
1223 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
1224#endif
1225
1226 if (HasAVX)
1227 setFeature(X86::FEATURE_AVX);
1228
1229 bool HasLeaf7 =
1230 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1231
1232 if (HasLeaf7 && ((EBX >> 3) & 1))
1233 setFeature(X86::FEATURE_BMI);
1234 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
1235 setFeature(X86::FEATURE_AVX2);
1236 if (HasLeaf7 && ((EBX >> 8) & 1))
1237 setFeature(X86::FEATURE_BMI2);
1238 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
1239 setFeature(X86::FEATURE_AVX512F);
1240 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
1241 setFeature(X86::FEATURE_AVX512DQ);
1242 if (HasLeaf7 && ((EBX >> 19) & 1))
1243 setFeature(X86::FEATURE_ADX);
1244 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
1245 setFeature(X86::FEATURE_AVX512IFMA);
1246 if (HasLeaf7 && ((EBX >> 23) & 1))
1247 setFeature(X86::FEATURE_CLFLUSHOPT);
1248 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
1249 setFeature(X86::FEATURE_AVX512PF);
1250 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
1251 setFeature(X86::FEATURE_AVX512ER);
1252 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
1253 setFeature(X86::FEATURE_AVX512CD);
1254 if (HasLeaf7 && ((EBX >> 29) & 1))
1255 setFeature(X86::FEATURE_SHA);
1256 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
1257 setFeature(X86::FEATURE_AVX512BW);
1258 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
1259 setFeature(X86::FEATURE_AVX512VL);
1260
1261 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
1262 setFeature(X86::FEATURE_AVX512VBMI);
1263 if (HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save)
1264 setFeature(X86::FEATURE_AVX512VBMI2);
1265 if (HasLeaf7 && ((ECX >> 8) & 1))
1266 setFeature(X86::FEATURE_GFNI);
1267 if (HasLeaf7 && ((ECX >> 10) & 1) && HasAVX)
1268 setFeature(X86::FEATURE_VPCLMULQDQ);
1269 if (HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save)
1270 setFeature(X86::FEATURE_AVX512VNNI);
1271 if (HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save)
1272 setFeature(X86::FEATURE_AVX512BITALG);
1273 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
1274 setFeature(X86::FEATURE_AVX512VPOPCNTDQ);
1275
1276 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
1277 setFeature(X86::FEATURE_AVX5124VNNIW);
1278 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
1279 setFeature(X86::FEATURE_AVX5124FMAPS);
1280 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save)
1281 setFeature(X86::FEATURE_AVX512VP2INTERSECT);
1282
1283 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
1284 // return all 0s for invalid subleaves so check the limit.
1285 bool HasLeaf7Subleaf1 =
1286 HasLeaf7 && EAX >= 1 &&
1287 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1288 if (HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save)
1289 setFeature(X86::FEATURE_AVX512BF16);
1290
1291 unsigned MaxExtLevel;
1292 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1293
1294 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1295 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1296 if (HasExtLeaf1 && ((ECX >> 6) & 1))
1297 setFeature(X86::FEATURE_SSE4_A);
1298 if (HasExtLeaf1 && ((ECX >> 11) & 1))
1299 setFeature(X86::FEATURE_XOP);
1300 if (HasExtLeaf1 && ((ECX >> 16) & 1))
1301 setFeature(X86::FEATURE_FMA4);
1302
1303 if (HasExtLeaf1 && ((EDX >> 29) & 1))
1304 setFeature(X86::FEATURE_64BIT);
1305}
1306
1308 unsigned MaxLeaf = 0;
1309 const VendorSignatures Vendor = getVendorSignature(&MaxLeaf);
1310 if (Vendor == VendorSignatures::UNKNOWN)
1311 return "generic";
1312
1313 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1314 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
1315
1316 unsigned Family = 0, Model = 0;
1317 unsigned Features[(X86::CPU_FEATURE_MAX + 31) / 32] = {0};
1318 detectX86FamilyModel(EAX, &Family, &Model);
1319 getAvailableFeatures(ECX, EDX, MaxLeaf, Features);
1320
1321 // These aren't consumed in this file, but we try to keep some source code the
1322 // same or similar to compiler-rt.
1323 unsigned Type = 0;
1324 unsigned Subtype = 0;
1325
1326 StringRef CPU;
1327
1328 if (Vendor == VendorSignatures::GENUINE_INTEL) {
1329 CPU = getIntelProcessorTypeAndSubtype(Family, Model, Features, &Type,
1330 &Subtype);
1331 } else if (Vendor == VendorSignatures::AUTHENTIC_AMD) {
1332 CPU = getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type,
1333 &Subtype);
1334 }
1335
1336 if (!CPU.empty())
1337 return CPU;
1338
1339 return "generic";
1340}
1341
1342#elif defined(__APPLE__) && defined(__powerpc__)
1344 host_basic_info_data_t hostInfo;
1345 mach_msg_type_number_t infoCount;
1346
1347 infoCount = HOST_BASIC_INFO_COUNT;
1348 mach_port_t hostPort = mach_host_self();
1349 host_info(hostPort, HOST_BASIC_INFO, (host_info_t)&hostInfo,
1350 &infoCount);
1351 mach_port_deallocate(mach_task_self(), hostPort);
1352
1353 if (hostInfo.cpu_type != CPU_TYPE_POWERPC)
1354 return "generic";
1355
1356 switch (hostInfo.cpu_subtype) {
1358 return "601";
1360 return "602";
1362 return "603";
1364 return "603e";
1366 return "603ev";
1368 return "604";
1370 return "604e";
1372 return "620";
1374 return "750";
1376 return "7400";
1378 return "7450";
1380 return "970";
1381 default:;
1382 }
1383
1384 return "generic";
1385}
1386#elif defined(__linux__) && defined(__powerpc__)
1388 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1389 StringRef Content = P ? P->getBuffer() : "";
1391}
1392#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1394 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1395 StringRef Content = P ? P->getBuffer() : "";
1397}
1398#elif defined(__linux__) && defined(__s390x__)
1400 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1401 StringRef Content = P ? P->getBuffer() : "";
1403}
1404#elif defined(__MVS__)
1406 // Get pointer to Communications Vector Table (CVT).
1407 // The pointer is located at offset 16 of the Prefixed Save Area (PSA).
1408 // It is stored as 31 bit pointer and will be zero-extended to 64 bit.
1409 int *StartToCVTOffset = reinterpret_cast<int *>(0x10);
1410 // Since its stored as a 31-bit pointer, get the 4 bytes from the start
1411 // of address.
1412 int ReadValue = *StartToCVTOffset;
1413 // Explicitly clear the high order bit.
1414 ReadValue = (ReadValue & 0x7FFFFFFF);
1415 char *CVT = reinterpret_cast<char *>(ReadValue);
1416 // The model number is located in the CVT prefix at offset -6 and stored as
1417 // signless packed decimal.
1418 uint16_t Id = *(uint16_t *)&CVT[-6];
1419 // Convert number to integer.
1420 Id = decodePackedBCD<uint16_t>(Id, false);
1421 // Check for vector support. It's stored in field CVTFLAG5 (offset 244),
1422 // bit CVTVEF (X'80'). The facilities list is part of the PSA but the vector
1423 // extension can only be used if bit CVTVEF is on.
1424 bool HaveVectorSupport = CVT[244] & 0x80;
1425 return getCPUNameFromS390Model(Id, HaveVectorSupport);
1426}
1427#elif defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
1428#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
1429#define CPUFAMILY_ARM_CYCLONE 0x37a09642
1430#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
1431#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
1432#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
1433#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
1434#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
1435#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
1436#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1b588bb3
1437
1439 uint32_t Family;
1440 size_t Length = sizeof(Family);
1441 sysctlbyname("hw.cpufamily", &Family, &Length, NULL, 0);
1442
1443 switch (Family) {
1444 case CPUFAMILY_ARM_SWIFT:
1445 return "swift";
1446 case CPUFAMILY_ARM_CYCLONE:
1447 return "apple-a7";
1448 case CPUFAMILY_ARM_TYPHOON:
1449 return "apple-a8";
1450 case CPUFAMILY_ARM_TWISTER:
1451 return "apple-a9";
1452 case CPUFAMILY_ARM_HURRICANE:
1453 return "apple-a10";
1454 case CPUFAMILY_ARM_MONSOON_MISTRAL:
1455 return "apple-a11";
1456 case CPUFAMILY_ARM_VORTEX_TEMPEST:
1457 return "apple-a12";
1458 case CPUFAMILY_ARM_LIGHTNING_THUNDER:
1459 return "apple-a13";
1460 case CPUFAMILY_ARM_FIRESTORM_ICESTORM:
1461 return "apple-m1";
1462 default:
1463 // Default to the newest CPU we know about.
1464 return "apple-m1";
1465 }
1466}
1467#elif defined(_AIX)
1469 switch (_system_configuration.implementation) {
1470 case POWER_4:
1471 if (_system_configuration.version == PV_4_3)
1472 return "970";
1473 return "pwr4";
1474 case POWER_5:
1475 if (_system_configuration.version == PV_5)
1476 return "pwr5";
1477 return "pwr5x";
1478 case POWER_6:
1479 if (_system_configuration.version == PV_6_Compat)
1480 return "pwr6";
1481 return "pwr6x";
1482 case POWER_7:
1483 return "pwr7";
1484 case POWER_8:
1485 return "pwr8";
1486 case POWER_9:
1487 return "pwr9";
1488// TODO: simplify this once the macro is available in all OS levels.
1489#ifdef POWER_10
1490 case POWER_10:
1491#else
1492 case 0x40000:
1493#endif
1494 return "pwr10";
1495 default:
1496 return "generic";
1497 }
1498}
1499#elif defined(__loongarch__)
1501 // Use processor id to detect cpu name.
1502 uint32_t processor_id;
1503 __asm__("cpucfg %[prid], $zero\n\t" : [prid] "=r"(processor_id));
1504 switch (processor_id & 0xff00) {
1505 case 0xc000: // Loongson 64bit, 4-issue
1506 return "la464";
1507 // TODO: Others.
1508 default:
1509 break;
1510 }
1511 return "generic";
1512}
1513#elif defined(__riscv)
1515#if defined(__linux__)
1516 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1517 StringRef Content = P ? P->getBuffer() : "";
1519#else
1520#if __riscv_xlen == 64
1521 return "generic-rv64";
1522#elif __riscv_xlen == 32
1523 return "generic-rv32";
1524#else
1525#error "Unhandled value of __riscv_xlen"
1526#endif
1527#endif
1528}
1529#elif defined(__sparc__)
1530#if defined(__linux__)
1533 ProcCpuinfoContent.split(Lines, "\n");
1534
1535 // Look for cpu line to determine cpu name
1536 StringRef Cpu;
1537 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
1538 if (Lines[I].startswith("cpu")) {
1539 Cpu = Lines[I].substr(5).ltrim("\t :");
1540 break;
1541 }
1542 }
1543
1544 return StringSwitch<const char *>(Cpu)
1545 .StartsWith("SuperSparc", "supersparc")
1546 .StartsWith("HyperSparc", "hypersparc")
1547 .StartsWith("SpitFire", "ultrasparc")
1548 .StartsWith("BlackBird", "ultrasparc")
1549 .StartsWith("Sabre", " ultrasparc")
1550 .StartsWith("Hummingbird", "ultrasparc")
1551 .StartsWith("Cheetah", "ultrasparc3")
1552 .StartsWith("Jalapeno", "ultrasparc3")
1553 .StartsWith("Jaguar", "ultrasparc3")
1554 .StartsWith("Panther", "ultrasparc3")
1555 .StartsWith("Serrano", "ultrasparc3")
1556 .StartsWith("UltraSparc T1", "niagara")
1557 .StartsWith("UltraSparc T2", "niagara2")
1558 .StartsWith("UltraSparc T3", "niagara3")
1559 .StartsWith("UltraSparc T4", "niagara4")
1560 .StartsWith("UltraSparc T5", "niagara4")
1561 .StartsWith("LEON", "leon3")
1562 // niagara7/m8 not supported by LLVM yet.
1563 .StartsWith("SPARC-M7", "niagara4" /* "niagara7" */)
1564 .StartsWith("SPARC-S7", "niagara4" /* "niagara7" */)
1565 .StartsWith("SPARC-M8", "niagara4" /* "m8" */)
1566 .Default("generic");
1567}
1568#endif
1569
1571#if defined(__linux__)
1572 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1573 StringRef Content = P ? P->getBuffer() : "";
1575#elif defined(__sun__) && defined(__svr4__)
1576 char *buf = NULL;
1577 kstat_ctl_t *kc;
1578 kstat_t *ksp;
1579 kstat_named_t *brand = NULL;
1580
1581 kc = kstat_open();
1582 if (kc != NULL) {
1583 ksp = kstat_lookup(kc, const_cast<char *>("cpu_info"), -1, NULL);
1584 if (ksp != NULL && kstat_read(kc, ksp, NULL) != -1 &&
1585 ksp->ks_type == KSTAT_TYPE_NAMED)
1586 brand =
1587 (kstat_named_t *)kstat_data_lookup(ksp, const_cast<char *>("brand"));
1588 if (brand != NULL && brand->data_type == KSTAT_DATA_STRING)
1589 buf = KSTAT_NAMED_STR_PTR(brand);
1590 }
1591 kstat_close(kc);
1592
1593 return StringSwitch<const char *>(buf)
1594 .Case("TMS390S10", "supersparc") // Texas Instruments microSPARC I
1595 .Case("TMS390Z50", "supersparc") // Texas Instruments SuperSPARC I
1596 .Case("TMS390Z55",
1597 "supersparc") // Texas Instruments SuperSPARC I with SuperCache
1598 .Case("MB86904", "supersparc") // Fujitsu microSPARC II
1599 .Case("MB86907", "supersparc") // Fujitsu TurboSPARC
1600 .Case("RT623", "hypersparc") // Ross hyperSPARC
1601 .Case("RT625", "hypersparc")
1602 .Case("RT626", "hypersparc")
1603 .Case("UltraSPARC-I", "ultrasparc")
1604 .Case("UltraSPARC-II", "ultrasparc")
1605 .Case("UltraSPARC-IIe", "ultrasparc")
1606 .Case("UltraSPARC-IIi", "ultrasparc")
1607 .Case("SPARC64-III", "ultrasparc")
1608 .Case("SPARC64-IV", "ultrasparc")
1609 .Case("UltraSPARC-III", "ultrasparc3")
1610 .Case("UltraSPARC-III+", "ultrasparc3")
1611 .Case("UltraSPARC-IIIi", "ultrasparc3")
1612 .Case("UltraSPARC-IIIi+", "ultrasparc3")
1613 .Case("UltraSPARC-IV", "ultrasparc3")
1614 .Case("UltraSPARC-IV+", "ultrasparc3")
1615 .Case("SPARC64-V", "ultrasparc3")
1616 .Case("SPARC64-VI", "ultrasparc3")
1617 .Case("SPARC64-VII", "ultrasparc3")
1618 .Case("UltraSPARC-T1", "niagara")
1619 .Case("UltraSPARC-T2", "niagara2")
1620 .Case("UltraSPARC-T2", "niagara2")
1621 .Case("UltraSPARC-T2+", "niagara2")
1622 .Case("SPARC-T3", "niagara3")
1623 .Case("SPARC-T4", "niagara4")
1624 .Case("SPARC-T5", "niagara4")
1625 // niagara7/m8 not supported by LLVM yet.
1626 .Case("SPARC-M7", "niagara4" /* "niagara7" */)
1627 .Case("SPARC-S7", "niagara4" /* "niagara7" */)
1628 .Case("SPARC-M8", "niagara4" /* "m8" */)
1629 .Default("generic");
1630#else
1631 return "generic";
1632#endif
1633}
1634#else
1635StringRef sys::getHostCPUName() { return "generic"; }
1636namespace llvm {
1637namespace sys {
1638namespace detail {
1639namespace x86 {
1640
1643}
1644
1645} // namespace x86
1646} // namespace detail
1647} // namespace sys
1648} // namespace llvm
1649#endif
1650
1651#if defined(__i386__) || defined(_M_IX86) || \
1652 defined(__x86_64__) || defined(_M_X64)
1654 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
1655 unsigned MaxLevel;
1656
1657 if (getX86CpuIDAndInfo(0, &MaxLevel, &EBX, &ECX, &EDX) || MaxLevel < 1)
1658 return false;
1659
1660 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
1661
1662 Features["cx8"] = (EDX >> 8) & 1;
1663 Features["cmov"] = (EDX >> 15) & 1;
1664 Features["mmx"] = (EDX >> 23) & 1;
1665 Features["fxsr"] = (EDX >> 24) & 1;
1666 Features["sse"] = (EDX >> 25) & 1;
1667 Features["sse2"] = (EDX >> 26) & 1;
1668
1669 Features["sse3"] = (ECX >> 0) & 1;
1670 Features["pclmul"] = (ECX >> 1) & 1;
1671 Features["ssse3"] = (ECX >> 9) & 1;
1672 Features["cx16"] = (ECX >> 13) & 1;
1673 Features["sse4.1"] = (ECX >> 19) & 1;
1674 Features["sse4.2"] = (ECX >> 20) & 1;
1675 Features["crc32"] = Features["sse4.2"];
1676 Features["movbe"] = (ECX >> 22) & 1;
1677 Features["popcnt"] = (ECX >> 23) & 1;
1678 Features["aes"] = (ECX >> 25) & 1;
1679 Features["rdrnd"] = (ECX >> 30) & 1;
1680
1681 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
1682 // indicates that the AVX registers will be saved and restored on context
1683 // switch, then we have full AVX support.
1684 bool HasXSave = ((ECX >> 27) & 1) && !getX86XCR0(&EAX, &EDX);
1685 bool HasAVXSave = HasXSave && ((ECX >> 28) & 1) && ((EAX & 0x6) == 0x6);
1686#if defined(__APPLE__)
1687 // Darwin lazily saves the AVX512 context on first use: trust that the OS will
1688 // save the AVX512 context if we use AVX512 instructions, even the bit is not
1689 // set right now.
1690 bool HasAVX512Save = true;
1691#else
1692 // AVX512 requires additional context to be saved by the OS.
1693 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
1694#endif
1695 // AMX requires additional context to be saved by the OS.
1696 const unsigned AMXBits = (1 << 17) | (1 << 18);
1697 bool HasAMXSave = HasXSave && ((EAX & AMXBits) == AMXBits);
1698
1699 Features["avx"] = HasAVXSave;
1700 Features["fma"] = ((ECX >> 12) & 1) && HasAVXSave;
1701 // Only enable XSAVE if OS has enabled support for saving YMM state.
1702 Features["xsave"] = ((ECX >> 26) & 1) && HasAVXSave;
1703 Features["f16c"] = ((ECX >> 29) & 1) && HasAVXSave;
1704
1705 unsigned MaxExtLevel;
1706 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
1707
1708 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
1709 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
1710 Features["sahf"] = HasExtLeaf1 && ((ECX >> 0) & 1);
1711 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
1712 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
1713 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
1714 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
1715 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1);
1716 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
1717 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
1718 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
1719
1720 Features["64bit"] = HasExtLeaf1 && ((EDX >> 29) & 1);
1721
1722 // Miscellaneous memory related features, detected by
1723 // using the 0x80000008 leaf of the CPUID instruction
1724 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
1725 !getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
1726 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
1727 Features["rdpru"] = HasExtLeaf8 && ((EBX >> 4) & 1);
1728 Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
1729
1730 bool HasLeaf7 =
1731 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
1732
1733 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
1734 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
1735 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
1736 // AVX2 is only supported if we have the OS save support from AVX.
1737 Features["avx2"] = HasLeaf7 && ((EBX >> 5) & 1) && HasAVXSave;
1738 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1);
1739 Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1);
1740 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1);
1741 // AVX512 is only supported if the OS supports the context save for it.
1742 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
1743 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
1744 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
1745 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
1746 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save;
1747 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
1748 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
1749 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save;
1750 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save;
1751 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save;
1752 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);
1753 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
1754 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
1755
1756 Features["prefetchwt1"] = HasLeaf7 && ((ECX >> 0) & 1);
1757 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
1758 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
1759 Features["waitpkg"] = HasLeaf7 && ((ECX >> 5) & 1);
1760 Features["avx512vbmi2"] = HasLeaf7 && ((ECX >> 6) & 1) && HasAVX512Save;
1761 Features["shstk"] = HasLeaf7 && ((ECX >> 7) & 1);
1762 Features["gfni"] = HasLeaf7 && ((ECX >> 8) & 1);
1763 Features["vaes"] = HasLeaf7 && ((ECX >> 9) & 1) && HasAVXSave;
1764 Features["vpclmulqdq"] = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
1765 Features["avx512vnni"] = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
1766 Features["avx512bitalg"] = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
1767 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
1768 Features["rdpid"] = HasLeaf7 && ((ECX >> 22) & 1);
1769 Features["kl"] = HasLeaf7 && ((ECX >> 23) & 1); // key locker
1770 Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
1771 Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
1772 Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
1773 Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
1774
1775 Features["uintr"] = HasLeaf7 && ((EDX >> 5) & 1);
1776 Features["avx512vp2intersect"] =
1777 HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save;
1778 Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1);
1779 Features["tsxldtrk"] = HasLeaf7 && ((EDX >> 16) & 1);
1780 // There are two CPUID leafs which information associated with the pconfig
1781 // instruction:
1782 // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
1783 // bit of EDX), while the EAX=0x1b leaf returns information on the
1784 // availability of specific pconfig leafs.
1785 // The target feature here only refers to the the first of these two.
1786 // Users might need to check for the availability of specific pconfig
1787 // leaves using cpuid, since that information is ignored while
1788 // detecting features using the "-march=native" flag.
1789 // For more info, see X86 ISA docs.
1790 Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
1791 Features["amx-bf16"] = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
1792 Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save;
1793 Features["amx-tile"] = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
1794 Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
1795 // EAX from subleaf 0 is the maximum subleaf supported. Some CPUs don't
1796 // return all 0s for invalid subleaves so check the limit.
1797 bool HasLeaf7Subleaf1 =
1798 HasLeaf7 && EAX >= 1 &&
1799 !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
1800 Features["sha512"] = HasLeaf7Subleaf1 && ((EAX >> 0) & 1);
1801 Features["sm3"] = HasLeaf7Subleaf1 && ((EAX >> 1) & 1);
1802 Features["sm4"] = HasLeaf7Subleaf1 && ((EAX >> 2) & 1);
1803 Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
1804 Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
1805 Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
1806 Features["amx-fp16"] = HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave;
1807 Features["cmpccxadd"] = HasLeaf7Subleaf1 && ((EAX >> 7) & 1);
1808 Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
1809 Features["avxifma"] = HasLeaf7Subleaf1 && ((EAX >> 23) & 1) && HasAVXSave;
1810 Features["avxvnniint8"] = HasLeaf7Subleaf1 && ((EDX >> 4) & 1) && HasAVXSave;
1811 Features["avxneconvert"] = HasLeaf7Subleaf1 && ((EDX >> 5) & 1) && HasAVXSave;
1812 Features["amx-complex"] = HasLeaf7Subleaf1 && ((EDX >> 8) & 1) && HasAMXSave;
1813 Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && HasAVXSave;
1814 Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
1815 Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
1816 Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
1817
1818 bool HasLeafD = MaxLevel >= 0xd &&
1819 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
1820
1821 // Only enable XSAVE if OS has enabled support for saving YMM state.
1822 Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
1823 Features["xsavec"] = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
1824 Features["xsaves"] = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
1825
1826 bool HasLeaf14 = MaxLevel >= 0x14 &&
1827 !getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
1828
1829 Features["ptwrite"] = HasLeaf14 && ((EBX >> 4) & 1);
1830
1831 bool HasLeaf19 =
1832 MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX);
1833 Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1);
1834
1835 bool HasLeaf24 =
1836 MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);
1837 Features["avx10.1-512"] =
1838 Features["avx10.1-256"] && HasLeaf24 && ((EBX >> 18) & 1);
1839
1840 return true;
1841}
1842#elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
1844 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent();
1845 if (!P)
1846 return false;
1847
1849 P->getBuffer().split(Lines, "\n");
1850
1852
1853 // Look for the CPU features.
1854 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
1855 if (Lines[I].startswith("Features")) {
1856 Lines[I].split(CPUFeatures, ' ');
1857 break;
1858 }
1859
1860#if defined(__aarch64__)
1861 // Keep track of which crypto features we have seen
1862 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 };
1863 uint32_t crypto = 0;
1864#endif
1865
1866 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
1867 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
1868#if defined(__aarch64__)
1869 .Case("asimd", "neon")
1870 .Case("fp", "fp-armv8")
1871 .Case("crc32", "crc")
1872 .Case("atomics", "lse")
1873 .Case("sve", "sve")
1874 .Case("sve2", "sve2")
1875#else
1876 .Case("half", "fp16")
1877 .Case("neon", "neon")
1878 .Case("vfpv3", "vfp3")
1879 .Case("vfpv3d16", "vfp3d16")
1880 .Case("vfpv4", "vfp4")
1881 .Case("idiva", "hwdiv-arm")
1882 .Case("idivt", "hwdiv")
1883#endif
1884 .Default("");
1885
1886#if defined(__aarch64__)
1887 // We need to check crypto separately since we need all of the crypto
1888 // extensions to enable the subtarget feature
1889 if (CPUFeatures[I] == "aes")
1890 crypto |= CAP_AES;
1891 else if (CPUFeatures[I] == "pmull")
1892 crypto |= CAP_PMULL;
1893 else if (CPUFeatures[I] == "sha1")
1894 crypto |= CAP_SHA1;
1895 else if (CPUFeatures[I] == "sha2")
1896 crypto |= CAP_SHA2;
1897#endif
1898
1899 if (LLVMFeatureStr != "")
1900 Features[LLVMFeatureStr] = true;
1901 }
1902
1903#if defined(__aarch64__)
1904 // If we have all crypto bits we can add the feature
1905 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
1906 Features["crypto"] = true;
1907#endif
1908
1909 return true;
1910}
1911#elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64))
1913 if (IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE))
1914 Features["neon"] = true;
1915 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
1916 Features["crc"] = true;
1917 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
1918 Features["crypto"] = true;
1919
1920 return true;
1921}
1922#elif defined(__linux__) && defined(__loongarch__)
1923#include <sys/auxv.h>
1925 unsigned long hwcap = getauxval(AT_HWCAP);
1926 bool HasFPU = hwcap & (1UL << 3); // HWCAP_LOONGARCH_FPU
1927 uint32_t cpucfg2 = 0x2;
1928 __asm__("cpucfg %[cpucfg2], %[cpucfg2]\n\t" : [cpucfg2] "+r"(cpucfg2));
1929
1930 Features["f"] = HasFPU && (cpucfg2 & (1U << 1)); // CPUCFG.2.FP_SP
1931 Features["d"] = HasFPU && (cpucfg2 & (1U << 2)); // CPUCFG.2.FP_DP
1932
1933 Features["lsx"] = hwcap & (1UL << 4); // HWCAP_LOONGARCH_LSX
1934 Features["lasx"] = hwcap & (1UL << 5); // HWCAP_LOONGARCH_LASX
1935 Features["lvz"] = hwcap & (1UL << 9); // HWCAP_LOONGARCH_LVZ
1936
1937 return true;
1938}
1939#else
1940bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; }
1941#endif
1942
1943#if __APPLE__
1944/// \returns the \p triple, but with the Host's arch spliced in.
1945static Triple withHostArch(Triple T) {
1946#if defined(__arm__)
1947 T.setArch(Triple::arm);
1948 T.setArchName("arm");
1949#elif defined(__arm64e__)
1951 T.setArchName("arm64e");
1952#elif defined(__aarch64__)
1953 T.setArch(Triple::aarch64);
1954 T.setArchName("arm64");
1955#elif defined(__x86_64h__)
1956 T.setArch(Triple::x86_64);
1957 T.setArchName("x86_64h");
1958#elif defined(__x86_64__)
1959 T.setArch(Triple::x86_64);
1960 T.setArchName("x86_64");
1961#elif defined(__i386__)
1962 T.setArch(Triple::x86);
1963 T.setArchName("i386");
1964#elif defined(__powerpc__)
1965 T.setArch(Triple::ppc);
1966 T.setArchName("powerpc");
1967#else
1968# error "Unimplemented host arch fixup"
1969#endif
1970 return T;
1971}
1972#endif
1973
1975 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE);
1976 Triple PT(Triple::normalize(TargetTripleString));
1977
1978#if __APPLE__
1979 /// In Universal builds, LLVM_HOST_TRIPLE will have the wrong arch in one of
1980 /// the slices. This fixes that up.
1981 PT = withHostArch(PT);
1982#endif
1983
1984 if (sizeof(void *) == 8 && PT.isArch32Bit())
1985 PT = PT.get64BitArchVariant();
1986 if (sizeof(void *) == 4 && PT.isArch64Bit())
1987 PT = PT.get32BitArchVariant();
1988
1989 return PT.str();
1990}
1991
1993#if LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO
1994 std::string CPU = std::string(sys::getHostCPUName());
1995 if (CPU == "generic")
1996 CPU = "(unknown)";
1997 OS << " Default target: " << sys::getDefaultTargetTriple() << '\n'
1998 << " Host CPU: " << CPU << '\n';
1999#endif
2000}
This file defines the StringMap class.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:203
Given that RA is a live value
T Content
static std::unique_ptr< llvm::MemoryBuffer > LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent()
Definition: Host.cpp:65
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Magic.cpp:28
#define P(N)
raw_pwrite_stream & OS
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Represents either an error or a value T.
Definition: ErrorOr.h:56
static ErrorOr< std::unique_ptr< MemoryBuffer > > getFileAsStream(const Twine &Filename)
Read all of the specified file into a MemoryBuffer as a stream (i.e.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
Definition: StringMap.h:112
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:704
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
iterator begin() const
Definition: StringRef.h:111
iterator end() const
Definition: StringRef.h:113
bool endswith(StringRef Suffix) const
Definition: StringRef.h:280
static constexpr size_t npos
Definition: StringRef.h:52
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
StringSwitch & StartsWith(StringLiteral S, T Value)
Definition: StringSwitch.h:83
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::Triple get32BitArchVariant() const
Form a triple with a 32-bit variant of the current architecture.
Definition: Triple.cpp:1481
std::string normalize() const
Return the normalized form of this triple's string.
Definition: Triple.h:350
llvm::Triple get64BitArchVariant() const
Form a triple with a 64-bit variant of the current architecture.
Definition: Triple.cpp:1562
const std::string & str() const
Definition: Triple.h:416
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1469
@ AArch64SubArch_arm64e
Definition: Triple.h:149
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1473
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
@ CPU_SUBTYPE_POWERPC_970
Definition: MachO.h:1663
@ CPU_SUBTYPE_POWERPC_604e
Definition: MachO.h:1658
@ CPU_SUBTYPE_POWERPC_603e
Definition: MachO.h:1655
@ CPU_SUBTYPE_POWERPC_7400
Definition: MachO.h:1661
@ CPU_SUBTYPE_POWERPC_604
Definition: MachO.h:1657
@ CPU_SUBTYPE_POWERPC_750
Definition: MachO.h:1660
@ CPU_SUBTYPE_POWERPC_601
Definition: MachO.h:1652
@ CPU_SUBTYPE_POWERPC_620
Definition: MachO.h:1659
@ CPU_SUBTYPE_POWERPC_603ev
Definition: MachO.h:1656
@ CPU_SUBTYPE_POWERPC_603
Definition: MachO.h:1654
@ CPU_SUBTYPE_POWERPC_7450
Definition: MachO.h:1662
@ CPU_SUBTYPE_POWERPC_602
Definition: MachO.h:1653
Helper functions to extract CPU details from CPUID on x86.
Definition: Host.h:72
VendorSignatures getVendorSignature(unsigned *MaxLeaf=nullptr)
Returns the host CPU's vendor.
Definition: Host.cpp:1641
StringRef getHostCPUNameForS390x(StringRef ProcCpuinfoContent)
Definition: Host.cpp:358
StringRef getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent)
Helper functions to extract HostCPUName from /proc/cpuinfo on linux.
Definition: Host.cpp:76
StringRef getHostCPUNameForBPF()
Definition: Host.cpp:423
StringRef getHostCPUNameForARM(StringRef ProcCpuinfoContent)
Definition: Host.cpp:159
StringRef getHostCPUNameForRISCV(StringRef ProcCpuinfoContent)
Definition: Host.cpp:403
StringRef getHostCPUNameForSPARC(StringRef ProcCpuinfoContent)
StringRef getHostCPUName()
getHostCPUName - Get the LLVM name for the host CPU.
Definition: Host.cpp:1635
void printDefaultTargetAndDetectedCPU(raw_ostream &OS)
This is a function compatible with cl::AddExtraVersionPrinter, which adds info about the current targ...
Definition: Host.cpp:1992
bool getHostCPUFeatures(StringMap< bool, MallocAllocator > &Features)
getHostCPUFeatures - Get the LLVM names for the host CPU features.
std::string getProcessTriple()
getProcessTriple() - Return an appropriate target triple for generating code to be loaded into the cu...
Definition: Host.cpp:1974
std::string getDefaultTargetTriple()
getDefaultTargetTriple() - Return the default target triple the compiler has been configured to produ...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Length
Definition: DWP.cpp:456
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.