28#define DEBUG_TYPE "regalloc"
31const InterferenceCache::BlockInterference
32 InterferenceCache::Cursor::NoInterference;
43 if (PhysRegEntriesCount == TRI->
getNumRegs())
return;
46 PhysRegEntries =
static_cast<unsigned char*
>(
47 safe_calloc(PhysRegEntriesCount,
sizeof(
unsigned char)));
59 for (Entry &
E : Entries)
60 E.clear(mf, indexes, lis);
63InterferenceCache::Entry *InterferenceCache::get(
MCRegister PhysReg) {
64 unsigned char E = PhysRegEntries[PhysReg.
id()];
65 if (
E < CacheEntries && Entries[
E].getPhysReg() == PhysReg) {
66 if (!Entries[
E].valid(LIUArray, TRI))
67 Entries[
E].revalidate(LIUArray, TRI);
72 if (++RoundRobin == CacheEntries)
74 for (
unsigned i = 0; i != CacheEntries; ++i) {
76 if (Entries[
E].hasRefs()) {
77 if (++
E == CacheEntries)
81 Entries[
E].reset(PhysReg, LIUArray, TRI, MF);
82 PhysRegEntries[PhysReg] =
E;
97 RegUnits[i].VirtTag = LIUArray[*Units].
getTag();
100void InterferenceCache::Entry::reset(
MCRegister physReg,
104 assert(!hasRefs() &&
"Cannot reset cache entry with references");
114 RegUnits.push_back(LIUArray[*Units]);
115 RegUnits.back().Fixed = &LIS->getRegUnit(*Units);
121 unsigned i = 0,
e = RegUnits.size();
125 if (LIUArray[*Units].changedSince(RegUnits[i].VirtTag))
131void InterferenceCache::Entry::update(
unsigned MBBNum) {
133 std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
136 if (PrevPos != Start) {
137 if (!PrevPos.isValid() || Start < PrevPos) {
138 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
139 RegUnitInfo &RUI = RegUnits[i];
140 RUI.VirtI.find(Start);
141 RUI.FixedI = RUI.Fixed->find(Start);
144 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
145 RegUnitInfo &RUI = RegUnits[i];
146 RUI.VirtI.advanceTo(Start);
147 if (RUI.FixedI != RUI.Fixed->end())
148 RUI.FixedI = RUI.Fixed->advanceTo(RUI.FixedI, Start);
156 BlockInterference *BI = &
Blocks[MBBNum];
164 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
171 if (!BI->First.isValid() || StartI < BI->First)
176 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
184 if (!BI->First.isValid() || StartI < BI->First)
189 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
190 RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
192 for (
unsigned i = 0, e = RegMaskSlots.
size();
193 i != e && RegMaskSlots[i] < Limit; ++i)
196 BI->First = RegMaskSlots[i];
201 if (BI->First.isValid())
205 if (++MFI == MF->
end())
207 MBBNum = MFI->getNumber();
211 std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
215 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
217 if (!
I.valid() ||
I.start() >= Stop)
220 bool Backup = !
I.valid() ||
I.start() >= Stop;
224 if (!BI->Last.isValid() || StopI > BI->Last)
231 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
234 if (
I == LR->
end() ||
I->start >= Stop)
237 bool Backup =
I == LR->
end() ||
I->start >= Stop;
241 if (!BI->Last.isValid() || StopI > BI->Last)
249 for (
unsigned i = RegMaskSlots.
size();
250 i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i)
254 BI->Last = RegMaskSlots[i-1].getDeadSlot();
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
DenseMap< Block *, BlockRelaxAux > Blocks
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
void init(MachineFunction *mf, LiveIntervalUnion *liuarray, SlotIndexes *indexes, LiveIntervals *lis, const TargetRegisterInfo *tri)
init - Prepare cache for a new function.
void reinitPhysRegEntries()
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
LiveSegments::iterator SegmentIter
This class represents the liveness of a register, stack slot, etc.
iterator advanceTo(iterator I, SlotIndex Pos)
advanceTo - Advance the specified iterator to point to the Segment containing the specified position,...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
SlotIndex - An opaque wrapper around machine indexes.
bool isValid() const
Returns true if this is a valid index.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Iterator for intrusive lists based on ilist_node.
self_iterator getIterator()
unsigned getTag(StringRef TagString)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ATTRIBUTE_RETURNS_NONNULL void * safe_calloc(size_t Count, size_t Sz)