#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IntervalMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/ByteProvider.h"
#include "llvm/CodeGen/DAGCombine.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/RuntimeLibcallUtil.h"
#include "llvm/CodeGen/SDPatternMatch.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Metadata.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/DebugCounter.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <functional>
#include <iterator>
#include <optional>
#include <string>
#include <tuple>
#include <utility>
#include <variant>
#include "MatchContext.h"
#include "llvm/IR/VPIntrinsics.def"

Macros
#define	DEBUG_TYPE "dagcombine"

#define	BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) case ISD::SDOPC:

Typedefs
using	SDByteProvider = ByteProvider< SDNode * >
	Recursively traverses the expression calculating the origin of the requested byte of the given value.

Functions
	STATISTIC (NodesCombined, "Number of dag nodes combined")

	STATISTIC (PreIndexedNodes, "Number of pre-indexed nodes created")

	STATISTIC (PostIndexedNodes, "Number of post-indexed nodes created")

	STATISTIC (OpsNarrowed, "Number of load/op/store narrowed")

	STATISTIC (LdStFP2Int, "Number of fp load/store pairs transformed to int")

	STATISTIC (SlicedLoads, "Number of load sliced")

	STATISTIC (NumFPLogicOpsConv, "Number of logic ops converted to fp ops")

	DEBUG_COUNTER (DAGCombineCounter, "dagcombine", "Controls whether a DAG combine is performed for a node")

static void	zeroExtendToMatch (APInt &LHS, APInt &RHS, unsigned Offset=0)

static bool	isConstantSplatVectorMaskForType (SDNode *N, EVT ScalarTy)

static bool	isConstantOrConstantVector (SDValue N, bool NoOpaques=false)

static bool	isAnyConstantBuildVector (SDValue V, bool NoOpaques=false)

static bool	canSplitIdx (LoadSDNode *LD)

static SDValue	getInputChainForNode (SDNode *N)
	Given a node, return its input chain if it has one, otherwise return a null sd operand.

static ConstantSDNode *	getAsNonOpaqueConstant (SDValue N)
	If `N` is a ConstantSDNode with isOpaque() == false return it casted to a ConstantSDNode pointer else nullptr.

static bool	isTruncateOf (SelectionDAG &DAG, SDValue N, SDValue &Op, KnownBits &Known)

static bool	canFoldInAddressingMode (SDNode N, SDNode Use, SelectionDAG &DAG, const TargetLowering &TLI)
	Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode.

static SDValue	foldSelectWithIdentityConstant (SDNode *N, SelectionDAG &DAG, bool ShouldCommuteOperands)
	This inverts a canonicalization in IR that replaces a variable select arm with an identity constant.

static SDValue	foldAddSubBoolOfMaskedVal (SDNode *N, const SDLoc &DL, SelectionDAG &DAG)

static SDValue	foldAddSubOfSignBit (SDNode *N, const SDLoc &DL, SelectionDAG &DAG)
	Try to fold a 'not' shifted sign-bit with add/sub with constant operand into a shift and add with a different constant.

static bool	areBitwiseNotOfEachother (SDValue Op0, SDValue Op1)

static SDValue	getAsCarry (const TargetLowering &TLI, SDValue V, bool ForceCarryReconstruction=false)

static SDValue	foldAddSubMasked1 (bool IsAdd, SDValue N0, SDValue N1, SelectionDAG &DAG, const SDLoc &DL)
	Given the operands of an add/sub operation, see if the 2nd operand is a masked 0/1 whose source operand is actually known to be 0/-1.

static SDValue	extractBooleanFlip (SDValue V, SelectionDAG &DAG, const TargetLowering &TLI, bool Force)
	Flips a boolean if it is cheaper to compute.

static SDValue	combineUADDO_CARRYDiamond (DAGCombiner &Combiner, SelectionDAG &DAG, SDValue X, SDValue Carry0, SDValue Carry1, SDNode *N)
	If we are facing some sort of diamond carry propagation pattern try to break it up to generate something like: (uaddo_carry X, 0, (uaddo_carry A, B, Z):Carry)

static SDValue	combineCarryDiamond (SelectionDAG &DAG, const TargetLowering &TLI, SDValue N0, SDValue N1, SDNode *N)

static SDValue	getTruncatedUSUBSAT (EVT DstVT, EVT SrcVT, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &DL)

static SDValue	tryFoldToZero (const SDLoc &DL, const TargetLowering &TLI, EVT VT, SelectionDAG &DAG, bool LegalOperations)

static bool	isDivRemLibcallAvailable (SDNode *Node, bool isSigned, const TargetLowering &TLI)
	Return true if divmod libcall is available.

static SDValue	simplifyDivRem (SDNode *N, SelectionDAG &DAG)

static bool	isDivisorPowerOfTwo (SDValue Divisor)

static SDValue	isSaturatingMinMax (SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, unsigned &BW, bool &Unsigned, SelectionDAG &DAG)

static SDValue	PerformMinMaxFpToSatCombine (SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, SelectionDAG &DAG)

static SDValue	PerformUMinFpToSatCombine (SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, SelectionDAG &DAG)

static bool	arebothOperandsNotSNan (SDValue Operand1, SDValue Operand2, SelectionDAG &DAG)

static bool	arebothOperandsNotNan (SDValue Operand1, SDValue Operand2, SelectionDAG &DAG)

static unsigned	getMinMaxOpcodeForFP (SDValue Operand1, SDValue Operand2, ISD::CondCode CC, unsigned OrAndOpcode, SelectionDAG &DAG, bool isFMAXNUMFMINNUM_IEEE, bool isFMAXNUMFMINNUM)

static SDValue	foldAndOrOfSETCC (SDNode *LogicOp, SelectionDAG &DAG)

static SDValue	combineSelectAsExtAnd (SDValue Cond, SDValue T, SDValue F, const SDLoc &DL, SelectionDAG &DAG)

static SDValue	combineShiftAnd1ToBitTest (SDNode *And, SelectionDAG &DAG)
	Try to replace shift/logic that tests if a bit is clear with mask + setcc.

static SDValue	foldAndToUsubsat (SDNode *N, SelectionDAG &DAG, const SDLoc &DL)
	For targets that support usubsat, match a bit-hack form of that operation that ends in 'and' and convert it.

static SDValue	foldLogicOfShifts (SDNode *N, SDValue LogicOp, SDValue ShiftOp, SelectionDAG &DAG)
	Given a bitwise logic operation N with a matching bitwise logic operand, fold a pattern where 2 of the source operands are identically shifted values.

static SDValue	foldLogicTreeOfShifts (SDNode *N, SDValue LeftHand, SDValue RightHand, SelectionDAG &DAG)
	Given a tree of logic operations with shape like (LOGIC (LOGIC (X, Y), LOGIC (Z, Y))) try to match and fold shift operations with the same shift amount.

static bool	isBSwapHWordElement (SDValue N, MutableArrayRef< SDNode * > Parts)
	Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap.

static bool	isBSwapHWordPair (SDValue N, MutableArrayRef< SDNode * > Parts)

static SDValue	matchBSwapHWordOrAndAnd (const TargetLowering &TLI, SelectionDAG &DAG, SDNode *N, SDValue N0, SDValue N1, EVT VT)

static SDValue	visitORCommutative (SelectionDAG &DAG, SDValue N0, SDValue N1, SDNode *N)
	OR combines for which the commuted variant will be tried as well.

static SDValue	stripConstantMask (const SelectionDAG &DAG, SDValue Op, SDValue &Mask)

static bool	matchRotateHalf (const SelectionDAG &DAG, SDValue Op, SDValue &Shift, SDValue &Mask)
	Match "(X shl/srl V1) & V2" where V2 may not be present.

static SDValue	extractShiftForRotate (SelectionDAG &DAG, SDValue OppShift, SDValue ExtractFrom, SDValue &Mask, const SDLoc &DL)
	Helper function for visitOR to extract the needed side of a rotate idiom from a shl/srl/mul/udiv.

static bool	matchRotateSub (SDValue Pos, SDValue Neg, unsigned EltSize, SelectionDAG &DAG, bool IsRotate)

static std::optional< SDByteProvider >	calculateByteProvider (SDValue Op, unsigned Index, unsigned Depth, std::optional< uint64_t > VectorIndex, unsigned StartingIndex=0)

static unsigned	littleEndianByteAt (unsigned BW, unsigned i)

static unsigned	bigEndianByteAt (unsigned BW, unsigned i)

static std::optional< bool >	isBigEndian (const ArrayRef< int64_t > ByteOffsets, int64_t FirstOffset)

static SDValue	stripTruncAndExt (SDValue Value)

static SDValue	combineShiftOfShiftedLogic (SDNode *Shift, SelectionDAG &DAG)
	If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with identical opcode, we may be able to convert that into 2 independent shifts followed by the logic op.

static SDValue	combineShiftToMULH (SDNode *N, const SDLoc &DL, SelectionDAG &DAG, const TargetLowering &TLI)

static SDValue	foldBitOrderCrossLogicOp (SDNode *N, SelectionDAG &DAG)

static bool	isLegalToCombineMinNumMaxNum (SelectionDAG &DAG, SDValue LHS, SDValue RHS, const SDNodeFlags Flags, const TargetLowering &TLI)

static SDValue	combineMinNumMaxNumImpl (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode CC, const TargetLowering &TLI, SelectionDAG &DAG)

static SDValue	foldSelectOfConstantsUsingSra (SDNode *N, const SDLoc &DL, SelectionDAG &DAG)
	If a (v)select has a condition value that is a sign-bit test, try to smear the condition operand sign-bit across the value width and use it as a mask.

static bool	shouldConvertSelectOfConstantsToMath (const SDValue &Cond, EVT VT, const TargetLowering &TLI)

template<class MatchContextClass >
static SDValue	foldBoolSelectToLogic (SDNode *N, const SDLoc &DL, SelectionDAG &DAG)

static SDValue	foldVSelectToSignBitSplatMask (SDNode *N, SelectionDAG &DAG)

static SDValue	ConvertSelectToConcatVector (SDNode *N, SelectionDAG &DAG)

bool	refineUniformBase (SDValue &BasePtr, SDValue &Index, bool IndexIsScaled, SelectionDAG &DAG, const SDLoc &DL)

bool	refineIndexType (SDValue &Index, ISD::MemIndexType &IndexType, EVT DataVT, SelectionDAG &DAG)

static bool	isCompatibleLoad (SDValue N, unsigned ExtOpcode)
	Check if N satisfies: N is used once.

static SDValue	tryToFoldExtendSelectLoad (SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG, const SDLoc &DL, CombineLevel Level)
	Fold (sext (select c, load x, load y)) -> (select c, sextload x, sextload y) (zext (select c, load x, load y)) -> (select c, zextload x, zextload y) (aext (select c, load x, load y)) -> (select c, extload x, extload y) This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).

static SDValue	tryToFoldExtendOfConstant (SDNode *N, const SDLoc &DL, const TargetLowering &TLI, SelectionDAG &DAG, bool LegalTypes)
	Try to fold a sext/zext/aext dag node into a ConstantSDNode or a build_vector of constants.

static bool	ExtendUsesToFormExtLoad (EVT VT, SDNode N, SDValue N0, unsigned ExtOpc, SmallVectorImpl< SDNode > &ExtendNodes, const TargetLowering &TLI)

static SDValue	tryToFoldExtOfExtload (SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType)

static SDValue	tryToFoldExtOfLoad (SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc, bool NonNegZExt=false)

static SDValue	tryToFoldExtOfMaskedLoad (SelectionDAG &DAG, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc)

static SDValue	tryToFoldExtOfAtomicLoad (SelectionDAG &DAG, const TargetLowering &TLI, EVT VT, SDValue N0, ISD::LoadExtType ExtLoadType)

static SDValue	foldExtendedSignBitTest (SDNode *N, SelectionDAG &DAG, bool LegalOperations)

static SDValue	widenCtPop (SDNode *Extend, SelectionDAG &DAG, const SDLoc &DL)
	Given an extending node with a pop-count operand, if the target does not support a pop-count in the narrow source type but does support it in the destination type, widen the pop-count to the destination type.

static SDValue	widenAbs (SDNode *Extend, SelectionDAG &DAG)

static SDValue	foldExtendVectorInregToExtendOfSubvector (SDNode *N, const SDLoc &DL, const TargetLowering &TLI, SelectionDAG &DAG, bool LegalOperations)

static SDValue	detectUSatUPattern (SDValue In, EVT VT)
	Detect patterns of truncation with unsigned saturation:

static SDValue	detectSSatSPattern (SDValue In, EVT VT)
	Detect patterns of truncation with signed saturation: (truncate (smin (smax (x, signed_min_of_dest_type), signed_max_of_dest_type)) to dest_type) or: (truncate (smax (smin (x, signed_max_of_dest_type), signed_min_of_dest_type)) to dest_type).

static SDValue	detectSSatUPattern (SDValue In, EVT VT, SelectionDAG &DAG, const SDLoc &DL)
	Detect patterns of truncation with unsigned saturation:

static SDValue	foldToSaturated (SDNode *N, EVT &VT, SDValue &Src, EVT &SrcVT, SDLoc &DL, const TargetLowering &TLI, SelectionDAG &DAG)

static SDNode *	getBuildPairElt (SDNode *N, unsigned i)

static unsigned	getPPCf128HiElementSelector (const SelectionDAG &DAG)

static bool	isContractableFMUL (const TargetOptions &Options, SDValue N)

static bool	hasNoInfs (const TargetOptions &Options, SDValue N)

static bool	CanCombineFCOPYSIGN_EXTEND_ROUND (EVT XTy, EVT YTy)
	copysign(x, fp_extend(y)) -> copysign(x, y) copysign(x, fp_round(y)) -> copysign(x, y) Operands to the functions are the type of X and Y respectively.

static bool	CanCombineFCOPYSIGN_EXTEND_ROUND (SDNode *N)

static SDValue	foldFPToIntToFP (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI)

static SDValue	FoldIntToFPToInt (SDNode *N, SelectionDAG &DAG)

static bool	getCombineLoadStoreParts (SDNode *N, unsigned Inc, unsigned Dec, bool &IsLoad, bool &IsMasked, SDValue &Ptr, const TargetLowering &TLI)

static bool	shouldCombineToPostInc (SDNode N, SDValue Ptr, SDNode PtrUse, SDValue &BasePtr, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG, const TargetLowering &TLI)

static SDNode *	getPostIndexedLoadStoreOp (SDNode *N, bool &IsLoad, bool &IsMasked, SDValue &Ptr, SDValue &BasePtr, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG, const TargetLowering &TLI)

static ElementCount	numVectorEltsOrZero (EVT T)

static bool	areUsedBitsDense (const APInt &UsedBits)
	Check that all bits set in `UsedBits` form a dense region, i.e., `UsedBits` looks like 0..0 1..1 0..0.

static bool	areSlicesNextToEachOther (const LoadedSlice &First, const LoadedSlice &Second)
	Check whether or not `First` and `Second` are next to each other in memory.

static void	adjustCostForPairing (SmallVectorImpl< LoadedSlice > &LoadedSlices, LoadedSlice::Cost &GlobalLSCost)
	Adjust the `GlobalLSCost` according to the target paring capabilities and the layout of the slices.

static bool	isSlicingProfitable (SmallVectorImpl< LoadedSlice > &LoadedSlices, const APInt &UsedBits, bool ForCodeSize)
	Check the profitability of all involved LoadedSlice.

static std::pair< unsigned, unsigned >	CheckForMaskedLoad (SDValue V, SDValue Ptr, SDValue Chain)
	Check to see if V is (and load (ptr), imm), where the load is having specific bytes cleared out.

static SDValue	ShrinkLoadReplaceStoreWithStore (const std::pair< unsigned, unsigned > &MaskInfo, SDValue IVal, StoreSDNode St, DAGCombiner DC)
	Check to see if IVal is something that provides a value as specified by MaskInfo.

static bool	mergeEltWithShuffle (SDValue &X, SDValue &Y, ArrayRef< int > Mask, SmallVectorImpl< int > &NewMask, SDValue Elt, unsigned InsIndex)

static SDValue	scalarizeExtractedBinop (SDNode *ExtElt, SelectionDAG &DAG, const SDLoc &DL, bool LegalOperations)
	Transform a vector binary operation into a scalar binary operation by moving the math/logic after an extract element of a vector.

static SDValue	reduceBuildVecToShuffleWithZero (SDNode *BV, SelectionDAG &DAG)

template<typename R , typename T >
static auto	getFirstIndexOf (R &&Range, const T &Val)

static SDValue	combineConcatVectorOfScalars (SDNode *N, SelectionDAG &DAG)

static SDValue	combineConcatVectorOfConcatVectors (SDNode *N, SelectionDAG &DAG)

static SDValue	combineConcatVectorOfExtracts (SDNode *N, SelectionDAG &DAG)

static SDValue	combineConcatVectorOfCasts (SDNode *N, SelectionDAG &DAG)

static SDValue	combineConcatVectorOfShuffleAndItsOperands (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalTypes, bool LegalOperations)

static SDValue	getSubVectorSrc (SDValue V, SDValue Index, EVT SubVT)

static SDValue	narrowInsertExtractVectorBinOp (SDNode *Extract, SelectionDAG &DAG, bool LegalOperations)

static SDValue	narrowExtractedVectorBinOp (SDNode *Extract, SelectionDAG &DAG, bool LegalOperations)
	If we are extracting a subvector produced by a wide binary operator try to use a narrow binary operator and/or avoid concatenation and extraction.

static SDValue	narrowExtractedVectorLoad (SDNode *Extract, SelectionDAG &DAG)
	If we are extracting a subvector from a wide vector load, convert to a narrow load to eliminate the extraction: (extract_subvector (load wide vector)) --> (load narrow vector)

static SDValue	foldExtractSubvectorFromShuffleVector (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations)
	Given EXTRACT_SUBVECTOR(VECTOR_SHUFFLE(Op0, Op1, Mask)), try to produce VECTOR_SHUFFLE(EXTRACT_SUBVECTOR(Op?, ?), EXTRACT_SUBVECTOR(Op?, ?), Mask')) iff it is legal and profitable to do so.

static SDValue	foldShuffleOfConcatUndefs (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG)
	Try to convert a wide shuffle of concatenated vectors into 2 narrow shuffles followed by concatenation.

static SDValue	partitionShuffleOfConcats (SDNode *N, SelectionDAG &DAG)

static SDValue	combineShuffleOfScalars (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI)

static std::optional< EVT >	canCombineShuffleToExtendVectorInreg (unsigned Opcode, EVT VT, std::function< bool(unsigned)> Match, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalTypes, bool LegalOperations)

static SDValue	combineShuffleToAnyExtendVectorInreg (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations)

static SDValue	combineShuffleToZeroExtendVectorInReg (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations)

static SDValue	combineTruncationShuffle (ShuffleVectorSDNode *SVN, SelectionDAG &DAG)

static SDValue	combineShuffleOfSplatVal (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG)

static SDValue	combineShuffleOfBitcast (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations)

static SDValue	formSplatFromShuffles (ShuffleVectorSDNode *OuterShuf, SelectionDAG &DAG)
	Combine shuffle of shuffle of the form: shuf (shuf X, undef, InnerMask), undef, OuterMask --> splat X.

static int	getShuffleMaskIndexOfOneElementFromOp0IntoOp1 (ArrayRef< int > Mask)
	If the shuffle mask is taking exactly one element from the first vector operand and passing through all other elements from the second vector operand, return the index of the mask element that is choosing an element from the first operand.

static SDValue	replaceShuffleOfInsert (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG)
	If a shuffle inserts exactly one element from a source vector operand into another vector operand and we can access the specified element as a scalar, then we can eliminate the shuffle.

static SDValue	simplifyShuffleOfShuffle (ShuffleVectorSDNode *Shuf)
	If we have a unary shuffle of a shuffle, see if it can be folded away completely.

static SDValue	scalarizeBinOpOfSplats (SDNode *N, SelectionDAG &DAG, const SDLoc &DL, bool LegalTypes)
	If a vector binop is performed on splat values, it may be profitable to extract, scalarize, and insert/splat.

static SDValue	takeInexpensiveLog2 (SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Op, unsigned Depth, bool AssumeNonZero)

Variables
static cl::opt< bool >	CombinerGlobalAA ("combiner-global-alias-analysis", cl::Hidden, cl::desc("Enable DAG combiner's use of IR alias analysis"))

static cl::opt< bool >	UseTBAA ("combiner-use-tbaa", cl::Hidden, cl::init(true), cl::desc("Enable DAG combiner's use of TBAA"))

static cl::opt< std::string >	CombinerAAOnlyFunc ("combiner-aa-only-func", cl::Hidden, cl::desc("Only use DAG-combiner alias analysis in this" " function"))

static cl::opt< bool >	StressLoadSlicing ("combiner-stress-load-slicing", cl::Hidden, cl::desc("Bypass the profitability model of load slicing"), cl::init(false))
	Hidden option to stress test load slicing, i.e., when this option is enabled, load slicing bypasses most of its profitability guards.

static cl::opt< bool >	MaySplitLoadIndex ("combiner-split-load-index", cl::Hidden, cl::init(true), cl::desc("DAG combiner may split indexing from loads"))

static cl::opt< bool >	EnableStoreMerging ("combiner-store-merging", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable merging multiple stores " "into a wider store"))

static cl::opt< unsigned >	TokenFactorInlineLimit ("combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048), cl::desc("Limit the number of operands to inline for Token Factors"))

static cl::opt< unsigned >	StoreMergeDependenceLimit ("combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10), cl::desc("Limit the number of times for the same StoreNode and RootNode " "to bail out in store merging dependence check"))

static cl::opt< bool >	EnableReduceLoadOpStoreWidth ("combiner-reduce-load-op-store-width", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable reducing the width of load/op/store " "sequence"))

static cl::opt< bool >	EnableShrinkLoadReplaceStoreWithStore ("combiner-shrink-load-replace-store-with-store", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable load/<replace bytes>/store with " "a narrower store"))

static cl::opt< bool >	EnableVectorFCopySignExtendRound ("combiner-vector-fcopysign-extend-round", cl::Hidden, cl::init(false), cl::desc("Enable merging extends and rounds into FCOPYSIGN on vector types"))

Macro Definition Documentation

◆ BEGIN_REGISTER_VP_SDNODE

#define BEGIN_REGISTER_VP_SDNODE	(	SDOPC,
		...
	)	case ISD::SDOPC:

◆ DEBUG_TYPE

#define DEBUG_TYPE "dagcombine"

Definition at line 85 of file DAGCombiner.cpp.

Typedef Documentation

◆ SDByteProvider

using SDByteProvider = ByteProvider<SDNode *>

Recursively traverses the expression calculating the origin of the requested byte of the given value.

Returns std::nullopt if the provider can't be calculated.

For all the values except the root of the expression, we verify that the value has exactly one use and if not then return std::nullopt. This way if the origin of the byte is returned it's guaranteed that the values which contribute to the byte are not used outside of this expression. However, there is a special case when dealing with vector loads – we allow more than one use if the load is a vector type. Since the values that contribute to the byte ultimately come from the ExtractVectorElements of the Load, we don't care if the Load has uses other than ExtractVectorElements, because those operations are independent from the pattern to be combined. For vector loads, we simply care that the ByteProviders are adjacent positions of the same vector, and their index matches the byte that is being provided. This is captured by the VectorIndex algorithm. VectorIndex is the index used in an ExtractVectorElement, and StartingIndex is the byte position we are trying to provide for the LoadCombine. If these do not match, then we can not combine the vector loads. Index uses the byte position we are trying to provide for and is matched against the shl and load size. The Index algorithm ensures the requested byte is provided for by the pattern, and the pattern does not over provide bytes.

*ExtractVectorElement

Definition at line 8653 of file DAGCombiner.cpp.

Function Documentation

◆ adjustCostForPairing()

static void adjustCostForPairing	(	SmallVectorImpl< LoadedSlice > &	LoadedSlices,
		LoadedSlice::Cost &	GlobalLSCost
	)

static

Adjust the GlobalLSCost according to the target paring capabilities and the layout of the slices.

Precondition: GlobalLSCost should account for at least as many loads as there is in the slices in LoadedSlices.

Definition at line 19631 of file DAGCombiner.cpp.

References areSlicesNextToEachOther(), assert(), llvm::First, LHS, RHS, llvm::SmallVectorBase< Size_T >::size(), and llvm::sort().

Referenced by isSlicingProfitable().

◆ areBitwiseNotOfEachother()

static bool areBitwiseNotOfEachother	(	SDValue	Op0,
		SDValue	Op1
	)

static

Definition at line 2622 of file DAGCombiner.cpp.

References llvm::SDValue::getOperand(), and llvm::isBitwiseNot().

◆ arebothOperandsNotNan()

static bool arebothOperandsNotNan	(	SDValue	Operand1,
		SDValue	Operand2,
		SelectionDAG &	DAG
	)

static

Definition at line 6068 of file DAGCombiner.cpp.

References llvm::SelectionDAG::isKnownNeverNaN().

Referenced by getMinMaxOpcodeForFP().

◆ arebothOperandsNotSNan()

static bool arebothOperandsNotSNan	(	SDValue	Operand1,
		SDValue	Operand2,
		SelectionDAG &	DAG
	)

static

Definition at line 6063 of file DAGCombiner.cpp.

References llvm::SelectionDAG::isKnownNeverSNaN().

Referenced by getMinMaxOpcodeForFP().

◆ areSlicesNextToEachOther()

static bool areSlicesNextToEachOther	(	const LoadedSlice &	First,
		const LoadedSlice &	Second
	)

static

Check whether or not First and Second are next to each other in memory.

This means that there is no hole between the bits loaded by First and the bits loaded by Second.

Definition at line 19616 of file DAGCombiner.cpp.

References areUsedBitsDense(), assert(), and llvm::First.

Referenced by adjustCostForPairing().

◆ areUsedBitsDense()

static bool areUsedBitsDense ( const APInt & UsedBits )

static

Check that all bits set in UsedBits form a dense region, i.e., UsedBits looks like 0..0 1..1 0..0.

Definition at line 19599 of file DAGCombiner.cpp.

References llvm::APInt::countl_zero(), llvm::APInt::countr_zero(), llvm::APInt::getActiveBits(), llvm::APInt::isAllOnes(), llvm::APInt::lshr(), and llvm::APInt::trunc().

Referenced by areSlicesNextToEachOther(), and isSlicingProfitable().

◆ bigEndianByteAt()

static unsigned bigEndianByteAt	(	unsigned	BW,
		unsigned	i
	)

static

Definition at line 8800 of file DAGCombiner.cpp.

◆ calculateByteProvider()

static std::optional< SDByteProvider > calculateByteProvider	(	SDValue	Op,
		unsigned	Index,
		unsigned	Depth,
		std::optional< uint64_t >	VectorIndex,
		unsigned	StartingIndex = `0`
	)

static

◆ CanCombineFCOPYSIGN_EXTEND_ROUND() [1/2]

static bool CanCombineFCOPYSIGN_EXTEND_ROUND	(	EVT	XTy,
		EVT	YTy
	)

inlinestatic

copysign(x, fp_extend(y)) -> copysign(x, y) copysign(x, fp_round(y)) -> copysign(x, y) Operands to the functions are the type of X and Y respectively.

Definition at line 17637 of file DAGCombiner.cpp.

References EnableVectorFCopySignExtendRound, and llvm::EVT::isVector().

Referenced by CanCombineFCOPYSIGN_EXTEND_ROUND().

◆ CanCombineFCOPYSIGN_EXTEND_ROUND() [2/2]

static bool CanCombineFCOPYSIGN_EXTEND_ROUND ( SDNode * N )

inlinestatic

Definition at line 17652 of file DAGCombiner.cpp.

References CanCombineFCOPYSIGN_EXTEND_ROUND(), llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), and N.

◆ canCombineShuffleToExtendVectorInreg()

static std::optional< EVT > canCombineShuffleToExtendVectorInreg	(	unsigned	Opcode,
		EVT	VT,
		std::function< bool(unsigned)>	Match,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalTypes,
		bool	LegalOperations
	)

static

Definition at line 25282 of file DAGCombiner.cpp.

References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::DataLayout::isBigEndian(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isTypeLegal(), and llvm::Match.

Referenced by combineShuffleToAnyExtendVectorInreg(), and combineShuffleToZeroExtendVectorInReg().

◆ canFoldInAddressingMode()

static bool canFoldInAddressingMode	(	SDNode *	N,
		SDNode *	Use,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)

static

Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode.

Definition at line 2320 of file DAGCombiner.cpp.

References llvm::ISD::ADD, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getTypeForEVT(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::TargetLoweringBase::isLegalAddressingMode(), N, llvm::Offset, llvm::TargetLoweringBase::AddrMode::Scale, and llvm::ISD::SUB.

◆ canSplitIdx()

static bool canSplitIdx ( LoadSDNode * LD )

static

Definition at line 1065 of file DAGCombiner.cpp.

References MaySplitLoadIndex, and llvm::ISD::TargetConstant.

◆ CheckForMaskedLoad()

static std::pair< unsigned, unsigned > CheckForMaskedLoad	(	SDValue	V,
		SDValue	Ptr,
		SDValue	Chain
	)

static

Check to see if V is (and load (ptr), imm), where the load is having specific bytes cleared out.

If so, return the byte size being masked out and the shift amount.

Definition at line 19840 of file DAGCombiner.cpp.

References llvm::ISD::AND, llvm::countl_zero(), llvm::countr_one(), llvm::countr_zero(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::hasOneUse(), llvm::ISD::isNormalLoad(), Ptr, and llvm::ISD::TokenFactor.

◆ combineCarryDiamond()

static SDValue combineCarryDiamond	(	SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		SDValue	N0,
		SDValue	N1,
		SDNode *	N
	)

static

◆ combineConcatVectorOfCasts()

static SDValue combineConcatVectorOfCasts	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

◆ combineConcatVectorOfConcatVectors()

static SDValue combineConcatVectorOfConcatVectors	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 23992 of file DAGCombiner.cpp.

References llvm::SmallVectorImpl< T >::append(), assert(), llvm::ISD::CONCAT_VECTORS, llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::TargetLoweringBase::isTypeLegal(), and N.

◆ combineConcatVectorOfExtracts()

static SDValue combineConcatVectorOfExtracts	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 24031 of file DAGCombiner.cpp.

References llvm::TargetLowering::buildLegalVectorShuffle(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::isScalableVector(), llvm::SDValue::isUndef(), N, and llvm::peekThroughBitcasts().

◆ combineConcatVectorOfScalars()

static SDValue combineConcatVectorOfScalars	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

◆ combineConcatVectorOfShuffleAndItsOperands()

static SDValue combineConcatVectorOfShuffleAndItsOperands	(	SDNode *	N,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalTypes,
		bool	LegalOperations
	)

static

Definition at line 24171 of file DAGCombiner.cpp.

References llvm::all_of(), llvm::append_range(), assert(), llvm::MutableArrayRef< T >::begin(), llvm::ISD::CONCAT_VECTORS, llvm::MutableArrayRef< T >::end(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), I, llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), isUndef(), llvm_unreachable, N, llvm::SDNode::ops(), llvm::SmallVectorImpl< T >::reserve(), llvm::ArrayRef< T >::size(), llvm::MutableArrayRef< T >::take_back(), llvm::MutableArrayRef< T >::take_front(), llvm::ISD::VECTOR_SHUFFLE, and llvm::zip().

◆ combineMinNumMaxNumImpl()

static SDValue combineMinNumMaxNumImpl	(	const SDLoc &	DL,
		EVT	VT,
		SDValue	LHS,
		SDValue	RHS,
		SDValue	True,
		SDValue	False,
		ISD::CondCode	CC,
		const TargetLowering &	TLI,
		SelectionDAG &	DAG
	)

static

◆ combineSelectAsExtAnd()

static SDValue combineSelectAsExtAnd	(	SDValue	Cond,
		SDValue	T,
		SDValue	F,
		const SDLoc &	DL,
		SelectionDAG &	DAG
	)

static

Definition at line 6317 of file DAGCombiner.cpp.

References llvm::ISD::AND, Cond, DL, F, llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::isNullConstant(), llvm::isOneConstant(), and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.

◆ combineShiftAnd1ToBitTest()

static SDValue combineShiftAnd1ToBitTest	(	SDNode *	And,
		SelectionDAG &	DAG
	)

static

Try to replace shift/logic that tests if a bit is clear with mask + setcc.

For a target with a bit test, this is expected to become test + set and save at least 1 instruction.

Definition at line 6740 of file DAGCombiner.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::BitWidth, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::TargetLoweringBase::hasBitTest(), llvm::SDValue::hasOneUse(), llvm::isBitwiseNot(), llvm::isOneConstant(), llvm::TargetLoweringBase::isTypeLegal(), llvm::ISD::SETEQ, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and X.

◆ combineShiftOfShiftedLogic()

static SDValue combineShiftOfShiftedLogic	(	SDNode *	Shift,
		SelectionDAG &	DAG
	)

static

If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with identical opcode, we may be able to convert that into 2 independent shifts followed by the logic op.

This is a throughput improvement.

Definition at line 9598 of file DAGCombiner.cpp.

References llvm::ISD::AND, assert(), DL, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::isConstOrConstSplat(), llvm::ISD::OR, llvm::APInt::uadd_ov(), llvm::APInt::uge(), X, llvm::ISD::XOR, and Y.

◆ combineShiftToMULH()

static SDValue combineShiftToMULH	(	SDNode *	N,
		const SDLoc &	DL,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)

static

◆ combineShuffleOfBitcast()

static SDValue combineShuffleOfBitcast	(	ShuffleVectorSDNode *	SVN,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalOperations
	)

static

◆ combineShuffleOfScalars()

static SDValue combineShuffleOfScalars	(	ShuffleVectorSDNode *	SVN,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)

static

Definition at line 25199 of file DAGCombiner.cpp.

References llvm::EVT::bitsLT(), llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getBuildVector(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDNode::hasOneUse(), Idx, llvm::SmallSet< T, N, C >::insert(), isAnyConstantBuildVector(), llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isInteger(), llvm::isIntOrFPConstant(), llvm::SDValue::isUndef(), llvm::TargetLoweringBase::isZExtFree(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ISD::SCALAR_TO_VECTOR.

◆ combineShuffleOfSplatVal()

static SDValue combineShuffleOfSplatVal	(	ShuffleVectorSDNode *	Shuf,
		SelectionDAG &	DAG
	)

static

Definition at line 25543 of file DAGCombiner.cpp.

References assert(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), Idx, llvm::ShuffleVectorSDNode::isSplat(), llvm::SelectionDAG::isSplatValue(), llvm::SDValue::isUndef(), llvm::APInt::popcount(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::APInt::setBit(), llvm::ArrayRef< T >::size(), and llvm::Splat.

◆ combineShuffleToAnyExtendVectorInreg()

static SDValue combineShuffleToAnyExtendVectorInreg	(	ShuffleVectorSDNode *	SVN,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalOperations
	)

static

Definition at line 25320 of file DAGCombiner.cpp.

References llvm::ISD::ANY_EXTEND_VECTOR_INREG, canCombineShuffleToExtendVectorInreg(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::DataLayout::isBigEndian(), and llvm::EVT::isInteger().

◆ combineShuffleToZeroExtendVectorInReg()

static SDValue combineShuffleToZeroExtendVectorInReg	(	ShuffleVectorSDNode *	SVN,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalOperations
	)

static

Definition at line 25358 of file DAGCombiner.cpp.

References llvm::all_of(), assert(), canCombineShuffleToExtendVectorInreg(), llvm::ShuffleVectorSDNode::commuteMask(), llvm::SelectionDAG::computeVectorKnownZeroElements(), llvm::ArrayRef< T >::drop_front(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::getShuffleMaskWithWidestElts(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::APInt::getZero(), I, llvm::DataLayout::isBigEndian(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDNode::ops(), llvm::ArrayRef< T >::size(), llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::ZERO_EXTEND_VECTOR_INREG, and llvm::zip().

◆ combineTruncationShuffle()

static SDValue combineTruncationShuffle	(	ShuffleVectorSDNode *	SVN,
		SelectionDAG &	DAG
	)

static

Definition at line 25484 of file DAGCombiner.cpp.

References llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::DataLayout::isBigEndian(), llvm::ISD::isExtVecInRegOpcode(), llvm::EVT::isInteger(), and llvm::peekThroughBitcasts().

◆ combineUADDO_CARRYDiamond()

static SDValue combineUADDO_CARRYDiamond	(	DAGCombiner &	Combiner,
		SelectionDAG &	DAG,
		SDValue	X,
		SDValue	Carry0,
		SDValue	Carry1,
		SDNode *	N
	)

static

If we are facing some sort of diamond carry propagation pattern try to break it up to generate something like: (uaddo_carry X, 0, (uaddo_carry A, B, Z):Carry)

The end result is usually an increase in operation required, but because the carry is now linearized, other transforms can kick in and optimize the DAG.

Patterns typically look something like (uaddo A, B) / \ Carry Sum | \ | (uaddo_carry *, 0, Z) | / \ Carry | / (uaddo_carry X, *, *)

But numerous variation exist. Our goal is to identify A, B, X and Z and produce a combine with a single path for carry propagation.

First look for a suitable Z. It will present itself in the form of (uaddo_carry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true

    (uaddo A, B)
         |
        Sum
         |

(uaddo_carry *, 0, Z)

(uaddo_carry A, 0, Z) | Sum | (uaddo *, B)

Definition at line 3437 of file DAGCombiner.cpp.

References A, B, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SDNode::getVTList(), llvm::isNullConstant(), llvm::isOneConstant(), N, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, and X.

◆ ConvertSelectToConcatVector()

static SDValue ConvertSelectToConcatVector	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 11793 of file DAGCombiner.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, Cond, DL, llvm::SelectionDAG::getNode(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::isZero(), LHS, N, and RHS.

◆ DEBUG_COUNTER()

DEBUG_COUNTER	(	DAGCombineCounter	,
		"dagcombine"	,
		"Controls whether a DAG combine is performed for a node"
	)

◆ detectSSatSPattern()

static SDValue detectSSatSPattern	(	SDValue	In,
		EVT	VT
	)

static

Detect patterns of truncation with signed saturation: (truncate (smin (smax (x, signed_min_of_dest_type), signed_max_of_dest_type)) to dest_type) or: (truncate (smax (smin (x, signed_max_of_dest_type), signed_min_of_dest_type)) to dest_type).

Return the source value to be truncated or SDValue() if the pattern was not matched.

Definition at line 14968 of file DAGCombiner.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), llvm::PatternMatch::m_SMax(), llvm::PatternMatch::m_SMin(), llvm::PatternMatch::m_SpecificInt(), llvm::PatternMatch::m_Value(), llvm::SDPatternMatch::sd_match(), and llvm::APInt::sext().

Referenced by foldToSaturated().

◆ detectSSatUPattern()

static SDValue detectSSatUPattern	(	SDValue	In,
		EVT	VT,
		SelectionDAG &	DAG,
		const SDLoc &	DL
	)

static

Detect patterns of truncation with unsigned saturation:

Definition at line 14990 of file DAGCombiner.cpp.

References assert(), llvm::APInt::getMaxValue(), llvm::EVT::getScalarSizeInBits(), llvm::PatternMatch::m_SMax(), llvm::PatternMatch::m_SMin(), llvm::PatternMatch::m_SpecificInt(), llvm::PatternMatch::m_UMin(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), llvm::SDPatternMatch::sd_match(), and llvm::APInt::zext().

Referenced by foldToSaturated().

◆ detectUSatUPattern()

static SDValue detectUSatUPattern	(	SDValue	In,
		EVT	VT
	)

static

Detect patterns of truncation with unsigned saturation:

(truncate (umin (x, unsigned_max_of_dest_type)) to dest_type). Return the source value x to be truncated or SDValue() if the pattern was not matched.

Definition at line 14945 of file DAGCombiner.cpp.

References assert(), llvm::APInt::getMaxValue(), llvm::EVT::getScalarSizeInBits(), llvm::PatternMatch::m_SpecificInt(), llvm::PatternMatch::m_UMin(), llvm::PatternMatch::m_Value(), llvm::SDPatternMatch::sd_match(), and llvm::APInt::zext().

Referenced by foldToSaturated().

◆ ExtendUsesToFormExtLoad()

static bool ExtendUsesToFormExtLoad	(	EVT	VT,
		SDNode *	N,
		SDValue	N0,
		unsigned	ExtOpc,
		SmallVectorImpl< SDNode * > &	ExtendNodes,
		const TargetLowering &	TLI
	)

static

◆ extractBooleanFlip()

static SDValue extractBooleanFlip	(	SDValue	V,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	Force
	)

static

Flips a boolean if it is cheaper to compute.

If the Force parameters is set, then the flip also occurs if computing the inverse is the same cost. This function returns an empty SDValue in case it cannot flip the boolean without increasing the cost of the computation. If you want to flip a boolean no matter what, use DAG.getLogicalNOT.

Definition at line 3254 of file DAGCombiner.cpp.

References llvm::SelectionDAG::getLogicalNOT(), llvm::SelectionDAG::isBoolConstant(), llvm::isConstOrConstSplat(), and llvm::ISD::XOR.

◆ extractShiftForRotate()

static SDValue extractShiftForRotate	(	SelectionDAG &	DAG,
		SDValue	OppShift,
		SDValue	ExtractFrom,
		SDValue &	Mask,
		const SDLoc &	DL
	)

static

Helper function for visitOR to extract the needed side of a rotate idiom from a shl/srl/mul/udiv.

This is meant to handle cases where InstCombine merged some outside op with one of the shifts from the rotate pattern.

Returns: An empty SDValue if the needed shift couldn't be extracted. Otherwise, returns an expansion of ExtractFrom based on the following patterns:

(or (add v v) (shrl v bitwidth-1)): expands (add v v) -> (shl v 1)

(or (mul v c0) (shrl (mul v c1) c2)): expands (mul v c0) -> (shl (mul v c1) c3)

(or (udiv v c0) (shl (udiv v c1) c2)): expands (udiv v c0) -> (shrl (udiv v c1) c3)

(or (shl v c0) (shrl (shl v c1) c2)): expands (shl v c0) -> (shl (shl v c1) c3)

(or (shrl v c0) (shl (shrl v c1) c2)): expands (shrl v c0) -> (shrl (shrl v c1) c3)

Such that in all cases, c3+c2==bitwidth(op v c1).

Definition at line 8041 of file DAGCombiner.cpp.

References llvm::ISD::ADD, assert(), llvm::ISD::DELETED_NODE, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::isConstOrConstSplat(), llvm::ISD::MUL, llvm::ISD::SHL, llvm::ISD::SRL, stripConstantMask(), llvm::ISD::UDIV, llvm::APInt::udivrem(), llvm::APInt::ugt(), zeroExtendToMatch(), and llvm::APInt::zextOrTrunc().

◆ foldAddSubBoolOfMaskedVal()

static SDValue foldAddSubBoolOfMaskedVal	(	SDNode *	N,
		const SDLoc &	DL,
		SelectionDAG &	DAG
	)

static

◆ foldAddSubMasked1()

static SDValue foldAddSubMasked1	(	bool	IsAdd,
		SDValue	N0,
		SDValue	N1,
		SelectionDAG &	DAG,
		const SDLoc &	DL
	)

static

Given the operands of an add/sub operation, see if the 2nd operand is a masked 0/1 whose source operand is actually known to be 0/-1.

If so, invert the opcode and bypass the mask operation.

Definition at line 3104 of file DAGCombiner.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::SelectionDAG::ComputeNumSignBits(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::isOneOrOneSplat(), llvm::ISD::SUB, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

◆ foldAddSubOfSignBit()

static SDValue foldAddSubOfSignBit	(	SDNode *	N,
		const SDLoc &	DL,
		SelectionDAG &	DAG
	)

static

Try to fold a 'not' shifted sign-bit with add/sub with constant operand into a shift and add with a different constant.

Definition at line 2581 of file DAGCombiner.cpp.

References llvm::ISD::ADD, assert(), DL, llvm::SelectionDAG::FoldConstantArithmetic(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::isBitwiseNot(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), llvm::isConstOrConstSplat(), N, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::SUB.

◆ foldAndOrOfSETCC()

static SDValue foldAndOrOfSETCC	(	SDNode *	LogicOp,
		SelectionDAG &	DAG
	)

static

Definition at line 6130 of file DAGCombiner.cpp.

References llvm::ISD::ABS, llvm::TargetLoweringBase::ABS, llvm::ISD::ADD, llvm::TargetLoweringBase::AddAnd, llvm::ISD::AND, assert(), llvm::CallingConv::C, CC, llvm::ISD::DELETED_NODE, DL, llvm::SelectionDAG::doesNodeExist(), llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::SelectionDAG::getConstant(), getMinMaxOpcodeForFP(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCSwappedOperands(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::Value::hasOneUse(), llvm::APInt::isAllOnes(), llvm::isAllOnesOrAllOnesSplat(), llvm::isConstOrConstSplat(), llvm::TargetLowering::isDesirableToCombineLogicOpOfSETCC(), llvm::EVT::isFloatingPoint(), llvm::ISD::isFPEqualitySetCC(), llvm::EVT::isInteger(), llvm::ISD::isIntEqualitySetCC(), llvm::APInt::isNegative(), llvm::isNullOrNullSplat(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::APInt::isPowerOf2(), llvm::APInt::isZero(), LHS, llvm::TargetLoweringBase::None, llvm::TargetLoweringBase::NotAnd, llvm::ISD::OR, RHS, llvm::ISD::SETCC, llvm::ISD::SETCC_INVALID, llvm::ISD::SETEQ, llvm::ISD::SETFALSE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETTRUE, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUO, llvm::APIntOps::smax(), llvm::ISD::SMAX, llvm::APIntOps::smin(), llvm::ISD::SMIN, llvm::ISD::UMAX, and llvm::ISD::UMIN.

◆ foldAndToUsubsat()

static SDValue foldAndToUsubsat	(	SDNode *	N,
		SelectionDAG &	DAG,
		const SDLoc &	DL
	)

static

For targets that support usubsat, match a bit-hack form of that operation that ends in 'and' and convert it.

Definition at line 6814 of file DAGCombiner.cpp.

References llvm::BitWidth, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::APInt::getSignMask(), llvm::PatternMatch::m_Add(), llvm::PatternMatch::m_And(), llvm::PatternMatch::m_Deferred(), llvm::SDPatternMatch::m_OneUse(), llvm::PatternMatch::m_SpecificInt(), llvm::SDPatternMatch::m_Sra(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Xor(), N, llvm::SDPatternMatch::sd_match(), llvm::ISD::USUBSAT, and X.

◆ foldBitOrderCrossLogicOp()

static SDValue foldBitOrderCrossLogicOp	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 10264 of file DAGCombiner.cpp.

References llvm::ISD::BITREVERSE, llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::isBitwiseLogicOp(), and N.

◆ foldBoolSelectToLogic()

template<class MatchContextClass >

static SDValue foldBoolSelectToLogic	(	SDNode *	N,
		const SDLoc &	DL,
		SelectionDAG &	DAG
	)

static

Definition at line 11478 of file DAGCombiner.cpp.

References llvm::ISD::AND, assert(), Cond, DL, F, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getFreeze(), llvm::SDValue::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::isNullOrNullSplat(), llvm::isOneOrOneSplat(), N, llvm::ISD::OR, llvm::ISD::SELECT, llvm::ISD::VSELECT, and llvm::ISD::XOR.

◆ foldExtendedSignBitTest()

static SDValue foldExtendedSignBitTest	(	SDNode *	N,
		SelectionDAG &	DAG,
		bool	LegalOperations
	)

static

◆ foldExtendVectorInregToExtendOfSubvector()

static SDValue foldExtendVectorInregToExtendOfSubvector	(	SDNode *	N,
		const SDLoc &	DL,
		const TargetLowering &	TLI,
		SelectionDAG &	DAG,
		bool	LegalOperations
	)

static

Definition at line 14858 of file DAGCombiner.cpp.

References assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getOpcode_EXTEND(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::ISD::isExtVecInRegOpcode(), llvm::TargetLoweringBase::isOperationLegal(), and N.

◆ foldExtractSubvectorFromShuffleVector()

static SDValue foldExtractSubvectorFromShuffleVector	(	SDNode *	N,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalOperations
	)

static

Given EXTRACT_SUBVECTOR(VECTOR_SHUFFLE(Op0, Op1, Mask)), try to produce VECTOR_SHUFFLE(EXTRACT_SUBVECTOR(Op?, ?), EXTRACT_SUBVECTOR(Op?, ?), Mask')) iff it is legal and profitable to do so.

Notably, the trimmed mask (containing only the elements that are extracted) must reference at most two subvectors.

Definition at line 24713 of file DAGCombiner.cpp.

References llvm::any_of(), assert(), DL, llvm::SmallVectorImpl< T >::emplace_back(), llvm::ISD::EXTRACT_SUBVECTOR, getFirstIndexOf(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLoweringBase::isExtractSubvectorCheap(), llvm::EVT::isFixedLengthVector(), llvm::ShuffleVectorInst::isIdentityMask(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isShuffleMaskLegal(), N, llvm::SmallVectorImpl< T >::reserve(), llvm::SmallVectorBase< Size_T >::size(), and llvm::ISD::VECTOR_SHUFFLE.

◆ foldFPToIntToFP()

static SDValue foldFPToIntToFP	(	SDNode *	N,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)

static

Definition at line 17797 of file DAGCombiner.cpp.

References llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FTRUNC, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTarget(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::isOperationLegal(), N, llvm::TargetOptions::NoSignedZerosFPMath, llvm::TargetMachine::Options, llvm::ISD::SINT_TO_FP, and llvm::ISD::UINT_TO_FP.

◆ FoldIntToFPToInt()

static SDValue FoldIntToFPToInt	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 17916 of file DAGCombiner.cpp.

References llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getBitcast(), llvm::EVT::getFltSemantics(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), N, llvm::APFloatBase::semanticsPrecision(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, and llvm::ISD::ZERO_EXTEND.

◆ foldLogicOfShifts()

static SDValue foldLogicOfShifts	(	SDNode *	N,
		SDValue	LogicOp,
		SDValue	ShiftOp,
		SelectionDAG &	DAG
	)

static

Given a bitwise logic operation N with a matching bitwise logic operand, fold a pattern where 2 of the source operands are identically shifted values.

For example: ((X0 << Y) | Z) | (X1 << Y) --> ((X0 | X1) << Y) | Z

Definition at line 6839 of file DAGCombiner.cpp.

References assert(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::isBitwiseLogicOp(), N, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and Y.

Referenced by foldLogicTreeOfShifts(), and visitORCommutative().

◆ foldLogicTreeOfShifts()

static SDValue foldLogicTreeOfShifts	(	SDNode *	N,
		SDValue	LeftHand,
		SDValue	RightHand,
		SelectionDAG &	DAG
	)

static

Given a tree of logic operations with shape like (LOGIC (LOGIC (X, Y), LOGIC (Z, Y))) try to match and fold shift operations with the same shift amount.

For example: LOGIC (LOGIC (SH X0, Y), Z), (LOGIC (SH X1, Y), W) --> --> LOGIC (SH (LOGIC X0, X1), Y), (LOGIC Z, W)

Definition at line 6887 of file DAGCombiner.cpp.

References assert(), DL, foldLogicOfShifts(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::isBitwiseLogicOp(), and N.

◆ foldSelectOfConstantsUsingSra()

static SDValue foldSelectOfConstantsUsingSra	(	SDNode *	N,
		const SDLoc &	DL,
		SelectionDAG &	DAG
	)

static

If a (v)select has a condition value that is a sign-bit test, try to smear the condition operand sign-bit across the value width and use it as a mask.

Definition at line 11305 of file DAGCombiner.cpp.

References llvm::ISD::AND, CC, Cond, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::isAllOnesOrAllOnesSplat(), llvm::isConstantOrConstantVector(), llvm::isNullOrNullSplat(), N, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SRA, and X.

◆ foldSelectWithIdentityConstant()

static SDValue foldSelectWithIdentityConstant	(	SDNode *	N,
		SelectionDAG &	DAG,
		bool	ShouldCommuteOperands
	)

static

This inverts a canonicalization in IR that replaces a variable select arm with an identity constant.

Codegen improves if we re-use the variable operand rather than load a constant. This can also be converted into a masked vector operation if the target supports it.

Definition at line 2380 of file DAGCombiner.cpp.

References Cond, llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSelect(), llvm::SDValue::hasOneUse(), llvm::isNeutralConstant(), llvm::SelectionDAG::isSafeToSpeculativelyExecuteNode(), N, std::swap(), and llvm::ISD::VSELECT.

◆ foldShuffleOfConcatUndefs()

static SDValue foldShuffleOfConcatUndefs	(	ShuffleVectorSDNode *	Shuf,
		SelectionDAG &	DAG
	)

static

Try to convert a wide shuffle of concatenated vectors into 2 narrow shuffles followed by concatenation.

Narrow vector ops may have better performance than wide ops, and this can unlock further narrowing of other vector ops. Targets can invert this transform later if it is not profitable.

Definition at line 25072 of file DAGCombiner.cpp.

References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getContext(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::SDValue::isUndef(), X, and Y.

◆ foldToSaturated()

static SDValue foldToSaturated	(	SDNode *	N,
		EVT &	VT,
		SDValue &	Src,
		EVT &	SrcVT,
		SDLoc &	DL,
		const TargetLowering &	TLI,
		SelectionDAG &	DAG
	)

static

Definition at line 15015 of file DAGCombiner.cpp.

References detectSSatSPattern(), detectSSatUPattern(), detectUSatUPattern(), DL, llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLowering::isTypeDesirableForOp(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::TRUNCATE_SSAT_S, llvm::ISD::TRUNCATE_SSAT_U, llvm::ISD::TRUNCATE_USAT_U, and llvm::ISD::UMIN.

◆ foldVSelectToSignBitSplatMask()

static SDValue foldVSelectToSignBitSplatMask	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

◆ formSplatFromShuffles()

static SDValue formSplatFromShuffles	(	ShuffleVectorSDNode *	OuterShuf,
		SelectionDAG &	DAG
	)

static

Combine shuffle of shuffle of the form: shuf (shuf X, undef, InnerMask), undef, OuterMask --> splat X.

Definition at line 25691 of file DAGCombiner.cpp.

References llvm::all_of(), assert(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::getSplatIndex(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::SDValue::isUndef(), and llvm::ArrayRef< T >::size().

◆ getAsCarry()

static SDValue getAsCarry	(	const TargetLowering &	TLI,
		SDValue	V,
		bool	ForceCarryReconstruction = `false`
	)

static

Definition at line 3052 of file DAGCombiner.cpp.

References llvm::ISD::AND, llvm::TargetLoweringBase::getBooleanContents(), llvm::isOneConstant(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::Masked, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::ISD::ZERO_EXTEND, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.

Referenced by combineCarryDiamond().

◆ getAsNonOpaqueConstant()

static ConstantSDNode * getAsNonOpaqueConstant ( SDValue N )

static

If N is a ConstantSDNode with isOpaque() == false return it casted to a ConstantSDNode pointer else nullptr.

Definition at line 2292 of file DAGCombiner.cpp.

References N.

◆ getBuildPairElt()

static SDNode * getBuildPairElt	(	SDNode *	N,
		unsigned	i
	)

static

Definition at line 15380 of file DAGCombiner.cpp.

References llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::ISD::MERGE_VALUES, and N.

◆ getCombineLoadStoreParts()

static bool getCombineLoadStoreParts	(	SDNode *	N,
		unsigned	Inc,
		unsigned	Dec,
		bool &	IsLoad,
		bool &	IsMasked,
		SDValue &	Ptr,
		const TargetLowering &	TLI
	)

static

Definition at line 18508 of file DAGCombiner.cpp.

References llvm::TargetLoweringBase::isIndexedLoadLegal(), llvm::TargetLoweringBase::isIndexedMaskedLoadLegal(), llvm::TargetLoweringBase::isIndexedMaskedStoreLegal(), llvm::TargetLoweringBase::isIndexedStoreLegal(), N, and Ptr.

Referenced by getPostIndexedLoadStoreOp(), and shouldCombineToPostInc().

◆ getFirstIndexOf()

template<typename R , typename T >

static auto getFirstIndexOf	(	R &&	Range,
		const T &	Val
	)

static

Definition at line 23400 of file DAGCombiner.cpp.

References llvm::find(), I, and Range.

Referenced by foldExtractSubvectorFromShuffleVector().

◆ getInputChainForNode()

static SDValue getInputChainForNode ( SDNode * N )

static

Given a node, return its input chain if it has one, otherwise return a null sd operand.

Definition at line 2071 of file DAGCombiner.cpp.

References N.

◆ getMinMaxOpcodeForFP()

static unsigned getMinMaxOpcodeForFP	(	SDValue	Operand1,
		SDValue	Operand2,
		ISD::CondCode	CC,
		unsigned	OrAndOpcode,
		SelectionDAG &	DAG,
		bool	isFMAXNUMFMINNUM_IEEE,
		bool	isFMAXNUMFMINNUM
	)

static

Definition at line 6074 of file DAGCombiner.cpp.

References llvm::ISD::AND, arebothOperandsNotNan(), arebothOperandsNotSNan(), CC, llvm::ISD::DELETED_NODE, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::OR, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.

Referenced by foldAndOrOfSETCC().

◆ getPostIndexedLoadStoreOp()

static SDNode * getPostIndexedLoadStoreOp	(	SDNode *	N,
		bool &	IsLoad,
		bool &	IsMasked,
		SDValue &	Ptr,
		SDValue &	BasePtr,
		SDValue &	Offset,
		ISD::MemIndexedMode &	AM,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)

static

Definition at line 18823 of file DAGCombiner.cpp.

References getCombineLoadStoreParts(), llvm::SDNode::hasPredecessorHelper(), llvm::SmallPtrSetImpl< PtrType >::insert(), N, llvm::Offset, llvm::ISD::POST_DEC, llvm::ISD::POST_INC, Ptr, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and shouldCombineToPostInc().

◆ getPPCf128HiElementSelector()

static unsigned getPPCf128HiElementSelector ( const SelectionDAG & DAG )

static

Definition at line 15419 of file DAGCombiner.cpp.

References llvm::SelectionDAG::getDataLayout(), and llvm::DataLayout::isBigEndian().

◆ getShuffleMaskIndexOfOneElementFromOp0IntoOp1()

static int getShuffleMaskIndexOfOneElementFromOp0IntoOp1 ( ArrayRef< int > Mask )

static

If the shuffle mask is taking exactly one element from the first vector operand and passing through all other elements from the second vector operand, return the index of the mask element that is choosing an element from the first operand.

Otherwise, return -1.

Definition at line 25744 of file DAGCombiner.cpp.

Referenced by replaceShuffleOfInsert().

◆ getSubVectorSrc()

static SDValue getSubVectorSrc	(	SDValue	V,
		SDValue	Index,
		EVT	SubVT
	)

static

Definition at line 24464 of file DAGCombiner.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::EVT::getVectorMinNumElements(), and llvm::ISD::INSERT_SUBVECTOR.

Referenced by narrowInsertExtractVectorBinOp().

◆ getTruncatedUSUBSAT()

static SDValue getTruncatedUSUBSAT	(	EVT	DstVT,
		EVT	SrcVT,
		SDValue	LHS,
		SDValue	RHS,
		SelectionDAG &	DAG,
		const SDLoc &	DL
	)

static

Definition at line 3684 of file DAGCombiner.cpp.

References assert(), DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), LHS, llvm::SelectionDAG::MaskedValueIsZero(), RHS, llvm::ISD::TRUNCATE, llvm::ISD::UMIN, and llvm::ISD::USUBSAT.

◆ hasNoInfs()

static bool hasNoInfs	(	const TargetOptions &	Options,
		SDValue	N
	)

static

Definition at line 15964 of file DAGCombiner.cpp.

References N, and Options.

Referenced by llvm::SDNode::print_details().

◆ isAnyConstantBuildVector()

static bool isAnyConstantBuildVector	(	SDValue	V,
		bool	NoOpaques = `false`
	)

static

Definition at line 1057 of file DAGCombiner.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::ISD::isBuildVectorOfConstantFPSDNodes(), and llvm::isConstantOrConstantVector().

Referenced by combineShuffleOfBitcast(), combineShuffleOfScalars(), and scalarizeExtractedBinop().

◆ isBigEndian()

static std::optional< bool > isBigEndian	(	const ArrayRef< int64_t >	ByteOffsets,
		int64_t	FirstOffset
	)

static

Definition at line 8807 of file DAGCombiner.cpp.

References assert(), bigEndianByteAt(), littleEndianByteAt(), and llvm::ArrayRef< T >::size().

◆ isBSwapHWordElement()

static bool isBSwapHWordElement	(	SDValue	N,
		MutableArrayRef< SDNode * >	Parts
	)

static

Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap.

((x & 0x000000ff) << 8) | ((x & 0x0000ff00) >> 8) | ((x & 0x00ff0000) << 8) | ((x & 0xff000000) >> 8)

Definition at line 7456 of file DAGCombiner.cpp.

References llvm::ISD::AND, llvm::CallingConv::C, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), N, llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by isBSwapHWordPair().

◆ isBSwapHWordPair()

static bool isBSwapHWordPair	(	SDValue	N,
		MutableArrayRef< SDNode * >	Parts
	)

static

Definition at line 7541 of file DAGCombiner.cpp.

References llvm::ISD::BSWAP, llvm::CallingConv::C, isBSwapHWordElement(), llvm::isConstOrConstSplat(), N, llvm::ISD::OR, and llvm::ISD::SRL.

◆ isCompatibleLoad()

static bool isCompatibleLoad	(	SDValue	N,
		unsigned	ExtOpcode
	)

static

Check if N satisfies: N is used once.

N is a Load. The load is compatible with ExtOpcode. It means If load has explicit zero/sign extension, ExpOpcode must have the same extension. Otherwise returns true.

Definition at line 12785 of file DAGCombiner.cpp.

References llvm::ISD::EXTLOAD, N, llvm::ISD::NON_EXTLOAD, llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

Referenced by tryToFoldExtendSelectLoad().

◆ isConstantOrConstantVector()

static bool isConstantOrConstantVector	(	SDValue	N,
		bool	NoOpaques = `false`
	)

static

Definition at line 1038 of file DAGCombiner.cpp.

References llvm::BitWidth, llvm::ISD::BUILD_VECTOR, N, and llvm::ISD::SPLAT_VECTOR.

◆ isConstantSplatVectorMaskForType()

static bool isConstantSplatVectorMaskForType	(	SDNode *	N,
		EVT	ScalarTy
	)

static

Definition at line 1008 of file DAGCombiner.cpp.

References llvm::APInt::getLimitedValue(), llvm::EVT::getSimpleVT(), llvm::ISD::isConstantSplatVector(), llvm::EVT::isSimple(), N, and llvm::MVT::SimpleTy.

Referenced by performSVEAndCombine().

◆ isContractableFMUL()

static bool isContractableFMUL	(	const TargetOptions &	Options,
		SDValue	N
	)

static

Definition at line 15956 of file DAGCombiner.cpp.

References assert(), llvm::FPOpFusion::Fast, llvm::ISD::FMUL, N, and Options.

◆ isDivisorPowerOfTwo()

static bool isDivisorPowerOfTwo ( SDValue Divisor )

static

Definition at line 4742 of file DAGCombiner.cpp.

References llvm::CallingConv::C, and llvm::ISD::matchUnaryPredicate().

◆ isDivRemLibcallAvailable()

static bool isDivRemLibcallAvailable	(	SDNode *	Node,
		bool	isSigned,
		const TargetLowering &	TLI
	)

static

Return true if divmod libcall is available.

Definition at line 4546 of file DAGCombiner.cpp.

References llvm::TargetLoweringBase::getLibcallName(), and isSigned().

◆ isLegalToCombineMinNumMaxNum()

static bool isLegalToCombineMinNumMaxNum	(	SelectionDAG &	DAG,
		SDValue	LHS,
		SDValue	RHS,
		const SDNodeFlags	Flags,
		const TargetLowering &	TLI
	)

static

Definition at line 11202 of file DAGCombiner.cpp.

References llvm::SelectionDAG::getTarget(), llvm::EVT::isFloatingPoint(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::TargetLoweringBase::isProfitableToCombineMinNumMaxNum(), LHS, llvm::TargetMachine::Options, Options, and RHS.

◆ isSaturatingMinMax()

static SDValue isSaturatingMinMax	(	SDValue	N0,
		SDValue	N1,
		SDValue	N2,
		SDValue	N3,
		ISD::CondCode	CC,
		unsigned &	BW,
		bool &	Unsigned,
		SelectionDAG &	DAG
	)

static

Definition at line 5492 of file DAGCombiner.cpp.

References CC, llvm::APInt::exactLogBase2(), llvm::ISD::FP_TO_SINT, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getContext(), llvm::Type::getFltSemantics(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::EVT::getSizeInBits(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::isConstOrConstSplat(), llvm::isNullOrNullSplat(), llvm::APInt::isPowerOf2(), llvm::EVT::isSimple(), llvm::peekThroughTruncates(), llvm::PowerOf2Ceil(), llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::APFloatBase::semanticsIntSizeInBits(), llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::APInt::sext(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, Unsigned, and llvm::ISD::VSELECT.

Referenced by PerformMinMaxFpToSatCombine().

◆ isSlicingProfitable()

static bool isSlicingProfitable	(	SmallVectorImpl< LoadedSlice > &	LoadedSlices,
		const APInt &	UsedBits,
		bool	ForCodeSize
	)

static

Check the profitability of all involved LoadedSlice.

Currently, it is considered profitable if there is exactly two involved slices (1) which are (2) next to each other in memory, and whose cost (

See also: LoadedSlice::Cost) is smaller than the original load (3).

Note: The order of the elements in LoadedSlices may be modified, but not the elements themselves.

FIXME: When the cost model will be mature enough, we can relax constraints (1) and (2).

Definition at line 19697 of file DAGCombiner.cpp.

References adjustCostForPairing(), areUsedBitsDense(), llvm::SmallVectorBase< Size_T >::size(), and StressLoadSlicing.

◆ isTruncateOf()

static bool isTruncateOf	(	SelectionDAG &	DAG,
		SDValue	N,
		SDValue &	Op,
		KnownBits &	Known
	)

static

Definition at line 2301 of file DAGCombiner.cpp.

References llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::isAllOnes(), llvm::SDPatternMatch::m_c_SetCC(), llvm::SDPatternMatch::m_SpecificCondCode(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), N, llvm::SDPatternMatch::sd_match(), llvm::ISD::SETNE, llvm::ISD::TRUNCATE, and llvm::KnownBits::Zero.

◆ littleEndianByteAt()

static unsigned littleEndianByteAt	(	unsigned	BW,
		unsigned	i
	)

static

Definition at line 8796 of file DAGCombiner.cpp.

◆ matchBSwapHWordOrAndAnd()

static SDValue matchBSwapHWordOrAndAnd	(	const TargetLowering &	TLI,
		SelectionDAG &	DAG,
		SDNode *	N,
		SDValue	N0,
		SDValue	N1,
		EVT	VT
	)

static

Definition at line 7561 of file DAGCombiner.cpp.

References llvm::ISD::AND, assert(), llvm::ISD::BSWAP, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SDNode::hasOneUse(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), N, llvm::ISD::OR, llvm::ISD::ROTR, llvm::ISD::SHL, and llvm::ISD::SRL.

◆ matchRotateHalf()

static bool matchRotateHalf	(	const SelectionDAG &	DAG,
		SDValue	Op,
		SDValue &	Shift,
		SDValue &	Mask
	)

static

Match "(X shl/srl V1) & V2" where V2 may not be present.

Definition at line 8007 of file DAGCombiner.cpp.

References llvm::ISD::SHL, llvm::ISD::SRL, and stripConstantMask().

◆ matchRotateSub()

static bool matchRotateSub	(	SDValue	Pos,
		SDValue	Neg,
		unsigned	EltSize,
		SelectionDAG &	DAG,
		bool	IsRotate
	)

static

Definition at line 8159 of file DAGCombiner.cpp.

References llvm::ISD::ADD, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getLoBits(), llvm::APInt::getLowBitsSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::isConstOrConstSplat(), llvm::isPowerOf2_64(), llvm::Log2_64(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::ISD::SUB, and llvm::ISD::TRUNCATE.

◆ mergeEltWithShuffle()

static bool mergeEltWithShuffle	(	SDValue &	X,
		SDValue &	Y,
		ArrayRef< int >	Mask,
		SmallVectorImpl< int > &	NewMask,
		SDValue	Elt,
		unsigned	InsIndex
	)

static

Definition at line 21921 of file DAGCombiner.cpp.

References assert(), llvm::SmallVectorImpl< T >::assign(), llvm::ISD::CONCAT_VECTORS, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorBase< Size_T >::empty(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SDNode::ops(), llvm::SmallVectorImpl< T >::pop_back_val(), llvm::reverse(), X, and Y.

◆ narrowExtractedVectorBinOp()

static SDValue narrowExtractedVectorBinOp	(	SDNode *	Extract,
		SelectionDAG &	DAG,
		bool	LegalOperations
	)

static

If we are extracting a subvector produced by a wide binary operator try to use a narrow binary operator and/or avoid concatenation and extraction.

Definition at line 24516 of file DAGCombiner.cpp.

References llvm::ISD::AND, assert(), llvm::CallingConv::C, llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FSUB, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::TargetLoweringBase::isBinOp(), llvm::isConstOrConstSplatFP(), llvm::TargetLoweringBase::isExtractSubvectorCheap(), llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), narrowInsertExtractVectorBinOp(), llvm::ISD::OR, llvm::peekThroughBitcasts(), X, llvm::ISD::XOR, and Y.

◆ narrowExtractedVectorLoad()

static SDValue narrowExtractedVectorLoad	(	SDNode *	Extract,
		SelectionDAG &	DAG
	)

static

If we are extracting a subvector from a wide vector load, convert to a narrow load to eliminate the extraction: (extract_subvector (load wide vector)) --> (load narrow vector)

Definition at line 24648 of file DAGCombiner.cpp.

References assert(), DL, llvm::MachinePointerInfo::getAddrSpace(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getDataLayout(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::MemSDNode::getMemOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getStoreSize(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::getVectorMinNumElements(), llvm::DataLayout::isBigEndian(), llvm::EVT::isByteSized(), llvm::MemSDNode::isSimple(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::Offset, llvm::LocationSize::precise(), and llvm::TargetLoweringBase::shouldReduceLoadWidth().

◆ narrowInsertExtractVectorBinOp()

static SDValue narrowInsertExtractVectorBinOp	(	SDNode *	Extract,
		SelectionDAG &	DAG,
		bool	LegalOperations
	)

static

Definition at line 24479 of file DAGCombiner.cpp.

References llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), getSubVectorSrc(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::TargetLoweringBase::isBinOp(), and llvm::TargetLoweringBase::isOperationLegalOrCustom().

Referenced by narrowExtractedVectorBinOp().

◆ numVectorEltsOrZero()

static ElementCount numVectorEltsOrZero ( EVT T )

inlinestatic

Definition at line 18936 of file DAGCombiner.cpp.

References llvm::ElementCount::getFixed().

◆ partitionShuffleOfConcats()

static SDValue partitionShuffleOfConcats	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 25120 of file DAGCombiner.cpp.

References llvm::all_of(), assert(), llvm::ISD::CONCAT_VECTORS, llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), I, llvm::SDValue::isUndef(), N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ PerformMinMaxFpToSatCombine()

static SDValue PerformMinMaxFpToSatCombine	(	SDValue	N0,
		SDValue	N1,
		SDValue	N2,
		SDValue	N3,
		ISD::CondCode	CC,
		SelectionDAG &	DAG
	)

static

◆ PerformUMinFpToSatCombine()

static SDValue PerformUMinFpToSatCombine	(	SDValue	N0,
		SDValue	N1,
		SDValue	N2,
		SDValue	N3,
		ISD::CondCode	CC,
		SelectionDAG &	DAG
	)

static

◆ reduceBuildVecToShuffleWithZero()

static SDValue reduceBuildVecToShuffleWithZero	(	SDNode *	BV,
		SelectionDAG &	DAG
	)

static

◆ refineIndexType()

bool refineIndexType	(	SDValue &	Index,
		ISD::MemIndexType &	IndexType,
		EVT	DataVT,
		SelectionDAG &	DAG
	)

Definition at line 11885 of file DAGCombiner.cpp.

References llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ISD::isIndexTypeSigned(), llvm::TargetLoweringBase::shouldRemoveExtendFromGSIndex(), llvm::ISD::SIGN_EXTEND, llvm::ISD::UNSIGNED_SCALED, and llvm::ISD::ZERO_EXTEND.

◆ refineUniformBase()

bool refineUniformBase	(	SDValue &	BasePtr,
		SDValue &	Index,
		bool	IndexIsScaled,
		SelectionDAG &	DAG,
		const SDLoc &	DL
	)

Definition at line 11846 of file DAGCombiner.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getSplatValue(), llvm::SDValue::getValueType(), and llvm::isNullConstant().

◆ replaceShuffleOfInsert()

static SDValue replaceShuffleOfInsert	(	ShuffleVectorSDNode *	Shuf,
		SelectionDAG &	DAG
	)

static

If a shuffle inserts exactly one element from a source vector operand into another vector operand and we can access the specified element as a scalar, then we can eliminate the shuffle.

Definition at line 25768 of file DAGCombiner.cpp.

References assert(), llvm::ShuffleVectorSDNode::commuteMask(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), getShuffleMaskIndexOfOneElementFromOp0IntoOp1(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::ISD::INSERT_VECTOR_ELT, and std::swap().

◆ scalarizeBinOpOfSplats()

static SDValue scalarizeBinOpOfSplats	(	SDNode *	N,
		SelectionDAG &	DAG,
		const SDLoc &	DL,
		bool	LegalTypes
	)

static

If a vector binop is performed on splat values, it may be profitable to extract, scalarize, and insert/splat.

Definition at line 27111 of file DAGCombiner.cpp.

◆ scalarizeExtractedBinop()

static SDValue scalarizeExtractedBinop	(	SDNode *	ExtElt,
		SelectionDAG &	DAG,
		const SDLoc &	DL,
		bool	LegalOperations
	)

static

Transform a vector binary operation into a scalar binary operation by moving the math/logic after an extract element of a vector.

Definition at line 22452 of file DAGCombiner.cpp.

References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), isAnyConstantBuildVector(), llvm::TargetLoweringBase::isBinOp(), llvm::ISD::isConstantSplatVector(), and llvm::TargetLoweringBase::shouldScalarizeBinop().

◆ shouldCombineToPostInc()

static bool shouldCombineToPostInc	(	SDNode *	N,
		SDValue	Ptr,
		SDNode *	PtrUse,
		SDValue &	BasePtr,
		SDValue &	Offset,
		ISD::MemIndexedMode &	AM,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI
	)

static

Definition at line 18774 of file DAGCombiner.cpp.

References llvm::ISD::ADD, canFoldInAddressingMode(), getCombineLoadStoreParts(), llvm::SDNode::getOpcode(), llvm::TargetLowering::getPostIndexedAddressParts(), llvm::SDNode::hasPredecessorHelper(), llvm::isNullConstant(), N, llvm::Offset, llvm::ISD::POST_DEC, llvm::ISD::POST_INC, Ptr, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SUB, and llvm::Value::uses().

Referenced by getPostIndexedLoadStoreOp().

◆ shouldConvertSelectOfConstantsToMath()

static bool shouldConvertSelectOfConstantsToMath	(	const SDValue &	Cond,
		EVT	VT,
		const TargetLowering &	TLI
	)

static

Definition at line 11339 of file DAGCombiner.cpp.

References CC, Cond, llvm::TargetLoweringBase::convertSelectOfConstantsToMath(), llvm::isAllOnesOrAllOnesSplat(), llvm::isNullOrNullSplat(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETGT, and llvm::ISD::SETLT.

◆ ShrinkLoadReplaceStoreWithStore()

static SDValue ShrinkLoadReplaceStoreWithStore	(	const std::pair< unsigned, unsigned > &	MaskInfo,
		SDValue	IVal,
		StoreSDNode *	St,
		DAGCombiner *	DC
	)

static

Check to see if IVal is something that provides a value as specified by MaskInfo.

If so, replace the specified store with a narrower store of truncated IVal.

Definition at line 19910 of file DAGCombiner.cpp.

◆ simplifyDivRem()

static SDValue simplifyDivRem	(	SDNode *	N,
		SelectionDAG &	DAG
	)

static

Definition at line 4633 of file DAGCombiner.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getUNDEF(), llvm::isConstOrConstSplat(), llvm::ConstantSDNode::isOne(), llvm::SDValue::isUndef(), llvm::SelectionDAG::isUndef(), llvm::ConstantSDNode::isZero(), N, llvm::ISD::SDIV, and llvm::ISD::UDIV.

◆ simplifyShuffleOfShuffle()

static SDValue simplifyShuffleOfShuffle ( ShuffleVectorSDNode * Shuf )

static

If we have a unary shuffle of a shuffle, see if it can be folded away completely.

This has the potential to lose undef knowledge because the first shuffle may not have an undef mask element where the second one does. So only call this after doing simplifications based on demanded elements.

Definition at line 25821 of file DAGCombiner.cpp.

References assert(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), and llvm::SDValue::isUndef().

◆ STATISTIC() [1/7]

STATISTIC	(	LdStFP2Int	,
		"Number of fp load/store pairs transformed to int"
	)

◆ STATISTIC() [2/7]

STATISTIC	(	NodesCombined	,
		"Number of dag nodes combined"
	)

◆ STATISTIC() [3/7]

STATISTIC	(	NumFPLogicOpsConv	,
		"Number of logic ops converted to fp ops"
	)

◆ STATISTIC() [4/7]

STATISTIC	(	OpsNarrowed	,
		"Number of load/op/store narrowed"
	)

◆ STATISTIC() [5/7]

STATISTIC	(	PostIndexedNodes	,
		"Number of post-indexed nodes created"
	)

◆ STATISTIC() [6/7]

STATISTIC	(	PreIndexedNodes	,
		"Number of pre-indexed nodes created"
	)

◆ STATISTIC() [7/7]

STATISTIC	(	SlicedLoads	,
		"Number of load sliced"
	)

◆ stripConstantMask()

static SDValue stripConstantMask	(	const SelectionDAG &	DAG,
		SDValue	Op,
		SDValue &	Mask
	)

static

Definition at line 7996 of file DAGCombiner.cpp.

References llvm::ISD::AND, and llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt().

Referenced by extractShiftForRotate(), and matchRotateHalf().

◆ stripTruncAndExt()

static SDValue stripTruncAndExt ( SDValue Value )

static

Definition at line 8829 of file DAGCombiner.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

◆ takeInexpensiveLog2()

static SDValue takeInexpensiveLog2	(	SelectionDAG &	DAG,
		const SDLoc &	DL,
		EVT	VT,
		SDValue	Op,
		unsigned	Depth,
		bool	AssumeNonZero
	)

static

Definition at line 28027 of file DAGCombiner.cpp.

Referenced by takeInexpensiveLog2().

◆ tryFoldToZero()

static SDValue tryFoldToZero	(	const SDLoc &	DL,
		const TargetLowering &	TLI,
		EVT	VT,
		SelectionDAG &	DAG,
		bool	LegalOperations
	)

static

Definition at line 3760 of file DAGCombiner.cpp.

References llvm::ISD::BUILD_VECTOR, DL, llvm::SelectionDAG::getConstant(), llvm::TargetLoweringBase::isOperationLegal(), and llvm::EVT::isVector().

◆ tryToFoldExtendOfConstant()

static SDValue tryToFoldExtendOfConstant	(	SDNode *	N,
		const SDLoc &	DL,
		const TargetLowering &	TLI,
		SelectionDAG &	DAG,
		bool	LegalTypes
	)

static

Try to fold a sext/zext/aext dag node into a ConstantSDNode or a build_vector of constants.

This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND). Vector extends are not folded if operations are legal; this is to avoid introducing illegal build_vector dag nodes.

Definition at line 12858 of file DAGCombiner.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, assert(), llvm::CallingConv::C, DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSelect(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isExtOpcode(), llvm::ISD::isExtVecInRegOpcode(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::TargetLoweringBase::isZExtFree(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SELECT, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, and llvm::ISD::ZERO_EXTEND.

◆ tryToFoldExtendSelectLoad()

static SDValue tryToFoldExtendSelectLoad	(	SDNode *	N,
		const TargetLowering &	TLI,
		SelectionDAG &	DAG,
		const SDLoc &	DL,
		CombineLevel	Level
	)

static

Fold (sext (select c, load x, load y)) -> (select c, sextload x, sextload y) (zext (select c, load x, load y)) -> (select c, zextload x, zextload y) (aext (select c, load x, load y)) -> (select c, extload x, extload y) This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).

Definition at line 12812 of file DAGCombiner.cpp.

References llvm::AfterLegalizeTypes, llvm::ISD::ANY_EXTEND, assert(), DL, llvm::ISD::EXTLOAD, llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getOperationAction(), llvm::SelectionDAG::getSelect(), llvm::SDValue::hasOneUse(), isCompatibleLoad(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::TargetLoweringBase::Legal, N, llvm::ISD::SELECT, llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::ISD::VSELECT, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

◆ tryToFoldExtOfAtomicLoad()

static SDValue tryToFoldExtOfAtomicLoad	(	SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		EVT	VT,
		SDValue	N0,
		ISD::LoadExtType	ExtLoadType
	)

static

Definition at line 13365 of file DAGCombiner.cpp.

References assert(), llvm::ISD::ATOMIC_LOAD, llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::TargetLoweringBase::isAtomicLoadExtLegal(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, llvm::ISD::TRUNCATE, and llvm::ISD::ZEXTLOAD.

◆ tryToFoldExtOfExtload()

static SDValue tryToFoldExtOfExtload	(	SelectionDAG &	DAG,
		DAGCombiner &	Combiner,
		const TargetLowering &	TLI,
		EVT	VT,
		bool	LegalOperations,
		SDNode *	N,
		SDValue	N0,
		ISD::LoadExtType	ExtLoadType
	)

static

◆ tryToFoldExtOfLoad()

static SDValue tryToFoldExtOfLoad	(	SelectionDAG &	DAG,
		DAGCombiner &	Combiner,
		const TargetLowering &	TLI,
		EVT	VT,
		bool	LegalOperations,
		SDNode *	N,
		SDValue	N0,
		ISD::LoadExtType	ExtLoadType,
		ISD::NodeType	ExtOpc,
		bool	NonNegZExt = `false`
	)

static

Definition at line 13275 of file DAGCombiner.cpp.

References assert(), CC, ExtendUsesToFormExtLoad(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getExtLoad(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::User::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::ISD::isNON_EXTLoad(), llvm::ISD::isSignedIntSetCC(), llvm::ISD::isUNINDEXEDLoad(), llvm::EVT::isVector(), llvm::TargetLoweringBase::isVectorLoadExtDesirable(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SETCC, llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, llvm::SDNode::uses(), llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

◆ tryToFoldExtOfMaskedLoad()

static SDValue tryToFoldExtOfMaskedLoad	(	SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		EVT	VT,
		bool	LegalOperations,
		SDNode *	N,
		SDValue	N0,
		ISD::LoadExtType	ExtLoadType,
		ISD::NodeType	ExtOpc
	)

static

◆ visitORCommutative()

static SDValue visitORCommutative	(	SelectionDAG &	DAG,
		SDValue	N0,
		SDValue	N1,
		SDNode *	N
	)

static

OR combines for which the commuted variant will be tried as well.

Definition at line 7719 of file DAGCombiner.cpp.

◆ widenAbs()

static SDValue widenAbs	(	SDNode *	Extend,
		SelectionDAG &	DAG
	)

static

◆ widenCtPop()

static SDValue widenCtPop	(	SDNode *	Extend,
		SelectionDAG &	DAG,
		const SDLoc &	DL
	)

static

Given an extending node with a pop-count operand, if the target does not support a pop-count in the narrow source type but does support it in the destination type, widen the pop-count to the destination type.

Definition at line 13783 of file DAGCombiner.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::CTPOP, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDValue::hasOneUse(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), and llvm::ISD::ZERO_EXTEND.

◆ zeroExtendToMatch()

static void zeroExtendToMatch	(	APInt &	LHS,
		APInt &	RHS,
		unsigned	Offset = `0`
	)

static

Definition at line 955 of file DAGCombiner.cpp.

References LHS, llvm::Offset, and RHS.

Referenced by extractShiftForRotate().

Variable Documentation

◆ CombinerAAOnlyFunc

cl::opt< std::string > CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden, cl::desc("Only use DAG-combiner alias analysis in this" " function"))	(	"combiner-aa-only-func"	,
		cl::Hidden	,
		cl::desc("Only use DAG-combiner alias analysis in this" " function")
	)

static

◆ CombinerGlobalAA

cl::opt< bool > CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, cl::desc("Enable DAG combiner's use of IR alias analysis"))	(	"combiner-global-alias-analysis"	,
		cl::Hidden	,
		cl::desc("Enable DAG combiner's use of IR alias analysis")
	)

static

◆ EnableReduceLoadOpStoreWidth

cl::opt< bool > EnableReduceLoadOpStoreWidth("combiner-reduce-load-op-store-width", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable reducing the width of load/op/store " "sequence"))	(	"combiner-reduce-load-op-store-width"	,
		cl::Hidden	,
		cl::init(true)	,
		cl::desc("DAG combiner enable reducing the width of load/op/store " "sequence")
	)

static

◆ EnableShrinkLoadReplaceStoreWithStore

cl::opt< bool > EnableShrinkLoadReplaceStoreWithStore("combiner-shrink-load-replace-store-with-store", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable load/<replace bytes>/store with " "a narrower store"))	(	"combiner-shrink-load-replace-store-with-store"	,
		cl::Hidden	,
		cl::init(true)	,
		cl::desc("DAG combiner enable load/<replace bytes>/store with " "a narrower store")
	)

static

◆ EnableStoreMerging

cl::opt< bool > EnableStoreMerging("combiner-store-merging", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable merging multiple stores " "into a wider store"))	(	"combiner-store-merging"	,
		cl::Hidden	,
		cl::init(true)	,
		cl::desc("DAG combiner enable merging multiple stores " "into a wider store")
	)

static

◆ EnableVectorFCopySignExtendRound

cl::opt< bool > EnableVectorFCopySignExtendRound("combiner-vector-fcopysign-extend-round", cl::Hidden, cl::init(false), cl::desc( "Enable merging extends and rounds into FCOPYSIGN on vector types"))	(	"combiner-vector-fcopysign-extend-round"	,
		cl::Hidden	,
		cl::init(false)	,
		cl::desc( "Enable merging extends and rounds into FCOPYSIGN on vector types")
	)

static

Referenced by CanCombineFCOPYSIGN_EXTEND_ROUND().

◆ MaySplitLoadIndex

cl::opt< bool > MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true), cl::desc("DAG combiner may split indexing from loads"))	(	"combiner-split-load-index"	,
		cl::Hidden	,
		cl::init(true)	,
		cl::desc("DAG combiner may split indexing from loads")
	)

static

Referenced by canSplitIdx().

◆ StoreMergeDependenceLimit

cl::opt< unsigned > StoreMergeDependenceLimit("combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10), cl::desc("Limit the number of times for the same StoreNode and RootNode " "to bail out in store merging dependence check"))	(	"combiner-store-merge-dependence-limit"	,
		cl::Hidden	,
		cl::init(10)	,
		cl::desc("Limit the number of times for the same StoreNode and RootNode " "to bail out in store merging dependence check")
	)

static

◆ StressLoadSlicing

cl::opt< bool > StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden, cl::desc("Bypass the profitability model of load slicing"), cl::init(false))	(	"combiner-stress-load-slicing"	,
		cl::Hidden	,
		cl::desc("Bypass the profitability model of load slicing")	,
		cl::init(false)
	)

static

Hidden option to stress test load slicing, i.e., when this option is enabled, load slicing bypasses most of its profitability guards.

Referenced by isSlicingProfitable().

◆ TokenFactorInlineLimit

cl::opt< unsigned > TokenFactorInlineLimit("combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048), cl::desc("Limit the number of operands to inline for Token Factors"))	(	"combiner-tokenfactor-inline-limit"	,
		cl::Hidden	,
		cl::init(2048)	,
		cl::desc("Limit the number of operands to inline for Token Factors")
	)

static

◆ UseTBAA

cl::opt< bool > UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true), cl::desc("Enable DAG combiner's use of TBAA"))	(	"combiner-use-tbaa"	,
		cl::Hidden	,
		cl::init(true)	,
		cl::desc("Enable DAG combiner's use of TBAA")
	)

static

Macros

Typedefs

Functions

Variables

Macro Definition Documentation

◆ BEGIN_REGISTER_VP_SDNODE

◆ DEBUG_TYPE

Typedef Documentation

◆ SDByteProvider

Function Documentation

◆ adjustCostForPairing()

◆ areBitwiseNotOfEachother()

◆ arebothOperandsNotNan()

◆ arebothOperandsNotSNan()

◆ areSlicesNextToEachOther()

◆ areUsedBitsDense()

◆ bigEndianByteAt()

◆ calculateByteProvider()

◆ CanCombineFCOPYSIGN_EXTEND_ROUND() [1/2]

◆ CanCombineFCOPYSIGN_EXTEND_ROUND() [2/2]

◆ canCombineShuffleToExtendVectorInreg()

◆ canFoldInAddressingMode()

◆ canSplitIdx()

◆ CheckForMaskedLoad()

◆ combineCarryDiamond()

◆ combineConcatVectorOfCasts()

◆ combineConcatVectorOfConcatVectors()

◆ combineConcatVectorOfExtracts()

◆ combineConcatVectorOfScalars()

◆ combineConcatVectorOfShuffleAndItsOperands()

◆ combineMinNumMaxNumImpl()

◆ combineSelectAsExtAnd()

◆ combineShiftAnd1ToBitTest()

◆ combineShiftOfShiftedLogic()

◆ combineShiftToMULH()

◆ combineShuffleOfBitcast()

◆ combineShuffleOfScalars()

◆ combineShuffleOfSplatVal()

◆ combineShuffleToAnyExtendVectorInreg()

◆ combineShuffleToZeroExtendVectorInReg()

◆ combineTruncationShuffle()

◆ combineUADDO_CARRYDiamond()

◆ ConvertSelectToConcatVector()

◆ DEBUG_COUNTER()

◆ detectSSatSPattern()

◆ detectSSatUPattern()

◆ detectUSatUPattern()

◆ ExtendUsesToFormExtLoad()

◆ extractBooleanFlip()

◆ extractShiftForRotate()

◆ foldAddSubBoolOfMaskedVal()

◆ foldAddSubMasked1()

◆ foldAddSubOfSignBit()

◆ foldAndOrOfSETCC()

◆ foldAndToUsubsat()

◆ foldBitOrderCrossLogicOp()

◆ foldBoolSelectToLogic()

◆ foldExtendedSignBitTest()

◆ foldExtendVectorInregToExtendOfSubvector()

◆ foldExtractSubvectorFromShuffleVector()

◆ foldFPToIntToFP()

◆ FoldIntToFPToInt()

◆ foldLogicOfShifts()

◆ foldLogicTreeOfShifts()

◆ foldSelectOfConstantsUsingSra()

◆ foldSelectWithIdentityConstant()

◆ foldShuffleOfConcatUndefs()

◆ foldToSaturated()

◆ foldVSelectToSignBitSplatMask()

◆ formSplatFromShuffles()

◆ getAsCarry()

◆ getAsNonOpaqueConstant()

◆ getBuildPairElt()

◆ getCombineLoadStoreParts()

◆ getFirstIndexOf()

◆ getInputChainForNode()

◆ getMinMaxOpcodeForFP()

◆ getPostIndexedLoadStoreOp()

◆ getPPCf128HiElementSelector()

◆ getShuffleMaskIndexOfOneElementFromOp0IntoOp1()