LLVM  13.0.0git
HexagonTargetTransformInfo.cpp
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1 //===- HexagonTargetTransformInfo.cpp - Hexagon specific TTI pass ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 /// This file implements a TargetTransformInfo analysis pass specific to the
9 /// Hexagon target machine. It uses the target's detailed information to provide
10 /// more precise answers to certain TTI queries, while letting the target
11 /// independent and default TTI implementations handle the rest.
12 ///
13 //===----------------------------------------------------------------------===//
14 
16 #include "HexagonSubtarget.h"
19 #include "llvm/IR/InstrTypes.h"
20 #include "llvm/IR/Instructions.h"
21 #include "llvm/IR/User.h"
22 #include "llvm/Support/Casting.h"
26 
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "hexagontti"
30 
31 static cl::opt<bool> HexagonAutoHVX("hexagon-autohvx", cl::init(false),
32  cl::Hidden, cl::desc("Enable loop vectorizer for HVX"));
33 
34 static cl::opt<bool> EmitLookupTables("hexagon-emit-lookup-tables",
35  cl::init(true), cl::Hidden,
36  cl::desc("Control lookup table emission on Hexagon target"));
37 
38 static cl::opt<bool> HexagonMaskedVMem("hexagon-masked-vmem", cl::init(true),
39  cl::Hidden, cl::desc("Enable masked loads/stores for HVX"));
40 
41 // Constant "cost factor" to make floating point operations more expensive
42 // in terms of vectorization cost. This isn't the best way, but it should
43 // do. Ultimately, the cost should use cycles.
44 static const unsigned FloatFactor = 4;
45 
46 bool HexagonTTIImpl::useHVX() const {
47  return ST.useHVXOps() && HexagonAutoHVX;
48 }
49 
50 unsigned HexagonTTIImpl::getTypeNumElements(Type *Ty) const {
51  if (auto *VTy = dyn_cast<FixedVectorType>(Ty))
52  return VTy->getNumElements();
53  assert((Ty->isIntegerTy() || Ty->isFloatingPointTy()) &&
54  "Expecting scalar type");
55  return 1;
56 }
57 
59 HexagonTTIImpl::getPopcntSupport(unsigned IntTyWidthInBit) const {
60  // Return fast hardware support as every input < 64 bits will be promoted
61  // to 64 bits.
63 }
64 
65 // The Hexagon target can unroll loops with run-time trip counts.
68  UP.Runtime = UP.Partial = true;
69 }
70 
74  // Only try to peel innermost loops with small runtime trip counts.
75  if (L && L->isInnermost() && canPeel(L) &&
76  SE.getSmallConstantTripCount(L) == 0 &&
77  SE.getSmallConstantMaxTripCount(L) > 0 &&
78  SE.getSmallConstantMaxTripCount(L) <= 5) {
79  PP.PeelCount = 2;
80  }
81 }
82 
85  ScalarEvolution *SE) const {
86  return TTI::AMK_PostIndexed;
87 }
88 
89 /// --- Vector TTI begin ---
90 
91 unsigned HexagonTTIImpl::getNumberOfRegisters(bool Vector) const {
92  if (Vector)
93  return useHVX() ? 32 : 0;
94  return 32;
95 }
96 
98  return useHVX() ? 2 : 1;
99 }
100 
101 TypeSize
103  switch (K) {
105  return TypeSize::getFixed(32);
109  return TypeSize::getScalable(0);
110  }
111 
112  llvm_unreachable("Unsupported register kind");
113 }
114 
116  return useHVX() ? ST.getVectorLength()*8 : 32;
117 }
118 
120  bool IsScalable) const {
121  assert(!IsScalable && "Scalable VFs are not supported for Hexagon");
122  return ElementCount::getFixed((8 * ST.getVectorLength()) / ElemWidth);
123 }
124 
126  VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) {
127  return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
128 }
129 
132  ArrayRef<Type *> Tys) {
134 }
135 
137  ArrayRef<Type *> Tys,
139  return BaseT::getCallInstrCost(F, RetTy, Tys, CostKind);
140 }
141 
145  if (ICA.getID() == Intrinsic::bswap) {
146  std::pair<InstructionCost, MVT> LT =
148  return LT.first + 2;
149  }
151 }
152 
154  ScalarEvolution *SE,
155  const SCEV *S) {
156  return 0;
157 }
158 
160  MaybeAlign Alignment,
161  unsigned AddressSpace,
163  const Instruction *I) {
164  assert(Opcode == Instruction::Load || Opcode == Instruction::Store);
165  // TODO: Handle other cost kinds.
167  return 1;
168 
169  if (Opcode == Instruction::Store)
170  return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
171  CostKind, I);
172 
173  if (Src->isVectorTy()) {
174  VectorType *VecTy = cast<VectorType>(Src);
175  unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedSize();
176  if (useHVX() && ST.isTypeForHVX(VecTy)) {
177  unsigned RegWidth =
179  .getFixedSize();
180  assert(RegWidth && "Non-zero vector register width expected");
181  // Cost of HVX loads.
182  if (VecWidth % RegWidth == 0)
183  return VecWidth / RegWidth;
184  // Cost of constructing HVX vector from scalar loads
185  const Align RegAlign(RegWidth / 8);
186  if (!Alignment || *Alignment > RegAlign)
187  Alignment = RegAlign;
188  assert(Alignment);
189  unsigned AlignWidth = 8 * Alignment->value();
190  unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth;
191  return 3 * NumLoads;
192  }
193 
194  // Non-HVX vectors.
195  // Add extra cost for floating point types.
196  unsigned Cost =
197  VecTy->getElementType()->isFloatingPointTy() ? FloatFactor : 1;
198 
199  // At this point unspecified alignment is considered as Align(1).
200  const Align BoundAlignment = std::min(Alignment.valueOrOne(), Align(8));
201  unsigned AlignWidth = 8 * BoundAlignment.value();
202  unsigned NumLoads = alignTo(VecWidth, AlignWidth) / AlignWidth;
203  if (Alignment == Align(4) || Alignment == Align(8))
204  return Cost * NumLoads;
205  // Loads of less than 32 bits will need extra inserts to compose a vector.
206  assert(BoundAlignment <= Align(8));
207  unsigned LogA = Log2(BoundAlignment);
208  return (3 - LogA) * Cost * NumLoads;
209  }
210 
211  return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
212  CostKind, I);
213 }
214 
217  Align Alignment, unsigned AddressSpace,
219  return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
220  CostKind);
221 }
222 
224  ArrayRef<int> Mask, int Index,
225  Type *SubTp) {
226  return 1;
227 }
228 
230  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
231  Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) {
232  return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
233  Alignment, CostKind, I);
234 }
235 
237  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
238  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
239  bool UseMaskForCond, bool UseMaskForGaps) {
240  if (Indices.size() != Factor || UseMaskForCond || UseMaskForGaps)
241  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
242  Alignment, AddressSpace,
243  CostKind,
244  UseMaskForCond, UseMaskForGaps);
245  return getMemoryOpCost(Opcode, VecTy, MaybeAlign(Alignment), AddressSpace,
246  CostKind);
247 }
248 
250  Type *CondTy,
251  CmpInst::Predicate VecPred,
253  const Instruction *I) {
254  if (ValTy->isVectorTy() && CostKind == TTI::TCK_RecipThroughput) {
255  std::pair<InstructionCost, MVT> LT = TLI.getTypeLegalizationCost(DL, ValTy);
256  if (Opcode == Instruction::FCmp)
257  return LT.first + FloatFactor * getTypeNumElements(ValTy);
258  }
259  return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
260 }
261 
263  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
264  TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info,
265  TTI::OperandValueProperties Opd1PropInfo,
267  const Instruction *CxtI) {
268  // TODO: Handle more cost kinds.
270  return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info,
271  Opd2Info, Opd1PropInfo,
272  Opd2PropInfo, Args, CxtI);
273 
274  if (Ty->isVectorTy()) {
275  std::pair<InstructionCost, MVT> LT = TLI.getTypeLegalizationCost(DL, Ty);
276  if (LT.second.isFloatingPoint())
277  return LT.first + FloatFactor * getTypeNumElements(Ty);
278  }
279  return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
280  Opd1PropInfo, Opd2PropInfo, Args, CxtI);
281 }
282 
284  Type *SrcTy,
287  const Instruction *I) {
288  if (SrcTy->isFPOrFPVectorTy() || DstTy->isFPOrFPVectorTy()) {
289  unsigned SrcN = SrcTy->isFPOrFPVectorTy() ? getTypeNumElements(SrcTy) : 0;
290  unsigned DstN = DstTy->isFPOrFPVectorTy() ? getTypeNumElements(DstTy) : 0;
291 
292  std::pair<InstructionCost, MVT> SrcLT =
293  TLI.getTypeLegalizationCost(DL, SrcTy);
294  std::pair<InstructionCost, MVT> DstLT =
295  TLI.getTypeLegalizationCost(DL, DstTy);
296  InstructionCost Cost =
297  std::max(SrcLT.first, DstLT.first) + FloatFactor * (SrcN + DstN);
298  // TODO: Allow non-throughput costs that aren't binary.
300  return Cost == 0 ? 0 : 1;
301  return Cost;
302  }
303  return 1;
304 }
305 
307  unsigned Index) {
308  Type *ElemTy = Val->isVectorTy() ? cast<VectorType>(Val)->getElementType()
309  : Val;
310  if (Opcode == Instruction::InsertElement) {
311  // Need two rotations for non-zero index.
312  unsigned Cost = (Index != 0) ? 2 : 0;
313  if (ElemTy->isIntegerTy(32))
314  return Cost;
315  // If it's not a 32-bit value, there will need to be an extract.
316  return Cost + getVectorInstrCost(Instruction::ExtractElement, Val, Index);
317  }
318 
319  if (Opcode == Instruction::ExtractElement)
320  return 2;
321 
322  return 1;
323 }
324 
325 bool HexagonTTIImpl::isLegalMaskedStore(Type *DataType, Align /*Alignment*/) {
326  return HexagonMaskedVMem && ST.isTypeForHVX(DataType);
327 }
328 
329 bool HexagonTTIImpl::isLegalMaskedLoad(Type *DataType, Align /*Alignment*/) {
330  return HexagonMaskedVMem && ST.isTypeForHVX(DataType);
331 }
332 
333 /// --- Vector TTI end ---
334 
336  return ST.getL1PrefetchDistance();
337 }
338 
340  return ST.getL1CacheLineSize();
341 }
342 
346  auto isCastFoldedIntoLoad = [this](const CastInst *CI) -> bool {
347  if (!CI->isIntegerCast())
348  return false;
349  // Only extensions from an integer type shorter than 32-bit to i32
350  // can be folded into the load.
351  const DataLayout &DL = getDataLayout();
352  unsigned SBW = DL.getTypeSizeInBits(CI->getSrcTy());
353  unsigned DBW = DL.getTypeSizeInBits(CI->getDestTy());
354  if (DBW != 32 || SBW >= DBW)
355  return false;
356 
357  const LoadInst *LI = dyn_cast<const LoadInst>(CI->getOperand(0));
358  // Technically, this code could allow multiple uses of the load, and
359  // check if all the uses are the same extension operation, but this
360  // should be sufficient for most cases.
361  return LI && LI->hasOneUse();
362  };
363 
364  if (const CastInst *CI = dyn_cast<const CastInst>(U))
365  if (isCastFoldedIntoLoad(CI))
368 }
369 
371  return EmitLookupTables;
372 }
llvm::InstructionCost
Definition: InstructionCost.h:26
llvm::TargetTransformInfo::PSK_FastHardware
@ PSK_FastHardware
Definition: TargetTransformInfo.h:586
llvm::HexagonTTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: HexagonTargetTransformInfo.cpp:115
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::HexagonSubtarget::getVectorLength
unsigned getVectorLength() const
Definition: HexagonSubtarget.h:273
ValueTypes.h
llvm::BasicTTIImplBase< HexagonTTIImpl >::DL
const DataLayout & DL
Definition: TargetTransformInfoImpl.h:38
llvm::TargetTransformInfo::UnrollingPreferences::Runtime
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
Definition: TargetTransformInfo.h:480
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:210
llvm::BasicTTIImplBase< HexagonTTIImpl >::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys)
Estimate the overhead of scalarizing an instructions unique non-constant operands.
Definition: BasicTTIImpl.h:696
llvm
Definition: AllocatorList.h:23
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::Value::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this value.
Definition: Value.h:435
Insert
Vector Rotate Left Mask Mask Insert
Definition: README_P9.txt:112
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
llvm::ElementCount
Definition: TypeSize.h:386
llvm::TypeSize::getFixedSize
ScalarTy getFixedSize() const
Definition: TypeSize.h:426
llvm::Function
Definition: Function.h:61
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:586
llvm::TargetTransformInfoImplCRTPBase< HexagonTTIImpl >::getUserCost
InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfoImpl.h:920
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TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:655
llvm::TargetTransformInfo::AMK_PostIndexed
@ AMK_PostIndexed
Definition: TargetTransformInfo.h:635
HexagonSubtarget.h
llvm::BasicTTIImplBase< HexagonTTIImpl >::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: BasicTTIImpl.h:739
llvm::IntrinsicCostAttributes::getReturnType
Type * getReturnType() const
Definition: TargetTransformInfo.h:149
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The main scalar evolution driver.
Definition: ScalarEvolution.h:443
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:929
llvm::Type::isFPOrFPVectorTy
bool isFPOrFPVectorTy() const
Return true if this is a FP type or a vector of FP.
Definition: Type.h:190
llvm::HexagonTTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: HexagonTargetTransformInfo.cpp:159
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
HexagonTargetTransformInfo.h
llvm::TargetTransformInfo::UnrollingPreferences::Partial
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
Definition: TargetTransformInfo.h:476
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::HexagonTTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency)
Definition: HexagonTargetTransformInfo.cpp:216
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:529
llvm::MaybeAlign::valueOrOne
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
Definition: Alignment.h:134
llvm::TargetLoweringBase::getTypeLegalizationCost
std::pair< InstructionCost, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
Definition: TargetLoweringBase.cpp:1836
llvm::VectorType::getElementType
Type * getElementType() const
Definition: DerivedTypes.h:424
llvm::HexagonTTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: HexagonTargetTransformInfo.cpp:97
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bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:163
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std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::HexagonSubtarget::isTypeForHVX
bool isTypeForHVX(Type *VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:165
F
#define F(x, y, z)
Definition: MD5.cpp:56
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bool canPeel(Loop *L)
Definition: LoopPeel.cpp:89
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InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Definition: HexagonTargetTransformInfo.cpp:229
llvm::AArch64CC::LT
@ LT
Definition: AArch64BaseInfo.h:247
llvm::HexagonTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
Definition: HexagonTargetTransformInfo.cpp:66
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const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:48
llvm::HexagonSubtarget::getL1CacheLineSize
unsigned getL1CacheLineSize() const
Definition: HexagonSubtarget.cpp:651
CommandLine.h
HexagonMaskedVMem
static cl::opt< bool > HexagonMaskedVMem("hexagon-masked-vmem", cl::init(true), cl::Hidden, cl::desc("Enable masked loads/stores for HVX"))
llvm::HexagonTTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: HexagonTargetTransformInfo.cpp:306
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TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Definition: HexagonTargetTransformInfo.cpp:59
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ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:850
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CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1084
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Definition: User.h:44
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InstructionCost getUserCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:343
InstrTypes.h
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unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:207
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bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:235
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This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
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bool useHVXOps() const
Definition: HexagonSubtarget.h:203
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Definition: Instruction.h:45
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bool shouldBuildLookupTables() const
Definition: HexagonTargetTransformInfo.cpp:370
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uint64_t Align
Definition: ELFObjHandler.cpp:83
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@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:929
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This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
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AddressSpace
Definition: NVPTXBaseInfo.h:21
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InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1022
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static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:284
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Kind
Definition: LLToken.h:18
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Definition: TargetTransformInfo.h:117
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mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
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unsigned getL1PrefetchDistance() const
Definition: HexagonSubtarget.cpp:655
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bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:202
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unsigned getSmallConstantTripCount(const Loop *L)
Returns the exact trip count of the loop if we can compute it, and the result is a small constant.
Definition: ScalarEvolution.cpp:7043
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Base class of all SIMD vector types.
Definition: DerivedTypes.h:391
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llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:78
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
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unsigned getSmallConstantMaxTripCount(const Loop *L)
Returns the upper bound of the loop trip count as a normal unsigned value.
Definition: ScalarEvolution.cpp:7059
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Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:423
I
#define I(x, y, z)
Definition: MD5.cpp:59
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OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:908
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initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
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InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, ArrayRef< int > Mask, int Index, Type *SubTp)
Definition: HexagonTargetTransformInfo.cpp:223
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
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InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: BasicTTIImpl.h:1138
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bool isLegalMaskedStore(Type *DataType, Align Alignment)
Definition: HexagonTargetTransformInfo.cpp:325
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OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:900
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InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: HexagonTargetTransformInfo.cpp:283
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Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::HexagonTTIImpl::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:136
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:261
llvm::TargetTransformInfo::PeelingPreferences::PeelCount
unsigned PeelCount
A forced peeling factor (the number of bodied of the original loop that should be peeled off before t...
Definition: TargetTransformInfo.h:533
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
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Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
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InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys)
Definition: HexagonTargetTransformInfo.cpp:131
llvm::BasicTTIImplBase< HexagonTTIImpl >::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *InTy, const APInt &DemandedElts, bool Insert, bool Extract)
Estimate the overhead of scalarizing an instruction.
Definition: BasicTTIImpl.h:660
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::HexagonTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: HexagonTargetTransformInfo.cpp:102
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::CastInst
This is the base class for all instructions that perform data casts.
Definition: InstrTypes.h:432
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:633
HexagonAutoHVX
static cl::opt< bool > HexagonAutoHVX("hexagon-autohvx", cl::init(false), cl::Hidden, cl::desc("Enable loop vectorizer for HVX"))
llvm::BasicTTIImplBase< HexagonTTIImpl >::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: BasicTTIImpl.h:548
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
llvm::BasicTTIImplBase< HexagonTTIImpl >::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency)
Compute a cost of the given call instruction.
Definition: BasicTTIImpl.h:1955
llvm::LoopBase::isInnermost
bool isInnermost() const
Return true if the loop does not contain any (natural) loops.
Definition: LoopInfo.h:165
llvm::HexagonTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: HexagonTargetTransformInfo.cpp:71
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::TypeSize
Definition: TypeSize.h:417
Casting.h
EmitLookupTables
static cl::opt< bool > EmitLookupTables("hexagon-emit-lookup-tables", cl::init(true), cl::Hidden, cl::desc("Control lookup table emission on Hexagon target"))
llvm::BasicTTIImplBase< HexagonTTIImpl >::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: BasicTTIImpl.h:1122
llvm::LinearPolySize< TypeSize >::getScalable
static TypeSize getScalable(ScalarTy MinVal)
Definition: TypeSize.h:287
llvm::HexagonTTIImpl::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *SE, const SCEV *S)
Definition: HexagonTargetTransformInfo.cpp:153
llvm::HexagonTTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: HexagonTargetTransformInfo.cpp:236
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:929
Vector
So we should use XX3Form_Rcr to implement instrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::BasicTTIImplBase< HexagonTTIImpl >::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1129
Instructions.h
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:147
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:929
User.h
llvm::HexagonTTIImpl::getPrefetchDistance
unsigned getPrefetchDistance() const override
— Vector TTI end —
Definition: HexagonTargetTransformInfo.cpp:335
llvm::BasicTTIImplBase< HexagonTTIImpl >::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Get intrinsic cost based on arguments.
Definition: BasicTTIImpl.h:1287
llvm::HexagonTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: HexagonTargetTransformInfo.cpp:143
UnrollLoop.h
llvm::HexagonTTIImpl::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Bias LSR towards creating post-increment opportunities.
Definition: HexagonTargetTransformInfo.cpp:84
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::HexagonTTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: HexagonTargetTransformInfo.cpp:249
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
TargetTransformInfo.h
llvm::BasicTTIImplBase< HexagonTTIImpl >::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:1078
llvm::HexagonTTIImpl::getCacheLineSize
unsigned getCacheLineSize() const override
Definition: HexagonTargetTransformInfo.cpp:339
llvm::HexagonTTIImpl::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract)
Definition: HexagonTargetTransformInfo.cpp:125
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::cl::desc
Definition: CommandLine.h:414
llvm::HexagonTTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
Definition: HexagonTargetTransformInfo.cpp:329
llvm::HexagonTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(bool vector) const
— Vector TTI begin —
Definition: HexagonTargetTransformInfo.cpp:91
LoopPeel.h
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:211
FloatFactor
static const unsigned FloatFactor
Definition: HexagonTargetTransformInfo.cpp:44
llvm::HexagonTTIImpl::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: HexagonTargetTransformInfo.cpp:119
llvm::HexagonTTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: HexagonTargetTransformInfo.cpp:262
llvm::Type::getPrimitiveSizeInBits
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:122