LLVM 19.0.0git
Mips16InstrInfo.h
Go to the documentation of this file.
1//===- Mips16InstrInfo.h - Mips16 Instruction Information -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips16 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
14#define LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
15
16#include "Mips16RegisterInfo.h"
17#include "MipsInstrInfo.h"
20#include <cstdint>
21
22namespace llvm {
23
24class MCInstrDesc;
25class MipsSubtarget;
26
28 const Mips16RegisterInfo RI;
29
30public:
31 explicit Mips16InstrInfo(const MipsSubtarget &STI);
32
33 const MipsRegisterInfo &getRegisterInfo() const override;
34
35 /// isLoadFromStackSlot - If the specified machine instruction is a direct
36 /// load from a stack slot, return the virtual or physical register number of
37 /// the destination along with the FrameIndex of the loaded stack slot. If
38 /// not, return 0. This predicate must return 0 if the instruction has
39 /// any side effects other than loading from the stack slot.
41 int &FrameIndex) const override;
42
43 /// isStoreToStackSlot - If the specified machine instruction is a direct
44 /// store to a stack slot, return the virtual or physical register number of
45 /// the source reg along with the FrameIndex of the loaded stack slot. If
46 /// not, return 0. This predicate must return 0 if the instruction has
47 /// any side effects other than storing to the stack slot.
49 int &FrameIndex) const override;
50
52 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
53 bool KillSrc) const override;
54
57 Register SrcReg, bool isKill, int FrameIndex,
58 const TargetRegisterClass *RC,
60 int64_t Offset) const override;
61
64 Register DestReg, int FrameIndex,
65 const TargetRegisterClass *RC,
67 int64_t Offset) const override;
68
69 bool expandPostRAPseudo(MachineInstr &MI) const override;
70
71 unsigned getOppositeBranchOpc(unsigned Opc) const override;
72
73 // Adjust SP by FrameSize bytes. Save RA, S0, S1
74 void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
76
77 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
78 void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
80
81 /// Adjust SP by Amount bytes.
82 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator I) const override;
84
85 /// Emit a series of instructions to load an immediate.
86 // This is to adjust some FrameReg. We return the new register to be used
87 // in place of FrameReg and the adjusted immediate field (&NewImm)
88 unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB,
90 unsigned &NewImm) const;
91
92 static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
93
94 static bool validSpImm8(int offset) {
95 return ((offset & 7) == 0) && isInt<11>(offset);
96 }
97
98 // build the proper one based on the Imm field
99
100 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
101
102 void BuildAddiuSpImm
103 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
104
105protected:
106 /// If the specific machine instruction is a instruction that moves/copies
107 /// value from one register to another register return destination and source
108 /// registers as machine operands.
109 std::optional<DestSourcePair>
110 isCopyInstrImpl(const MachineInstr &MI) const override;
111
112private:
113 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
114
116 unsigned Opc) const;
117
118 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
119 void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
121 unsigned Reg1, unsigned Reg2) const;
122
123 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
124 void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
127};
128
129} // end namespace llvm
130
131#endif // LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
uint64_t IntrinsicInst * II
A debug info location.
Definition: DebugLoc.h:33
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
bool expandPostRAPseudo(MachineInstr &MI) const override
static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount)
const MCInstrDesc & AddiuSpImm(int64_t Imm) const
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
void BuildAddiuSpImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
unsigned getOppositeBranchOpc(unsigned Opc) const override
GetOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
static bool validSpImm8(int offset)
void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned &NewImm) const
Emit a series of instructions to load an immediate.
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456