LLVM 20.0.0git
LoongArchMCCodeEmitter.cpp
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1//=- LoongArchMCCodeEmitter.cpp - Convert LoongArch code to machine code --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the LoongArchMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "LoongArchFixupKinds.h"
14#include "MCTargetDesc/LoongArchMCExpr.h"
15#include "MCTargetDesc/LoongArchMCTargetDesc.h"
16#include "llvm/MC/MCCodeEmitter.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCInstBuilder.h"
19#include "llvm/MC/MCInstrInfo.h"
20#include "llvm/MC/MCRegisterInfo.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/Support/Casting.h"
23#include "llvm/Support/EndianStream.h"
24
25using namespace llvm;
26
27#define DEBUG_TYPE "mccodeemitter"
28
29namespace {
30class LoongArchMCCodeEmitter : public MCCodeEmitter {
31 LoongArchMCCodeEmitter(const LoongArchMCCodeEmitter &) = delete;
32 void operator=(const LoongArchMCCodeEmitter &) = delete;
33 MCContext &Ctx;
34 MCInstrInfo const &MCII;
35
36public:
37 LoongArchMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
38 : Ctx(ctx), MCII(MCII) {}
39
40 ~LoongArchMCCodeEmitter() override {}
41
42 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
43 SmallVectorImpl<MCFixup> &Fixups,
44 const MCSubtargetInfo &STI) const override;
45
46 template <unsigned Opc>
47 void expandToVectorLDI(const MCInst &MI, SmallVectorImpl<char> &CB,
48 SmallVectorImpl<MCFixup> &Fixups,
49 const MCSubtargetInfo &STI) const;
50
51 void expandAddTPRel(const MCInst &MI, SmallVectorImpl<char> &CB,
52 SmallVectorImpl<MCFixup> &Fixups,
53 const MCSubtargetInfo &STI) const;
54
55 /// TableGen'erated function for getting the binary encoding for an
56 /// instruction.
57 uint64_t getBinaryCodeForInstr(const MCInst &MI,
58 SmallVectorImpl<MCFixup> &Fixups,
59 const MCSubtargetInfo &STI) const;
60
61 /// Return binary encoding of operand. If the machine operand requires
62 /// relocation, record the relocation and return zero.
63 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
64 SmallVectorImpl<MCFixup> &Fixups,
65 const MCSubtargetInfo &STI) const;
66
67 /// Return binary encoding of an immediate operand specified by OpNo.
68 /// The value returned is the value of the immediate minus 1.
69 /// Note that this function is dedicated to specific immediate types,
70 /// e.g. uimm2_plus1.
71 unsigned getImmOpValueSub1(const MCInst &MI, unsigned OpNo,
72 SmallVectorImpl<MCFixup> &Fixups,
73 const MCSubtargetInfo &STI) const;
74
75 /// Return binary encoding of an immediate operand specified by OpNo.
76 /// The value returned is the value of the immediate shifted right
77 // arithmetically by N.
78 /// Note that this function is dedicated to specific immediate types,
79 /// e.g. simm14_lsl2, simm16_lsl2, simm21_lsl2 and simm26_lsl2.
80 template <unsigned N>
81 unsigned getImmOpValueAsr(const MCInst &MI, unsigned OpNo,
82 SmallVectorImpl<MCFixup> &Fixups,
83 const MCSubtargetInfo &STI) const {
84 const MCOperand &MO = MI.getOperand(OpNo);
85 if (MO.isImm()) {
86 unsigned Res = MI.getOperand(OpNo).getImm();
87 assert((Res & ((1U << N) - 1U)) == 0 && "lowest N bits are non-zero");
88 return Res >> N;
89 }
90 return getExprOpValue(MI, MO, Fixups, STI);
91 }
92
93 unsigned getExprOpValue(const MCInst &MI, const MCOperand &MO,
94 SmallVectorImpl<MCFixup> &Fixups,
95 const MCSubtargetInfo &STI) const;
96};
97} // end namespace
98
99unsigned
100LoongArchMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
101 SmallVectorImpl<MCFixup> &Fixups,
102 const MCSubtargetInfo &STI) const {
103
104 if (MO.isReg())
105 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
106
107 if (MO.isImm())
108 return static_cast<unsigned>(MO.getImm());
109
110 // MO must be an Expr.
111 assert(MO.isExpr());
112 return getExprOpValue(MI, MO, Fixups, STI);
113}
114
115unsigned
116LoongArchMCCodeEmitter::getImmOpValueSub1(const MCInst &MI, unsigned OpNo,
117 SmallVectorImpl<MCFixup> &Fixups,
118 const MCSubtargetInfo &STI) const {
119 return MI.getOperand(OpNo).getImm() - 1;
120}
121
122unsigned
123LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
124 SmallVectorImpl<MCFixup> &Fixups,
125 const MCSubtargetInfo &STI) const {
126 assert(MO.isExpr() && "getExprOpValue expects only expressions");
127 bool RelaxCandidate = false;
128 bool EnableRelax = STI.hasFeature(LoongArch::FeatureRelax);
129 const MCExpr *Expr = MO.getExpr();
130 MCExpr::ExprKind Kind = Expr->getKind();
131 LoongArch::Fixups FixupKind = LoongArch::fixup_loongarch_invalid;
132 if (Kind == MCExpr::Target) {
133 const LoongArchMCExpr *LAExpr = cast<LoongArchMCExpr>(Expr);
134
135 RelaxCandidate = LAExpr->getRelaxHint();
136 switch (LAExpr->getKind()) {
137 case LoongArchMCExpr::VK_LoongArch_None:
138 case LoongArchMCExpr::VK_LoongArch_Invalid:
139 llvm_unreachable("Unhandled fixup kind!");
140 case LoongArchMCExpr::VK_LoongArch_TLS_LE_ADD_R:
141 llvm_unreachable("VK_LoongArch_TLS_LE_ADD_R should not represent an "
142 "instruction operand");
143 case LoongArchMCExpr::VK_LoongArch_B16:
144 FixupKind = LoongArch::fixup_loongarch_b16;
145 break;
146 case LoongArchMCExpr::VK_LoongArch_B21:
147 FixupKind = LoongArch::fixup_loongarch_b21;
148 break;
149 case LoongArchMCExpr::VK_LoongArch_B26:
150 case LoongArchMCExpr::VK_LoongArch_CALL:
151 case LoongArchMCExpr::VK_LoongArch_CALL_PLT:
152 FixupKind = LoongArch::fixup_loongarch_b26;
153 break;
154 case LoongArchMCExpr::VK_LoongArch_ABS_HI20:
155 FixupKind = LoongArch::fixup_loongarch_abs_hi20;
156 break;
157 case LoongArchMCExpr::VK_LoongArch_ABS_LO12:
158 FixupKind = LoongArch::fixup_loongarch_abs_lo12;
159 break;
160 case LoongArchMCExpr::VK_LoongArch_ABS64_LO20:
161 FixupKind = LoongArch::fixup_loongarch_abs64_lo20;
162 break;
163 case LoongArchMCExpr::VK_LoongArch_ABS64_HI12:
164 FixupKind = LoongArch::fixup_loongarch_abs64_hi12;
165 break;
166 case LoongArchMCExpr::VK_LoongArch_PCALA_HI20:
167 FixupKind = LoongArch::fixup_loongarch_pcala_hi20;
168 break;
169 case LoongArchMCExpr::VK_LoongArch_PCALA_LO12:
170 FixupKind = LoongArch::fixup_loongarch_pcala_lo12;
171 break;
172 case LoongArchMCExpr::VK_LoongArch_PCALA64_LO20:
173 FixupKind = LoongArch::fixup_loongarch_pcala64_lo20;
174 break;
175 case LoongArchMCExpr::VK_LoongArch_PCALA64_HI12:
176 FixupKind = LoongArch::fixup_loongarch_pcala64_hi12;
177 break;
178 case LoongArchMCExpr::VK_LoongArch_GOT_PC_HI20:
179 FixupKind = LoongArch::fixup_loongarch_got_pc_hi20;
180 break;
181 case LoongArchMCExpr::VK_LoongArch_GOT_PC_LO12:
182 FixupKind = LoongArch::fixup_loongarch_got_pc_lo12;
183 break;
184 case LoongArchMCExpr::VK_LoongArch_GOT64_PC_LO20:
185 FixupKind = LoongArch::fixup_loongarch_got64_pc_lo20;
186 break;
187 case LoongArchMCExpr::VK_LoongArch_GOT64_PC_HI12:
188 FixupKind = LoongArch::fixup_loongarch_got64_pc_hi12;
189 break;
190 case LoongArchMCExpr::VK_LoongArch_GOT_HI20:
191 FixupKind = LoongArch::fixup_loongarch_got_hi20;
192 break;
193 case LoongArchMCExpr::VK_LoongArch_GOT_LO12:
194 FixupKind = LoongArch::fixup_loongarch_got_lo12;
195 break;
196 case LoongArchMCExpr::VK_LoongArch_GOT64_LO20:
197 FixupKind = LoongArch::fixup_loongarch_got64_lo20;
198 break;
199 case LoongArchMCExpr::VK_LoongArch_GOT64_HI12:
200 FixupKind = LoongArch::fixup_loongarch_got64_hi12;
201 break;
202 case LoongArchMCExpr::VK_LoongArch_TLS_LE_HI20:
203 FixupKind = LoongArch::fixup_loongarch_tls_le_hi20;
204 break;
205 case LoongArchMCExpr::VK_LoongArch_TLS_LE_LO12:
206 FixupKind = LoongArch::fixup_loongarch_tls_le_lo12;
207 break;
208 case LoongArchMCExpr::VK_LoongArch_TLS_LE64_LO20:
209 FixupKind = LoongArch::fixup_loongarch_tls_le64_lo20;
210 break;
211 case LoongArchMCExpr::VK_LoongArch_TLS_LE64_HI12:
212 FixupKind = LoongArch::fixup_loongarch_tls_le64_hi12;
213 break;
214 case LoongArchMCExpr::VK_LoongArch_TLS_IE_PC_HI20:
215 FixupKind = LoongArch::fixup_loongarch_tls_ie_pc_hi20;
216 break;
217 case LoongArchMCExpr::VK_LoongArch_TLS_IE_PC_LO12:
218 FixupKind = LoongArch::fixup_loongarch_tls_ie_pc_lo12;
219 break;
220 case LoongArchMCExpr::VK_LoongArch_TLS_IE64_PC_LO20:
221 FixupKind = LoongArch::fixup_loongarch_tls_ie64_pc_lo20;
222 break;
223 case LoongArchMCExpr::VK_LoongArch_TLS_IE64_PC_HI12:
224 FixupKind = LoongArch::fixup_loongarch_tls_ie64_pc_hi12;
225 break;
226 case LoongArchMCExpr::VK_LoongArch_TLS_IE_HI20:
227 FixupKind = LoongArch::fixup_loongarch_tls_ie_hi20;
228 break;
229 case LoongArchMCExpr::VK_LoongArch_TLS_IE_LO12:
230 FixupKind = LoongArch::fixup_loongarch_tls_ie_lo12;
231 break;
232 case LoongArchMCExpr::VK_LoongArch_TLS_IE64_LO20:
233 FixupKind = LoongArch::fixup_loongarch_tls_ie64_lo20;
234 break;
235 case LoongArchMCExpr::VK_LoongArch_TLS_IE64_HI12:
236 FixupKind = LoongArch::fixup_loongarch_tls_ie64_hi12;
237 break;
238 case LoongArchMCExpr::VK_LoongArch_TLS_LD_PC_HI20:
239 FixupKind = LoongArch::fixup_loongarch_tls_ld_pc_hi20;
240 break;
241 case LoongArchMCExpr::VK_LoongArch_TLS_LD_HI20:
242 FixupKind = LoongArch::fixup_loongarch_tls_ld_hi20;
243 break;
244 case LoongArchMCExpr::VK_LoongArch_TLS_GD_PC_HI20:
245 FixupKind = LoongArch::fixup_loongarch_tls_gd_pc_hi20;
246 break;
247 case LoongArchMCExpr::VK_LoongArch_TLS_GD_HI20:
248 FixupKind = LoongArch::fixup_loongarch_tls_gd_hi20;
249 break;
250 case LoongArchMCExpr::VK_LoongArch_CALL36:
251 FixupKind = LoongArch::fixup_loongarch_call36;
252 break;
253 case LoongArchMCExpr::VK_LoongArch_TLS_DESC_PC_HI20:
254 FixupKind = LoongArch::fixup_loongarch_tls_desc_pc_hi20;
255 break;
256 case LoongArchMCExpr::VK_LoongArch_TLS_DESC_PC_LO12:
257 FixupKind = LoongArch::fixup_loongarch_tls_desc_pc_lo12;
258 break;
259 case LoongArchMCExpr::VK_LoongArch_TLS_DESC64_PC_LO20:
260 FixupKind = LoongArch::fixup_loongarch_tls_desc64_pc_lo20;
261 break;
262 case LoongArchMCExpr::VK_LoongArch_TLS_DESC64_PC_HI12:
263 FixupKind = LoongArch::fixup_loongarch_tls_desc64_pc_hi12;
264 break;
265 case LoongArchMCExpr::VK_LoongArch_TLS_DESC_HI20:
266 FixupKind = LoongArch::fixup_loongarch_tls_desc_hi20;
267 break;
268 case LoongArchMCExpr::VK_LoongArch_TLS_DESC_LO12:
269 FixupKind = LoongArch::fixup_loongarch_tls_desc_lo12;
270 break;
271 case LoongArchMCExpr::VK_LoongArch_TLS_DESC64_LO20:
272 FixupKind = LoongArch::fixup_loongarch_tls_desc64_lo20;
273 break;
274 case LoongArchMCExpr::VK_LoongArch_TLS_DESC64_HI12:
275 FixupKind = LoongArch::fixup_loongarch_tls_desc64_hi12;
276 break;
277 case LoongArchMCExpr::VK_LoongArch_TLS_DESC_LD:
278 FixupKind = LoongArch::fixup_loongarch_tls_desc_ld;
279 break;
280 case LoongArchMCExpr::VK_LoongArch_TLS_DESC_CALL:
281 FixupKind = LoongArch::fixup_loongarch_tls_desc_call;
282 break;
283 case LoongArchMCExpr::VK_LoongArch_TLS_LE_HI20_R:
284 FixupKind = LoongArch::fixup_loongarch_tls_le_hi20_r;
285 break;
286 case LoongArchMCExpr::VK_LoongArch_TLS_LE_LO12_R:
287 FixupKind = LoongArch::fixup_loongarch_tls_le_lo12_r;
288 break;
289 case LoongArchMCExpr::VK_LoongArch_PCREL20_S2:
290 FixupKind = LoongArch::fixup_loongarch_pcrel20_s2;
291 break;
292 case LoongArchMCExpr::VK_LoongArch_TLS_LD_PCREL20_S2:
293 FixupKind = LoongArch::fixup_loongarch_tls_ld_pcrel20_s2;
294 break;
295 case LoongArchMCExpr::VK_LoongArch_TLS_GD_PCREL20_S2:
296 FixupKind = LoongArch::fixup_loongarch_tls_gd_pcrel20_s2;
297 break;
298 case LoongArchMCExpr::VK_LoongArch_TLS_DESC_PCREL20_S2:
299 FixupKind = LoongArch::fixup_loongarch_tls_desc_pcrel20_s2;
300 break;
301 }
302 } else if (Kind == MCExpr::SymbolRef &&
303 cast<MCSymbolRefExpr>(Expr)->getKind() ==
304 MCSymbolRefExpr::VK_None) {
305 switch (MI.getOpcode()) {
306 default:
307 break;
308 case LoongArch::BEQ:
309 case LoongArch::BNE:
310 case LoongArch::BLT:
311 case LoongArch::BGE:
312 case LoongArch::BLTU:
313 case LoongArch::BGEU:
314 FixupKind = LoongArch::fixup_loongarch_b16;
315 break;
316 case LoongArch::BEQZ:
317 case LoongArch::BNEZ:
318 case LoongArch::BCEQZ:
319 case LoongArch::BCNEZ:
320 FixupKind = LoongArch::fixup_loongarch_b21;
321 break;
322 case LoongArch::B:
323 case LoongArch::BL:
324 FixupKind = LoongArch::fixup_loongarch_b26;
325 break;
326 }
327 }
328
329 assert(FixupKind != LoongArch::fixup_loongarch_invalid &&
330 "Unhandled expression!");
331
332 Fixups.push_back(
333 MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
334
335 // Emit an R_LARCH_RELAX if linker relaxation is enabled and LAExpr has relax
336 // hint.
337 if (EnableRelax && RelaxCandidate) {
338 const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
339 Fixups.push_back(MCFixup::create(
340 0, Dummy, MCFixupKind(LoongArch::fixup_loongarch_relax), MI.getLoc()));
341 }
342
343 return 0;
344}
345
346template <unsigned Opc>
347void LoongArchMCCodeEmitter::expandToVectorLDI(
348 const MCInst &MI, SmallVectorImpl<char> &CB,
349 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
350 int64_t Imm = MI.getOperand(1).getImm() & 0x3FF;
351 switch (MI.getOpcode()) {
352 case LoongArch::PseudoVREPLI_B:
353 case LoongArch::PseudoXVREPLI_B:
354 break;
355 case LoongArch::PseudoVREPLI_H:
356 case LoongArch::PseudoXVREPLI_H:
357 Imm |= 0x400;
358 break;
359 case LoongArch::PseudoVREPLI_W:
360 case LoongArch::PseudoXVREPLI_W:
361 Imm |= 0x800;
362 break;
363 case LoongArch::PseudoVREPLI_D:
364 case LoongArch::PseudoXVREPLI_D:
365 Imm |= 0xC00;
366 break;
367 }
368 MCInst TmpInst = MCInstBuilder(Opc).addOperand(MI.getOperand(0)).addImm(Imm);
369 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
370 support::endian::write(CB, Binary, llvm::endianness::little);
371}
372
373void LoongArchMCCodeEmitter::expandAddTPRel(const MCInst &MI,
374 SmallVectorImpl<char> &CB,
375 SmallVectorImpl<MCFixup> &Fixups,
376 const MCSubtargetInfo &STI) const {
377 MCOperand Rd = MI.getOperand(0);
378 MCOperand Rj = MI.getOperand(1);
379 MCOperand Rk = MI.getOperand(2);
380 MCOperand Symbol = MI.getOperand(3);
381 assert(Symbol.isExpr() &&
382 "Expected expression as third input to TP-relative add");
383
384 const LoongArchMCExpr *Expr = dyn_cast<LoongArchMCExpr>(Symbol.getExpr());
385 assert(Expr &&
386 Expr->getKind() == LoongArchMCExpr::VK_LoongArch_TLS_LE_ADD_R &&
387 "Expected %le_add_r relocation on TP-relative symbol");
388
389 // Emit the correct %le_add_r relocation for the symbol.
390 // TODO: Emit R_LARCH_RELAX for %le_add_r where the relax feature is enabled.
391 Fixups.push_back(MCFixup::create(
392 0, Expr, MCFixupKind(LoongArch::fixup_loongarch_tls_le_add_r),
393 MI.getLoc()));
394
395 // Emit a normal ADD instruction with the given operands.
396 unsigned ADD = MI.getOpcode() == LoongArch::PseudoAddTPRel_D
397 ? LoongArch::ADD_D
398 : LoongArch::ADD_W;
399 MCInst TmpInst =
400 MCInstBuilder(ADD).addOperand(Rd).addOperand(Rj).addOperand(Rk);
401 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
402 support::endian::write(CB, Binary, llvm::endianness::little);
403}
404
405void LoongArchMCCodeEmitter::encodeInstruction(
406 const MCInst &MI, SmallVectorImpl<char> &CB,
407 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
408 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
409 // Get byte count of instruction.
410 unsigned Size = Desc.getSize();
411
412 switch (MI.getOpcode()) {
413 default:
414 break;
415 case LoongArch::PseudoVREPLI_B:
416 case LoongArch::PseudoVREPLI_H:
417 case LoongArch::PseudoVREPLI_W:
418 case LoongArch::PseudoVREPLI_D:
419 return expandToVectorLDI<LoongArch::VLDI>(MI, CB, Fixups, STI);
420 case LoongArch::PseudoXVREPLI_B:
421 case LoongArch::PseudoXVREPLI_H:
422 case LoongArch::PseudoXVREPLI_W:
423 case LoongArch::PseudoXVREPLI_D:
424 return expandToVectorLDI<LoongArch::XVLDI>(MI, CB, Fixups, STI);
425 case LoongArch::PseudoAddTPRel_W:
426 case LoongArch::PseudoAddTPRel_D:
427 return expandAddTPRel(MI, CB, Fixups, STI);
428 }
429
430 switch (Size) {
431 default:
432 llvm_unreachable("Unhandled encodeInstruction length!");
433 case 4: {
434 uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
435 support::endian::write(CB, Bits, llvm::endianness::little);
436 break;
437 }
438 }
439}
440
441MCCodeEmitter *llvm::createLoongArchMCCodeEmitter(const MCInstrInfo &MCII,
442 MCContext &Ctx) {
443 return new LoongArchMCCodeEmitter(Ctx, MCII);
444}
445
446#include "LoongArchGenMCCodeEmitter.inc"
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:112
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LoongArchMCExpr::getKind
VariantKind getKind() const
Definition: LoongArchMCExpr.h:97
llvm::LoongArchMCExpr::getRelaxHint
bool getRelaxHint() const
Definition: LoongArchMCExpr.h:99
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::MCCodeEmitter::encodeInstruction
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
llvm::MCCodeEmitter::operator=
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:222
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:83
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:39
llvm::MCExpr::Target
@ Target
Target specific expression.
Definition: MCExpr.h:41
llvm::MCExpr::getKind
ExprKind getKind() const
Definition: MCExpr.h:78
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
llvm::MCInstBuilder::addOperand
MCInstBuilder & addOperand(const MCOperand &Op)
Add an operand.
Definition: MCInstBuilder.h:73
llvm::MCInstBuilder::addImm
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:43
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:37
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:81
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:63
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:62
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition: MCInst.h:70
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:115
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:66
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition: MCSubtargetInfo.h:121
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
uint32_t
uint64_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:246
llvm::support::endian::write
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:92
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::createLoongArchMCCodeEmitter
MCCodeEmitter * createLoongArchMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: LoongArchMCCodeEmitter.cpp:441
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
N
#define N
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:66
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