LLVM  15.0.0git
LoongArchMCCodeEmitter.cpp
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1 //=- LoongArchMCCodeEmitter.cpp - Convert LoongArch code to machine code --===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the LoongArchMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
15 #include "llvm/MC/MCCodeEmitter.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCInstBuilder.h"
18 #include "llvm/MC/MCInstrInfo.h"
19 #include "llvm/MC/MCRegisterInfo.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "mccodeemitter"
25 
26 namespace {
27 class LoongArchMCCodeEmitter : public MCCodeEmitter {
28  LoongArchMCCodeEmitter(const LoongArchMCCodeEmitter &) = delete;
29  void operator=(const LoongArchMCCodeEmitter &) = delete;
30  MCContext &Ctx;
31  MCInstrInfo const &MCII;
32 
33 public:
34  LoongArchMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
35  : Ctx(ctx), MCII(MCII) {}
36 
37  ~LoongArchMCCodeEmitter() override {}
38 
39  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
41  const MCSubtargetInfo &STI) const override;
42 
43  /// TableGen'erated function for getting the binary encoding for an
44  /// instruction.
45  uint64_t getBinaryCodeForInstr(const MCInst &MI,
47  const MCSubtargetInfo &STI) const;
48 
49  /// Return binary encoding of operand. If the machine operand requires
50  /// relocation, record the relocation and return zero.
51  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
53  const MCSubtargetInfo &STI) const;
54 
55  /// Return binary encoding of an immediate operand specified by OpNo.
56  /// The value returned is the value of the immediate minus 1.
57  /// Note that this function is dedicated to specific immediate types,
58  /// e.g. uimm2_plus1.
59  unsigned getImmOpValueSub1(const MCInst &MI, unsigned OpNo,
61  const MCSubtargetInfo &STI) const;
62 
63  /// Return binary encoding of an immediate operand specified by OpNo.
64  /// The value returned is the value of the immediate shifted right
65  // arithmetically by 2.
66  /// Note that this function is dedicated to specific immediate types,
67  /// e.g. simm14_lsl2, simm16_lsl2, simm21_lsl2 and simm26_lsl2.
68  unsigned getImmOpValueAsr2(const MCInst &MI, unsigned OpNo,
70  const MCSubtargetInfo &STI) const;
71 };
72 } // end anonymous namespace
73 
74 unsigned
75 LoongArchMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
77  const MCSubtargetInfo &STI) const {
78 
79  if (MO.isReg())
80  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
81 
82  if (MO.isImm())
83  return static_cast<unsigned>(MO.getImm());
84 
85  llvm_unreachable("Unhandled expression!");
86 }
87 
88 unsigned
89 LoongArchMCCodeEmitter::getImmOpValueSub1(const MCInst &MI, unsigned OpNo,
91  const MCSubtargetInfo &STI) const {
92  return MI.getOperand(OpNo).getImm() - 1;
93 }
94 
95 unsigned
96 LoongArchMCCodeEmitter::getImmOpValueAsr2(const MCInst &MI, unsigned OpNo,
98  const MCSubtargetInfo &STI) const {
99  unsigned Res = MI.getOperand(OpNo).getImm();
100  assert((Res & 3) == 0 && "lowest 2 bits are non-zero");
101  return Res >> 2;
102 }
103 
104 void LoongArchMCCodeEmitter::encodeInstruction(
106  const MCSubtargetInfo &STI) const {
107  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
108  // Get byte count of instruction.
109  unsigned Size = Desc.getSize();
110 
111  switch (Size) {
112  default:
113  llvm_unreachable("Unhandled encodeInstruction length!");
114  case 4: {
115  uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
117  break;
118  }
119  }
120 }
121 
123  MCContext &Ctx) {
124  return new LoongArchMCCodeEmitter(Ctx, MCII);
125 }
126 
127 #include "LoongArchGenMCCodeEmitter.inc"
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
MCCodeEmitter.h
MCInstBuilder.h
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCInstrDesc::getSize
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:622
llvm::support::little
@ little
Definition: Endian.h:27
MCContext.h
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::support::endian::write
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:97
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
uint64_t
MCRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
uint32_t
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
EndianStream.h
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
LoongArchBaseInfo.h
llvm::createLoongArchMCCodeEmitter
MCCodeEmitter * createLoongArchMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: LoongArchMCCodeEmitter.cpp:122
LoongArchMCTargetDesc.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69