LLVM  14.0.0git
MipsTargetMachine.cpp
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1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Mips target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsTargetMachine.h"
16 #include "Mips.h"
17 #include "Mips16ISelDAGToDAG.h"
18 #include "MipsSEISelDAGToDAG.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
32 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/InitializePasses.h"
37 #include "llvm/Support/CodeGen.h"
38 #include "llvm/Support/Debug.h"
42 #include <string>
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "mips"
47 
49  // Register the target.
54 
61 }
62 
63 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
64  const TargetOptions &Options,
65  bool isLittle) {
66  std::string Ret;
68 
69  // There are both little and big endian mips.
70  if (isLittle)
71  Ret += "e";
72  else
73  Ret += "E";
74 
75  if (ABI.IsO32())
76  Ret += "-m:m";
77  else
78  Ret += "-m:e";
79 
80  // Pointers are 32 bit on some ABIs.
81  if (!ABI.IsN64())
82  Ret += "-p:32:32";
83 
84  // 8 and 16 bit integers only need to have natural alignment, but try to
85  // align them to 32 bits. 64 bit integers have natural alignment.
86  Ret += "-i8:8:32-i16:16:32-i64:64";
87 
88  // 32 bit registers are always available and the stack is at least 64 bit
89  // aligned. On N64 64 bit registers are also available and the stack is
90  // 128 bit aligned.
91  if (ABI.IsN64() || ABI.IsN32())
92  Ret += "-n32:64-S128";
93  else
94  Ret += "-n32-S64";
95 
96  return Ret;
97 }
98 
101  if (!RM.hasValue() || JIT)
102  return Reloc::Static;
103  return *RM;
104 }
105 
106 // On function prologue, the stack is created by decrementing
107 // its pointer. Once decremented, all references are done with positive
108 // offset from the stack/frame pointer, using StackGrowsUp enables
109 // an easier handling.
110 // Using CodeModel::Large enables different CALL behavior.
112  StringRef CPU, StringRef FS,
113  const TargetOptions &Options,
116  CodeGenOpt::Level OL, bool JIT,
117  bool isLittle)
118  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
120  getEffectiveCodeModel(CM, CodeModel::Small), OL),
121  isLittle(isLittle), TLOF(std::make_unique<MipsTargetObjectFile>()),
122  ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
123  Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, None),
124  NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
125  isLittle, *this, None),
126  Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
127  isLittle, *this, None) {
128  Subtarget = &DefaultSubtarget;
129  initAsmInfo();
130 
131  // Mips supports the debug entry values.
133 }
134 
136 
137 void MipsebTargetMachine::anchor() {}
138 
140  StringRef CPU, StringRef FS,
141  const TargetOptions &Options,
144  CodeGenOpt::Level OL, bool JIT)
145  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
146 
147 void MipselTargetMachine::anchor() {}
148 
150  StringRef CPU, StringRef FS,
151  const TargetOptions &Options,
154  CodeGenOpt::Level OL, bool JIT)
155  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
156 
157 const MipsSubtarget *
159  Attribute CPUAttr = F.getFnAttribute("target-cpu");
160  Attribute FSAttr = F.getFnAttribute("target-features");
161 
162  std::string CPU =
163  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
164  std::string FS =
165  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
166  bool hasMips16Attr = F.getFnAttribute("mips16").isValid();
167  bool hasNoMips16Attr = F.getFnAttribute("nomips16").isValid();
168 
169  bool HasMicroMipsAttr = F.getFnAttribute("micromips").isValid();
170  bool HasNoMicroMipsAttr = F.getFnAttribute("nomicromips").isValid();
171 
172  // FIXME: This is related to the code below to reset the target options,
173  // we need to know whether or not the soft float flag is set on the
174  // function, so we can enable it as a subtarget feature.
175  bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
176 
177  if (hasMips16Attr)
178  FS += FS.empty() ? "+mips16" : ",+mips16";
179  else if (hasNoMips16Attr)
180  FS += FS.empty() ? "-mips16" : ",-mips16";
181  if (HasMicroMipsAttr)
182  FS += FS.empty() ? "+micromips" : ",+micromips";
183  else if (HasNoMicroMipsAttr)
184  FS += FS.empty() ? "-micromips" : ",-micromips";
185  if (softFloat)
186  FS += FS.empty() ? "+soft-float" : ",+soft-float";
187 
188  auto &I = SubtargetMap[CPU + FS];
189  if (!I) {
190  // This needs to be done before we create a new subtarget since any
191  // creation will depend on the TM and the code generation flags on the
192  // function that reside in TargetOptions.
194  I = std::make_unique<MipsSubtarget>(
195  TargetTriple, CPU, FS, isLittle, *this,
196  MaybeAlign(F.getParent()->getOverrideStackAlignment()));
197  }
198  return I.get();
199 }
200 
202  LLVM_DEBUG(dbgs() << "resetSubtarget\n");
203 
204  Subtarget = &MF->getSubtarget<MipsSubtarget>();
205 }
206 
207 namespace {
208 
209 /// Mips Code Generator Pass Configuration Options.
210 class MipsPassConfig : public TargetPassConfig {
211 public:
212  MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM)
213  : TargetPassConfig(TM, PM) {
214  // The current implementation of long branch pass requires a scratch
215  // register ($at) to be available before branch instructions. Tail merging
216  // can break this requirement, so disable it when long branch pass is
217  // enabled.
218  EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
219  }
220 
221  MipsTargetMachine &getMipsTargetMachine() const {
222  return getTM<MipsTargetMachine>();
223  }
224 
225  const MipsSubtarget &getMipsSubtarget() const {
226  return *getMipsTargetMachine().getSubtargetImpl();
227  }
228 
229  void addIRPasses() override;
230  bool addInstSelector() override;
231  void addPreEmitPass() override;
232  void addPreRegAlloc() override;
233  bool addIRTranslator() override;
234  void addPreLegalizeMachineIR() override;
235  bool addLegalizeMachineIR() override;
236  bool addRegBankSelect() override;
237  bool addGlobalInstructionSelect() override;
238 
239  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
240 };
241 
242 } // end anonymous namespace
243 
245  return new MipsPassConfig(*this, PM);
246 }
247 
248 std::unique_ptr<CSEConfigBase> MipsPassConfig::getCSEConfig() const {
249  return getStandardCSEConfigForOpt(TM->getOptLevel());
250 }
251 
252 void MipsPassConfig::addIRPasses() {
254  addPass(createAtomicExpandPass());
255  if (getMipsSubtarget().os16())
256  addPass(createMipsOs16Pass());
257  if (getMipsSubtarget().inMips16HardFloat())
258  addPass(createMips16HardFloatPass());
259 }
260 // Install an instruction selector pass using
261 // the ISelDag to gen Mips code.
262 bool MipsPassConfig::addInstSelector() {
263  addPass(createMipsModuleISelDagPass());
264  addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
265  addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
266  return false;
267 }
268 
269 void MipsPassConfig::addPreRegAlloc() {
271 }
272 
275  if (Subtarget->allowMixed16_32()) {
276  LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n");
277  // FIXME: This is no longer necessary as the TTI returned is per-function.
278  return TargetTransformInfo(F.getParent()->getDataLayout());
279  }
280 
281  LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n");
282  return TargetTransformInfo(BasicTTIImpl(this, F));
283 }
284 
285 // Implemented by targets that want to run passes immediately before
286 // machine code is emitted.
287 void MipsPassConfig::addPreEmitPass() {
288  // Expand pseudo instructions that are sensitive to register allocation.
289  addPass(createMipsExpandPseudoPass());
290 
291  // The microMIPS size reduction pass performs instruction reselection for
292  // instructions which can be remapped to a 16 bit instruction.
294 
295  // The delay slot filler pass can potientially create forbidden slot hazards
296  // for MIPSR6 and therefore it should go before MipsBranchExpansion pass.
298 
299  // This pass expands branches and takes care about the forbidden slot hazards.
300  // Expanding branches may potentially create forbidden slot hazards for
301  // MIPSR6, and fixing such hazard may potentially break a branch by extending
302  // its offset out of range. That's why this pass combine these two tasks, and
303  // runs them alternately until one of them finishes without any changes. Only
304  // then we can be sure that all branches are expanded properly and no hazards
305  // exists.
306  // Any new pass should go before this pass.
307  addPass(createMipsBranchExpansion());
308 
309  addPass(createMipsConstantIslandPass());
310 }
311 
312 bool MipsPassConfig::addIRTranslator() {
313  addPass(new IRTranslator(getOptLevel()));
314  return false;
315 }
316 
317 void MipsPassConfig::addPreLegalizeMachineIR() {
319 }
320 
321 bool MipsPassConfig::addLegalizeMachineIR() {
322  addPass(new Legalizer());
323  return false;
324 }
325 
326 bool MipsPassConfig::addRegBankSelect() {
327  addPass(new RegBankSelect());
328  return false;
329 }
330 
331 bool MipsPassConfig::addGlobalInstructionSelect() {
332  addPass(new InstructionSelect(getOptLevel()));
333  return false;
334 }
Mips16ISelDAGToDAG.h
llvm::createMipsExpandPseudoPass
FunctionPass * createMipsExpandPseudoPass()
createMipsExpandPseudoPass - returns an instance of the pseudo instruction expansion pass.
Definition: MipsExpandPseudo.cpp:911
llvm::MipsTargetMachine::MipsTargetMachine
MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT, bool isLittle)
Definition: MipsTargetMachine.cpp:111
ABI
Generic address nodes are lowered to some combination of target independent and machine specific ABI
Definition: Relocation.txt:34
llvm::MipsTargetMachine
Definition: MipsTargetMachine.h:27
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:167
LLVMInitializeMipsTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget()
Definition: MipsTargetMachine.cpp:48
Optional.h
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Definition: TargetOptions.h:124
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Definition: MipsABIInfo.h:22
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Definition: Function.h:61
llvm::Attribute
Definition: Attributes.h:52
StringRef.h
llvm::createMipsOs16Pass
ModulePass * createMipsOs16Pass()
Definition: MipsOs16.cpp:159
MipsTargetObjectFile.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::MipsTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: MipsTargetMachine.cpp:274
llvm::MipsSubtarget::allowMixed16_32
bool allowMixed16_32() const
Definition: MipsSubtarget.h:347
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
InstructionSelect.h
llvm::Optional< Reloc::Model >
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:892
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
STLExtras.h
llvm::createMips16HardFloatPass
ModulePass * createMips16HardFloatPass()
Definition: Mips16HardFloat.cpp:531
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MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: MipsTargetMachine.cpp:139
MipsTargetMachine.h
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const MipsSubtarget * getSubtargetImpl() const
Definition: MipsTargetMachine.h:48
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#define LLVM_DEBUG(X)
Definition: Debug.h:101
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#define F(x, y, z)
Definition: MD5.cpp:56
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Definition: CodeGen.h:22
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dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
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static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
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Definition: Legalizer.h:31
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FunctionPass * createMipsOptimizePICCallPass()
Return an OptimizeCall object.
Definition: MipsOptimizePICCall.cpp:318
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static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
Definition: MipsABIInfo.cpp:56
Y
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Mips.h
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FunctionPass * createMipsPreLegalizeCombiner()
Definition: MipsPreLegalizerCombiner.cpp:116
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Definition: StackSlotColoring.cpp:142
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This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
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static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
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@ Small
Definition: CodeGen.h:28
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FunctionPass * createAtomicExpandPass()
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This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:31
llvm::createMipsModuleISelDagPass
FunctionPass * createMipsModuleISelDagPass()
Definition: MipsModuleISelDAGToDAG.cpp:54
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RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1275
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PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
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const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
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Definition: TargetMachine.h:100
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LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
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FunctionPass * createMipsBranchExpansion()
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StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:301
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const NoneType None
Definition: None.h:23
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static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
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void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
Passes.h
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Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
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static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
Definition: ARMTargetMachine.cpp:118
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const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
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static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
Definition: MipsTargetMachine.cpp:63
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Definition: TargetMachine.h:98
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Definition: MipsSEISelDAGToDAG.cpp:1413
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@ JIT
Definition: ExecutionEngine.h:524
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#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
I
#define I(x, y, z)
Definition: MD5.cpp:59
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virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:850
TargetPassConfig.h
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Target & getTheMipsTarget()
Definition: MipsTargetInfo.cpp:13
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FunctionPass * createMicroMipsSizeReducePass()
Returns an instance of the MicroMips size reduction pass.
Definition: MicroMipsSizeReduction.cpp:795
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void resetSubtarget(MachineFunction *MF)
Reset the subtarget for the Mips target.
Definition: MipsTargetMachine.cpp:201
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@ FS
Definition: X86.h:188
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Definition: MachineFunction.h:230
TargetOptions.h
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@ RM
Definition: AArch64ISelLowering.h:472
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StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
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Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
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Definition: CodeGen.h:22
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Definition: CSEInfo.cpp:74
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Definition: MipsTargetInfo.cpp:25
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Definition: MipsTargetInfo.cpp:21
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Definition: CodeGen.h:52
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Definition: MipsSubtarget.h:39
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Definition: AVRTargetMachine.cpp:40
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Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:481
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Definition: LLVMTargetMachine.cpp:41
Attributes.h
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Concrete BasicTTIImpl that can be used if no further customization is needed.
Definition: BasicTTIImpl.h:2215
llvm::empty
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:254
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void initializeMipsPreLegalizerCombinerPass(PassRegistry &)
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Definition: MipsTargetObjectFile.h:16
std
Definition: BitVector.h:838
MipsABIInfo.h
RegBankSelect.h
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This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:393
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FunctionPass * createMipsDelaySlotFillerPass()
createMipsDelaySlotFillerPass - Returns a pass that fills in delay slots in Mips MachineFunctions
Definition: MipsDelaySlotFiller.cpp:969
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~MipsTargetMachine() override
llvm::MipsTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: MipsTargetMachine.cpp:244
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Legalizer.h
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void initializeMipsBranchExpansionPass(PassRegistry &)
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Definition: MipsTargetMachine.cpp:149
MipsSubtarget.h
TargetTransformInfo.h
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Definition: LegacyPassManager.h:39
llvm::IRTranslator
Definition: IRTranslator.h:62
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
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This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::TargetMachine::setSupportsDebugEntryValues
void setSupportsDebugEntryValues(bool Enable)
Definition: TargetMachine.h:258
BasicTTIImpl.h
raw_ostream.h
MachineFunction.h
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1815
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InitializePasses.h
MipsSEISelDAGToDAG.h
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Definition: TargetMachine.h:99
Debug.h
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FunctionPass * createMipsConstantIslandPass()
Returns a pass that converts branches to long branches.
Definition: MipsConstantIslandPass.cpp:1672
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FunctionPass * createMips16ISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel)
Definition: Mips16ISelDAGToDAG.cpp:222
llvm::getTheMipselTarget
Target & getTheMipselTarget()
Definition: MipsTargetInfo.cpp:17