LLVM  14.0.0git
MipsTargetMachine.cpp
Go to the documentation of this file.
1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Mips target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsTargetMachine.h"
16 #include "Mips.h"
17 #include "Mips16ISelDAGToDAG.h"
18 #include "MipsSEISelDAGToDAG.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
32 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/InitializePasses.h"
37 #include "llvm/MC/TargetRegistry.h"
38 #include "llvm/Support/CodeGen.h"
39 #include "llvm/Support/Debug.h"
42 #include <string>
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "mips"
47 
48 static cl::opt<bool>
49  EnableMulMulFix("mfix4300", cl::init(false),
50  cl::desc("Enable the VR4300 mulmul bug fix."), cl::Hidden);
51 
53  // Register the target.
58 
66 }
67 
68 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
69  const TargetOptions &Options,
70  bool isLittle) {
71  std::string Ret;
73 
74  // There are both little and big endian mips.
75  if (isLittle)
76  Ret += "e";
77  else
78  Ret += "E";
79 
80  if (ABI.IsO32())
81  Ret += "-m:m";
82  else
83  Ret += "-m:e";
84 
85  // Pointers are 32 bit on some ABIs.
86  if (!ABI.IsN64())
87  Ret += "-p:32:32";
88 
89  // 8 and 16 bit integers only need to have natural alignment, but try to
90  // align them to 32 bits. 64 bit integers have natural alignment.
91  Ret += "-i8:8:32-i16:16:32-i64:64";
92 
93  // 32 bit registers are always available and the stack is at least 64 bit
94  // aligned. On N64 64 bit registers are also available and the stack is
95  // 128 bit aligned.
96  if (ABI.IsN64() || ABI.IsN32())
97  Ret += "-n32:64-S128";
98  else
99  Ret += "-n32-S64";
100 
101  return Ret;
102 }
103 
106  if (!RM.hasValue() || JIT)
107  return Reloc::Static;
108  return *RM;
109 }
110 
111 // On function prologue, the stack is created by decrementing
112 // its pointer. Once decremented, all references are done with positive
113 // offset from the stack/frame pointer, using StackGrowsUp enables
114 // an easier handling.
115 // Using CodeModel::Large enables different CALL behavior.
117  StringRef CPU, StringRef FS,
118  const TargetOptions &Options,
121  CodeGenOpt::Level OL, bool JIT,
122  bool isLittle)
123  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
126  isLittle(isLittle), TLOF(std::make_unique<MipsTargetObjectFile>()),
127  ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
128  Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, None),
129  NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
130  isLittle, *this, None),
131  Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
132  isLittle, *this, None) {
133  Subtarget = &DefaultSubtarget;
134  initAsmInfo();
135 
136  // Mips supports the debug entry values.
138 }
139 
141 
142 void MipsebTargetMachine::anchor() {}
143 
145  StringRef CPU, StringRef FS,
146  const TargetOptions &Options,
149  CodeGenOpt::Level OL, bool JIT)
150  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
151 
152 void MipselTargetMachine::anchor() {}
153 
155  StringRef CPU, StringRef FS,
156  const TargetOptions &Options,
159  CodeGenOpt::Level OL, bool JIT)
160  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
161 
162 const MipsSubtarget *
164  Attribute CPUAttr = F.getFnAttribute("target-cpu");
165  Attribute FSAttr = F.getFnAttribute("target-features");
166 
167  std::string CPU =
168  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
169  std::string FS =
170  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
171  bool hasMips16Attr = F.getFnAttribute("mips16").isValid();
172  bool hasNoMips16Attr = F.getFnAttribute("nomips16").isValid();
173 
174  bool HasMicroMipsAttr = F.getFnAttribute("micromips").isValid();
175  bool HasNoMicroMipsAttr = F.getFnAttribute("nomicromips").isValid();
176 
177  // FIXME: This is related to the code below to reset the target options,
178  // we need to know whether or not the soft float flag is set on the
179  // function, so we can enable it as a subtarget feature.
180  bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
181 
182  if (hasMips16Attr)
183  FS += FS.empty() ? "+mips16" : ",+mips16";
184  else if (hasNoMips16Attr)
185  FS += FS.empty() ? "-mips16" : ",-mips16";
186  if (HasMicroMipsAttr)
187  FS += FS.empty() ? "+micromips" : ",+micromips";
188  else if (HasNoMicroMipsAttr)
189  FS += FS.empty() ? "-micromips" : ",-micromips";
190  if (softFloat)
191  FS += FS.empty() ? "+soft-float" : ",+soft-float";
192 
193  auto &I = SubtargetMap[CPU + FS];
194  if (!I) {
195  // This needs to be done before we create a new subtarget since any
196  // creation will depend on the TM and the code generation flags on the
197  // function that reside in TargetOptions.
199  I = std::make_unique<MipsSubtarget>(
200  TargetTriple, CPU, FS, isLittle, *this,
201  MaybeAlign(F.getParent()->getOverrideStackAlignment()));
202  }
203  return I.get();
204 }
205 
207  LLVM_DEBUG(dbgs() << "resetSubtarget\n");
208 
209  Subtarget = &MF->getSubtarget<MipsSubtarget>();
210 }
211 
212 namespace {
213 
214 /// Mips Code Generator Pass Configuration Options.
215 class MipsPassConfig : public TargetPassConfig {
216 public:
217  MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM)
218  : TargetPassConfig(TM, PM) {
219  // The current implementation of long branch pass requires a scratch
220  // register ($at) to be available before branch instructions. Tail merging
221  // can break this requirement, so disable it when long branch pass is
222  // enabled.
223  EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
224  }
225 
226  MipsTargetMachine &getMipsTargetMachine() const {
227  return getTM<MipsTargetMachine>();
228  }
229 
230  const MipsSubtarget &getMipsSubtarget() const {
231  return *getMipsTargetMachine().getSubtargetImpl();
232  }
233 
234  void addIRPasses() override;
235  bool addInstSelector() override;
236  void addPreEmitPass() override;
237  void addPreRegAlloc() override;
238  bool addIRTranslator() override;
239  void addPreLegalizeMachineIR() override;
240  bool addLegalizeMachineIR() override;
241  bool addRegBankSelect() override;
242  bool addGlobalInstructionSelect() override;
243 
244  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
245 };
246 
247 } // end anonymous namespace
248 
250  return new MipsPassConfig(*this, PM);
251 }
252 
253 std::unique_ptr<CSEConfigBase> MipsPassConfig::getCSEConfig() const {
254  return getStandardCSEConfigForOpt(TM->getOptLevel());
255 }
256 
257 void MipsPassConfig::addIRPasses() {
259  addPass(createAtomicExpandPass());
260  if (getMipsSubtarget().os16())
261  addPass(createMipsOs16Pass());
262  if (getMipsSubtarget().inMips16HardFloat())
263  addPass(createMips16HardFloatPass());
264 }
265 // Install an instruction selector pass using
266 // the ISelDag to gen Mips code.
267 bool MipsPassConfig::addInstSelector() {
268  addPass(createMipsModuleISelDagPass());
269  addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
270  addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
271  return false;
272 }
273 
274 void MipsPassConfig::addPreRegAlloc() {
276 }
277 
280  if (Subtarget->allowMixed16_32()) {
281  LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n");
282  // FIXME: This is no longer necessary as the TTI returned is per-function.
283  return TargetTransformInfo(F.getParent()->getDataLayout());
284  }
285 
286  LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n");
287  return TargetTransformInfo(BasicTTIImpl(this, F));
288 }
289 
290 // Implemented by targets that want to run passes immediately before
291 // machine code is emitted.
292 void MipsPassConfig::addPreEmitPass() {
293  // Expand pseudo instructions that are sensitive to register allocation.
294  addPass(createMipsExpandPseudoPass());
295 
296  // The microMIPS size reduction pass performs instruction reselection for
297  // instructions which can be remapped to a 16 bit instruction.
299 
300  // This pass inserts a nop instruction between two back-to-back multiplication
301  // instructions when the "mfix4300" flag is passed.
302  if (EnableMulMulFix)
303  addPass(createMipsMulMulBugPass());
304 
305  // The delay slot filler pass can potientially create forbidden slot hazards
306  // for MIPSR6 and therefore it should go before MipsBranchExpansion pass.
308 
309  // This pass expands branches and takes care about the forbidden slot hazards.
310  // Expanding branches may potentially create forbidden slot hazards for
311  // MIPSR6, and fixing such hazard may potentially break a branch by extending
312  // its offset out of range. That's why this pass combine these two tasks, and
313  // runs them alternately until one of them finishes without any changes. Only
314  // then we can be sure that all branches are expanded properly and no hazards
315  // exists.
316  // Any new pass should go before this pass.
317  addPass(createMipsBranchExpansion());
318 
319  addPass(createMipsConstantIslandPass());
320 }
321 
322 bool MipsPassConfig::addIRTranslator() {
323  addPass(new IRTranslator(getOptLevel()));
324  return false;
325 }
326 
327 void MipsPassConfig::addPreLegalizeMachineIR() {
329 }
330 
331 bool MipsPassConfig::addLegalizeMachineIR() {
332  addPass(new Legalizer());
333  return false;
334 }
335 
336 bool MipsPassConfig::addRegBankSelect() {
337  addPass(new RegBankSelect());
338  return false;
339 }
340 
341 bool MipsPassConfig::addGlobalInstructionSelect() {
342  addPass(new InstructionSelect(getOptLevel()));
343  return false;
344 }
Mips16ISelDAGToDAG.h
llvm::createMipsExpandPseudoPass
FunctionPass * createMipsExpandPseudoPass()
createMipsExpandPseudoPass - returns an instance of the pseudo instruction expansion pass.
Definition: MipsExpandPseudo.cpp:910
llvm::MipsTargetMachine::MipsTargetMachine
MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT, bool isLittle)
Definition: MipsTargetMachine.cpp:116
ABI
Generic address nodes are lowered to some combination of target independent and machine specific ABI
Definition: Relocation.txt:34
llvm::MipsTargetMachine
Definition: MipsTargetMachine.h:27
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:22
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:168
LLVMInitializeMipsTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget()
Definition: MipsTargetMachine.cpp:52
Optional.h
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::initializeMipsDelaySlotFillerPass
void initializeMipsDelaySlotFillerPass(PassRegistry &)
llvm::MipsABIInfo
Definition: MipsABIInfo.h:22
T
EnableMulMulFix
static cl::opt< bool > EnableMulMulFix("mfix4300", cl::init(false), cl::desc("Enable the VR4300 mulmul bug fix."), cl::Hidden)
llvm::Function
Definition: Function.h:62
llvm::Attribute
Definition: Attributes.h:52
StringRef.h
llvm::createMipsOs16Pass
ModulePass * createMipsOs16Pass()
Definition: MipsOs16.cpp:159
MipsTargetObjectFile.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::MipsTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: MipsTargetMachine.cpp:279
llvm::MipsSubtarget::allowMixed16_32
bool allowMixed16_32() const
Definition: MipsSubtarget.h:347
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1886
InstructionSelect.h
llvm::Optional< Reloc::Model >
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
STLExtras.h
llvm::createMips16HardFloatPass
ModulePass * createMips16HardFloatPass()
Definition: Mips16HardFloat.cpp:529
llvm::MipsebTargetMachine::MipsebTargetMachine
MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: MipsTargetMachine.cpp:144
MipsTargetMachine.h
llvm::MipsTargetMachine::getSubtargetImpl
const MipsSubtarget * getSubtargetImpl() const
Definition: MipsTargetMachine.h:48
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MSP430Attrs::CodeModel
CodeModel
Definition: MSP430Attributes.h:37
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::initializeMipsMulMulBugFixPass
void initializeMipsMulMulBugFixPass(PassRegistry &)
llvm::Legalizer
Definition: Legalizer.h:30
llvm::createMipsOptimizePICCallPass
FunctionPass * createMipsOptimizePICCallPass()
Return an OptimizeCall object.
Definition: MipsOptimizePICCall.cpp:318
llvm::MipsABIInfo::computeTargetABI
static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
Definition: MipsABIInfo.cpp:56
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
Mips.h
llvm::createMipsPreLegalizeCombiner
FunctionPass * createMipsPreLegalizeCombiner()
Definition: MipsPreLegalizerCombiner.cpp:116
false
Definition: StackSlotColoring.cpp:142
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:31
llvm::createMipsModuleISelDagPass
FunctionPass * createMipsModuleISelDagPass()
Definition: MipsModuleISelDAGToDAG.cpp:54
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1275
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::initializeMicroMipsSizeReducePass
void initializeMicroMipsSizeReducePass(PassRegistry &)
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:101
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::createMipsBranchExpansion
FunctionPass * createMipsBranchExpansion()
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
llvm::None
const NoneType None
Definition: None.h:23
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
computeTargetABI
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
Definition: ARMTargetMachine.cpp:120
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::cl::opt< bool >
computeDataLayout
static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
Definition: MipsTargetMachine.cpp:68
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:99
llvm::createMipsSEISelDag
FunctionPass * createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel)
Definition: MipsSEISelDAGToDAG.cpp:1414
MipsTargetInfo.h
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:133
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:844
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
TargetPassConfig.h
MipsMCTargetDesc.h
llvm::getTheMipsTarget
Target & getTheMipsTarget()
Definition: MipsTargetInfo.cpp:13
llvm::createMicroMipsSizeReducePass
FunctionPass * createMicroMipsSizeReducePass()
Returns an instance of the MicroMips size reduction pass.
Definition: MicroMipsSizeReduction.cpp:795
llvm::MipsTargetMachine::resetSubtarget
void resetSubtarget(MachineFunction *MF)
Reset the subtarget for the Mips target.
Definition: MipsTargetMachine.cpp:206
llvm::MachineFunction
Definition: MachineFunction.h:241
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:483
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:74
IRTranslator.h
llvm::getTheMips64elTarget
Target & getTheMips64elTarget()
Definition: MipsTargetInfo.cpp:25
llvm::getTheMips64Target
Target & getTheMips64Target()
Definition: MipsTargetInfo.cpp:21
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:498
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
Attributes.h
llvm::BasicTTIImpl
Concrete BasicTTIImpl that can be used if no further customization is needed.
Definition: BasicTTIImpl.h:2245
llvm::empty
constexpr bool empty(const T &RangeOrContainer)
Test whether RangeOrContainer is empty. Similar to C++17 std::empty.
Definition: STLExtras.h:252
llvm::initializeMipsPreLegalizerCombinerPass
void initializeMipsPreLegalizerCombinerPass(PassRegistry &)
llvm::MipsTargetObjectFile
Definition: MipsTargetObjectFile.h:16
std
Definition: BitVector.h:850
MipsABIInfo.h
RegBankSelect.h
Function.h
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:406
llvm::createMipsDelaySlotFillerPass
FunctionPass * createMipsDelaySlotFillerPass()
createMipsDelaySlotFillerPass - Returns a pass that fills in delay slots in Mips MachineFunctions
Definition: MipsDelaySlotFiller.cpp:966
llvm::MipsTargetMachine::~MipsTargetMachine
~MipsTargetMachine() override
llvm::MipsTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: MipsTargetMachine.cpp:249
CodeGen.h
Legalizer.h
llvm::initializeMipsBranchExpansionPass
void initializeMipsBranchExpansionPass(PassRegistry &)
llvm::MipselTargetMachine::MipselTargetMachine
MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: MipsTargetMachine.cpp:154
MipsSubtarget.h
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::IRTranslator
Definition: IRTranslator.h:63
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::TargetMachine::setSupportsDebugEntryValues
void setSupportsDebugEntryValues(bool Enable)
Definition: TargetMachine.h:259
BasicTTIImpl.h
llvm::cl::desc
Definition: CommandLine.h:412
raw_ostream.h
MachineFunction.h
TargetRegistry.h
InitializePasses.h
MipsSEISelDAGToDAG.h
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:100
Debug.h
llvm::createMipsConstantIslandPass
FunctionPass * createMipsConstantIslandPass()
Returns a pass that converts branches to long branches.
Definition: MipsConstantIslandPass.cpp:1671
llvm::createMipsMulMulBugPass
FunctionPass * createMipsMulMulBugPass()
Definition: MipsMulMulBugPass.cpp:136
llvm::createMips16ISelDag
FunctionPass * createMips16ISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel)
Definition: Mips16ISelDAGToDAG.cpp:222
llvm::getTheMipselTarget
Target & getTheMipselTarget()
Definition: MipsTargetInfo.cpp:17