27#include "llvm/IR/IntrinsicsMips.h"
33#define DEBUG_TYPE "mips-isel"
47void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(
bool IsDef,
MachineInstr &
MI,
50 unsigned Mask =
MI.getOperand(1).getImm();
55 MIB.addReg(Mips::DSPPos, Flag);
58 MIB.addReg(Mips::DSPSCount, Flag);
61 MIB.addReg(Mips::DSPCarry, Flag);
64 MIB.addReg(Mips::DSPOutFlag, Flag);
67 MIB.addReg(Mips::DSPCCond, Flag);
70 MIB.addReg(Mips::DSPEFI, Flag);
75 return Mips::MSACtrlRegClass.getRegister(RegNum);
80 unsigned DstReg = 0, ZeroReg = 0;
83 if ((
MI.getOpcode() == Mips::ADDiu) &&
84 (
MI.getOperand(1).getReg() == Mips::ZERO) &&
85 (
MI.getOperand(2).isImm()) &&
86 (
MI.getOperand(2).getImm() == 0)) {
87 DstReg =
MI.getOperand(0).getReg();
89 }
else if ((
MI.getOpcode() == Mips::DADDiu) &&
90 (
MI.getOperand(1).getReg() == Mips::ZERO_64) &&
91 (
MI.getOperand(2).isImm()) &&
92 (
MI.getOperand(2).getImm() == 0)) {
93 DstReg =
MI.getOperand(0).getReg();
94 ZeroReg = Mips::ZERO_64;
102 E =
MRI->use_end(); U !=
E;) {
103 MachineOperand &MO = *
U;
104 unsigned OpNo =
U.getOperandNo();
109 if (
MI->isPHI() ||
MI->isRegTiedToDefOperand(OpNo) ||
MI->isPseudo())
114 if (!
MRI->getRegClass(MO.
getReg())->contains(ZeroReg))
125 MachineInstrBuilder MIB(
MF, &
MI);
150void MipsSEDAGToDAGISel::processFunctionAfterISel(
MachineFunction &MF) {
151 MF.getInfo<MipsFunctionInfo>()->initGlobalBaseReg(
MF);
153 MachineRegisterInfo *
MRI = &
MF.getRegInfo();
155 for (
auto &
MBB:
MF) {
156 for (
auto &
MI:
MBB) {
157 switch (
MI.getOpcode()) {
159 addDSPCtrlRegOperands(
false,
MI,
MF);
162 addDSPCtrlRegOperands(
true,
MI,
MF);
164 case Mips::BuildPairF64_64:
165 case Mips::ExtractElementF64_64:
171 case Mips::BuildPairF64:
172 case Mips::ExtractElementF64:
178 if (
MI.getOperand(0).isGlobal() &&
179 MI.getOperand(0).getGlobal()->hasExternalLinkage() &&
180 MI.getOperand(0).getGlobal()->getName() ==
"_mcount")
183 case Mips::JALRPseudo:
184 case Mips::JALR64Pseudo:
185 case Mips::JALR16_MM:
186 if (
MI.getOperand(2).isMCSymbol() &&
187 MI.getOperand(2).getMCSymbol()->getName() ==
"_mcount")
191 if (
MI.getOperand(3).isMCSymbol() &&
192 MI.getOperand(3).getMCSymbol()->getName() ==
"_mcount")
196 replaceUsesWithZeroReg(
MRI,
MI);
202void MipsSEDAGToDAGISel::selectAddE(
SDNode *Node,
const SDLoc &
DL)
const {
206 EVT VT =
LHS.getValueType();
212 CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue,
Ops);
234 SDNode *DSPCtrlField =
CurDAG->getMachineNode(Mips::RDDSP,
DL, MVT::i32,
235 MVT::Glue, CstOne, InGlue);
237 SDNode *Carry =
CurDAG->getMachineNode(
238 Mips::EXT,
DL, MVT::i32,
SDValue(DSPCtrlField, 0), OuFlag, CstOne);
241 CurDAG->getTargetConstant(6,
DL, MVT::i32), CstOne,
243 SDNode *DSPCFWithCarry =
CurDAG->getMachineNode(Mips::INS,
DL, MVT::i32,
Ops);
253 SDNode *DSPCtrlFinal =
254 CurDAG->getMachineNode(Mips::INS,
DL, MVT::i32, InsOps);
256 SDNode *WrDSP =
CurDAG->getMachineNode(Mips::WRDSP,
DL, MVT::Glue,
257 SDValue(DSPCtrlFinal, 0), CstOne);
269 Base =
CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
270 Offset =
CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
277bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
279 unsigned ShiftAmount = 0)
const {
280 if (
CurDAG->isBaseWithConstantOffset(Addr)) {
282 if (
isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
286 if (FrameIndexSDNode *FIN =
288 Base =
CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
293 const Align Alignment(1ULL << ShiftAmount);
294 if (!
isAligned(Alignment, CN->getZExtValue()))
298 Offset =
CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
321 if (!
TM.isPositionIndependent()) {
328 if (selectAddrFrameIndexOffset(Addr,
Base,
Offset, 16))
367 return selectAddrRegImm(Addr,
Base,
Offset) ||
376 if (selectAddrFrameIndexOffset(Addr,
Base,
Offset, 9))
388 if (selectAddrFrameIndexOffset(Addr,
Base,
Offset, 11))
400 if (selectAddrFrameIndexOffset(Addr,
Base,
Offset, 12))
411 if (selectAddrFrameIndexOffset(Addr,
Base,
Offset, 16))
419 return selectAddrRegImm11(Addr,
Base,
Offset) ||
425 return selectAddrRegImm12(Addr,
Base,
Offset) ||
431 return selectAddrRegImm16(Addr,
Base,
Offset) ||
437 if (selectAddrFrameIndexOffset(Addr,
Base,
Offset, 7)) {
442 unsigned CnstOff = CN->getZExtValue();
443 return (CnstOff == (CnstOff & 0x3c));
463 if (selectAddrFrameIndexOffset(Addr,
Base,
Offset, 10))
474 if (selectAddrFrameIndexOffset(Addr,
Base,
Offset, 10, 1))
485 if (selectAddrFrameIndexOffset(Addr,
Base,
Offset, 10, 2))
496 if (selectAddrFrameIndexOffset(Addr,
Base,
Offset, 10, 3))
507bool MipsSEDAGToDAGISel::selectVSplat(
SDNode *
N,
APInt &Imm,
508 unsigned MinSizeInBits)
const {
517 APInt SplatValue, SplatUndef;
518 unsigned SplatBitSize;
521 if (!
Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
546bool MipsSEDAGToDAGISel::
548 unsigned ImmBitSize)
const {
550 EVT EltTy =
N->getValueType(0).getVectorElementType();
552 if (
N->getOpcode() == ISD::BITCAST)
553 N =
N->getOperand(0);
560 Imm =
CurDAG->getTargetConstant(ImmValue, SDLoc(
N), EltTy);
578bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(
SDValue N,
SDValue &Imm)
const {
582 if (
N->getOpcode() == ISD::BITCAST)
583 N =
N->getOperand(0);
609bool MipsSEDAGToDAGISel::selectVSplatMaskL(
SDValue N,
SDValue &Imm)
const {
613 if (
N->getOpcode() == ISD::BITCAST)
614 N =
N->getOperand(0);
640bool MipsSEDAGToDAGISel::selectVSplatMaskR(
SDValue N,
SDValue &Imm)
const {
644 if (
N->getOpcode() == ISD::BITCAST)
645 N =
N->getOperand(0);
658bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(
SDValue N,
663 if (
N->getOpcode() == ISD::BITCAST)
664 N =
N->getOperand(0);
668 int32_t
Log2 = (~ImmValue).exactLogBase2();
680bool MipsSEDAGToDAGISel::selectVSplatImmEq1(
SDValue N)
const {
684 if (
N->getOpcode() == ISD::BITCAST)
685 N =
N->getOperand(0);
687 return selectVSplat(
N.getNode(), ImmValue, EltTy.
getSizeInBits()) &&
691bool MipsSEDAGToDAGISel::trySelect(
SDNode *Node) {
692 unsigned Opcode =
Node->getOpcode();
704 MVT VT =
Subtarget->isGP64bit() ? MVT::i64 : MVT::i32;
712 EVT NodeTys[] = {VT, VT};
714 ? Mips::PseudoD_SELECT_I64
715 : Mips::PseudoD_SELECT_I,
721 selectAddE(Node,
DL);
727 if (
Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
730 Mips::ZERO_64, MVT::i64);
732 CurDAG->getMachineNode(Mips::DMTC1,
DL, MVT::f64, Zero));
735 Mips::ZERO, MVT::i32);
737 MVT::f64, Zero, Zero));
740 Mips::ZERO, MVT::i32);
742 MVT::f64, Zero, Zero));
751 int64_t
Imm = CN->getSExtValue();
752 unsigned Size = CN->getValueSizeInBits(0);
757 MipsAnalyzeImmediate AnalyzeImm;
771 if (Inst->Opc == Mips::LUi64)
772 RegOpnd =
CurDAG->getMachineNode(Inst->Opc,
DL, MVT::i64, ImmOpnd);
775 CurDAG->getMachineNode(Inst->Opc,
DL, MVT::i64,
776 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
780 for (++Inst; Inst != Seq.
end(); ++Inst) {
783 RegOpnd =
CurDAG->getMachineNode(Inst->Opc,
DL, MVT::i64,
792 const unsigned IntrinsicOpcode =
Node->getConstantOperandVal(1);
793 switch (IntrinsicOpcode) {
797 case Intrinsic::mips_cfcmsa: {
801 getMSACtrlReg(RegIdx), MVT::i32);
805 case Intrinsic::mips_ldr_d:
806 case Intrinsic::mips_ldr_w: {
807 unsigned Op = (IntrinsicOpcode == Intrinsic::mips_ldr_d) ? Mips::LDR_D
811 assert(
Node->getNumOperands() == 4 &&
"Unexpected number of operands.");
821 "Invalid instruction operand.");
824 const ConstantInt *Val =
832 assert(
Node->getValueType(0).is128BitVector());
845 switch (
Node->getConstantOperandVal(0)) {
849 case Intrinsic::mips_move_v:
853 Node->getValueType(0),
854 Node->getOperand(1)));
861 const unsigned IntrinsicOpcode =
Node->getConstantOperandVal(1);
862 switch (IntrinsicOpcode) {
866 case Intrinsic::mips_ctcmsa: {
871 getMSACtrlReg(RegIdx),
Value);
875 case Intrinsic::mips_str_d:
876 case Intrinsic::mips_str_w: {
877 unsigned Op = (IntrinsicOpcode == Intrinsic::mips_str_d) ? Mips::STR_D
881 assert(
Node->getNumOperands() == 5 &&
"Unexpected number of operands.");
892 "Invalid instruction operand.");
895 const ConstantInt *Val =
914 MVT ResTy =
Node->getSimpleValueType(0);
915 assert((ResTy == MVT::f64 || ResTy == MVT::f32) &&
916 "Unsupported float type!");
918 if (ResTy == MVT::f64)
919 Opc = (
Subtarget->isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32);
926 Opc = Mips::FABS_D64_MM;
929 Opc = Mips::FABS_D32_MM;
932 Opc = Mips::FABS_S_MM;
954 if (
Node->getValueType(0) != MVT::i32 &&
Node->getValueType(0) != MVT::i64)
957 if (
Node->getNumOperands() != 4)
964 MVT ResTy =
Node->getSimpleValueType(0);
965 uint64_t Pos =
Node->getConstantOperandVal(1);
966 uint64_t
Size =
Node->getConstantOperandVal(2);
975 if (ResTy != MVT::i32 && ResTy != MVT::i64)
979 if (ResTy == MVT::i32) {
980 if (Pos +
Size <= 32)
983 if (Pos +
Size <= 32)
985 else if (Pos < 32 && 1 <
Size)
986 Opcode = Mips::DINSM;
988 Opcode = Mips::DINSU;
993 Node->getOperand(0),
CurDAG->getTargetConstant(Pos,
DL, MVT::i32),
1005 unsigned RdhwrOpc, DestReg;
1007 if (PtrVT == MVT::i32) {
1008 RdhwrOpc = Mips::RDHWR;
1011 RdhwrOpc = Mips::RDHWR64;
1012 DestReg = Mips::V1_64;
1016 CurDAG->getMachineNode(RdhwrOpc,
DL,
Node->getValueType(0), MVT::Glue,
1017 CurDAG->getRegister(Mips::HWR29, MVT::i32),
1018 CurDAG->getTargetConstant(0,
DL, MVT::i32));
1040 const MipsABIInfo &
ABI =
1041 static_cast<const MipsTargetMachine &
>(
TM).getABI();
1044 APInt SplatValue, SplatUndef;
1045 unsigned SplatBitSize;
1059 switch (SplatBitSize) {
1063 LdiOp = Mips::LDI_B;
1064 ViaVecTy = MVT::v16i8;
1067 LdiOp = Mips::LDI_H;
1068 ViaVecTy = MVT::v8i16;
1071 LdiOp = Mips::LDI_W;
1072 ViaVecTy = MVT::v4i32;
1075 LdiOp = Mips::LDI_D;
1076 ViaVecTy = MVT::v2i64;
1080 SDNode *Res =
nullptr;
1090 Res =
CurDAG->getMachineNode(LdiOp,
DL, ViaVecTy, Imm);
1092 ((
ABI.IsO32() && SplatBitSize < 64) ||
1093 (
ABI.IsN32() ||
ABI.IsN64()))) {
1099 bool Is32BitSplat =
ABI.IsO32() || SplatBitSize < 64;
1100 const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
1101 const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64;
1103 Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT);
1105 const unsigned FILLOp =
1108 : (SplatBitSize == 32 ? Mips::FILL_W
1109 : (SplatBitSize == 64 ? Mips::FILL_D : 0));
1111 assert(FILLOp != 0 &&
"Unknown FILL Op for splat synthesis!");
1112 assert((!
ABI.IsO32() || (FILLOp != Mips::FILL_D)) &&
1113 "Attempting to use fill.d on MIPS32!");
1118 Res =
CurDAG->getMachineNode(ADDiuOp,
DL, SplatMVT, ZeroVal, LoVal);
1121 }
else if (SplatValue.
isSignedIntN(32) && SplatBitSize == 32) {
1126 SDValue ZeroVal =
CurDAG->getRegister(Mips::ZERO, MVT::i32);
1132 Res =
CurDAG->getMachineNode(Mips::LUi,
DL, MVT::i32, HiVal);
1135 Res =
CurDAG->getMachineNode(Mips::ORi,
DL, MVT::i32,
1138 assert((
Hi ||
Lo) &&
"Zero case reached 32 bit case splat synthesis!");
1140 CurDAG->getMachineNode(Mips::FILL_W,
DL, MVT::v4i32,
SDValue(Res, 0));
1142 }
else if (SplatValue.
isSignedIntN(32) && SplatBitSize == 64 &&
1143 (
ABI.IsN32() ||
ABI.IsN64())) {
1149 SDValue ZeroVal =
CurDAG->getRegister(Mips::ZERO, MVT::i32);
1155 Res =
CurDAG->getMachineNode(Mips::LUi,
DL, MVT::i32, HiVal);
1158 Res =
CurDAG->getMachineNode(Mips::ORi,
DL, MVT::i32,
1161 Res =
CurDAG->getMachineNode(
1162 Mips::SUBREG_TO_REG,
DL, MVT::i64,
1163 CurDAG->getTargetConstant(((
Hi >> 15) & 0x1),
DL, MVT::i64),
1165 CurDAG->getTargetConstant(Mips::sub_32,
DL, MVT::i64));
1168 CurDAG->getMachineNode(Mips::FILL_D,
DL, MVT::v2i64,
SDValue(Res, 0));
1204 SDValue HighestVal =
CurDAG->getTargetConstant(Highest,
DL, MVT::i32);
1205 SDValue ZeroVal =
CurDAG->getRegister(Mips::ZERO, MVT::i32);
1224 Res =
CurDAG->getMachineNode(Mips::LUi,
DL, MVT::i32, HiVal);
1227 Res =
CurDAG->getMachineNode(Mips::ORi,
DL, MVT::i32,
1232 HiRes =
CurDAG->getMachineNode(Mips::LUi,
DL, MVT::i32, HighestVal);
1235 HiRes =
CurDAG->getMachineNode(Mips::ORi,
DL, MVT::i32,
1236 Highest ?
SDValue(HiRes, 0) : ZeroVal,
1241 Res =
CurDAG->getMachineNode(Mips::FILL_W,
DL, MVT::v4i32,
1244 Res =
CurDAG->getMachineNode(
1245 Mips::INSERT_W,
DL, MVT::v4i32,
SDValue(Res, 0),
1246 (Highest || Higher) ?
SDValue(HiRes, 0) : ZeroVal,
1247 CurDAG->getTargetConstant(1,
DL, MVT::i32));
1250 const TargetRegisterClass *RC =
1253 Res =
CurDAG->getMachineNode(
1254 Mips::COPY_TO_REGCLASS,
DL, ViaVecTy,
SDValue(Res, 0),
1257 Res =
CurDAG->getMachineNode(
1258 Mips::SPLATI_D,
DL, MVT::v2i64,
SDValue(Res, 0),
1259 CurDAG->getTargetConstant(0,
DL, MVT::i32));
1260 }
else if (
ABI.IsN64() ||
ABI.IsN32()) {
1262 SDValue Zero64Val =
CurDAG->getRegister(Mips::ZERO_64, MVT::i64);
1264 const bool ResNonZero =
Hi ||
Lo;
1267 HiRes =
CurDAG->getMachineNode(
1268 Mips::SUBREG_TO_REG,
DL, MVT::i64,
1269 CurDAG->getTargetConstant(((Highest >> 15) & 0x1),
DL, MVT::i64),
1271 CurDAG->getTargetConstant(Mips::sub_32,
DL, MVT::i64));
1274 Res =
CurDAG->getMachineNode(
1275 Mips::SUBREG_TO_REG,
DL, MVT::i64,
1276 CurDAG->getTargetConstant(((
Hi >> 15) & 0x1),
DL, MVT::i64),
1278 CurDAG->getTargetConstant(Mips::sub_32,
DL, MVT::i64));
1290 const ConstantInt *Const32 = ConstantInt::get(
Int32Ty, 32);
1296 Res =
CurDAG->getMachineNode(Mips::DINSU,
DL, MVT::i64,
Ops);
1297 }
else if (HiResNonZero) {
1298 Res =
CurDAG->getMachineNode(
1299 Mips::DSLL32,
DL, MVT::i64,
SDValue(HiRes, 0),
1300 CurDAG->getTargetConstant(0,
DL, MVT::i32));
1303 "Zero splat value handled by non-zero 64bit splat synthesis!");
1305 Res =
CurDAG->getMachineNode(Mips::FILL_D,
DL, MVT::v2i64,
1313 if (ResVecTy != ViaVecTy) {
1320 const TargetRegisterClass *RC =
TLI->getRegClassFor(ResVecTySimple);
1321 Res =
CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS,
DL,
1336bool MipsSEDAGToDAGISel::SelectInlineAsmMemoryOperand(
1338 std::vector<SDValue> &OutOps) {
1341 switch(ConstraintID) {
1348 OutOps.push_back(
Base);
1349 OutOps.push_back(
Offset);
1352 OutOps.push_back(
Op);
1353 OutOps.push_back(
CurDAG->getTargetConstant(0, SDLoc(
Op), MVT::i32));
1362 OutOps.push_back(
Base);
1363 OutOps.push_back(
Offset);
1366 OutOps.push_back(
Op);
1367 OutOps.push_back(
CurDAG->getTargetConstant(0, SDLoc(
Op), MVT::i32));
1375 OutOps.push_back(
Base);
1376 OutOps.push_back(
Offset);
1382 OutOps.push_back(
Base);
1383 OutOps.push_back(
Offset);
1388 OutOps.push_back(
Base);
1389 OutOps.push_back(
Offset);
1393 OutOps.push_back(
Op);
1394 OutOps.push_back(
CurDAG->getTargetConstant(0, SDLoc(
Op), MVT::i32));
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static uint64_t getConstant(const Value *IndexValue)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
mir Rename Register Operands
Class for arbitrary precision integers.
LLVM_ABI APInt getLoBits(unsigned numBits) const
Compute an APInt containing numBits lowbits from this APInt.
uint64_t getZExtValue() const
Get zero extended value.
unsigned popcount() const
Count the number of bits set.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool isNegative() const
Determine sign of this APInt.
int32_t exactLogBase2() const
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
bool isShiftedMask() const
Return true if this APInt value contains a non-empty sequence of ones with the remainder zero.
bool isMask(unsigned numBits) const
bool isIntN(unsigned N) const
Check if this APInt has an N-bits unsigned integer value.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
LLVM_ABI bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector.
Legacy analysis pass which computes a DominatorTree.
FunctionPass class - This class is used to implement most global optimizations.
static LLVM_ABI IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Wrapper class representing physical registers. Should be passed by value.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
LLVM_ABI void setReg(Register Reg)
Change the register this operand corresponds to.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
defusechain_iterator< true, false, false, true, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
MipsDAGToDAGISelLegacy(std::unique_ptr< SelectionDAGISel > S)
bool runOnMachineFunction(MachineFunction &MF) override
const MipsSubtarget * Subtarget
Keep a pointer to the MipsSubtarget around so that we can make the right decision when generating cod...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MipsSEDAGToDAGISelLegacy(MipsTargetMachine &TM, CodeGenOptLevel OL)
bool inMips16Mode() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const TargetLowering * TLI
const TargetInstrInfo * TII
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
const TargetLowering * getTargetLowering() const
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
unsigned getID() const
Return the register class ID number.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ ADD
Simple integer binary arithmetic operators.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Undef
Value of the register doesn't matter.
NodeAddr< NodeBase * > Node
This is an optimization pass for GlobalISel generic memory operations.
FunctionAddr VTableAddr Value
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
FunctionAddr VTableAddr uintptr_t uintptr_t Int32Ty
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
FunctionPass * createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOptLevel OptLevel)
CodeGenOptLevel
Code generation optimization level.
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
DWARFExpression::Operation Op
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
constexpr bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
unsigned Log2(Align A)
Returns the log2 of the alignment.
Implement std::hash so that hash_code can be used in STL containers.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
bool is128BitVector() const
Return true if this is a 128-bit vector type.
EVT getVectorElementType() const
Given a vector type, return the type of each element.