LLVM  14.0.0git
ARMTargetMachine.cpp
Go to the documentation of this file.
1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMMacroFusion.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
36 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/TargetRegistry.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
50 #include "llvm/Transforms/IPO.h"
51 #include "llvm/Transforms/Scalar.h"
52 #include <cassert>
53 #include <memory>
54 #include <string>
55 
56 using namespace llvm;
57 
58 static cl::opt<bool>
59 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
60  cl::desc("Inhibit optimization of S->D register accesses on A15"),
61  cl::init(false));
62 
63 static cl::opt<bool>
64 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
65  cl::desc("Run SimplifyCFG after expanding atomic operations"
66  " to make use of cmpxchg flow-based information"),
67  cl::init(true));
68 
69 static cl::opt<bool>
70 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
71  cl::desc("Enable ARM load/store optimization pass"),
72  cl::init(true));
73 
74 // FIXME: Unify control over GlobalMerge.
76 EnableGlobalMerge("arm-global-merge", cl::Hidden,
77  cl::desc("Enable the global merge pass"));
78 
79 namespace llvm {
81 }
82 
84  // Register the target.
89 
108 }
109 
110 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
111  if (TT.isOSBinFormatMachO())
112  return std::make_unique<TargetLoweringObjectFileMachO>();
113  if (TT.isOSWindows())
114  return std::make_unique<TargetLoweringObjectFileCOFF>();
115  return std::make_unique<ARMElfTargetObjectFile>();
116 }
117 
120  const TargetOptions &Options) {
121  StringRef ABIName = Options.MCOptions.getABIName();
122 
123  if (ABIName.empty())
124  ABIName = ARM::computeDefaultTargetABI(TT, CPU);
125 
126  if (ABIName == "aapcs16")
128  else if (ABIName.startswith("aapcs"))
130  else if (ABIName.startswith("apcs"))
132 
133  llvm_unreachable("Unhandled/unknown ABI Name!");
135 }
136 
137 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
138  const TargetOptions &Options,
139  bool isLittle) {
140  auto ABI = computeTargetABI(TT, CPU, Options);
141  std::string Ret;
142 
143  if (isLittle)
144  // Little endian.
145  Ret += "e";
146  else
147  // Big endian.
148  Ret += "E";
149 
151 
152  // Pointers are 32 bits and aligned to 32 bits.
153  Ret += "-p:32:32";
154 
155  // Function pointers are aligned to 8 bits (because the LSB stores the
156  // ARM/Thumb state).
157  Ret += "-Fi8";
158 
159  // ABIs other than APCS have 64 bit integers with natural alignment.
161  Ret += "-i64:64";
162 
163  // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
164  // bits, others to 64 bits. We always try to align to 64 bits.
166  Ret += "-f64:32:64";
167 
168  // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
169  // to 64. We always ty to give them natural alignment.
171  Ret += "-v64:32:64-v128:32:128";
173  Ret += "-v128:64:128";
174 
175  // Try to align aggregates to 32 bits (the default is 64 bits, which has no
176  // particular hardware support on 32-bit ARM).
177  Ret += "-a:0:32";
178 
179  // Integer registers are 32 bits.
180  Ret += "-n32";
181 
182  // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
183  // aligned everywhere else.
184  if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
185  Ret += "-S128";
187  Ret += "-S64";
188  else
189  Ret += "-S32";
190 
191  return Ret;
192 }
193 
196  if (!RM.hasValue())
197  // Default relocation model on Darwin is PIC.
198  return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
199 
200  if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
201  assert(TT.isOSBinFormatELF() &&
202  "ROPI/RWPI currently only supported for ELF");
203 
204  // DynamicNoPIC is only used on darwin.
205  if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
206  return Reloc::Static;
207 
208  return *RM;
209 }
210 
211 /// Create an ARM architecture model.
212 ///
214  StringRef CPU, StringRef FS,
215  const TargetOptions &Options,
218  CodeGenOpt::Level OL, bool isLittle)
219  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
220  CPU, FS, Options, getEffectiveRelocModel(TT, RM),
222  TargetABI(computeTargetABI(TT, CPU, Options)),
223  TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
224 
225  // Default to triple-appropriate float ABI
227  if (isTargetHardFloat())
228  this->Options.FloatABIType = FloatABI::Hard;
229  else
230  this->Options.FloatABIType = FloatABI::Soft;
231  }
232 
233  // Default to triple-appropriate EABI
236  // musl is compatible with glibc with regard to EABI version
242  this->Options.EABIVersion = EABI::GNU;
243  else
244  this->Options.EABIVersion = EABI::EABI5;
245  }
246 
247  if (TT.isOSBinFormatMachO()) {
248  this->Options.TrapUnreachable = true;
249  this->Options.NoTrapAfterNoreturn = true;
250  }
251 
252  // ARM supports the debug entry values.
254 
255  initAsmInfo();
256 
257  // ARM supports the MachineOutliner.
258  setMachineOutliner(true);
260 }
261 
263 
264 const ARMSubtarget *
266  Attribute CPUAttr = F.getFnAttribute("target-cpu");
267  Attribute FSAttr = F.getFnAttribute("target-features");
268 
269  std::string CPU =
270  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
271  std::string FS =
272  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
273 
274  // FIXME: This is related to the code below to reset the target options,
275  // we need to know whether or not the soft float flag is set on the
276  // function before we can generate a subtarget. We also need to use
277  // it as a key for the subtarget since that can be the only difference
278  // between two functions.
279  bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
280  // If the soft float attribute is set on the function turn on the soft float
281  // subtarget feature.
282  if (SoftFloat)
283  FS += FS.empty() ? "+soft-float" : ",+soft-float";
284 
285  // Use the optminsize to identify the subtarget, but don't use it in the
286  // feature string.
287  std::string Key = CPU + FS;
288  if (F.hasMinSize())
289  Key += "+minsize";
290 
291  auto &I = SubtargetMap[Key];
292  if (!I) {
293  // This needs to be done before we create a new subtarget since any
294  // creation will depend on the TM and the code generation flags on the
295  // function that reside in TargetOptions.
297  I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
298  F.hasMinSize());
299 
300  if (!I->isThumb() && !I->hasARMOps())
301  F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
302  "instructions, but the target does not support ARM mode execution.");
303  }
304 
305  return I.get();
306 }
307 
310  return TargetTransformInfo(ARMTTIImpl(this, F));
311 }
312 
314  StringRef CPU, StringRef FS,
315  const TargetOptions &Options,
318  CodeGenOpt::Level OL, bool JIT)
319  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
320 
322  StringRef CPU, StringRef FS,
323  const TargetOptions &Options,
326  CodeGenOpt::Level OL, bool JIT)
327  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
328 
329 namespace {
330 
331 /// ARM Code Generator Pass Configuration Options.
332 class ARMPassConfig : public TargetPassConfig {
333 public:
334  ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
335  : TargetPassConfig(TM, PM) {}
336 
337  ARMBaseTargetMachine &getARMTargetMachine() const {
338  return getTM<ARMBaseTargetMachine>();
339  }
340 
342  createMachineScheduler(MachineSchedContext *C) const override {
344  // add DAG Mutations here.
345  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
346  if (ST.hasFusion())
348  return DAG;
349  }
350 
352  createPostMachineScheduler(MachineSchedContext *C) const override {
354  // add DAG Mutations here.
355  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
356  if (ST.hasFusion())
358  return DAG;
359  }
360 
361  void addIRPasses() override;
362  void addCodeGenPrepare() override;
363  bool addPreISel() override;
364  bool addInstSelector() override;
365  bool addIRTranslator() override;
366  bool addLegalizeMachineIR() override;
367  bool addRegBankSelect() override;
368  bool addGlobalInstructionSelect() override;
369  void addPreRegAlloc() override;
370  void addPreSched2() override;
371  void addPreEmitPass() override;
372  void addPreEmitPass2() override;
373 
374  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
375 };
376 
377 class ARMExecutionDomainFix : public ExecutionDomainFix {
378 public:
379  static char ID;
380  ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
381  StringRef getPassName() const override {
382  return "ARM Execution Domain Fix";
383  }
384 };
386 
387 } // end anonymous namespace
388 
389 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
390  "ARM Execution Domain Fix", false, false)
392 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
393  "ARM Execution Domain Fix", false, false)
394 
396  return new ARMPassConfig(*this, PM);
397 }
398 
399 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
400  return getStandardCSEConfigForOpt(TM->getOptLevel());
401 }
402 
403 void ARMPassConfig::addIRPasses() {
404  if (TM->Options.ThreadModel == ThreadModel::Single)
405  addPass(createLowerAtomicPass());
406  else
407  addPass(createAtomicExpandPass());
408 
409  // Cmpxchg instructions are often used with a subsequent comparison to
410  // determine whether it succeeded. We can exploit existing control-flow in
411  // ldrex/strex loops to simplify this, but it needs tidying up.
412  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
414  SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
415  [this](const Function &F) {
416  const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
417  return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
418  }));
419 
422 
424 
425  // Run the parallel DSP pass.
426  if (getOptLevel() == CodeGenOpt::Aggressive)
427  addPass(createARMParallelDSPPass());
428 
429  // Match interleaved memory accesses to ldN/stN intrinsics.
430  if (TM->getOptLevel() != CodeGenOpt::None)
431  addPass(createInterleavedAccessPass());
432 
433  // Add Control Flow Guard checks.
434  if (TM->getTargetTriple().isOSWindows())
435  addPass(createCFGuardCheckPass());
436 }
437 
438 void ARMPassConfig::addCodeGenPrepare() {
439  if (getOptLevel() != CodeGenOpt::None)
440  addPass(createTypePromotionPass());
442 }
443 
444 bool ARMPassConfig::addPreISel() {
445  if ((TM->getOptLevel() != CodeGenOpt::None &&
448  // FIXME: This is using the thumb1 only constant value for
449  // maximal global offset for merging globals. We may want
450  // to look into using the old value for non-thumb1 code of
451  // 4095 based on the TargetMachine, but this starts to become
452  // tricky when doing code gen per function.
453  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
455  // Merging of extern globals is enabled by default on non-Mach-O as we
456  // expect it to be generally either beneficial or harmless. On Mach-O it
457  // is disabled as we emit the .subsections_via_symbols directive which
458  // means that merging extern globals is not safe.
459  bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
460  addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
461  MergeExternalByDefault));
462  }
463 
464  if (TM->getOptLevel() != CodeGenOpt::None) {
465  addPass(createHardwareLoopsPass());
466  addPass(createMVETailPredicationPass());
467  // FIXME: IR passes can delete address-taken basic blocks, deleting
468  // corresponding blockaddresses. ARMConstantPoolConstant holds references to
469  // address-taken basic blocks which can be invalidated if the function
470  // containing the blockaddress has already been codegen'd and the basic
471  // block is removed. Work around this by forcing all IR passes to run before
472  // any ISel takes place. We should have a more principled way of handling
473  // this. See D99707 for more details.
474  addPass(createBarrierNoopPass());
475  }
476 
477  return false;
478 }
479 
480 bool ARMPassConfig::addInstSelector() {
481  addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
482  return false;
483 }
484 
485 bool ARMPassConfig::addIRTranslator() {
486  addPass(new IRTranslator(getOptLevel()));
487  return false;
488 }
489 
490 bool ARMPassConfig::addLegalizeMachineIR() {
491  addPass(new Legalizer());
492  return false;
493 }
494 
495 bool ARMPassConfig::addRegBankSelect() {
496  addPass(new RegBankSelect());
497  return false;
498 }
499 
500 bool ARMPassConfig::addGlobalInstructionSelect() {
501  addPass(new InstructionSelect(getOptLevel()));
502  return false;
503 }
504 
505 void ARMPassConfig::addPreRegAlloc() {
506  if (getOptLevel() != CodeGenOpt::None) {
508 
509  addPass(createMLxExpansionPass());
510 
512  addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
513 
515  addPass(createA15SDOptimizerPass());
516  }
517 }
518 
519 void ARMPassConfig::addPreSched2() {
520  if (getOptLevel() != CodeGenOpt::None) {
523 
524  addPass(new ARMExecutionDomainFix());
525  addPass(createBreakFalseDeps());
526  }
527 
528  // Expand some pseudo instructions into multiple instructions to allow
529  // proper scheduling.
530  addPass(createARMExpandPseudoPass());
531 
532  if (getOptLevel() != CodeGenOpt::None) {
533  // When optimising for size, always run the Thumb2SizeReduction pass before
534  // IfConversion. Otherwise, check whether IT blocks are restricted
535  // (e.g. in v8, IfConversion depends on Thumb instruction widths)
536  addPass(createThumb2SizeReductionPass([this](const Function &F) {
537  return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
538  this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
539  }));
540 
541  addPass(createIfConverter([](const MachineFunction &MF) {
542  return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
543  }));
544  }
545  addPass(createThumb2ITBlockPass());
546 
547  // Add both scheduling passes to give the subtarget an opportunity to pick
548  // between them.
549  if (getOptLevel() != CodeGenOpt::None) {
550  addPass(&PostMachineSchedulerID);
551  addPass(&PostRASchedulerID);
552  }
553 
554  addPass(createMVEVPTBlockPass());
555  addPass(createARMIndirectThunks());
556  addPass(createARMSLSHardeningPass());
557 }
558 
559 void ARMPassConfig::addPreEmitPass() {
561 
562  // Constant island pass work on unbundled instructions.
563  addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
564  return MF.getSubtarget<ARMSubtarget>().isThumb2();
565  }));
566 
567  // Don't optimize barriers or block placement at -O0.
568  if (getOptLevel() != CodeGenOpt::None) {
569  addPass(createARMBlockPlacementPass());
571  }
572 }
573 
574 void ARMPassConfig::addPreEmitPass2() {
575  addPass(createARMBranchTargetsPass());
576  addPass(createARMConstantIslandPass());
578 
579  if (TM->getTargetTriple().isOSWindows()) {
580  // Identify valid longjmp targets for Windows Control Flow Guard.
581  addPass(createCFGuardLongjmpPass());
582  // Identify valid eh continuation targets for Windows EHCont Guard.
584  }
585 }
ARMSubtarget.h
llvm::initializeARMBlockPlacementPass
void initializeARMBlockPlacementPass(PassRegistry &)
llvm::initializeARMExpandPseudoPass
void initializeARMExpandPseudoPass(PassRegistry &)
llvm::ARMBaseTargetMachine::ARM_ABI_APCS
@ ARM_ABI_APCS
Definition: ARMTargetMachine.h:31
ABI
Generic address nodes are lowered to some combination of target independent and machine specific ABI
Definition: Relocation.txt:34
llvm::StringRef::startswith
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:285
EnableAtomicTidy
static cl::opt< bool > EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:169
ARMTargetInfo.h
Optional.h
llvm::EABI::GNU
@ GNU
llvm::initializeThumb2SizeReducePass
void initializeThumb2SizeReducePass(PassRegistry &)
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::ReachingDefAnalysis
This class provides the reaching def analysis.
Definition: ReachingDefAnalysis.h:69
ARMMCTargetDesc.h
CallLowering.h
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::getTheARMBETarget
Target & getTheARMBETarget()
Definition: ARMTargetInfo.cpp:17
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
Scalar.h
T
llvm::initializeARMBranchTargetsPass
void initializeARMBranchTargetsPass(PassRegistry &)
llvm::Function
Definition: Function.h:62
llvm::Attribute
Definition: Attributes.h:53
llvm::createARMLowOverheadLoopsPass
FunctionPass * createARMLowOverheadLoopsPass()
Definition: ARMLowOverheadLoops.cpp:1877
StringRef.h
llvm::createARMConstantIslandPass
FunctionPass * createARMConstantIslandPass()
createARMConstantIslandPass - returns an instance of the constpool island pass.
Definition: ARMConstantIslandPass.cpp:2550
Fix
arm execution domain ARM Execution Domain Fix
Definition: ARMTargetMachine.cpp:393
fix
arm execution domain fix
Definition: ARMTargetMachine.cpp:392
Pass.h
llvm::createCFGSimplificationPass
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
Definition: SimplifyCFGPass.cpp:426
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::initializeARMLowOverheadLoopsPass
void initializeARMLowOverheadLoopsPass(PassRegistry &)
llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS
@ ARM_ABI_AAPCS
Definition: ARMTargetMachine.h:32
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::Triple::MuslEABIHF
@ MuslEABIHF
Definition: Triple.h:226
RegisterBankInfo.h
llvm::EABI::Default
@ Default
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::TargetOptions::EABIVersion
EABI EABIVersion
EABIVersion - This flag specifies the EABI version.
Definition: TargetOptions.h:384
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1886
llvm::TargetMachine::setSupportsDefaultOutlining
void setSupportsDefaultOutlining(bool Enable)
Definition: TargetMachine.h:256
llvm::DataLayout::getManglingComponent
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:152
llvm::createMLxExpansionPass
FunctionPass * createMLxExpansionPass()
Definition: MLxExpansionPass.cpp:390
llvm::TargetOptions::TrapUnreachable
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Definition: TargetOptions.h:274
ARMMacroFusion.h
InstructionSelect.h
llvm::Reloc::ROPI_RWPI
@ ROPI_RWPI
Definition: CodeGen.h:22
EnableGlobalMerge
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("arm-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
llvm::createMVEVPTBlockPass
FunctionPass * createMVEVPTBlockPass()
createMVEVPTBlock - Returns an instance of the MVE VPT block insertion pass.
Definition: MVEVPTBlockPass.cpp:337
llvm::Optional< Reloc::Model >
llvm::createBarrierNoopPass
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
Definition: BarrierNoopPass.cpp:43
llvm::FloatABI::Hard
@ Hard
Definition: TargetOptions.h:31
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
llvm::ExecutionDomainFix
Definition: ExecutionDomainFix.h:116
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS16
@ ARM_ABI_AAPCS16
Definition: ARMTargetMachine.h:33
STLExtras.h
TargetParser.h
llvm::WinEH::EncodingType::ARM
@ ARM
Windows AXP64.
LegalizerInfo.h
llvm::ARMBETargetMachine::ARMBETargetMachine
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: ARMTargetMachine.cpp:321
llvm::Triple::GNUEABI
@ GNUEABI
Definition: Triple.h:216
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::ARMBaseTargetMachine::getSubtargetImpl
const ARMSubtarget * getSubtargetImpl() const =delete
llvm::ARMTTIImpl
Definition: ARMTargetTransformInfo.h:56
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::getTheARMLETarget
Target & getTheARMLETarget()
Definition: ARMTargetInfo.cpp:13
llvm::ARMBaseTargetMachine::~ARMBaseTargetMachine
~ARMBaseTargetMachine() override
CommandLine.h
llvm::MSP430Attrs::CodeModel
CodeModel
Definition: MSP430Attributes.h:37
llvm::createEHContGuardCatchretPass
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::ARMBaseTargetMachine::isTargetHardFloat
bool isTargetHardFloat() const
Definition: ARMTargetMachine.h:64
llvm::getTheThumbLETarget
Target & getTheThumbLETarget()
Definition: ARMTargetInfo.cpp:21
llvm::TargetMachine::setMachineOutliner
void setMachineOutliner(bool Enable)
Definition: TargetMachine.h:253
llvm::Triple::isOSDarwin
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS or watchOS).
Definition: Triple.h:468
llvm::Legalizer
Definition: Legalizer.h:30
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::initializeARMSLSHardeningPass
void initializeARMSLSHardeningPass(PassRegistry &)
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:704
llvm::initializeARMConstantIslandsPass
void initializeARMConstantIslandsPass(PassRegistry &)
llvm::createA15SDOptimizerPass
FunctionPass * createA15SDOptimizerPass()
Definition: A15SDOptimizer.cpp:682
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:481
llvm::initializeARMParallelDSPPass
void initializeARMParallelDSPPass(PassRegistry &)
llvm::initializeARMPreAllocLoadStoreOptPass
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &)
false
Definition: StackSlotColoring.cpp:142
llvm::FloatABI::Default
@ Default
Definition: TargetOptions.h:29
llvm::initializeARMExecutionDomainFixPass
void initializeARMExecutionDomainFixPass(PassRegistry &)
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::createGenericSchedPostRA
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Definition: MachineScheduler.cpp:3649
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:31
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1275
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:323
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::createARMBlockPlacementPass
FunctionPass * createARMBlockPlacementPass()
Definition: ARMBlockPlacement.cpp:56
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createARMBranchTargetsPass
FunctionPass * createARMBranchTargetsPass()
llvm::Triple::MuslEABI
@ MuslEABI
Definition: Triple.h:225
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:101
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:244
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
llvm::TargetOptions::FloatABIType
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line.
Definition: TargetOptions.h:359
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
InstructionSelector.h
computeTargetABI
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
Definition: ARMTargetMachine.cpp:119
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::cl::opt< bool >
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:99
llvm::cl::BOU_UNSET
@ BOU_UNSET
Definition: CommandLine.h:623
llvm::EABI::Unknown
@ Unknown
LLVMInitializeARMTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget()
Definition: ARMTargetMachine.cpp:83
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:152
CFGuard.h
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3492
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:136
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
ARMTargetObjectFile.h
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
IPO.h
llvm::createMVETPAndVPTOptimisationsPass
FunctionPass * createMVETPAndVPTOptimisationsPass()
createMVETPAndVPTOptimisationsPass
Definition: MVETPAndVPTOptimisationsPass.cpp:1078
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:125
llvm::createLowerAtomicPass
Pass * createLowerAtomicPass()
llvm::TargetOptions::NoTrapAfterNoreturn
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
Definition: TargetOptions.h:278
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::createARMExpandPseudoPass
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass.
Definition: ARMExpandPseudoInsts.cpp:3155
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:844
llvm::createUnpackMachineBundles
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
Definition: MachineInstrBundle.cpp:80
llvm::createMVEGatherScatterLoweringPass
Pass * createMVEGatherScatterLoweringPass()
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
TargetPassConfig.h
llvm::initializeARMLoadStoreOptPass
void initializeARMLoadStoreOptPass(PassRegistry &)
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:121
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:973
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::createTypePromotionPass
FunctionPass * createTypePromotionPass()
Create IR Type Promotion pass.
Definition: TypePromotion.cpp:959
llvm::createCFGuardCheckPass
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:300
llvm::Reloc::ROPI
@ ROPI
Definition: CodeGen.h:22
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
ARM.h
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::Reloc::DynamicNoPIC
@ DynamicNoPIC
Definition: CodeGen.h:22
llvm::MachineFunction
Definition: MachineFunction.h:241
EnableARMLoadStoreOpt
static cl::opt< bool > EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden, cl::desc("Enable ARM load/store optimization pass"), cl::init(true))
Triple.h
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::initializeMVETailPredicationPass
void initializeMVETailPredicationPass(PassRegistry &)
TargetOptions.h
llvm::Reloc::RWPI
@ RWPI
Definition: CodeGen.h:22
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:480
llvm::createARMSLSHardeningPass
FunctionPass * createARMSLSHardeningPass()
Definition: ARMSLSHardening.cpp:361
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::createHardwareLoopsPass
FunctionPass * createHardwareLoopsPass()
Create Hardware Loop pass.
Definition: HardwareLoops.cpp:546
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:74
llvm::createMVELaneInterleavingPass
Pass * createMVELaneInterleavingPass()
llvm::initializeMVEGatherScatterLoweringPass
void initializeMVEGatherScatterLoweringPass(PassRegistry &)
IRTranslator.h
llvm::createARMParallelDSPPass
Pass * createARMParallelDSPPass()
Definition: ARMParallelDSP.cpp:804
llvm::createThumb2SizeReductionPass
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
Definition: Thumb2SizeReduction.cpp:1157
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:498
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
llvm::createARMISelDag
FunctionPass * createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel)
createARMISelDag - This pass converts a legalized DAG into a ARM-specific DAG, ready for instruction ...
Definition: ARMISelDAGToDAG.cpp:5917
llvm::createARMIndirectThunks
FunctionPass * createARMIndirectThunks()
Definition: ARMSLSHardening.cpp:407
llvm::EABI::EABI5
@ EABI5
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:531
llvm::createInterleavedAccessPass
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
Definition: InterleavedAccessPass.cpp:145
Attributes.h
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: ARMTargetMachine.cpp:110
llvm::createBreakFalseDeps
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
Definition: BreakFalseDeps.cpp:105
llvm::ARMBaseTargetMachine::ARMBaseTargetMachine
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool isLittle)
Create an ARM architecture model.
Definition: ARMTargetMachine.cpp:213
computeDataLayout
static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
Definition: ARMTargetMachine.cpp:137
RegBankSelect.h
Function.h
llvm::createThumb2ITBlockPass
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
Definition: Thumb2ITBlockPass.cpp:310
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:406
llvm::ThreadModel::Single
@ Single
Definition: TargetOptions.h:57
llvm::ARMBaseTargetMachine::ARMABI
ARMABI
Definition: ARMTargetMachine.h:29
llvm::createIfConverter
FunctionPass * createIfConverter(std::function< bool(const MachineFunction &)> Ftor)
Definition: IfConversion.cpp:2366
llvm::initializeMVELaneInterleavingPass
void initializeMVELaneInterleavingPass(PassRegistry &)
llvm::createMVETailPredicationPass
Pass * createMVETailPredicationPass()
Definition: MVETailPredication.cpp:426
llvm::createGlobalMergePass
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
Definition: GlobalMerge.cpp:678
CodeGen.h
ExecutionDomainFix.h
llvm::ARMLETargetMachine::ARMLETargetMachine
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: ARMTargetMachine.cpp:313
llvm::cl::BOU_TRUE
@ BOU_TRUE
Definition: CommandLine.h:623
Legalizer.h
llvm::SimplifyCFGOptions
Definition: SimplifyCFGOptions.h:23
MachineScheduler.h
llvm::initializeMVEVPTBlockPass
void initializeMVEVPTBlockPass(PassRegistry &)
llvm::Registry
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:44
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:199
llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN
@ ARM_ABI_UNKNOWN
Definition: ARMTargetMachine.h:30
llvm::ARM::computeDefaultTargetABI
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
Definition: ARMTargetParser.cpp:606
llvm::ARMBaseTargetMachine::SubtargetMap
StringMap< std::unique_ptr< ARMSubtarget > > SubtargetMap
Definition: ARMTargetMachine.h:39
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
ARMTargetTransformInfo.h
llvm::ARMSubtarget::restrictIT
bool restrictIT() const
Definition: ARMSubtarget.h:869
llvm::FloatABI::Soft
@ Soft
Definition: TargetOptions.h:30
llvm::IRTranslator
Definition: IRTranslator.h:63
llvm::Triple::getEnvironment
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:328
DisableA15SDOptimization
static cl::opt< bool > DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, cl::desc("Inhibit optimization of S->D register accesses on A15"), cl::init(false))
llvm::ARMBaseTargetMachine::isLittle
bool isLittle
Definition: ARMTargetMachine.h:38
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::Triple::GNUEABIHF
@ GNUEABIHF
Definition: Triple.h:217
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::TargetMachine::setSupportsDebugEntryValues
void setSupportsDebugEntryValues(bool Enable)
Definition: TargetMachine.h:259
llvm::getTheThumbBETarget
Target & getTheThumbBETarget()
Definition: ARMTargetInfo.cpp:25
llvm::createARMOptimizeBarriersPass
FunctionPass * createARMOptimizeBarriersPass()
createARMOptimizeBarriersPass - Returns an instance of the remove double barriers pass.
Definition: ARMOptimizeBarriersPass.cpp:104
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:245
llvm::initializeMVETPAndVPTOptimisationsPass
void initializeMVETPAndVPTOptimisationsPass(PassRegistry &)
llvm::cl::desc
Definition: CommandLine.h:412
llvm::ARMBaseTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: ARMTargetMachine.cpp:309
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:390
execution
speculative execution
Definition: SpeculativeExecution.cpp:135
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
ARMTargetMachine.h
llvm::createARMLoadStoreOptimizationPass
FunctionPass * createARMLoadStoreOptimizationPass(bool PreAlloc=false)
Returns an instance of the load / store optimization pass.
Definition: ARMLoadStoreOptimizer.cpp:3015
MachineFunction.h
llvm::createARMMacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createARMMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createARMMacroFusionDAGMutation()); to ARMPassConfig::crea...
Definition: ARMMacroFusion.cpp:65
TargetRegistry.h
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:100
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix", "ARM Execution Domain Fix", false, false) INITIALIZE_PASS_END(ARMExecutionDomainFix
llvm::createCFGuardLongjmpPass
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38