LLVM  15.0.0git
ARMTargetMachine.cpp
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1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMMacroFusion.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
36 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/MC/TargetRegistry.h"
43 #include "llvm/Pass.h"
45 #include "llvm/Support/CodeGen.h"
52 #include "llvm/Transforms/IPO.h"
53 #include "llvm/Transforms/Scalar.h"
54 #include <cassert>
55 #include <memory>
56 #include <string>
57 
58 using namespace llvm;
59 
60 static cl::opt<bool>
61 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
62  cl::desc("Inhibit optimization of S->D register accesses on A15"),
63  cl::init(false));
64 
65 static cl::opt<bool>
66 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
67  cl::desc("Run SimplifyCFG after expanding atomic operations"
68  " to make use of cmpxchg flow-based information"),
69  cl::init(true));
70 
71 static cl::opt<bool>
72 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
73  cl::desc("Enable ARM load/store optimization pass"),
74  cl::init(true));
75 
76 // FIXME: Unify control over GlobalMerge.
78 EnableGlobalMerge("arm-global-merge", cl::Hidden,
79  cl::desc("Enable the global merge pass"));
80 
81 namespace llvm {
83 }
84 
86  // Register the target.
91 
111 }
112 
113 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
114  if (TT.isOSBinFormatMachO())
115  return std::make_unique<TargetLoweringObjectFileMachO>();
116  if (TT.isOSWindows())
117  return std::make_unique<TargetLoweringObjectFileCOFF>();
118  return std::make_unique<ARMElfTargetObjectFile>();
119 }
120 
123  const TargetOptions &Options) {
124  StringRef ABIName = Options.MCOptions.getABIName();
125 
126  if (ABIName.empty())
127  ABIName = ARM::computeDefaultTargetABI(TT, CPU);
128 
129  if (ABIName == "aapcs16")
131  else if (ABIName.startswith("aapcs"))
133  else if (ABIName.startswith("apcs"))
135 
136  llvm_unreachable("Unhandled/unknown ABI Name!");
138 }
139 
140 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
141  const TargetOptions &Options,
142  bool isLittle) {
143  auto ABI = computeTargetABI(TT, CPU, Options);
144  std::string Ret;
145 
146  if (isLittle)
147  // Little endian.
148  Ret += "e";
149  else
150  // Big endian.
151  Ret += "E";
152 
154 
155  // Pointers are 32 bits and aligned to 32 bits.
156  Ret += "-p:32:32";
157 
158  // Function pointers are aligned to 8 bits (because the LSB stores the
159  // ARM/Thumb state).
160  Ret += "-Fi8";
161 
162  // ABIs other than APCS have 64 bit integers with natural alignment.
164  Ret += "-i64:64";
165 
166  // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
167  // bits, others to 64 bits. We always try to align to 64 bits.
169  Ret += "-f64:32:64";
170 
171  // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
172  // to 64. We always ty to give them natural alignment.
174  Ret += "-v64:32:64-v128:32:128";
176  Ret += "-v128:64:128";
177 
178  // Try to align aggregates to 32 bits (the default is 64 bits, which has no
179  // particular hardware support on 32-bit ARM).
180  Ret += "-a:0:32";
181 
182  // Integer registers are 32 bits.
183  Ret += "-n32";
184 
185  // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
186  // aligned everywhere else.
187  if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
188  Ret += "-S128";
190  Ret += "-S64";
191  else
192  Ret += "-S32";
193 
194  return Ret;
195 }
196 
199  if (!RM)
200  // Default relocation model on Darwin is PIC.
201  return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
202 
203  if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
204  assert(TT.isOSBinFormatELF() &&
205  "ROPI/RWPI currently only supported for ELF");
206 
207  // DynamicNoPIC is only used on darwin.
208  if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
209  return Reloc::Static;
210 
211  return *RM;
212 }
213 
214 /// Create an ARM architecture model.
215 ///
217  StringRef CPU, StringRef FS,
218  const TargetOptions &Options,
221  CodeGenOpt::Level OL, bool isLittle)
222  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
223  CPU, FS, Options, getEffectiveRelocModel(TT, RM),
225  TargetABI(computeTargetABI(TT, CPU, Options)),
226  TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
227 
228  // Default to triple-appropriate float ABI
230  if (isTargetHardFloat())
231  this->Options.FloatABIType = FloatABI::Hard;
232  else
233  this->Options.FloatABIType = FloatABI::Soft;
234  }
235 
236  // Default to triple-appropriate EABI
239  // musl is compatible with glibc with regard to EABI version
245  this->Options.EABIVersion = EABI::GNU;
246  else
247  this->Options.EABIVersion = EABI::EABI5;
248  }
249 
250  if (TT.isOSBinFormatMachO()) {
251  this->Options.TrapUnreachable = true;
252  this->Options.NoTrapAfterNoreturn = true;
253  }
254 
255  // ARM supports the debug entry values.
257 
258  initAsmInfo();
259 
260  // ARM supports the MachineOutliner.
261  setMachineOutliner(true);
263 }
264 
266 
267 const ARMSubtarget *
269  Attribute CPUAttr = F.getFnAttribute("target-cpu");
270  Attribute FSAttr = F.getFnAttribute("target-features");
271 
272  std::string CPU =
273  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
274  std::string FS =
275  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
276 
277  // FIXME: This is related to the code below to reset the target options,
278  // we need to know whether or not the soft float flag is set on the
279  // function before we can generate a subtarget. We also need to use
280  // it as a key for the subtarget since that can be the only difference
281  // between two functions.
282  bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
283  // If the soft float attribute is set on the function turn on the soft float
284  // subtarget feature.
285  if (SoftFloat)
286  FS += FS.empty() ? "+soft-float" : ",+soft-float";
287 
288  // Use the optminsize to identify the subtarget, but don't use it in the
289  // feature string.
290  std::string Key = CPU + FS;
291  if (F.hasMinSize())
292  Key += "+minsize";
293 
294  auto &I = SubtargetMap[Key];
295  if (!I) {
296  // This needs to be done before we create a new subtarget since any
297  // creation will depend on the TM and the code generation flags on the
298  // function that reside in TargetOptions.
300  I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
301  F.hasMinSize());
302 
303  if (!I->isThumb() && !I->hasARMOps())
304  F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
305  "instructions, but the target does not support ARM mode execution.");
306  }
307 
308  return I.get();
309 }
310 
313  return TargetTransformInfo(ARMTTIImpl(this, F));
314 }
315 
317  StringRef CPU, StringRef FS,
318  const TargetOptions &Options,
321  CodeGenOpt::Level OL, bool JIT)
322  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
323 
325  StringRef CPU, StringRef FS,
326  const TargetOptions &Options,
329  CodeGenOpt::Level OL, bool JIT)
330  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
331 
332 namespace {
333 
334 /// ARM Code Generator Pass Configuration Options.
335 class ARMPassConfig : public TargetPassConfig {
336 public:
337  ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
338  : TargetPassConfig(TM, PM) {}
339 
340  ARMBaseTargetMachine &getARMTargetMachine() const {
341  return getTM<ARMBaseTargetMachine>();
342  }
343 
345  createMachineScheduler(MachineSchedContext *C) const override {
347  // add DAG Mutations here.
348  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
349  if (ST.hasFusion())
351  return DAG;
352  }
353 
355  createPostMachineScheduler(MachineSchedContext *C) const override {
357  // add DAG Mutations here.
358  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
359  if (ST.hasFusion())
361  return DAG;
362  }
363 
364  void addIRPasses() override;
365  void addCodeGenPrepare() override;
366  bool addPreISel() override;
367  bool addInstSelector() override;
368  bool addIRTranslator() override;
369  bool addLegalizeMachineIR() override;
370  bool addRegBankSelect() override;
371  bool addGlobalInstructionSelect() override;
372  void addPreRegAlloc() override;
373  void addPreSched2() override;
374  void addPreEmitPass() override;
375  void addPreEmitPass2() override;
376 
377  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
378 };
379 
380 class ARMExecutionDomainFix : public ExecutionDomainFix {
381 public:
382  static char ID;
383  ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
384  StringRef getPassName() const override {
385  return "ARM Execution Domain Fix";
386  }
387 };
389 
390 } // end anonymous namespace
391 
392 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
393  "ARM Execution Domain Fix", false, false)
395 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
396  "ARM Execution Domain Fix", false, false)
397 
399  return new ARMPassConfig(*this, PM);
400 }
401 
402 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
403  return getStandardCSEConfigForOpt(TM->getOptLevel());
404 }
405 
406 void ARMPassConfig::addIRPasses() {
407  if (TM->Options.ThreadModel == ThreadModel::Single)
408  addPass(createLowerAtomicPass());
409  else
410  addPass(createAtomicExpandPass());
411 
412  // Cmpxchg instructions are often used with a subsequent comparison to
413  // determine whether it succeeded. We can exploit existing control-flow in
414  // ldrex/strex loops to simplify this, but it needs tidying up.
415  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
417  SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
418  [this](const Function &F) {
419  const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
420  return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
421  }));
422 
425 
427 
428  // Run the parallel DSP pass.
429  if (getOptLevel() == CodeGenOpt::Aggressive)
430  addPass(createARMParallelDSPPass());
431 
432  // Match interleaved memory accesses to ldN/stN intrinsics.
433  if (TM->getOptLevel() != CodeGenOpt::None)
434  addPass(createInterleavedAccessPass());
435 
436  // Add Control Flow Guard checks.
437  if (TM->getTargetTriple().isOSWindows())
438  addPass(createCFGuardCheckPass());
439 
440  if (TM->Options.JMCInstrument)
441  addPass(createJMCInstrumenterPass());
442 }
443 
444 void ARMPassConfig::addCodeGenPrepare() {
445  if (getOptLevel() != CodeGenOpt::None)
446  addPass(createTypePromotionPass());
448 }
449 
450 bool ARMPassConfig::addPreISel() {
451  if ((TM->getOptLevel() != CodeGenOpt::None &&
454  // FIXME: This is using the thumb1 only constant value for
455  // maximal global offset for merging globals. We may want
456  // to look into using the old value for non-thumb1 code of
457  // 4095 based on the TargetMachine, but this starts to become
458  // tricky when doing code gen per function.
459  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
461  // Merging of extern globals is enabled by default on non-Mach-O as we
462  // expect it to be generally either beneficial or harmless. On Mach-O it
463  // is disabled as we emit the .subsections_via_symbols directive which
464  // means that merging extern globals is not safe.
465  bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
466  addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
467  MergeExternalByDefault));
468  }
469 
470  if (TM->getOptLevel() != CodeGenOpt::None) {
471  addPass(createHardwareLoopsPass());
472  addPass(createMVETailPredicationPass());
473  // FIXME: IR passes can delete address-taken basic blocks, deleting
474  // corresponding blockaddresses. ARMConstantPoolConstant holds references to
475  // address-taken basic blocks which can be invalidated if the function
476  // containing the blockaddress has already been codegen'd and the basic
477  // block is removed. Work around this by forcing all IR passes to run before
478  // any ISel takes place. We should have a more principled way of handling
479  // this. See D99707 for more details.
480  addPass(createBarrierNoopPass());
481  }
482 
483  return false;
484 }
485 
486 bool ARMPassConfig::addInstSelector() {
487  addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
488  return false;
489 }
490 
491 bool ARMPassConfig::addIRTranslator() {
492  addPass(new IRTranslator(getOptLevel()));
493  return false;
494 }
495 
496 bool ARMPassConfig::addLegalizeMachineIR() {
497  addPass(new Legalizer());
498  return false;
499 }
500 
501 bool ARMPassConfig::addRegBankSelect() {
502  addPass(new RegBankSelect());
503  return false;
504 }
505 
506 bool ARMPassConfig::addGlobalInstructionSelect() {
507  addPass(new InstructionSelect(getOptLevel()));
508  return false;
509 }
510 
511 void ARMPassConfig::addPreRegAlloc() {
512  if (getOptLevel() != CodeGenOpt::None) {
513  if (getOptLevel() == CodeGenOpt::Aggressive)
514  addPass(&MachinePipelinerID);
515 
517 
518  addPass(createMLxExpansionPass());
519 
521  addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
522 
524  addPass(createA15SDOptimizerPass());
525  }
526 }
527 
528 void ARMPassConfig::addPreSched2() {
529  if (getOptLevel() != CodeGenOpt::None) {
532 
533  addPass(new ARMExecutionDomainFix());
534  addPass(createBreakFalseDeps());
535  }
536 
537  // Expand some pseudo instructions into multiple instructions to allow
538  // proper scheduling.
539  addPass(createARMExpandPseudoPass());
540 
541  if (getOptLevel() != CodeGenOpt::None) {
542  // When optimising for size, always run the Thumb2SizeReduction pass before
543  // IfConversion. Otherwise, check whether IT blocks are restricted
544  // (e.g. in v8, IfConversion depends on Thumb instruction widths)
545  addPass(createThumb2SizeReductionPass([this](const Function &F) {
546  return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
547  this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
548  }));
549 
550  addPass(createIfConverter([](const MachineFunction &MF) {
551  return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
552  }));
553  }
554  addPass(createThumb2ITBlockPass());
555 
556  // Add both scheduling passes to give the subtarget an opportunity to pick
557  // between them.
558  if (getOptLevel() != CodeGenOpt::None) {
559  addPass(&PostMachineSchedulerID);
560  addPass(&PostRASchedulerID);
561  }
562 
563  addPass(createMVEVPTBlockPass());
564  addPass(createARMIndirectThunks());
565  addPass(createARMSLSHardeningPass());
566 }
567 
568 void ARMPassConfig::addPreEmitPass() {
570 
571  // Constant island pass work on unbundled instructions.
572  addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
573  return MF.getSubtarget<ARMSubtarget>().isThumb2();
574  }));
575 
576  // Don't optimize barriers or block placement at -O0.
577  if (getOptLevel() != CodeGenOpt::None) {
578  addPass(createARMBlockPlacementPass());
580  }
581 }
582 
583 void ARMPassConfig::addPreEmitPass2() {
584  // Inserts fixup instructions before unsafe AES operations. Instructions may
585  // be inserted at the start of blocks and at within blocks so this pass has to
586  // come before those below.
588  // Inserts BTIs at the start of functions and indirectly-called basic blocks,
589  // so passes cannot add to the start of basic blocks once this has run.
590  addPass(createARMBranchTargetsPass());
591  // Inserts Constant Islands. Block sizes cannot be increased after this point,
592  // as this may push the branch ranges and load offsets of accessing constant
593  // pools out of range..
594  addPass(createARMConstantIslandPass());
595  // Finalises Low-Overhead Loops. This replaces pseudo instructions with real
596  // instructions, but the pseudos all have conservative sizes so that block
597  // sizes will only be decreased by this pass.
599 
600  if (TM->getTargetTriple().isOSWindows()) {
601  // Identify valid longjmp targets for Windows Control Flow Guard.
602  addPass(createCFGuardLongjmpPass());
603  // Identify valid eh continuation targets for Windows EHCont Guard.
605  }
606 }
ARMSubtarget.h
llvm::initializeARMBlockPlacementPass
void initializeARMBlockPlacementPass(PassRegistry &)
llvm::createJMCInstrumenterPass
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
llvm::initializeARMExpandPseudoPass
void initializeARMExpandPseudoPass(PassRegistry &)
llvm::ARMBaseTargetMachine::ARM_ABI_APCS
@ ARM_ABI_APCS
Definition: ARMTargetMachine.h:31
ABI
Generic address nodes are lowered to some combination of target independent and machine specific ABI
Definition: Relocation.txt:34
llvm::StringRef::startswith
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:290
EnableAtomicTidy
static cl::opt< bool > EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:182
ARMTargetInfo.h
Optional.h
llvm::EABI::GNU
@ GNU
llvm::initializeThumb2SizeReducePass
void initializeThumb2SizeReducePass(PassRegistry &)
llvm::ReachingDefAnalysis
This class provides the reaching def analysis.
Definition: ReachingDefAnalysis.h:69
ARMMCTargetDesc.h
CallLowering.h
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::getTheARMBETarget
Target & getTheARMBETarget()
Definition: ARMTargetInfo.cpp:17
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
Scalar.h
T
llvm::initializeARMBranchTargetsPass
void initializeARMBranchTargetsPass(PassRegistry &)
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Definition: Function.h:60
llvm::Attribute
Definition: Attributes.h:65
llvm::createARMLowOverheadLoopsPass
FunctionPass * createARMLowOverheadLoopsPass()
Definition: ARMLowOverheadLoops.cpp:1879
StringRef.h
llvm::createARMConstantIslandPass
FunctionPass * createARMConstantIslandPass()
createARMConstantIslandPass - returns an instance of the constpool island pass.
Definition: ARMConstantIslandPass.cpp:2550
Fix
arm execution domain ARM Execution Domain Fix
Definition: ARMTargetMachine.cpp:396
fix
arm execution domain fix
Definition: ARMTargetMachine.cpp:395
Pass.h
llvm::createCFGSimplificationPass
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
Definition: SimplifyCFGPass.cpp:432
llvm::MachinePipelinerID
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
Definition: MachinePipeliner.cpp:182
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
llvm::ARMBaseTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: ARMTargetMachine.cpp:312
llvm::initializeARMLowOverheadLoopsPass
void initializeARMLowOverheadLoopsPass(PassRegistry &)
llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS
@ ARM_ABI_AAPCS
Definition: ARMTargetMachine.h:32
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::Triple::MuslEABIHF
@ MuslEABIHF
Definition: Triple.h:240
RegisterBankInfo.h
llvm::EABI::Default
@ Default
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::TargetOptions::EABIVersion
EABI EABIVersion
EABIVersion - This flag specifies the EABI version.
Definition: TargetOptions.h:406
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1886
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void setSupportsDefaultOutlining(bool Enable)
Definition: TargetMachine.h:256
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static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:153
llvm::createMLxExpansionPass
FunctionPass * createMLxExpansionPass()
Definition: MLxExpansionPass.cpp:390
llvm::TargetOptions::TrapUnreachable
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Definition: TargetOptions.h:280
ARMMacroFusion.h
InstructionSelect.h
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@ ROPI_RWPI
Definition: CodeGen.h:22
EnableGlobalMerge
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("arm-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
llvm::createMVEVPTBlockPass
FunctionPass * createMVEVPTBlockPass()
createMVEVPTBlock - Returns an instance of the MVE VPT block insertion pass.
Definition: MVEVPTBlockPass.cpp:336
llvm::Optional< Reloc::Model >
llvm::createBarrierNoopPass
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
Definition: BarrierNoopPass.cpp:43
llvm::FloatABI::Hard
@ Hard
Definition: TargetOptions.h:31
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
llvm::ExecutionDomainFix
Definition: ExecutionDomainFix.h:116
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS16
@ ARM_ABI_AAPCS16
Definition: ARMTargetMachine.h:33
STLExtras.h
TargetParser.h
llvm::WinEH::EncodingType::ARM
@ ARM
Windows AXP64.
LegalizerInfo.h
llvm::ARMBETargetMachine::ARMBETargetMachine
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: ARMTargetMachine.cpp:324
llvm::Triple::GNUEABI
@ GNUEABI
Definition: Triple.h:230
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::ARMBaseTargetMachine::getSubtargetImpl
const ARMSubtarget * getSubtargetImpl() const =delete
llvm::ARMTTIImpl
Definition: ARMTargetTransformInfo.h:56
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
CSEInfo.h
llvm::getTheARMLETarget
Target & getTheARMLETarget()
Definition: ARMTargetInfo.cpp:13
llvm::ARMBaseTargetMachine::~ARMBaseTargetMachine
~ARMBaseTargetMachine() override
CommandLine.h
llvm::MSP430Attrs::CodeModel
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Definition: MSP430Attributes.h:37
llvm::createEHContGuardCatchretPass
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::ARMBaseTargetMachine::isTargetHardFloat
bool isTargetHardFloat() const
Definition: ARMTargetMachine.h:64
llvm::getTheThumbLETarget
Target & getTheThumbLETarget()
Definition: ARMTargetInfo.cpp:21
llvm::TargetMachine::setMachineOutliner
void setMachineOutliner(bool Enable)
Definition: TargetMachine.h:253
llvm::Triple::isOSDarwin
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
Definition: Triple.h:508
llvm::Legalizer
Definition: Legalizer.h:36
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::initializeARMSLSHardeningPass
void initializeARMSLSHardeningPass(PassRegistry &)
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:710
llvm::initializeARMConstantIslandsPass
void initializeARMConstantIslandsPass(PassRegistry &)
llvm::createA15SDOptimizerPass
FunctionPass * createA15SDOptimizerPass()
Definition: A15SDOptimizer.cpp:681
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:486
llvm::initializeARMParallelDSPPass
void initializeARMParallelDSPPass(PassRegistry &)
llvm::initializeARMPreAllocLoadStoreOptPass
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &)
false
Definition: StackSlotColoring.cpp:141
llvm::FloatABI::Default
@ Default
Definition: TargetOptions.h:29
llvm::initializeARMExecutionDomainFixPass
void initializeARMExecutionDomainFixPass(PassRegistry &)
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::createGenericSchedPostRA
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Definition: MachineScheduler.cpp:3646
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1318
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:323
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::createARMBlockPlacementPass
FunctionPass * createARMBlockPlacementPass()
Definition: ARMBlockPlacement.cpp:57
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createARMBranchTargetsPass
FunctionPass * createARMBranchTargetsPass()
llvm::Triple::MuslEABI
@ MuslEABI
Definition: Triple.h:239
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:98
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:249
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
llvm::TargetOptions::FloatABIType
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line.
Definition: TargetOptions.h:381
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::createARMFixCortexA57AES1742098Pass
FunctionPass * createARMFixCortexA57AES1742098Pass()
Definition: ARMFixCortexA57AES1742098Pass.cpp:430
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
InstructionSelector.h
computeTargetABI
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
Definition: ARMTargetMachine.cpp:122
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::cl::opt< bool >
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
llvm::cl::BOU_UNSET
@ BOU_UNSET
Definition: CommandLine.h:611
llvm::EABI::Unknown
@ Unknown
LLVMInitializeARMTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget()
Definition: ARMTargetMachine.cpp:85
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
CFGuard.h
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3489
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
ARMTargetObjectFile.h
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
IPO.h
llvm::createMVETPAndVPTOptimisationsPass
FunctionPass * createMVETPAndVPTOptimisationsPass()
createMVETPAndVPTOptimisationsPass
Definition: MVETPAndVPTOptimisationsPass.cpp:1088
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:125
llvm::createLowerAtomicPass
Pass * createLowerAtomicPass()
llvm::TargetOptions::NoTrapAfterNoreturn
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
Definition: TargetOptions.h:284
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::createARMExpandPseudoPass
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass.
Definition: ARMExpandPseudoInsts.cpp:3168
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:853
llvm::createUnpackMachineBundles
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
Definition: MachineInstrBundle.cpp:81
llvm::createMVEGatherScatterLoweringPass
Pass * createMVEGatherScatterLoweringPass()
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
ARMTargetParser.h
TargetPassConfig.h
llvm::initializeARMLoadStoreOptPass
void initializeARMLoadStoreOptPass(PassRegistry &)
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:995
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::createTypePromotionPass
FunctionPass * createTypePromotionPass()
Create IR Type Promotion pass.
Definition: TypePromotion.cpp:954
llvm::X86AS::FS
@ FS
Definition: X86.h:192
llvm::createCFGuardCheckPass
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:300
llvm::Reloc::ROPI
@ ROPI
Definition: CodeGen.h:22
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
ARM.h
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::Reloc::DynamicNoPIC
@ DynamicNoPIC
Definition: CodeGen.h:22
llvm::MachineFunction
Definition: MachineFunction.h:257
EnableARMLoadStoreOpt
static cl::opt< bool > EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden, cl::desc("Enable ARM load/store optimization pass"), cl::init(true))
Triple.h
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::initializeMVETailPredicationPass
void initializeMVETailPredicationPass(PassRegistry &)
TargetOptions.h
llvm::Reloc::RWPI
@ RWPI
Definition: CodeGen.h:22
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:471
llvm::initializeARMFixCortexA57AES1742098Pass
void initializeARMFixCortexA57AES1742098Pass(PassRegistry &)
llvm::createARMSLSHardeningPass
FunctionPass * createARMSLSHardeningPass()
Definition: ARMSLSHardening.cpp:361
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::createHardwareLoopsPass
FunctionPass * createHardwareLoopsPass()
Create Hardware Loop pass.
Definition: HardwareLoops.cpp:543
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:75
llvm::createMVELaneInterleavingPass
Pass * createMVELaneInterleavingPass()
llvm::initializeMVEGatherScatterLoweringPass
void initializeMVEGatherScatterLoweringPass(PassRegistry &)
IRTranslator.h
llvm::createARMParallelDSPPass
Pass * createARMParallelDSPPass()
Definition: ARMParallelDSP.cpp:809
llvm::createThumb2SizeReductionPass
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
Definition: Thumb2SizeReduction.cpp:1165
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:506
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
llvm::createARMISelDag
FunctionPass * createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel)
createARMISelDag - This pass converts a legalized DAG into a ARM-specific DAG, ready for instruction ...
Definition: ARMISelDAGToDAG.cpp:5916
llvm::createARMIndirectThunks
FunctionPass * createARMIndirectThunks()
Definition: ARMSLSHardening.cpp:407
llvm::EABI::EABI5
@ EABI5
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:571
llvm::createInterleavedAccessPass
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
Definition: InterleavedAccessPass.cpp:145
Attributes.h
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: ARMTargetMachine.cpp:113
llvm::createBreakFalseDeps
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
Definition: BreakFalseDeps.cpp:107
llvm::ARMBaseTargetMachine::ARMBaseTargetMachine
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool isLittle)
Create an ARM architecture model.
Definition: ARMTargetMachine.cpp:216
computeDataLayout
static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
Definition: ARMTargetMachine.cpp:140
RegBankSelect.h
Function.h
llvm::createThumb2ITBlockPass
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
Definition: Thumb2ITBlockPass.cpp:310
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:414
llvm::ThreadModel::Single
@ Single
Definition: TargetOptions.h:57
llvm::ARMBaseTargetMachine::ARMABI
ARMABI
Definition: ARMTargetMachine.h:29
llvm::createIfConverter
FunctionPass * createIfConverter(std::function< bool(const MachineFunction &)> Ftor)
Definition: IfConversion.cpp:2364
llvm::initializeMVELaneInterleavingPass
void initializeMVELaneInterleavingPass(PassRegistry &)
llvm::createMVETailPredicationPass
Pass * createMVETailPredicationPass()
Definition: MVETailPredication.cpp:426
llvm::createGlobalMergePass
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
Definition: GlobalMerge.cpp:692
CodeGen.h
ExecutionDomainFix.h
llvm::ARMLETargetMachine::ARMLETargetMachine
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: ARMTargetMachine.cpp:316
llvm::cl::BOU_TRUE
@ BOU_TRUE
Definition: CommandLine.h:611
Legalizer.h
llvm::SimplifyCFGOptions
Definition: SimplifyCFGOptions.h:23
MachineScheduler.h
llvm::initializeMVEVPTBlockPass
void initializeMVEVPTBlockPass(PassRegistry &)
llvm::Registry
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:44
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:197
llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN
@ ARM_ABI_UNKNOWN
Definition: ARMTargetMachine.h:30
llvm::ARM::computeDefaultTargetABI
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
Definition: ARMTargetParser.cpp:606
llvm::ARMBaseTargetMachine::SubtargetMap
StringMap< std::unique_ptr< ARMSubtarget > > SubtargetMap
Definition: ARMTargetMachine.h:39
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
ARMTargetTransformInfo.h
llvm::ARMSubtarget::restrictIT
bool restrictIT() const
Definition: ARMSubtarget.h:461
llvm::FloatABI::Soft
@ Soft
Definition: TargetOptions.h:30
llvm::IRTranslator
Definition: IRTranslator.h:62
llvm::Triple::getEnvironment
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:362
DisableA15SDOptimization
static cl::opt< bool > DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, cl::desc("Inhibit optimization of S->D register accesses on A15"), cl::init(false))
llvm::ARMBaseTargetMachine::isLittle
bool isLittle
Definition: ARMTargetMachine.h:38
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::Triple::GNUEABIHF
@ GNUEABIHF
Definition: Triple.h:231
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::TargetMachine::setSupportsDebugEntryValues
void setSupportsDebugEntryValues(bool Enable)
Definition: TargetMachine.h:259
llvm::getTheThumbBETarget
Target & getTheThumbBETarget()
Definition: ARMTargetInfo.cpp:25
llvm::createARMOptimizeBarriersPass
FunctionPass * createARMOptimizeBarriersPass()
createARMOptimizeBarriersPass - Returns an instance of the remove double barriers pass.
Definition: ARMOptimizeBarriersPass.cpp:104
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:244
llvm::initializeMVETPAndVPTOptimisationsPass
void initializeMVETPAndVPTOptimisationsPass(PassRegistry &)
llvm::cl::desc
Definition: CommandLine.h:405
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:390
execution
speculative execution
Definition: SpeculativeExecution.cpp:135
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
ARMTargetMachine.h
llvm::createARMLoadStoreOptimizationPass
FunctionPass * createARMLoadStoreOptimizationPass(bool PreAlloc=false)
Returns an instance of the load / store optimization pass.
Definition: ARMLoadStoreOptimizer.cpp:3019
MachineFunction.h
llvm::createARMMacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createARMMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createARMMacroFusionDAGMutation()); to ARMPassConfig::crea...
Definition: ARMMacroFusion.cpp:65
TargetRegistry.h
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:97
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix", "ARM Execution Domain Fix", false, false) INITIALIZE_PASS_END(ARMExecutionDomainFix
llvm::createCFGuardLongjmpPass
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38