Go to the documentation of this file.
62 cl::desc(
"Inhibit optimization of S->D register accesses on A15"),
67 cl::desc(
"Run SimplifyCFG after expanding atomic operations"
68 " to make use of cmpxchg flow-based information"),
73 cl::desc(
"Enable ARM load/store optimization pass"),
79 cl::desc(
"Enable the global merge pass"));
114 if (TT.isOSBinFormatMachO())
115 return std::make_unique<TargetLoweringObjectFileMachO>();
116 if (TT.isOSWindows())
117 return std::make_unique<TargetLoweringObjectFileCOFF>();
118 return std::make_unique<ARMElfTargetObjectFile>();
129 if (ABIName ==
"aapcs16")
174 Ret +=
"-v64:32:64-v128:32:128";
176 Ret +=
"-v128:64:128";
204 assert(TT.isOSBinFormatELF() &&
205 "ROPI/RWPI currently only supported for ELF");
226 TLOF(
createTLOF(getTargetTriple())), isLittle(isLittle) {
250 if (TT.isOSBinFormatMachO()) {
269 Attribute CPUAttr =
F.getFnAttribute(
"target-cpu");
270 Attribute FSAttr =
F.getFnAttribute(
"target-features");
282 bool SoftFloat =
F.getFnAttribute(
"use-soft-float").getValueAsBool();
286 FS +=
FS.empty() ?
"+soft-float" :
",+soft-float";
290 std::string
Key = CPU +
FS;
303 if (!
I->isThumb() && !
I->hasARMOps())
304 F.getContext().emitError(
"Function '" +
F.getName() +
"' uses ARM "
305 "instructions, but the target does not support ARM mode execution.");
341 return getTM<ARMBaseTargetMachine>();
364 void addIRPasses()
override;
365 void addCodeGenPrepare()
override;
366 bool addPreISel()
override;
367 bool addInstSelector()
override;
368 bool addIRTranslator()
override;
369 bool addLegalizeMachineIR()
override;
370 bool addRegBankSelect()
override;
371 bool addGlobalInstructionSelect()
override;
372 void addPreRegAlloc()
override;
373 void addPreSched2()
override;
374 void addPreEmitPass()
override;
375 void addPreEmitPass2()
override;
377 std::unique_ptr<CSEConfigBase> getCSEConfig()
const override;
385 return "ARM Execution Domain Fix";
393 "ARM Execution Domain Fix",
false,
false)
399 return new ARMPassConfig(*
this, PM);
402 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig()
const {
406 void ARMPassConfig::addIRPasses() {
420 return ST.hasAnyDataBarrier() && !
ST.isThumb1Only();
437 if (
TM->getTargetTriple().isOSWindows())
440 if (
TM->Options.JMCInstrument)
444 void ARMPassConfig::addCodeGenPrepare() {
450 bool ARMPassConfig::addPreISel() {
465 bool MergeExternalByDefault = !
TM->getTargetTriple().isOSBinFormatMachO();
467 MergeExternalByDefault));
486 bool ARMPassConfig::addInstSelector() {
491 bool ARMPassConfig::addIRTranslator() {
496 bool ARMPassConfig::addLegalizeMachineIR() {
501 bool ARMPassConfig::addRegBankSelect() {
506 bool ARMPassConfig::addGlobalInstructionSelect() {
511 void ARMPassConfig::addPreRegAlloc() {
528 void ARMPassConfig::addPreSched2() {
533 addPass(
new ARMExecutionDomainFix());
568 void ARMPassConfig::addPreEmitPass() {
583 void ARMPassConfig::addPreEmitPass2() {
600 if (
TM->getTargetTriple().isOSWindows()) {
void initializeARMBlockPlacementPass(PassRegistry &)
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
void initializeARMExpandPseudoPass(PassRegistry &)
Generic address nodes are lowered to some combination of target independent and machine specific ABI
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
static cl::opt< bool > EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
This is an optimization pass for GlobalISel generic memory operations.
bool isValid() const
Return true if the attribute is any kind of attribute.
void initializeThumb2SizeReducePass(PassRegistry &)
This class provides the reaching def analysis.
Target & getTheARMBETarget()
void initializeARMBranchTargetsPass(PassRegistry &)
FunctionPass * createARMLowOverheadLoopsPass()
FunctionPass * createARMConstantIslandPass()
createARMConstantIslandPass - returns an instance of the constpool island pass.
arm execution domain ARM Execution Domain Fix
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
Target - Wrapper for Target specific information.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
void initializeARMLowOverheadLoopsPass(PassRegistry &)
Triple - Helper class for working with autoconf configuration names.
EABI EABIVersion
EABIVersion - This flag specifies the EABI version.
void setSupportsDefaultOutlining(bool Enable)
static const char * getManglingComponent(const Triple &T)
FunctionPass * createMLxExpansionPass()
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("arm-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
FunctionPass * createMVEVPTBlockPass()
createMVEVPTBlock - Returns an instance of the MVE VPT block insertion pass.
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
const ARMSubtarget * getSubtargetImpl() const =delete
Target & getTheARMLETarget()
~ARMBaseTargetMachine() override
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool isTargetHardFloat() const
Target & getTheThumbLETarget()
void setMachineOutliner(bool Enable)
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
(vector float) vec_cmpeq(*A, *B) C
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
void initializeARMSLSHardeningPass(PassRegistry &)
void initializeARMConstantIslandsPass(PassRegistry &)
FunctionPass * createA15SDOptimizerPass()
void initializeARMParallelDSPPass(PassRegistry &)
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &)
void initializeARMExecutionDomainFixPass(PassRegistry &)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
This pass is responsible for selecting generic machine instructions to target-specific instructions.
RegisterTargetMachine - Helper template for registering a target machine implementation,...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
FunctionPass * createARMBlockPlacementPass()
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
FunctionPass * createARMBranchTargetsPass()
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
StringRef getValueAsString() const
Return the attribute's value as a string.
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
FunctionPass * createARMFixCortexA57AES1742098Pass()
Target-Independent Code Generator Pass Configuration Options.
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget()
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
#define LLVM_EXTERNAL_VISIBILITY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
FunctionPass * createMVETPAndVPTOptimisationsPass()
createMVETPAndVPTOptimisationsPass
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Pass * createLowerAtomicPass()
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
Pass * createMVEGatherScatterLoweringPass()
initializer< Ty > init(const Ty &Val)
void initializeARMLoadStoreOptPass(PassRegistry &)
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass * createTypePromotionPass()
Create IR Type Promotion pass.
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
static cl::opt< bool > EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden, cl::desc("Enable ARM load/store optimization pass"), cl::init(true))
void initializeMVETailPredicationPass(PassRegistry &)
void initializeARMFixCortexA57AES1742098Pass(PassRegistry &)
FunctionPass * createARMSLSHardeningPass()
StringRef - Represent a constant reference to a string, i.e.
FunctionPass * createHardwareLoopsPass()
Create Hardware Loop pass.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Pass * createMVELaneInterleavingPass()
void initializeMVEGatherScatterLoweringPass(PassRegistry &)
Pass * createARMParallelDSPPass()
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
FunctionPass * createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel)
createARMISelDag - This pass converts a legalized DAG into a ARM-specific DAG, ready for instruction ...
FunctionPass * createARMIndirectThunks()
bool isOSWindows() const
Tests whether the OS is Windows.
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool isLittle)
Create an ARM architecture model.
static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
FunctionPass * createIfConverter(std::function< bool(const MachineFunction &)> Ftor)
void initializeMVELaneInterleavingPass(PassRegistry &)
Pass * createMVETailPredicationPass()
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
void initializeMVEVPTBlockPass(PassRegistry &)
A global registry used in conjunction with static constructors to make pluggable components (like tar...
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
StringMap< std::unique_ptr< ARMSubtarget > > SubtargetMap
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
static cl::opt< bool > DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, cl::desc("Inhibit optimization of S->D register accesses on A15"), cl::init(false))
const char LLVMTargetMachineRef TM
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
void setSupportsDebugEntryValues(bool Enable)
Target & getTheThumbBETarget()
FunctionPass * createARMOptimizeBarriersPass()
createARMOptimizeBarriersPass - Returns an instance of the remove double barriers pass.
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
void initializeMVETPAndVPTOptimisationsPass(PassRegistry &)
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
A ScheduleDAG for scheduling lists of MachineInstr.
FunctionPass * createARMLoadStoreOptimizationPass(bool PreAlloc=false)
Returns an instance of the load / store optimization pass.
std::unique_ptr< ScheduleDAGMutation > createARMMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createARMMacroFusionDAGMutation()); to ARMPassConfig::crea...
INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix", "ARM Execution Domain Fix", false, false) INITIALIZE_PASS_END(ARMExecutionDomainFix
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.