LLVM 19.0.0git
ARMTargetMachine.cpp
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1//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "ARMTargetMachine.h"
13#include "ARM.h"
15#include "ARMMacroFusion.h"
16#include "ARMSubtarget.h"
17#include "ARMTargetObjectFile.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/ADT/StringRef.h"
36#include "llvm/CodeGen/Passes.h"
39#include "llvm/IR/Attributes.h"
40#include "llvm/IR/DataLayout.h"
41#include "llvm/IR/Function.h"
43#include "llvm/Pass.h"
53#include "llvm/Transforms/IPO.h"
55#include <cassert>
56#include <memory>
57#include <optional>
58#include <string>
59
60using namespace llvm;
61
62static cl::opt<bool>
63DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
64 cl::desc("Inhibit optimization of S->D register accesses on A15"),
65 cl::init(false));
66
67static cl::opt<bool>
68EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
69 cl::desc("Run SimplifyCFG after expanding atomic operations"
70 " to make use of cmpxchg flow-based information"),
71 cl::init(true));
72
73static cl::opt<bool>
74EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
75 cl::desc("Enable ARM load/store optimization pass"),
76 cl::init(true));
77
78// FIXME: Unify control over GlobalMerge.
80EnableGlobalMerge("arm-global-merge", cl::Hidden,
81 cl::desc("Enable the global merge pass"));
82
83namespace llvm {
85}
86
88 // Register the target.
93
114}
115
116static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
117 if (TT.isOSBinFormatMachO())
118 return std::make_unique<TargetLoweringObjectFileMachO>();
119 if (TT.isOSWindows())
120 return std::make_unique<TargetLoweringObjectFileCOFF>();
121 return std::make_unique<ARMElfTargetObjectFile>();
122}
123
126 const TargetOptions &Options) {
127 StringRef ABIName = Options.MCOptions.getABIName();
128
129 if (ABIName.empty())
130 ABIName = ARM::computeDefaultTargetABI(TT, CPU);
131
132 if (ABIName == "aapcs16")
134 else if (ABIName.starts_with("aapcs"))
136 else if (ABIName.starts_with("apcs"))
138
139 llvm_unreachable("Unhandled/unknown ABI Name!");
141}
142
143static std::string computeDataLayout(const Triple &TT, StringRef CPU,
144 const TargetOptions &Options,
145 bool isLittle) {
146 auto ABI = computeTargetABI(TT, CPU, Options);
147 std::string Ret;
148
149 if (isLittle)
150 // Little endian.
151 Ret += "e";
152 else
153 // Big endian.
154 Ret += "E";
155
157
158 // Pointers are 32 bits and aligned to 32 bits.
159 Ret += "-p:32:32";
160
161 // Function pointers are aligned to 8 bits (because the LSB stores the
162 // ARM/Thumb state).
163 Ret += "-Fi8";
164
165 // ABIs other than APCS have 64 bit integers with natural alignment.
167 Ret += "-i64:64";
168
169 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
170 // bits, others to 64 bits. We always try to align to 64 bits.
172 Ret += "-f64:32:64";
173
174 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
175 // to 64. We always ty to give them natural alignment.
177 Ret += "-v64:32:64-v128:32:128";
179 Ret += "-v128:64:128";
180
181 // Try to align aggregates to 32 bits (the default is 64 bits, which has no
182 // particular hardware support on 32-bit ARM).
183 Ret += "-a:0:32";
184
185 // Integer registers are 32 bits.
186 Ret += "-n32";
187
188 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
189 // aligned everywhere else.
190 if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
191 Ret += "-S128";
193 Ret += "-S64";
194 else
195 Ret += "-S32";
196
197 return Ret;
198}
199
201 std::optional<Reloc::Model> RM) {
202 if (!RM)
203 // Default relocation model on Darwin is PIC.
204 return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
205
206 if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
207 assert(TT.isOSBinFormatELF() &&
208 "ROPI/RWPI currently only supported for ELF");
209
210 // DynamicNoPIC is only used on darwin.
211 if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
212 return Reloc::Static;
213
214 return *RM;
215}
216
217/// Create an ARM architecture model.
218///
220 StringRef CPU, StringRef FS,
221 const TargetOptions &Options,
222 std::optional<Reloc::Model> RM,
223 std::optional<CodeModel::Model> CM,
224 CodeGenOptLevel OL, bool isLittle)
225 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
226 CPU, FS, Options, getEffectiveRelocModel(TT, RM),
227 getEffectiveCodeModel(CM, CodeModel::Small), OL),
228 TargetABI(computeTargetABI(TT, CPU, Options)),
229 TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
230
231 // Default to triple-appropriate float ABI
233 if (isTargetHardFloat())
234 this->Options.FloatABIType = FloatABI::Hard;
235 else
236 this->Options.FloatABIType = FloatABI::Soft;
237 }
238
239 // Default to triple-appropriate EABI
242 // musl is compatible with glibc with regard to EABI version
249 this->Options.EABIVersion = EABI::GNU;
250 else
251 this->Options.EABIVersion = EABI::EABI5;
252 }
253
254 if (TT.isOSBinFormatMachO()) {
255 this->Options.TrapUnreachable = true;
256 this->Options.NoTrapAfterNoreturn = true;
257 }
258
259 // ARM supports the debug entry values.
261
262 initAsmInfo();
263
264 // ARM supports the MachineOutliner.
265 setMachineOutliner(true);
267}
268
270
272 BumpPtrAllocator &Allocator, const Function &F,
273 const TargetSubtargetInfo *STI) const {
274 return ARMFunctionInfo::create<ARMFunctionInfo>(
275 Allocator, F, static_cast<const ARMSubtarget *>(STI));
276}
277
278const ARMSubtarget *
280 Attribute CPUAttr = F.getFnAttribute("target-cpu");
281 Attribute FSAttr = F.getFnAttribute("target-features");
282
283 std::string CPU =
284 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
285 std::string FS =
286 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
287
288 // FIXME: This is related to the code below to reset the target options,
289 // we need to know whether or not the soft float flag is set on the
290 // function before we can generate a subtarget. We also need to use
291 // it as a key for the subtarget since that can be the only difference
292 // between two functions.
293 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
294 // If the soft float attribute is set on the function turn on the soft float
295 // subtarget feature.
296 if (SoftFloat)
297 FS += FS.empty() ? "+soft-float" : ",+soft-float";
298
299 // Use the optminsize to identify the subtarget, but don't use it in the
300 // feature string.
301 std::string Key = CPU + FS;
302 if (F.hasMinSize())
303 Key += "+minsize";
304
305 auto &I = SubtargetMap[Key];
306 if (!I) {
307 // This needs to be done before we create a new subtarget since any
308 // creation will depend on the TM and the code generation flags on the
309 // function that reside in TargetOptions.
311 I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
312 F.hasMinSize());
313
314 if (!I->isThumb() && !I->hasARMOps())
315 F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
316 "instructions, but the target does not support ARM mode execution.");
317 }
318
319 return I.get();
320}
321
324 return TargetTransformInfo(ARMTTIImpl(this, F));
325}
326
328 StringRef CPU, StringRef FS,
329 const TargetOptions &Options,
330 std::optional<Reloc::Model> RM,
331 std::optional<CodeModel::Model> CM,
332 CodeGenOptLevel OL, bool JIT)
333 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
334
336 StringRef CPU, StringRef FS,
337 const TargetOptions &Options,
338 std::optional<Reloc::Model> RM,
339 std::optional<CodeModel::Model> CM,
340 CodeGenOptLevel OL, bool JIT)
341 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
342
343namespace {
344
345/// ARM Code Generator Pass Configuration Options.
346class ARMPassConfig : public TargetPassConfig {
347public:
348 ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
349 : TargetPassConfig(TM, PM) {}
350
351 ARMBaseTargetMachine &getARMTargetMachine() const {
352 return getTM<ARMBaseTargetMachine>();
353 }
354
356 createMachineScheduler(MachineSchedContext *C) const override {
358 // add DAG Mutations here.
359 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
360 if (ST.hasFusion())
362 return DAG;
363 }
364
366 createPostMachineScheduler(MachineSchedContext *C) const override {
368 // add DAG Mutations here.
369 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
370 if (ST.hasFusion())
372 return DAG;
373 }
374
375 void addIRPasses() override;
376 void addCodeGenPrepare() override;
377 bool addPreISel() override;
378 bool addInstSelector() override;
379 bool addIRTranslator() override;
380 bool addLegalizeMachineIR() override;
381 bool addRegBankSelect() override;
382 bool addGlobalInstructionSelect() override;
383 void addPreRegAlloc() override;
384 void addPreSched2() override;
385 void addPreEmitPass() override;
386 void addPreEmitPass2() override;
387
388 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
389};
390
391class ARMExecutionDomainFix : public ExecutionDomainFix {
392public:
393 static char ID;
394 ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
395 StringRef getPassName() const override {
396 return "ARM Execution Domain Fix";
397 }
398};
399char ARMExecutionDomainFix::ID;
400
401} // end anonymous namespace
402
403INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
404 "ARM Execution Domain Fix", false, false)
406INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
407 "ARM Execution Domain Fix", false, false)
408
410 return new ARMPassConfig(*this, PM);
411}
412
413std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
414 return getStandardCSEConfigForOpt(TM->getOptLevel());
415}
416
417void ARMPassConfig::addIRPasses() {
418 if (TM->Options.ThreadModel == ThreadModel::Single)
419 addPass(createLowerAtomicPass());
420 else
422
423 // Cmpxchg instructions are often used with a subsequent comparison to
424 // determine whether it succeeded. We can exploit existing control-flow in
425 // ldrex/strex loops to simplify this, but it needs tidying up.
426 if (TM->getOptLevel() != CodeGenOptLevel::None && EnableAtomicTidy)
428 SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
429 [this](const Function &F) {
430 const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
431 return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
432 }));
433
436
438
439 // Run the parallel DSP pass.
440 if (getOptLevel() == CodeGenOptLevel::Aggressive)
441 addPass(createARMParallelDSPPass());
442
443 // Match complex arithmetic patterns
444 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
446
447 // Match interleaved memory accesses to ldN/stN intrinsics.
448 if (TM->getOptLevel() != CodeGenOptLevel::None)
450
451 // Add Control Flow Guard checks.
452 if (TM->getTargetTriple().isOSWindows())
453 addPass(createCFGuardCheckPass());
454
455 if (TM->Options.JMCInstrument)
456 addPass(createJMCInstrumenterPass());
457}
458
459void ARMPassConfig::addCodeGenPrepare() {
460 if (getOptLevel() != CodeGenOptLevel::None)
463}
464
465bool ARMPassConfig::addPreISel() {
466 if ((TM->getOptLevel() != CodeGenOptLevel::None &&
469 // FIXME: This is using the thumb1 only constant value for
470 // maximal global offset for merging globals. We may want
471 // to look into using the old value for non-thumb1 code of
472 // 4095 based on the TargetMachine, but this starts to become
473 // tricky when doing code gen per function.
474 bool OnlyOptimizeForSize =
475 (TM->getOptLevel() < CodeGenOptLevel::Aggressive) &&
477 // Merging of extern globals is enabled by default on non-Mach-O as we
478 // expect it to be generally either beneficial or harmless. On Mach-O it
479 // is disabled as we emit the .subsections_via_symbols directive which
480 // means that merging extern globals is not safe.
481 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
482 addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
483 MergeExternalByDefault));
484 }
485
486 if (TM->getOptLevel() != CodeGenOptLevel::None) {
489 // FIXME: IR passes can delete address-taken basic blocks, deleting
490 // corresponding blockaddresses. ARMConstantPoolConstant holds references to
491 // address-taken basic blocks which can be invalidated if the function
492 // containing the blockaddress has already been codegen'd and the basic
493 // block is removed. Work around this by forcing all IR passes to run before
494 // any ISel takes place. We should have a more principled way of handling
495 // this. See D99707 for more details.
496 addPass(createBarrierNoopPass());
497 }
498
499 return false;
500}
501
502bool ARMPassConfig::addInstSelector() {
503 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
504 return false;
505}
506
507bool ARMPassConfig::addIRTranslator() {
508 addPass(new IRTranslator(getOptLevel()));
509 return false;
510}
511
512bool ARMPassConfig::addLegalizeMachineIR() {
513 addPass(new Legalizer());
514 return false;
515}
516
517bool ARMPassConfig::addRegBankSelect() {
518 addPass(new RegBankSelect());
519 return false;
520}
521
522bool ARMPassConfig::addGlobalInstructionSelect() {
523 addPass(new InstructionSelect(getOptLevel()));
524 return false;
525}
526
527void ARMPassConfig::addPreRegAlloc() {
528 if (getOptLevel() != CodeGenOptLevel::None) {
529 if (getOptLevel() == CodeGenOptLevel::Aggressive)
530 addPass(&MachinePipelinerID);
531
533
534 addPass(createMLxExpansionPass());
535
537 addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
538
540 addPass(createA15SDOptimizerPass());
541 }
542}
543
544void ARMPassConfig::addPreSched2() {
545 if (getOptLevel() != CodeGenOptLevel::None) {
548
549 addPass(new ARMExecutionDomainFix());
550 addPass(createBreakFalseDeps());
551 }
552
553 // Expand some pseudo instructions into multiple instructions to allow
554 // proper scheduling.
555 addPass(createARMExpandPseudoPass());
556
557 if (getOptLevel() != CodeGenOptLevel::None) {
558 // When optimising for size, always run the Thumb2SizeReduction pass before
559 // IfConversion. Otherwise, check whether IT blocks are restricted
560 // (e.g. in v8, IfConversion depends on Thumb instruction widths)
561 addPass(createThumb2SizeReductionPass([this](const Function &F) {
562 return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
563 this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
564 }));
565
566 addPass(createIfConverter([](const MachineFunction &MF) {
567 return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
568 }));
569 }
570 addPass(createThumb2ITBlockPass());
571
572 // Add both scheduling passes to give the subtarget an opportunity to pick
573 // between them.
574 if (getOptLevel() != CodeGenOptLevel::None) {
575 addPass(&PostMachineSchedulerID);
576 addPass(&PostRASchedulerID);
577 }
578
579 addPass(createMVEVPTBlockPass());
580 addPass(createARMIndirectThunks());
581 addPass(createARMSLSHardeningPass());
582}
583
584void ARMPassConfig::addPreEmitPass() {
586
587 // Constant island pass work on unbundled instructions.
588 addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
589 return MF.getSubtarget<ARMSubtarget>().isThumb2();
590 }));
591
592 // Don't optimize barriers or block placement at -O0.
593 if (getOptLevel() != CodeGenOptLevel::None) {
596 }
597}
598
599void ARMPassConfig::addPreEmitPass2() {
600 // Inserts fixup instructions before unsafe AES operations. Instructions may
601 // be inserted at the start of blocks and at within blocks so this pass has to
602 // come before those below.
604 // Inserts BTIs at the start of functions and indirectly-called basic blocks,
605 // so passes cannot add to the start of basic blocks once this has run.
607 // Inserts Constant Islands. Block sizes cannot be increased after this point,
608 // as this may push the branch ranges and load offsets of accessing constant
609 // pools out of range..
611 // Finalises Low-Overhead Loops. This replaces pseudo instructions with real
612 // instructions, but the pseudos all have conservative sizes so that block
613 // sizes will only be decreased by this pass.
615
616 if (TM->getTargetTriple().isOSWindows()) {
617 // Identify valid longjmp targets for Windows Control Flow Guard.
618 addPass(createCFGuardLongjmpPass());
619 // Identify valid eh continuation targets for Windows EHCont Guard.
621 }
622}
623
626 return new yaml::ARMFunctionInfo();
627}
628
631 const auto *MFI = MF.getInfo<ARMFunctionInfo>();
632 return new yaml::ARMFunctionInfo(*MFI);
633}
634
637 SMDiagnostic &Error, SMRange &SourceRange) const {
638 const auto &YamlMFI = static_cast<const yaml::ARMFunctionInfo &>(MFI);
639 MachineFunction &MF = PFS.MF;
640 MF.getInfo<ARMFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
641 return false;
642}
Falkor HW Prefetch Fix
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
static cl::opt< bool > DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, cl::desc("Inhibit optimization of S->D register accesses on A15"), cl::init(false))
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("arm-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget()
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
arm execution domain fix
static cl::opt< bool > EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden, cl::desc("Enable ARM load/store optimization pass"), cl::init(true))
static cl::opt< bool > EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional< Reloc::Model > RM)
This file a TargetTransformInfo::Concept conforming object specific to the ARM target machine.
This file contains the simple types necessary to represent the attributes associated with functions a...
basic Basic Alias true
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Provides analysis for continuously CSEing during GISel passes.
This file describes how to lower LLVM calls to machine code calls.
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
Interface for Targets to specify which operations they can successfully select and how the others sho...
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
Basic Register Allocator
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
speculative execution
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
const ARMSubtarget * getSubtargetImpl() const =delete
StringMap< std::unique_ptr< ARMSubtarget > > SubtargetMap
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool isLittle)
Create an ARM architecture model.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
bool restrictIT() const
Definition: ARMSubtarget.h:473
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:349
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:193
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:169
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class provides the reaching def analysis.
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:44
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
Represents a range in source code.
Definition: SMLoc.h:48
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:222
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:257
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:95
void setMachineOutliner(bool Enable)
void setSupportsDefaultOutlining(bool Enable)
std::string TargetFS
Definition: TargetMachine.h:97
std::string TargetCPU
Definition: TargetMachine.h:96
std::unique_ptr< const MCSubtargetInfo > STI
TargetOptions Options
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line.
EABI EABIVersion
EABIVersion - This flag specifies the EABI version.
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Target-Independent Code Generator Pass Configuration Options.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
@ MuslEABIHF
Definition: Triple.h:262
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:389
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:619
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Definition: Triple.h:553
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ DynamicNoPIC
Definition: CodeGen.h:25
@ ROPI_RWPI
Definition: CodeGen.h:25
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializeARMConstantIslandsPass(PassRegistry &)
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
FunctionPass * createMVETPAndVPTOptimisationsPass()
createMVETPAndVPTOptimisationsPass
Pass * createMVELaneInterleavingPass()
FunctionPass * createARMOptimizeBarriersPass()
createARMOptimizeBarriersPass - Returns an instance of the remove double barriers pass.
FunctionPass * createIfConverter(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createTypePromotionLegacyPass()
Create IR Type Promotion pass.
void initializeMVETailPredicationPass(PassRegistry &)
void initializeMVELaneInterleavingPass(PassRegistry &)
Pass * createMVEGatherScatterLoweringPass()
Target & getTheThumbBETarget()
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOptLevel OptLevel)
createARMISelDag - This pass converts a legalized DAG into a ARM-specific DAG, ready for instruction ...
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)
Definition: CSEInfo.cpp:79
FunctionPass * createARMLowOverheadLoopsPass()
FunctionPass * createARMLoadStoreOptimizationPass(bool PreAlloc=false)
Returns an instance of the load / store optimization pass.
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createARMBranchTargetsPass()
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
void initializeARMBranchTargetsPass(PassRegistry &)
Pass * createMVETailPredicationPass()
FunctionPass * createComplexDeinterleavingPass(const TargetMachine *TM)
This pass implements generation of target-specific intrinsics to support handling of complex number a...
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
FunctionPass * createARMBlockPlacementPass()
std::unique_ptr< ScheduleDAGMutation > createARMMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createARMMacroFusionDAGMutation()); to ARMPassConfig::crea...
Pass * createLowerAtomicPass()
void initializeARMDAGToDAGISelPass(PassRegistry &)
void initializeARMParallelDSPPass(PassRegistry &)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
void initializeARMExpandPseudoPass(PassRegistry &)
FunctionPass * createA15SDOptimizerPass()
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
void initializeARMSLSHardeningPass(PassRegistry &)
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
FunctionPass * createARMSLSHardeningPass()
FunctionPass * createARMConstantIslandPass()
createARMConstantIslandPass - returns an instance of the constpool island pass.
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
void initializeARMLowOverheadLoopsPass(PassRegistry &)
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:313
void initializeMVETPAndVPTOptimisationsPass(PassRegistry &)
void initializeARMExecutionDomainFixPass(PassRegistry &)
void initializeThumb2SizeReducePass(PassRegistry &)
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
void initializeMVEGatherScatterLoweringPass(PassRegistry &)
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass.
FunctionPass * createARMIndirectThunks()
void initializeARMFixCortexA57AES1742098Pass(PassRegistry &)
FunctionPass * createARMFixCortexA57AES1742098Pass()
Pass * createARMParallelDSPPass()
FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
Target & getTheARMLETarget()
void initializeMVEVPTBlockPass(PassRegistry &)
FunctionPass * createMLxExpansionPass()
void initializeARMLoadStoreOptPass(PassRegistry &)
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &)
void initializeARMBlockPlacementPass(PassRegistry &)
FunctionPass * createHardwareLoopsLegacyPass()
Create Hardware Loop pass.
Target & getTheARMBETarget()
Target & getTheThumbLETarget()
FunctionPass * createMVEVPTBlockPass()
createMVEVPTBlock - Returns an instance of the MVE VPT block insertion pass.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.