LLVM  9.0.0svn
Thumb2ITBlockPass.cpp
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1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARM.h"
10 #include "ARMMachineFunctionInfo.h"
11 #include "ARMSubtarget.h"
13 #include "Thumb2InstrInfo.h"
14 #include "llvm/ADT/SmallSet.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/ADT/StringRef.h"
25 #include "llvm/IR/DebugLoc.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include <cassert>
29 #include <new>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "thumb2-it"
34 
35 STATISTIC(NumITs, "Number of IT blocks inserted");
36 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
37 
38 namespace {
39 
40  class Thumb2ITBlockPass : public MachineFunctionPass {
41  public:
42  static char ID;
43 
44  bool restrictIT;
45  const Thumb2InstrInfo *TII;
46  const TargetRegisterInfo *TRI;
47  ARMFunctionInfo *AFI;
48 
49  Thumb2ITBlockPass() : MachineFunctionPass(ID) {}
50 
51  bool runOnMachineFunction(MachineFunction &Fn) override;
52 
53  MachineFunctionProperties getRequiredProperties() const override {
56  }
57 
58  StringRef getPassName() const override {
59  return "Thumb IT blocks insertion pass";
60  }
61 
62  private:
63  bool MoveCopyOutOfITBlock(MachineInstr *MI,
66  SmallSet<unsigned, 4> &Uses);
67  bool InsertITInstructions(MachineBasicBlock &MBB);
68  };
69 
70  char Thumb2ITBlockPass::ID = 0;
71 
72 } // end anonymous namespace
73 
74 /// TrackDefUses - Tracking what registers are being defined and used by
75 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
76 /// in the IT block that are defined before the IT instruction.
80  const TargetRegisterInfo *TRI) {
81  SmallVector<unsigned, 4> LocalDefs;
82  SmallVector<unsigned, 4> LocalUses;
83 
84  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
85  MachineOperand &MO = MI->getOperand(i);
86  if (!MO.isReg())
87  continue;
88  unsigned Reg = MO.getReg();
89  if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
90  continue;
91  if (MO.isUse())
92  LocalUses.push_back(Reg);
93  else
94  LocalDefs.push_back(Reg);
95  }
96 
97  for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
98  unsigned Reg = LocalUses[i];
99  for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
100  Subreg.isValid(); ++Subreg)
101  Uses.insert(*Subreg);
102  }
103 
104  for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
105  unsigned Reg = LocalDefs[i];
106  for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
107  Subreg.isValid(); ++Subreg)
108  Defs.insert(*Subreg);
109  if (Reg == ARM::CPSR)
110  continue;
111  }
112 }
113 
114 /// Clear kill flags for any uses in the given set. This will likely
115 /// conservatively remove more kill flags than are necessary, but removing them
116 /// is safer than incorrect kill flags remaining on instructions.
118  for (MachineOperand &MO : MI->operands()) {
119  if (!MO.isReg() || MO.isDef() || !MO.isKill())
120  continue;
121  if (!Uses.count(MO.getReg()))
122  continue;
123  MO.setIsKill(false);
124  }
125 }
126 
127 static bool isCopy(MachineInstr *MI) {
128  switch (MI->getOpcode()) {
129  default:
130  return false;
131  case ARM::MOVr:
132  case ARM::MOVr_TC:
133  case ARM::tMOVr:
134  case ARM::t2MOVr:
135  return true;
136  }
137 }
138 
139 bool
140 Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
142  SmallSet<unsigned, 4> &Defs,
143  SmallSet<unsigned, 4> &Uses) {
144  if (!isCopy(MI))
145  return false;
146  // llvm models select's as two-address instructions. That means a copy
147  // is inserted before a t2MOVccr, etc. If the copy is scheduled in
148  // between selects we would end up creating multiple IT blocks.
149  assert(MI->getOperand(0).getSubReg() == 0 &&
150  MI->getOperand(1).getSubReg() == 0 &&
151  "Sub-register indices still around?");
152 
153  unsigned DstReg = MI->getOperand(0).getReg();
154  unsigned SrcReg = MI->getOperand(1).getReg();
155 
156  // First check if it's safe to move it.
157  if (Uses.count(DstReg) || Defs.count(SrcReg))
158  return false;
159 
160  // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
161  // if we have:
162  //
163  // movs r1, r1
164  // rsb r1, 0
165  // movs r2, r2
166  // rsb r2, 0
167  //
168  // we don't want this to be converted to:
169  //
170  // movs r1, r1
171  // movs r2, r2
172  // itt mi
173  // rsb r1, 0
174  // rsb r2, 0
175  //
176  const MCInstrDesc &MCID = MI->getDesc();
177  if (MI->hasOptionalDef() &&
178  MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
179  return false;
180 
181  // Then peek at the next instruction to see if it's predicated on CC or OCC.
182  // If not, then there is nothing to be gained by moving the copy.
185  while (I != E && I->isDebugInstr())
186  ++I;
187  if (I != E) {
188  unsigned NPredReg = 0;
189  ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg);
190  if (NCC == CC || NCC == OCC)
191  return true;
192  }
193  return false;
194 }
195 
196 bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
197  bool Modified = false;
198 
201  MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
202  while (MBBI != E) {
203  MachineInstr *MI = &*MBBI;
204  DebugLoc dl = MI->getDebugLoc();
205  unsigned PredReg = 0;
206  ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
207  if (CC == ARMCC::AL) {
208  ++MBBI;
209  continue;
210  }
211 
212  Defs.clear();
213  Uses.clear();
214  TrackDefUses(MI, Defs, Uses, TRI);
215 
216  // Insert an IT instruction.
217  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
218  .addImm(CC);
219 
220  // Add implicit use of ITSTATE to IT block instructions.
221  MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
222  true/*isImp*/, false/*isKill*/));
223 
224  MachineInstr *LastITMI = MI;
225  MachineBasicBlock::iterator InsertPos = MIB.getInstr();
226  ++MBBI;
227 
228  // Form IT block.
230  unsigned Mask = 0, Pos = 3;
231 
232  // v8 IT blocks are limited to one conditional op unless -arm-no-restrict-it
233  // is set: skip the loop
234  if (!restrictIT) {
235  // Branches, including tricky ones like LDM_RET, need to end an IT
236  // block so check the instruction we just put in the block.
237  for (; MBBI != E && Pos &&
238  (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
239  if (MBBI->isDebugInstr())
240  continue;
241 
242  MachineInstr *NMI = &*MBBI;
243  MI = NMI;
244 
245  unsigned NPredReg = 0;
246  ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg);
247  if (NCC == CC || NCC == OCC) {
248  Mask |= ((NCC ^ CC) & 1) << Pos;
249  // Add implicit use of ITSTATE.
250  NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
251  true/*isImp*/, false/*isKill*/));
252  LastITMI = NMI;
253  } else {
254  if (NCC == ARMCC::AL &&
255  MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
256  --MBBI;
257  MBB.remove(NMI);
258  MBB.insert(InsertPos, NMI);
259  ClearKillFlags(MI, Uses);
260  ++NumMovedInsts;
261  continue;
262  }
263  break;
264  }
265  TrackDefUses(NMI, Defs, Uses, TRI);
266  --Pos;
267  }
268  }
269 
270  // Finalize IT mask.
271  Mask |= (1 << Pos);
272  MIB.addImm(Mask);
273 
274  // Last instruction in IT block kills ITSTATE.
275  LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
276 
277  // Finalize the bundle.
278  finalizeBundle(MBB, InsertPos.getInstrIterator(),
279  ++LastITMI->getIterator());
280 
281  Modified = true;
282  ++NumITs;
283  }
284 
285  return Modified;
286 }
287 
288 bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
289  const ARMSubtarget &STI =
290  static_cast<const ARMSubtarget &>(Fn.getSubtarget());
291  if (!STI.isThumb2())
292  return false;
293  AFI = Fn.getInfo<ARMFunctionInfo>();
294  TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
295  TRI = STI.getRegisterInfo();
296  restrictIT = STI.restrictIT();
297 
298  if (!AFI->isThumbFunction())
299  return false;
300 
301  bool Modified = false;
302  for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) {
303  MachineBasicBlock &MBB = *MFI;
304  ++MFI;
305  Modified |= InsertITInstructions(MBB);
306  }
307 
308  if (Modified)
309  AFI->setHasITBlocks(true);
310 
311  return Modified;
312 }
313 
314 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
315 /// insertion pass.
317  return new Thumb2ITBlockPass();
318 }
319 
320 #undef DEBUG_TYPE
321 #define DEBUG_TYPE "arm-mve-vpt"
322 
323 namespace {
324  class MVEVPTBlock : public MachineFunctionPass {
325  public:
326  static char ID;
327  const Thumb2InstrInfo *TII;
328  const TargetRegisterInfo *TRI;
329 
330  MVEVPTBlock() : MachineFunctionPass(ID) {}
331 
332  bool runOnMachineFunction(MachineFunction &Fn) override;
333 
334  MachineFunctionProperties getRequiredProperties() const override {
337  }
338 
339  StringRef getPassName() const override {
340  return "MVE VPT block insertion pass";
341  }
342 
343  private:
344  bool InsertVPTBlocks(MachineBasicBlock &MBB);
345  };
346 
347  char MVEVPTBlock::ID = 0;
348 
349 } // end anonymous namespace
350 
351 INITIALIZE_PASS(MVEVPTBlock, DEBUG_TYPE, "ARM MVE VPT block pass", false, false)
352 
354  T = 8, // 0b1000
355  TT = 4, // 0b0100
356  TE = 12, // 0b1100
357  TTT = 2, // 0b0010
358  TTE = 6, // 0b0110
359  TEE = 10, // 0b1010
360  TET = 14, // 0b1110
361  TTTT = 1, // 0b0001
362  TTTE = 3, // 0b0011
363  TTEE = 5, // 0b0101
364  TTET = 7, // 0b0111
365  TEEE = 9, // 0b1001
366  TEET = 11, // 0b1011
367  TETT = 13, // 0b1101
368  TETE = 15 // 0b1111
369 };
370 
371 bool MVEVPTBlock::InsertVPTBlocks(MachineBasicBlock &Block) {
372  bool Modified = false;
373  MachineBasicBlock::iterator MBIter = Block.begin();
374  MachineBasicBlock::iterator EndIter = Block.end();
375 
376  while (MBIter != EndIter) {
377  MachineInstr *MI = &*MBIter;
378  unsigned PredReg = 0;
379  DebugLoc dl = MI->getDebugLoc();
380 
381  ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*MI, PredReg);
382 
383  // The idea of the predicate is that None, Then and Else are for use when
384  // handling assembly language: they correspond to the three possible
385  // suffixes "", "t" and "e" on the mnemonic. So when instructions are read
386  // from assembly source or disassembled from object code, you expect to see
387  // a mixture whenever there's a long VPT block. But in code generation, we
388  // hope we'll never generate an Else as input to this pass.
389 
390  assert(Pred != ARMVCC::Else && "VPT block pass does not expect Else preds");
391 
392  if (Pred == ARMVCC::None) {
393  ++MBIter;
394  continue;
395  }
396 
397  MachineInstrBuilder MIBuilder =
398  BuildMI(Block, MBIter, dl, TII->get(ARM::t2VPST));
399  MachineInstr *LastITMI = MI;
400  MachineBasicBlock::iterator InsertPos = MIBuilder.getInstr();
401 
402  // The mask value for the VPST instruction is T = 0b1000 = 8
403  MIBuilder.addImm(VPTMaskValue::T);
404 
405  finalizeBundle(Block, InsertPos.getInstrIterator(),
406  ++LastITMI->getIterator());
407  Modified = true;
408  LLVM_DEBUG(dbgs() << "VPT block created for: "; MI->dump(););
409 
410  ++MBIter;
411  }
412  return Modified;
413 }
414 
415 bool MVEVPTBlock::runOnMachineFunction(MachineFunction &Fn) {
416  const ARMSubtarget &STI =
417  static_cast<const ARMSubtarget &>(Fn.getSubtarget());
418 
419  if (!STI.isThumb2() || !STI.hasMVEIntegerOps())
420  return false;
421 
422  TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
423  TRI = STI.getRegisterInfo();
424 
425  LLVM_DEBUG(dbgs() << "********** ARM MVE VPT BLOCKS **********\n"
426  << "********** Function: " << Fn.getName() << '\n');
427 
428  bool Modified = false;
429  for (MachineBasicBlock &MBB : Fn)
430  Modified |= InsertVPTBlocks(MBB);
431 
432  LLVM_DEBUG(dbgs() << "**************************************\n");
433  return Modified;
434 }
435 
436 /// createMVEVPTBlock - Returns an instance of the MVE VPT block
437 /// insertion pass.
438 FunctionPass *llvm::createMVEVPTBlockPass() { return new MVEVPTBlock(); }
static bool isCopy(MachineInstr *MI)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void push_back(const T &Elt)
Definition: SmallVector.h:211
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned getReg() const
getReg - Returns the register number.
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
unsigned Reg
unsigned getSubReg() const
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
static void ClearKillFlags(MachineInstr *MI, SmallSet< unsigned, 4 > &Uses)
Clear kill flags for any uses in the given set.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:460
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:521
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:211
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
void clear()
Definition: SmallSet.h:218
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:658
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:624
FunctionPass * createMVEVPTBlockPass()
createMVEVPTBlock - Returns an instance of the MVE VPT block insertion pass.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool restrictIT() const
Definition: ARMSubtarget.h:785
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
static void TrackDefUses(MachineInstr *MI, SmallSet< unsigned, 4 > &Defs, SmallSet< unsigned, 4 > &Uses, const TargetRegisterInfo *TRI)
TrackDefUses - Tracking what registers are being defined and used by instructions in the IT block...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
self_iterator getIterator()
Definition: ilist_node.h:81
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
size_t size() const
Definition: SmallVector.h:52
void setIsKill(bool Val=true)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:33
#define DEBUG_TYPE
Iterator for intrusive lists based on ilist_node.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
MachineOperand class - Representation of each machine instruction operand.
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly. ...
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
MachineFunctionProperties & set(Property P)
bool isThumb2() const
Definition: ARMSubtarget.h:752
Representation of each machine instruction.
Definition: MachineInstr.h:63
static CondCodes getOppositeCondition(CondCodes CC)
Definition: ARMBaseInfo.h:48
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
#define I(x, y, z)
Definition: MD5.cpp:58
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:533
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:614
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
bool hasMVEIntegerOps() const
Definition: ARMSubtarget.h:580
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
Properties which a MachineFunction may have at a given point in time.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164