Go to the documentation of this file.
33 #define DEBUG_TYPE "thumb2-it"
34 #define PASS_NAME "Thumb IT blocks insertion pass"
36 STATISTIC(NumITs,
"Number of IT blocks inserted");
37 STATISTIC(NumMovedInsts,
"Number of predicated instructions moved");
87 for (
auto &MO :
MI->operands()) {
91 if (!
Reg ||
Reg == ARM::ITSTATE ||
Reg == ARM::SP)
94 LocalUses.push_back(
Reg);
96 LocalDefs.push_back(
Reg);
99 auto InsertUsesDefs = [&](RegList &Regs,
RegisterSet &UsesDefs) {
100 for (
unsigned Reg : Regs)
103 UsesDefs.insert(*Subreg);
106 InsertUsesDefs(LocalDefs, Defs);
107 InsertUsesDefs(LocalUses,
Uses);
115 if (!MO.isReg() || MO.isDef() || !MO.isKill())
117 if (!
Uses.count(MO.getReg()))
124 switch (
MI->getOpcode()) {
144 assert(
MI->getOperand(0).getSubReg() == 0 &&
145 MI->getOperand(1).getSubReg() == 0 &&
146 "Sub-register indices still around?");
152 if (
Uses.count(DstReg) || Defs.count(SrcReg))
172 if (
MI->hasOptionalDef() &&
182 while (
I !=
E &&
I->isDebugInstr())
188 if (NCC == CC || NCC == OCC)
227 unsigned Mask = 0, Pos = 3;
235 for (;
MBBI !=
E && Pos &&
236 (!
MI->isBranch() && !
MI->isReturn()) ; ++
MBBI) {
237 if (
MBBI->isDebugInstr())
245 if (NCC == CC || NCC == OCC) {
246 Mask |= ((NCC ^ CC) & 1) << Pos;
253 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs,
Uses)) {
295 if (!AFI->isThumbFunction())
299 for (
auto &
MBB : Fn )
303 AFI->setHasITBlocks(
true);
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
void setIsKill(bool Val=true)
Reg
All possible values of the reg field in the ModR/M byte.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineOperand * findRegisterUseOperand(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
const ARMBaseInstrInfo * getInstrInfo() const override
Properties which a MachineFunction may have at a given point in time.
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
SmallSet< unsigned, 4 > RegisterSet
unsigned const TargetRegisterInfo * TRI
SmallPtrSet< MachineInstr *, 2 > Uses
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
MachineFunctionProperties & set(Property P)
STATISTIC(NumFunctions, "Total number of functions")
static void ClearKillFlags(MachineInstr *MI, RegisterSet &Uses)
Clear kill flags for any uses in the given set.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, const TargetRegisterInfo *TRI)
TrackDefUses - Tracking what registers are being defined and used by instructions in the IT block.
instr_iterator getInstrIterator() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const ARMBaseRegisterInfo * getRegisterInfo() const override
StringRef - Represent a constant reference to a string, i.e.
MachineBasicBlock MachineBasicBlock::iterator MBBI
self_iterator getIterator()
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Wrapper class representing virtual and physical registers.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
MCSubRegIterator enumerates all sub-registers of Reg.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
static bool isCopy(MachineInstr *MI)
FunctionPass class - This class is used to implement most global optimizations.
static CondCodes getOppositeCondition(CondCodes CC)
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.