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MipsSEISelDAGToDAG.cpp
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1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsSEISelDAGToDAG.h"
15 #include "Mips.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
25 #include "llvm/IR/CFG.h"
26 #include "llvm/IR/Dominators.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "mips-isel"
38 
39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40  Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
41  if (Subtarget->inMips16Mode())
42  return false;
44 }
45 
46 void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
49 }
50 
51 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
53  MachineInstrBuilder MIB(MF, &MI);
54  unsigned Mask = MI.getOperand(1).getImm();
55  unsigned Flag =
57 
58  if (Mask & 1)
59  MIB.addReg(Mips::DSPPos, Flag);
60 
61  if (Mask & 2)
62  MIB.addReg(Mips::DSPSCount, Flag);
63 
64  if (Mask & 4)
65  MIB.addReg(Mips::DSPCarry, Flag);
66 
67  if (Mask & 8)
68  MIB.addReg(Mips::DSPOutFlag, Flag);
69 
70  if (Mask & 16)
71  MIB.addReg(Mips::DSPCCond, Flag);
72 
73  if (Mask & 32)
74  MIB.addReg(Mips::DSPEFI, Flag);
75 }
76 
77 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
78  uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue();
79  return Mips::MSACtrlRegClass.getRegister(RegNum);
80 }
81 
82 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
83  const MachineInstr& MI) {
84  unsigned DstReg = 0, ZeroReg = 0;
85 
86  // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
87  if ((MI.getOpcode() == Mips::ADDiu) &&
88  (MI.getOperand(1).getReg() == Mips::ZERO) &&
89  (MI.getOperand(2).isImm()) &&
90  (MI.getOperand(2).getImm() == 0)) {
91  DstReg = MI.getOperand(0).getReg();
92  ZeroReg = Mips::ZERO;
93  } else if ((MI.getOpcode() == Mips::DADDiu) &&
94  (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
95  (MI.getOperand(2).isImm()) &&
96  (MI.getOperand(2).getImm() == 0)) {
97  DstReg = MI.getOperand(0).getReg();
98  ZeroReg = Mips::ZERO_64;
99  }
100 
101  if (!DstReg)
102  return false;
103 
104  // Replace uses with ZeroReg.
105  for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
106  E = MRI->use_end(); U != E;) {
107  MachineOperand &MO = *U;
108  unsigned OpNo = U.getOperandNo();
109  MachineInstr *MI = MO.getParent();
110  ++U;
111 
112  // Do not replace if it is a phi's operand or is tied to def operand.
113  if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
114  continue;
115 
116  // Also, we have to check that the register class of the operand
117  // contains the zero register.
118  if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
119  continue;
120 
121  MO.setReg(ZeroReg);
122  }
123 
124  return true;
125 }
126 
127 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
128  MF.getInfo<MipsFunctionInfo>()->initGlobalBaseReg();
129 
130  MachineRegisterInfo *MRI = &MF.getRegInfo();
131 
132  for (auto &MBB: MF) {
133  for (auto &MI: MBB) {
134  switch (MI.getOpcode()) {
135  case Mips::RDDSP:
136  addDSPCtrlRegOperands(false, MI, MF);
137  break;
138  case Mips::WRDSP:
139  addDSPCtrlRegOperands(true, MI, MF);
140  break;
141  case Mips::BuildPairF64_64:
142  case Mips::ExtractElementF64_64:
143  if (!Subtarget->useOddSPReg()) {
144  MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
145  break;
146  }
148  case Mips::BuildPairF64:
150  if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
151  MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
152  break;
153  default:
154  replaceUsesWithZeroReg(MRI, MI);
155  }
156  }
157  }
158 }
159 
160 void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
161  SDValue InFlag = Node->getOperand(2);
162  unsigned Opc = InFlag.getOpcode();
163  SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
164  EVT VT = LHS.getValueType();
165 
166  // In the base case, we can rely on the carry bit from the addsc
167  // instruction.
168  if (Opc == ISD::ADDC) {
169  SDValue Ops[3] = {LHS, RHS, InFlag};
170  CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Ops);
171  return;
172  }
173 
174  assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!");
175 
176  // The more complex case is when there is a chain of ISD::ADDE nodes like:
177  // (adde (adde (adde (addc a b) c) d) e).
178  //
179  // The addwc instruction does not write to the carry bit, instead it writes
180  // to bit 20 of the dsp control register. To match this series of nodes, each
181  // intermediate adde node must be expanded to write the carry bit before the
182  // addition.
183 
184  // Start by reading the overflow field for addsc and moving the value to the
185  // carry field. The usage of 1 here with MipsISD::RDDSP / Mips::WRDSP
186  // corresponds to reading/writing the entire control register to/from a GPR.
187 
188  SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32);
189 
190  SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
191 
192  SDNode *DSPCtrlField =
193  CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, MVT::Glue, CstOne, InFlag);
194 
195  SDNode *Carry = CurDAG->getMachineNode(
196  Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
197 
198  SDValue Ops[4] = {SDValue(DSPCtrlField, 0),
199  CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne,
200  SDValue(Carry, 0)};
201  SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops);
202 
203  // My reading of the MIPS DSP 3.01 specification isn't as clear as I
204  // would like about whether bit 20 always gets overwritten by addwc.
205  // Hence take an extremely conservative view and presume it's sticky. We
206  // therefore need to clear it.
207 
208  SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
209 
210  SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)};
211  SDNode *DSPCtrlFinal = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
212 
213  SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
214  SDValue(DSPCtrlFinal, 0), CstOne);
215 
216  SDValue Operands[3] = {LHS, RHS, SDValue(WrDSP, 0)};
217  CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Operands);
218 }
219 
220 /// Match frameindex
221 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
222  SDValue &Offset) const {
223  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
224  EVT ValTy = Addr.getValueType();
225 
226  Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
227  Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
228  return true;
229  }
230  return false;
231 }
232 
233 /// Match frameindex+offset and frameindex|offset
234 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
235  SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits,
236  unsigned ShiftAmount = 0) const {
237  if (CurDAG->isBaseWithConstantOffset(Addr)) {
239  if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
240  EVT ValTy = Addr.getValueType();
241 
242  // If the first operand is a FI, get the TargetFI Node
243  if (FrameIndexSDNode *FIN =
244  dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
245  Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
246  else {
247  Base = Addr.getOperand(0);
248  // If base is a FI, additional offset calculation is done in
249  // eliminateFrameIndex, otherwise we need to check the alignment
250  if (OffsetToAlignment(CN->getZExtValue(), 1ull << ShiftAmount) != 0)
251  return false;
252  }
253 
254  Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
255  ValTy);
256  return true;
257  }
258  }
259  return false;
260 }
261 
262 /// ComplexPattern used on MipsInstrInfo
263 /// Used on Mips Load/Store instructions
264 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
265  SDValue &Offset) const {
266  // if Address is FI, get the TargetFrameIndex.
267  if (selectAddrFrameIndex(Addr, Base, Offset))
268  return true;
269 
270  // on PIC code Load GA
271  if (Addr.getOpcode() == MipsISD::Wrapper) {
272  Base = Addr.getOperand(0);
273  Offset = Addr.getOperand(1);
274  return true;
275  }
276 
277  if (!TM.isPositionIndependent()) {
278  if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
280  return false;
281  }
282 
283  // Addresses of the form FI+const or FI|const
284  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
285  return true;
286 
287  // Operand is a result from an ADD.
288  if (Addr.getOpcode() == ISD::ADD) {
289  // When loading from constant pools, load the lower address part in
290  // the instruction itself. Example, instead of:
291  // lui $2, %hi($CPI1_0)
292  // addiu $2, $2, %lo($CPI1_0)
293  // lwc1 $f0, 0($2)
294  // Generate:
295  // lui $2, %hi($CPI1_0)
296  // lwc1 $f0, %lo($CPI1_0)($2)
297  if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
298  Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
299  SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
300  if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
301  isa<JumpTableSDNode>(Opnd0)) {
302  Base = Addr.getOperand(0);
303  Offset = Opnd0;
304  return true;
305  }
306  }
307  }
308 
309  return false;
310 }
311 
312 /// ComplexPattern used on MipsInstrInfo
313 /// Used on Mips Load/Store instructions
314 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
315  SDValue &Offset) const {
316  Base = Addr;
317  Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
318  return true;
319 }
320 
321 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
322  SDValue &Offset) const {
323  return selectAddrRegImm(Addr, Base, Offset) ||
324  selectAddrDefault(Addr, Base, Offset);
325 }
326 
327 bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
328  SDValue &Offset) const {
329  if (selectAddrFrameIndex(Addr, Base, Offset))
330  return true;
331 
332  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
333  return true;
334 
335  return false;
336 }
337 
338 /// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
339 bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base,
340  SDValue &Offset) const {
341  if (selectAddrFrameIndex(Addr, Base, Offset))
342  return true;
343 
344  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 11))
345  return true;
346 
347  return false;
348 }
349 
350 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
351 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
352  SDValue &Offset) const {
353  if (selectAddrFrameIndex(Addr, Base, Offset))
354  return true;
355 
356  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
357  return true;
358 
359  return false;
360 }
361 
362 bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
363  SDValue &Offset) const {
364  if (selectAddrFrameIndex(Addr, Base, Offset))
365  return true;
366 
367  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
368  return true;
369 
370  return false;
371 }
372 
373 bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
374  SDValue &Offset) const {
375  return selectAddrRegImm11(Addr, Base, Offset) ||
376  selectAddrDefault(Addr, Base, Offset);
377 }
378 
379 bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
380  SDValue &Offset) const {
381  return selectAddrRegImm12(Addr, Base, Offset) ||
382  selectAddrDefault(Addr, Base, Offset);
383 }
384 
385 bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
386  SDValue &Offset) const {
387  return selectAddrRegImm16(Addr, Base, Offset) ||
388  selectAddrDefault(Addr, Base, Offset);
389 }
390 
391 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
392  SDValue &Offset) const {
393  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
394  if (isa<FrameIndexSDNode>(Base))
395  return false;
396 
397  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
398  unsigned CnstOff = CN->getZExtValue();
399  return (CnstOff == (CnstOff & 0x3c));
400  }
401 
402  return false;
403  }
404 
405  // For all other cases where "lw" would be selected, don't select "lw16"
406  // because it would result in additional instructions to prepare operands.
407  if (selectAddrRegImm(Addr, Base, Offset))
408  return false;
409 
410  return selectAddrDefault(Addr, Base, Offset);
411 }
412 
413 bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
414  SDValue &Offset) const {
415 
416  if (selectAddrFrameIndex(Addr, Base, Offset))
417  return true;
418 
419  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
420  return true;
421 
422  return selectAddrDefault(Addr, Base, Offset);
423 }
424 
425 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
426  SDValue &Offset) const {
427  if (selectAddrFrameIndex(Addr, Base, Offset))
428  return true;
429 
430  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 1))
431  return true;
432 
433  return selectAddrDefault(Addr, Base, Offset);
434 }
435 
436 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
437  SDValue &Offset) const {
438  if (selectAddrFrameIndex(Addr, Base, Offset))
439  return true;
440 
441  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 2))
442  return true;
443 
444  return selectAddrDefault(Addr, Base, Offset);
445 }
446 
447 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
448  SDValue &Offset) const {
449  if (selectAddrFrameIndex(Addr, Base, Offset))
450  return true;
451 
452  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 3))
453  return true;
454 
455  return selectAddrDefault(Addr, Base, Offset);
456 }
457 
458 // Select constant vector splats.
459 //
460 // Returns true and sets Imm if:
461 // * MSA is enabled
462 // * N is a ISD::BUILD_VECTOR representing a constant splat
463 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
464  unsigned MinSizeInBits) const {
465  if (!Subtarget->hasMSA())
466  return false;
467 
469 
470  if (!Node)
471  return false;
472 
473  APInt SplatValue, SplatUndef;
474  unsigned SplatBitSize;
475  bool HasAnyUndefs;
476 
477  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
478  MinSizeInBits, !Subtarget->isLittle()))
479  return false;
480 
481  Imm = SplatValue;
482 
483  return true;
484 }
485 
486 // Select constant vector splats.
487 //
488 // In addition to the requirements of selectVSplat(), this function returns
489 // true and sets Imm if:
490 // * The splat value is the same width as the elements of the vector
491 // * The splat value fits in an integer with the specified signed-ness and
492 // width.
493 //
494 // This function looks through ISD::BITCAST nodes.
495 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
496 // sometimes a shuffle in big-endian mode.
497 //
498 // It's worth noting that this function is not used as part of the selection
499 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
500 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
501 // MipsSEDAGToDAGISel::selectNode.
502 bool MipsSEDAGToDAGISel::
503 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
504  unsigned ImmBitSize) const {
505  APInt ImmValue;
506  EVT EltTy = N->getValueType(0).getVectorElementType();
507 
508  if (N->getOpcode() == ISD::BITCAST)
509  N = N->getOperand(0);
510 
511  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
512  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
513 
514  if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
515  (!Signed && ImmValue.isIntN(ImmBitSize))) {
516  Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
517  return true;
518  }
519  }
520 
521  return false;
522 }
523 
524 // Select constant vector splats.
525 bool MipsSEDAGToDAGISel::
526 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
527  return selectVSplatCommon(N, Imm, false, 1);
528 }
529 
530 bool MipsSEDAGToDAGISel::
531 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
532  return selectVSplatCommon(N, Imm, false, 2);
533 }
534 
535 bool MipsSEDAGToDAGISel::
536 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
537  return selectVSplatCommon(N, Imm, false, 3);
538 }
539 
540 // Select constant vector splats.
541 bool MipsSEDAGToDAGISel::
542 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
543  return selectVSplatCommon(N, Imm, false, 4);
544 }
545 
546 // Select constant vector splats.
547 bool MipsSEDAGToDAGISel::
548 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
549  return selectVSplatCommon(N, Imm, false, 5);
550 }
551 
552 // Select constant vector splats.
553 bool MipsSEDAGToDAGISel::
554 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
555  return selectVSplatCommon(N, Imm, false, 6);
556 }
557 
558 // Select constant vector splats.
559 bool MipsSEDAGToDAGISel::
560 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
561  return selectVSplatCommon(N, Imm, false, 8);
562 }
563 
564 // Select constant vector splats.
565 bool MipsSEDAGToDAGISel::
566 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
567  return selectVSplatCommon(N, Imm, true, 5);
568 }
569 
570 // Select constant vector splats whose value is a power of 2.
571 //
572 // In addition to the requirements of selectVSplat(), this function returns
573 // true and sets Imm if:
574 // * The splat value is the same width as the elements of the vector
575 // * The splat value is a power of two.
576 //
577 // This function looks through ISD::BITCAST nodes.
578 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
579 // sometimes a shuffle in big-endian mode.
580 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
581  APInt ImmValue;
582  EVT EltTy = N->getValueType(0).getVectorElementType();
583 
584  if (N->getOpcode() == ISD::BITCAST)
585  N = N->getOperand(0);
586 
587  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
588  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
589  int32_t Log2 = ImmValue.exactLogBase2();
590 
591  if (Log2 != -1) {
592  Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
593  return true;
594  }
595  }
596 
597  return false;
598 }
599 
600 // Select constant vector splats whose value only has a consecutive sequence
601 // of left-most bits set (e.g. 0b11...1100...00).
602 //
603 // In addition to the requirements of selectVSplat(), this function returns
604 // true and sets Imm if:
605 // * The splat value is the same width as the elements of the vector
606 // * The splat value is a consecutive sequence of left-most bits.
607 //
608 // This function looks through ISD::BITCAST nodes.
609 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
610 // sometimes a shuffle in big-endian mode.
611 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
612  APInt ImmValue;
613  EVT EltTy = N->getValueType(0).getVectorElementType();
614 
615  if (N->getOpcode() == ISD::BITCAST)
616  N = N->getOperand(0);
617 
618  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
619  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
620  // Extract the run of set bits starting with bit zero from the bitwise
621  // inverse of ImmValue, and test that the inverse of this is the same
622  // as the original value.
623  if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
624 
625  Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
626  EltTy);
627  return true;
628  }
629  }
630 
631  return false;
632 }
633 
634 // Select constant vector splats whose value only has a consecutive sequence
635 // of right-most bits set (e.g. 0b00...0011...11).
636 //
637 // In addition to the requirements of selectVSplat(), this function returns
638 // true and sets Imm if:
639 // * The splat value is the same width as the elements of the vector
640 // * The splat value is a consecutive sequence of right-most bits.
641 //
642 // This function looks through ISD::BITCAST nodes.
643 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
644 // sometimes a shuffle in big-endian mode.
645 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
646  APInt ImmValue;
647  EVT EltTy = N->getValueType(0).getVectorElementType();
648 
649  if (N->getOpcode() == ISD::BITCAST)
650  N = N->getOperand(0);
651 
652  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
653  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
654  // Extract the run of set bits starting with bit zero, and test that the
655  // result is the same as the original value
656  if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
657  Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
658  EltTy);
659  return true;
660  }
661  }
662 
663  return false;
664 }
665 
666 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
667  SDValue &Imm) const {
668  APInt ImmValue;
669  EVT EltTy = N->getValueType(0).getVectorElementType();
670 
671  if (N->getOpcode() == ISD::BITCAST)
672  N = N->getOperand(0);
673 
674  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
675  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
676  int32_t Log2 = (~ImmValue).exactLogBase2();
677 
678  if (Log2 != -1) {
679  Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
680  return true;
681  }
682  }
683 
684  return false;
685 }
686 
687 bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
688  unsigned Opcode = Node->getOpcode();
689  SDLoc DL(Node);
690 
691  ///
692  // Instruction Selection not handled by the auto-generated
693  // tablegen selection should be handled here.
694  ///
695  switch(Opcode) {
696  default: break;
697 
698  case Mips::PseudoD_SELECT_I:
699  case Mips::PseudoD_SELECT_I64: {
701  SDValue cond = Node->getOperand(0);
702  SDValue Hi1 = Node->getOperand(1);
703  SDValue Lo1 = Node->getOperand(2);
704  SDValue Hi2 = Node->getOperand(3);
705  SDValue Lo2 = Node->getOperand(4);
706 
707  SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2};
708  EVT NodeTys[] = {VT, VT};
710  ? Mips::PseudoD_SELECT_I64
711  : Mips::PseudoD_SELECT_I,
712  DL, NodeTys, ops));
713  return true;
714  }
715 
716  case ISD::ADDE: {
717  selectAddE(Node, DL);
718  return true;
719  }
720 
721  case ISD::ConstantFP: {
723  if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
724  if (Subtarget->isGP64bit()) {
726  Mips::ZERO_64, MVT::i64);
727  ReplaceNode(Node,
728  CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
729  } else if (Subtarget->isFP64bit()) {
731  Mips::ZERO, MVT::i32);
732  ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL,
733  MVT::f64, Zero, Zero));
734  } else {
736  Mips::ZERO, MVT::i32);
738  MVT::f64, Zero, Zero));
739  }
740  return true;
741  }
742  break;
743  }
744 
745  case ISD::Constant: {
746  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
747  int64_t Imm = CN->getSExtValue();
748  unsigned Size = CN->getValueSizeInBits(0);
749 
750  if (isInt<32>(Imm))
751  break;
752 
753  MipsAnalyzeImmediate AnalyzeImm;
754 
755  const MipsAnalyzeImmediate::InstSeq &Seq =
756  AnalyzeImm.Analyze(Imm, Size, false);
757 
759  SDLoc DL(CN);
760  SDNode *RegOpnd;
761  SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
762  DL, MVT::i64);
763 
764  // The first instruction can be a LUi which is different from other
765  // instructions (ADDiu, ORI and SLL) in that it does not have a register
766  // operand.
767  if (Inst->Opc == Mips::LUi64)
768  RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
769  else
770  RegOpnd =
771  CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
772  CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
773  ImmOpnd);
774 
775  // The remaining instructions in the sequence are handled here.
776  for (++Inst; Inst != Seq.end(); ++Inst) {
777  ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
778  MVT::i64);
779  RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
780  SDValue(RegOpnd, 0), ImmOpnd);
781  }
782 
783  ReplaceNode(Node, RegOpnd);
784  return true;
785  }
786 
787  case ISD::INTRINSIC_W_CHAIN: {
788  switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
789  default:
790  break;
791 
792  case Intrinsic::mips_cfcmsa: {
793  SDValue ChainIn = Node->getOperand(0);
794  SDValue RegIdx = Node->getOperand(2);
795  SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
796  getMSACtrlReg(RegIdx), MVT::i32);
797  ReplaceNode(Node, Reg.getNode());
798  return true;
799  }
800  }
801  break;
802  }
803 
805  switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
806  default:
807  break;
808 
809  case Intrinsic::mips_move_v:
810  // Like an assignment but will always produce a move.v even if
811  // unnecessary.
812  ReplaceNode(Node, CurDAG->getMachineNode(Mips::MOVE_V, DL,
813  Node->getValueType(0),
814  Node->getOperand(1)));
815  return true;
816  }
817  break;
818  }
819 
820  case ISD::INTRINSIC_VOID: {
821  switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
822  default:
823  break;
824 
825  case Intrinsic::mips_ctcmsa: {
826  SDValue ChainIn = Node->getOperand(0);
827  SDValue RegIdx = Node->getOperand(2);
828  SDValue Value = Node->getOperand(3);
829  SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
830  getMSACtrlReg(RegIdx), Value);
831  ReplaceNode(Node, ChainOut.getNode());
832  return true;
833  }
834  }
835  break;
836  }
837 
838  // Manually match MipsISD::Ins nodes to get the correct instruction. It has
839  // to be done in this fashion so that we respect the differences between
840  // dins and dinsm, as the difference is that the size operand has the range
841  // 0 < size <= 32 for dins while dinsm has the range 2 <= size <= 64 which
842  // means SelectionDAGISel would have to test all the operands at once to
843  // match the instruction.
844  case MipsISD::Ins: {
845 
846  // Sanity checking for the node operands.
847  if (Node->getValueType(0) != MVT::i32 && Node->getValueType(0) != MVT::i64)
848  return false;
849 
850  if (Node->getNumOperands() != 4)
851  return false;
852 
853  if (Node->getOperand(1)->getOpcode() != ISD::Constant ||
854  Node->getOperand(2)->getOpcode() != ISD::Constant)
855  return false;
856 
857  MVT ResTy = Node->getSimpleValueType(0);
858  uint64_t Pos = Node->getConstantOperandVal(1);
859  uint64_t Size = Node->getConstantOperandVal(2);
860 
861  // Size has to be >0 for 'ins', 'dins' and 'dinsu'.
862  if (!Size)
863  return false;
864 
865  if (Pos + Size > 64)
866  return false;
867 
868  if (ResTy != MVT::i32 && ResTy != MVT::i64)
869  return false;
870 
871  unsigned Opcode = 0;
872  if (ResTy == MVT::i32) {
873  if (Pos + Size <= 32)
874  Opcode = Mips::INS;
875  } else {
876  if (Pos + Size <= 32)
877  Opcode = Mips::DINS;
878  else if (Pos < 32 && 1 < Size)
879  Opcode = Mips::DINSM;
880  else
881  Opcode = Mips::DINSU;
882  }
883 
884  if (Opcode) {
885  SDValue Ops[4] = {
886  Node->getOperand(0), CurDAG->getTargetConstant(Pos, DL, MVT::i32),
887  CurDAG->getTargetConstant(Size, DL, MVT::i32), Node->getOperand(3)};
888 
889  ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, ResTy, Ops));
890  return true;
891  }
892 
893  return false;
894  }
895 
896  case MipsISD::ThreadPointer: {
898  unsigned RdhwrOpc, DestReg;
899 
900  if (PtrVT == MVT::i32) {
901  RdhwrOpc = Mips::RDHWR;
902  DestReg = Mips::V1;
903  } else {
904  RdhwrOpc = Mips::RDHWR64;
905  DestReg = Mips::V1_64;
906  }
907 
908  SDNode *Rdhwr =
909  CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0),
910  CurDAG->getRegister(Mips::HWR29, MVT::i32),
912  SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
913  SDValue(Rdhwr, 0));
914  SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
915  ReplaceNode(Node, ResNode.getNode());
916  return true;
917  }
918 
919  case ISD::BUILD_VECTOR: {
920  // Select appropriate ldi.[bhwd] instructions for constant splats of
921  // 128-bit when MSA is enabled. Fixup any register class mismatches that
922  // occur as a result.
923  //
924  // This allows the compiler to use a wider range of immediates than would
925  // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
926  // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
927  // 0x01010101 } without using a constant pool. This would be sub-optimal
928  // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
929  // same set/ of registers. Similarly, ldi.h isn't capable of producing {
930  // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
931 
932  const MipsABIInfo &ABI =
933  static_cast<const MipsTargetMachine &>(TM).getABI();
934 
935  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
936  APInt SplatValue, SplatUndef;
937  unsigned SplatBitSize;
938  bool HasAnyUndefs;
939  unsigned LdiOp;
940  EVT ResVecTy = BVN->getValueType(0);
941  EVT ViaVecTy;
942 
943  if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
944  return false;
945 
946  if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
947  HasAnyUndefs, 8,
948  !Subtarget->isLittle()))
949  return false;
950 
951  switch (SplatBitSize) {
952  default:
953  return false;
954  case 8:
955  LdiOp = Mips::LDI_B;
956  ViaVecTy = MVT::v16i8;
957  break;
958  case 16:
959  LdiOp = Mips::LDI_H;
960  ViaVecTy = MVT::v8i16;
961  break;
962  case 32:
963  LdiOp = Mips::LDI_W;
964  ViaVecTy = MVT::v4i32;
965  break;
966  case 64:
967  LdiOp = Mips::LDI_D;
968  ViaVecTy = MVT::v2i64;
969  break;
970  }
971 
972  SDNode *Res;
973 
974  // If we have a signed 10 bit integer, we can splat it directly.
975  //
976  // If we have something bigger we can synthesize the value into a GPR and
977  // splat from there.
978  if (SplatValue.isSignedIntN(10)) {
979  SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
980  ViaVecTy.getVectorElementType());
981 
982  Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
983  } else if (SplatValue.isSignedIntN(16) &&
984  ((ABI.IsO32() && SplatBitSize < 64) ||
985  (ABI.IsN32() || ABI.IsN64()))) {
986  // Only handle signed 16 bit values when the element size is GPR width.
987  // MIPS64 can handle all the cases but MIPS32 would need to handle
988  // negative cases specifically here. Instead, handle those cases as
989  // 64bit values.
990 
991  bool Is32BitSplat = ABI.IsO32() || SplatBitSize < 64;
992  const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
993  const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64;
994  SDValue ZeroVal = CurDAG->getRegister(
995  Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT);
996 
997  const unsigned FILLOp =
998  SplatBitSize == 16
999  ? Mips::FILL_H
1000  : (SplatBitSize == 32 ? Mips::FILL_W
1001  : (SplatBitSize == 64 ? Mips::FILL_D : 0));
1002 
1003  assert(FILLOp != 0 && "Unknown FILL Op for splat synthesis!");
1004  assert((!ABI.IsO32() || (FILLOp != Mips::FILL_D)) &&
1005  "Attempting to use fill.d on MIPS32!");
1006 
1007  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1008  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, SplatMVT);
1009 
1010  Res = CurDAG->getMachineNode(ADDiuOp, DL, SplatMVT, ZeroVal, LoVal);
1011  Res = CurDAG->getMachineNode(FILLOp, DL, ViaVecTy, SDValue(Res, 0));
1012 
1013  } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 32) {
1014  // Only handle the cases where the splat size agrees with the size
1015  // of the SplatValue here.
1016  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1017  const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1018  SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1019 
1020  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1021  SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1022 
1023  if (Hi)
1024  Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1025 
1026  if (Lo)
1027  Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1028  Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1029 
1030  assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!");
1031  Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
1032 
1033  } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 64 &&
1034  (ABI.IsN32() || ABI.IsN64())) {
1035  // N32 and N64 can perform some tricks that O32 can't for signed 32 bit
1036  // integers due to having 64bit registers. lui will cause the necessary
1037  // zero/sign extension.
1038  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1039  const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1040  SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1041 
1042  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1043  SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1044 
1045  if (Hi)
1046  Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1047 
1048  if (Lo)
1049  Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1050  Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1051 
1052  Res = CurDAG->getMachineNode(
1053  Mips::SUBREG_TO_REG, DL, MVT::i64,
1054  CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1055  SDValue(Res, 0),
1056  CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1057 
1058  Res =
1059  CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1060 
1061  } else if (SplatValue.isSignedIntN(64)) {
1062  // If we have a 64 bit Splat value, we perform a similar sequence to the
1063  // above:
1064  //
1065  // MIPS32: MIPS64:
1066  // lui $res, %highest(val) lui $res, %highest(val)
1067  // ori $res, $res, %higher(val) ori $res, $res, %higher(val)
1068  // lui $res2, %hi(val) lui $res2, %hi(val)
1069  // ori $res2, %res2, %lo(val) ori $res2, %res2, %lo(val)
1070  // $res3 = fill $res2 dinsu $res, $res2, 0, 32
1071  // $res4 = insert.w $res3[1], $res fill.d $res
1072  // splat.d $res4, 0
1073  //
1074  // The ability to use dinsu is guaranteed as MSA requires MIPSR5. This saves
1075  // having to materialize the value by shifts and ors.
1076  //
1077  // FIXME: Implement the preferred sequence for MIPS64R6:
1078  //
1079  // MIPS64R6:
1080  // ori $res, $zero, %lo(val)
1081  // daui $res, $res, %hi(val)
1082  // dahi $res, $res, %higher(val)
1083  // dati $res, $res, %highest(cal)
1084  // fill.d $res
1085  //
1086 
1087  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1088  const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1089  const unsigned Higher = SplatValue.lshr(32).getLoBits(16).getZExtValue();
1090  const unsigned Highest = SplatValue.lshr(48).getLoBits(16).getZExtValue();
1091 
1092  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1093  SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1094  SDValue HigherVal = CurDAG->getTargetConstant(Higher, DL, MVT::i32);
1095  SDValue HighestVal = CurDAG->getTargetConstant(Highest, DL, MVT::i32);
1096  SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1097 
1098  // Independent of whether we're targeting MIPS64 or not, the basic
1099  // operations are the same. Also, directly use the $zero register if
1100  // the 16 bit chunk is zero.
1101  //
1102  // For optimization purposes we always synthesize the splat value as
1103  // an i32 value, then if we're targetting MIPS64, use SUBREG_TO_REG
1104  // just before combining the values with dinsu to produce an i64. This
1105  // enables SelectionDAG to aggressively share components of splat values
1106  // where possible.
1107  //
1108  // FIXME: This is the general constant synthesis problem. This code
1109  // should be factored out into a class shared between all the
1110  // classes that need it. Specifically, for a splat size of 64
1111  // bits that's a negative number we can do better than LUi/ORi
1112  // for the upper 32bits.
1113 
1114  if (Hi)
1115  Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1116 
1117  if (Lo)
1118  Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1119  Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1120 
1121  SDNode *HiRes;
1122  if (Highest)
1123  HiRes = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HighestVal);
1124 
1125  if (Higher)
1126  HiRes = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1127  Highest ? SDValue(HiRes, 0) : ZeroVal,
1128  HigherVal);
1129 
1130 
1131  if (ABI.IsO32()) {
1132  Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32,
1133  (Hi || Lo) ? SDValue(Res, 0) : ZeroVal);
1134 
1135  Res = CurDAG->getMachineNode(
1136  Mips::INSERT_W, DL, MVT::v4i32, SDValue(Res, 0),
1137  (Highest || Higher) ? SDValue(HiRes, 0) : ZeroVal,
1138  CurDAG->getTargetConstant(1, DL, MVT::i32));
1139 
1141  const TargetRegisterClass *RC =
1142  TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1143 
1144  Res = CurDAG->getMachineNode(
1145  Mips::COPY_TO_REGCLASS, DL, ViaVecTy, SDValue(Res, 0),
1146  CurDAG->getTargetConstant(RC->getID(), DL, MVT::i32));
1147 
1148  Res = CurDAG->getMachineNode(
1149  Mips::SPLATI_D, DL, MVT::v2i64, SDValue(Res, 0),
1150  CurDAG->getTargetConstant(0, DL, MVT::i32));
1151  } else if (ABI.IsN64() || ABI.IsN32()) {
1152 
1153  SDValue Zero64Val = CurDAG->getRegister(Mips::ZERO_64, MVT::i64);
1154  const bool HiResNonZero = Highest || Higher;
1155  const bool ResNonZero = Hi || Lo;
1156 
1157  if (HiResNonZero)
1158  HiRes = CurDAG->getMachineNode(
1159  Mips::SUBREG_TO_REG, DL, MVT::i64,
1160  CurDAG->getTargetConstant(((Highest >> 15) & 0x1), DL, MVT::i64),
1161  SDValue(HiRes, 0),
1162  CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1163 
1164  if (ResNonZero)
1165  Res = CurDAG->getMachineNode(
1166  Mips::SUBREG_TO_REG, DL, MVT::i64,
1167  CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1168  SDValue(Res, 0),
1169  CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1170 
1171  // We have 3 cases:
1172  // The HiRes is nonzero but Res is $zero => dsll32 HiRes, 0
1173  // The Res is nonzero but HiRes is $zero => dinsu Res, $zero, 32, 32
1174  // Both are non zero => dinsu Res, HiRes, 32, 32
1175  //
1176  // The obvious "missing" case is when both are zero, but that case is
1177  // handled by the ldi case.
1178  if (ResNonZero) {
1179  IntegerType *Int32Ty =
1181  const ConstantInt *Const32 = ConstantInt::get(Int32Ty, 32);
1182  SDValue Ops[4] = {HiResNonZero ? SDValue(HiRes, 0) : Zero64Val,
1183  CurDAG->getConstant(*Const32, DL, MVT::i32),
1184  CurDAG->getConstant(*Const32, DL, MVT::i32),
1185  SDValue(Res, 0)};
1186 
1187  Res = CurDAG->getMachineNode(Mips::DINSU, DL, MVT::i64, Ops);
1188  } else if (HiResNonZero) {
1189  Res = CurDAG->getMachineNode(
1190  Mips::DSLL32, DL, MVT::i64, SDValue(HiRes, 0),
1191  CurDAG->getTargetConstant(0, DL, MVT::i32));
1192  } else
1194  "Zero splat value handled by non-zero 64bit splat synthesis!");
1195 
1196  Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1197  } else
1198  llvm_unreachable("Unknown ABI in MipsISelDAGToDAG!");
1199 
1200  } else
1201  return false;
1202 
1203  if (ResVecTy != ViaVecTy) {
1204  // If LdiOp is writing to a different register class to ResVecTy, then
1205  // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
1206  // since the source and destination register sets contain the same
1207  // registers.
1209  MVT ResVecTySimple = ResVecTy.getSimpleVT();
1210  const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
1211  Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
1212  ResVecTy, SDValue(Res, 0),
1213  CurDAG->getTargetConstant(RC->getID(), DL,
1214  MVT::i32));
1215  }
1216 
1217  ReplaceNode(Node, Res);
1218  return true;
1219  }
1220 
1221  }
1222 
1223  return false;
1224 }
1225 
1226 bool MipsSEDAGToDAGISel::
1227 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
1228  std::vector<SDValue> &OutOps) {
1229  SDValue Base, Offset;
1230 
1231  switch(ConstraintID) {
1232  default:
1233  llvm_unreachable("Unexpected asm memory constraint");
1234  // All memory constraints can at least accept raw pointers.
1236  OutOps.push_back(Op);
1237  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1238  return false;
1241  if (selectAddrRegImm16(Op, Base, Offset)) {
1242  OutOps.push_back(Base);
1243  OutOps.push_back(Offset);
1244  return false;
1245  }
1246  OutOps.push_back(Op);
1247  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1248  return false;
1250  // The 'R' constraint is supposed to be much more complicated than this.
1251  // However, it's becoming less useful due to architectural changes and
1252  // ought to be replaced by other constraints such as 'ZC'.
1253  // For now, support 9-bit signed offsets which is supportable by all
1254  // subtargets for all instructions.
1255  if (selectAddrRegImm9(Op, Base, Offset)) {
1256  OutOps.push_back(Base);
1257  OutOps.push_back(Offset);
1258  return false;
1259  }
1260  OutOps.push_back(Op);
1261  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1262  return false;
1264  // ZC matches whatever the pref, ll, and sc instructions can handle for the
1265  // given subtarget.
1266  if (Subtarget->inMicroMipsMode()) {
1267  // On microMIPS, they can handle 12-bit offsets.
1268  if (selectAddrRegImm12(Op, Base, Offset)) {
1269  OutOps.push_back(Base);
1270  OutOps.push_back(Offset);
1271  return false;
1272  }
1273  } else if (Subtarget->hasMips32r6()) {
1274  // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
1275  if (selectAddrRegImm9(Op, Base, Offset)) {
1276  OutOps.push_back(Base);
1277  OutOps.push_back(Offset);
1278  return false;
1279  }
1280  } else if (selectAddrRegImm16(Op, Base, Offset)) {
1281  // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
1282  OutOps.push_back(Base);
1283  OutOps.push_back(Offset);
1284  return false;
1285  }
1286  // In all cases, 0-bit offsets are acceptable.
1287  OutOps.push_back(Op);
1288  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1289  return false;
1290  }
1291  return true;
1292 }
1293 
1296  return new MipsSEDAGToDAGISel(TM, OptLevel);
1297 }
bool isABI_FPXX() const
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:137
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
SDNode * SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type...
EVT getValueType() const
Return the ValueType of the referenced return value.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool hasMTHC1() const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:320
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
FunctionPass * createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel)
bool inMips16Mode() const
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
Definition: ISDOpcodes.h:130
unsigned getValueSizeInBits(unsigned ResNo) const
Returns MVT::getSizeInBits(getValueType(ResNo)).
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
SDNode * getNode() const
get the SDNode which holds the desired result
bool isPHI() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineFunction * MF
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1515
return AArch64::GPR64RegClass contains(Reg)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
AnalysisUsage & addRequired()
static use_iterator use_end()
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
bool inMicroMipsMode() const
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
const TargetLowering * TLI
bool isGP64bit() const
bool hasMips32r6() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:473
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:413
bool IsN32() const
Definition: MipsABIInfo.h:42
unsigned getID() const
Return the register class ID number.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
int64_t getSExtValue() const
bool IsN64() const
Definition: MipsABIInfo.h:43
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
SDValue getTargetFrameIndex(int FI, EVT VT)
Definition: SelectionDAG.h:643
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
int32_t exactLogBase2() const
Definition: APInt.h:1794
const InstSeq & Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu)
Analyze - Get an instruction sequence to load immediate Imm.
void setReg(Register Reg)
Change the register this operand corresponds to.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:592
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:150
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:351
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:165
CodeGenOpt::Level OptLevel
unsigned const MachineRegisterInfo * MRI
unsigned countPopulation() const
Count the number of bits set.
Definition: APInt.h:1664
const MipsSubtarget * Subtarget
Keep a pointer to the MipsSubtarget around so that we can make the right decision when generating cod...
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MachineInstr.h:621
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const SDValue & getOperand(unsigned Num) const
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
Represent the analysis usage information of a pass.
bool isExactlyValue(double V) const
We don&#39;t rely on operator== working on double values, as it returns true for things that are clearly ...
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool IsO32() const
Definition: MipsABIInfo.h:41
Class to represent integer types.
Definition: DerivedTypes.h:40
bool isIntN(unsigned N) const
Check if this APInt has an N-bits unsigned integer value.
Definition: APInt.h:449
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Extended Value Type.
Definition: ValueTypes.h:33
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:397
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:239
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isLittle() const
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
MachineOperand class - Representation of each machine instruction operand.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:640
Represents one node in the SelectionDAG.
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:691
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Class for arbitrary precision integers.
Definition: APInt.h:69
A "pseudo-class" with methods for operating on BUILD_VECTORs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:717
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
use_iterator use_begin(unsigned RegNo) const
xray Insert XRay ops
bool is128BitVector() const
Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:181
bool isPositionIndependent() const
#define N
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t Size
Definition: Profile.cpp:46
bool useOddSPReg() const
MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
unsigned getOpcode() const
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:455
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
const TargetLowering * getTargetLowering() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
SDValue getRegister(unsigned Reg, EVT VT)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:258
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align)
Returns the offset to the next integer (mod 2**64) that is greater than or equal to Value and is a mu...
Definition: MathExtras.h:731
IRTranslator LLVM IR MI
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
Legacy analysis pass which computes a DominatorTree.
Definition: Dominators.h:259
Register getReg() const
getReg - Returns the register number.
const SDValue & getOperand(unsigned i) const
uint64_t getZExtValue() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool isFP64bit() const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasMSA() const
IntegerType * Int32Ty