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MipsSEISelDAGToDAG.cpp
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1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsSEISelDAGToDAG.h"
15 #include "Mips.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
25 #include "llvm/IR/CFG.h"
26 #include "llvm/IR/Dominators.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "mips-isel"
38 
39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40  Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
41  if (Subtarget->inMips16Mode())
42  return false;
44 }
45 
46 void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
49 }
50 
51 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
53  MachineInstrBuilder MIB(MF, &MI);
54  unsigned Mask = MI.getOperand(1).getImm();
55  unsigned Flag =
57 
58  if (Mask & 1)
59  MIB.addReg(Mips::DSPPos, Flag);
60 
61  if (Mask & 2)
62  MIB.addReg(Mips::DSPSCount, Flag);
63 
64  if (Mask & 4)
65  MIB.addReg(Mips::DSPCarry, Flag);
66 
67  if (Mask & 8)
68  MIB.addReg(Mips::DSPOutFlag, Flag);
69 
70  if (Mask & 16)
71  MIB.addReg(Mips::DSPCCond, Flag);
72 
73  if (Mask & 32)
74  MIB.addReg(Mips::DSPEFI, Flag);
75 }
76 
77 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
78  switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
79  default:
80  llvm_unreachable("Could not map int to register");
81  case 0: return Mips::MSAIR;
82  case 1: return Mips::MSACSR;
83  case 2: return Mips::MSAAccess;
84  case 3: return Mips::MSASave;
85  case 4: return Mips::MSAModify;
86  case 5: return Mips::MSARequest;
87  case 6: return Mips::MSAMap;
88  case 7: return Mips::MSAUnmap;
89  }
90 }
91 
92 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
93  const MachineInstr& MI) {
94  unsigned DstReg = 0, ZeroReg = 0;
95 
96  // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
97  if ((MI.getOpcode() == Mips::ADDiu) &&
98  (MI.getOperand(1).getReg() == Mips::ZERO) &&
99  (MI.getOperand(2).isImm()) &&
100  (MI.getOperand(2).getImm() == 0)) {
101  DstReg = MI.getOperand(0).getReg();
102  ZeroReg = Mips::ZERO;
103  } else if ((MI.getOpcode() == Mips::DADDiu) &&
104  (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
105  (MI.getOperand(2).isImm()) &&
106  (MI.getOperand(2).getImm() == 0)) {
107  DstReg = MI.getOperand(0).getReg();
108  ZeroReg = Mips::ZERO_64;
109  }
110 
111  if (!DstReg)
112  return false;
113 
114  // Replace uses with ZeroReg.
115  for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
116  E = MRI->use_end(); U != E;) {
117  MachineOperand &MO = *U;
118  unsigned OpNo = U.getOperandNo();
119  MachineInstr *MI = MO.getParent();
120  ++U;
121 
122  // Do not replace if it is a phi's operand or is tied to def operand.
123  if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
124  continue;
125 
126  // Also, we have to check that the register class of the operand
127  // contains the zero register.
128  if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
129  continue;
130 
131  MO.setReg(ZeroReg);
132  }
133 
134  return true;
135 }
136 
137 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
138  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
139 
140  if (!MipsFI->globalBaseRegSet())
141  return;
142 
143  MachineBasicBlock &MBB = MF.front();
147  DebugLoc DL;
148  unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
149  const TargetRegisterClass *RC;
150  const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
151  RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
152 
153  V0 = RegInfo.createVirtualRegister(RC);
154  V1 = RegInfo.createVirtualRegister(RC);
155 
156  if (ABI.IsN64()) {
157  MF.getRegInfo().addLiveIn(Mips::T9_64);
158  MBB.addLiveIn(Mips::T9_64);
159 
160  // lui $v0, %hi(%neg(%gp_rel(fname)))
161  // daddu $v1, $v0, $t9
162  // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
163  const GlobalValue *FName = &MF.getFunction();
164  BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
165  .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
166  BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
167  .addReg(Mips::T9_64);
168  BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
170  return;
171  }
172 
173  if (!MF.getTarget().isPositionIndependent()) {
174  // Set global register to __gnu_local_gp.
175  //
176  // lui $v0, %hi(__gnu_local_gp)
177  // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
178  BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
179  .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
180  BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
181  .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
182  return;
183  }
184 
185  MF.getRegInfo().addLiveIn(Mips::T9);
186  MBB.addLiveIn(Mips::T9);
187 
188  if (ABI.IsN32()) {
189  // lui $v0, %hi(%neg(%gp_rel(fname)))
190  // addu $v1, $v0, $t9
191  // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
192  const GlobalValue *FName = &MF.getFunction();
193  BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
194  .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
195  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
196  BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
198  return;
199  }
200 
201  assert(ABI.IsO32());
202 
203  // For O32 ABI, the following instruction sequence is emitted to initialize
204  // the global base register:
205  //
206  // 0. lui $2, %hi(_gp_disp)
207  // 1. addiu $2, $2, %lo(_gp_disp)
208  // 2. addu $globalbasereg, $2, $t9
209  //
210  // We emit only the last instruction here.
211  //
212  // GNU linker requires that the first two instructions appear at the beginning
213  // of a function and no instructions be inserted before or between them.
214  // The two instructions are emitted during lowering to MC layer in order to
215  // avoid any reordering.
216  //
217  // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
218  // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
219  // reads it.
220  MF.getRegInfo().addLiveIn(Mips::V0);
221  MBB.addLiveIn(Mips::V0);
222  BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
223  .addReg(Mips::V0).addReg(Mips::T9);
224 }
225 
226 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
227  initGlobalBaseReg(MF);
228 
229  MachineRegisterInfo *MRI = &MF.getRegInfo();
230 
231  for (auto &MBB: MF) {
232  for (auto &MI: MBB) {
233  switch (MI.getOpcode()) {
234  case Mips::RDDSP:
235  addDSPCtrlRegOperands(false, MI, MF);
236  break;
237  case Mips::WRDSP:
238  addDSPCtrlRegOperands(true, MI, MF);
239  break;
240  case Mips::BuildPairF64_64:
241  case Mips::ExtractElementF64_64:
242  if (!Subtarget->useOddSPReg()) {
243  MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
244  break;
245  }
247  case Mips::BuildPairF64:
249  if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
250  MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
251  break;
252  default:
253  replaceUsesWithZeroReg(MRI, MI);
254  }
255  }
256  }
257 }
258 
259 void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
260  SDValue InFlag = Node->getOperand(2);
261  unsigned Opc = InFlag.getOpcode();
262  SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
263  EVT VT = LHS.getValueType();
264 
265  // In the base case, we can rely on the carry bit from the addsc
266  // instruction.
267  if (Opc == ISD::ADDC) {
268  SDValue Ops[3] = {LHS, RHS, InFlag};
269  CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Ops);
270  return;
271  }
272 
273  assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!");
274 
275  // The more complex case is when there is a chain of ISD::ADDE nodes like:
276  // (adde (adde (adde (addc a b) c) d) e).
277  //
278  // The addwc instruction does not write to the carry bit, instead it writes
279  // to bit 20 of the dsp control register. To match this series of nodes, each
280  // intermediate adde node must be expanded to write the carry bit before the
281  // addition.
282 
283  // Start by reading the overflow field for addsc and moving the value to the
284  // carry field. The usage of 1 here with MipsISD::RDDSP / Mips::WRDSP
285  // corresponds to reading/writing the entire control register to/from a GPR.
286 
287  SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32);
288 
289  SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
290 
291  SDNode *DSPCtrlField =
292  CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, MVT::Glue, CstOne, InFlag);
293 
294  SDNode *Carry = CurDAG->getMachineNode(
295  Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
296 
297  SDValue Ops[4] = {SDValue(DSPCtrlField, 0),
298  CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne,
299  SDValue(Carry, 0)};
300  SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops);
301 
302  // My reading of the MIPS DSP 3.01 specification isn't as clear as I
303  // would like about whether bit 20 always gets overwritten by addwc.
304  // Hence take an extremely conservative view and presume it's sticky. We
305  // therefore need to clear it.
306 
307  SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
308 
309  SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)};
310  SDNode *DSPCtrlFinal = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
311 
312  SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
313  SDValue(DSPCtrlFinal, 0), CstOne);
314 
315  SDValue Operands[3] = {LHS, RHS, SDValue(WrDSP, 0)};
316  CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Operands);
317 }
318 
319 /// Match frameindex
320 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
321  SDValue &Offset) const {
322  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
323  EVT ValTy = Addr.getValueType();
324 
325  Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
326  Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
327  return true;
328  }
329  return false;
330 }
331 
332 /// Match frameindex+offset and frameindex|offset
333 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
334  SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits,
335  unsigned ShiftAmount = 0) const {
336  if (CurDAG->isBaseWithConstantOffset(Addr)) {
338  if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
339  EVT ValTy = Addr.getValueType();
340 
341  // If the first operand is a FI, get the TargetFI Node
342  if (FrameIndexSDNode *FIN =
343  dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
344  Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
345  else {
346  Base = Addr.getOperand(0);
347  // If base is a FI, additional offset calculation is done in
348  // eliminateFrameIndex, otherwise we need to check the alignment
349  if (OffsetToAlignment(CN->getZExtValue(), 1ull << ShiftAmount) != 0)
350  return false;
351  }
352 
353  Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
354  ValTy);
355  return true;
356  }
357  }
358  return false;
359 }
360 
361 /// ComplexPattern used on MipsInstrInfo
362 /// Used on Mips Load/Store instructions
363 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
364  SDValue &Offset) const {
365  // if Address is FI, get the TargetFrameIndex.
366  if (selectAddrFrameIndex(Addr, Base, Offset))
367  return true;
368 
369  // on PIC code Load GA
370  if (Addr.getOpcode() == MipsISD::Wrapper) {
371  Base = Addr.getOperand(0);
372  Offset = Addr.getOperand(1);
373  return true;
374  }
375 
376  if (!TM.isPositionIndependent()) {
377  if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
379  return false;
380  }
381 
382  // Addresses of the form FI+const or FI|const
383  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
384  return true;
385 
386  // Operand is a result from an ADD.
387  if (Addr.getOpcode() == ISD::ADD) {
388  // When loading from constant pools, load the lower address part in
389  // the instruction itself. Example, instead of:
390  // lui $2, %hi($CPI1_0)
391  // addiu $2, $2, %lo($CPI1_0)
392  // lwc1 $f0, 0($2)
393  // Generate:
394  // lui $2, %hi($CPI1_0)
395  // lwc1 $f0, %lo($CPI1_0)($2)
396  if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
397  Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
398  SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
399  if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
400  isa<JumpTableSDNode>(Opnd0)) {
401  Base = Addr.getOperand(0);
402  Offset = Opnd0;
403  return true;
404  }
405  }
406  }
407 
408  return false;
409 }
410 
411 /// ComplexPattern used on MipsInstrInfo
412 /// Used on Mips Load/Store instructions
413 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
414  SDValue &Offset) const {
415  Base = Addr;
416  Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
417  return true;
418 }
419 
420 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
421  SDValue &Offset) const {
422  return selectAddrRegImm(Addr, Base, Offset) ||
423  selectAddrDefault(Addr, Base, Offset);
424 }
425 
426 bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
427  SDValue &Offset) const {
428  if (selectAddrFrameIndex(Addr, Base, Offset))
429  return true;
430 
431  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
432  return true;
433 
434  return false;
435 }
436 
437 /// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
438 bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base,
439  SDValue &Offset) const {
440  if (selectAddrFrameIndex(Addr, Base, Offset))
441  return true;
442 
443  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 11))
444  return true;
445 
446  return false;
447 }
448 
449 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
450 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
451  SDValue &Offset) const {
452  if (selectAddrFrameIndex(Addr, Base, Offset))
453  return true;
454 
455  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
456  return true;
457 
458  return false;
459 }
460 
461 bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
462  SDValue &Offset) const {
463  if (selectAddrFrameIndex(Addr, Base, Offset))
464  return true;
465 
466  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
467  return true;
468 
469  return false;
470 }
471 
472 bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
473  SDValue &Offset) const {
474  return selectAddrRegImm11(Addr, Base, Offset) ||
475  selectAddrDefault(Addr, Base, Offset);
476 }
477 
478 bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
479  SDValue &Offset) const {
480  return selectAddrRegImm12(Addr, Base, Offset) ||
481  selectAddrDefault(Addr, Base, Offset);
482 }
483 
484 bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
485  SDValue &Offset) const {
486  return selectAddrRegImm16(Addr, Base, Offset) ||
487  selectAddrDefault(Addr, Base, Offset);
488 }
489 
490 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
491  SDValue &Offset) const {
492  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
493  if (isa<FrameIndexSDNode>(Base))
494  return false;
495 
496  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
497  unsigned CnstOff = CN->getZExtValue();
498  return (CnstOff == (CnstOff & 0x3c));
499  }
500 
501  return false;
502  }
503 
504  // For all other cases where "lw" would be selected, don't select "lw16"
505  // because it would result in additional instructions to prepare operands.
506  if (selectAddrRegImm(Addr, Base, Offset))
507  return false;
508 
509  return selectAddrDefault(Addr, Base, Offset);
510 }
511 
512 bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
513  SDValue &Offset) const {
514 
515  if (selectAddrFrameIndex(Addr, Base, Offset))
516  return true;
517 
518  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
519  return true;
520 
521  return selectAddrDefault(Addr, Base, Offset);
522 }
523 
524 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
525  SDValue &Offset) const {
526  if (selectAddrFrameIndex(Addr, Base, Offset))
527  return true;
528 
529  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 1))
530  return true;
531 
532  return selectAddrDefault(Addr, Base, Offset);
533 }
534 
535 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
536  SDValue &Offset) const {
537  if (selectAddrFrameIndex(Addr, Base, Offset))
538  return true;
539 
540  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 2))
541  return true;
542 
543  return selectAddrDefault(Addr, Base, Offset);
544 }
545 
546 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
547  SDValue &Offset) const {
548  if (selectAddrFrameIndex(Addr, Base, Offset))
549  return true;
550 
551  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 3))
552  return true;
553 
554  return selectAddrDefault(Addr, Base, Offset);
555 }
556 
557 // Select constant vector splats.
558 //
559 // Returns true and sets Imm if:
560 // * MSA is enabled
561 // * N is a ISD::BUILD_VECTOR representing a constant splat
562 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
563  unsigned MinSizeInBits) const {
564  if (!Subtarget->hasMSA())
565  return false;
566 
568 
569  if (!Node)
570  return false;
571 
572  APInt SplatValue, SplatUndef;
573  unsigned SplatBitSize;
574  bool HasAnyUndefs;
575 
576  if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
577  MinSizeInBits, !Subtarget->isLittle()))
578  return false;
579 
580  Imm = SplatValue;
581 
582  return true;
583 }
584 
585 // Select constant vector splats.
586 //
587 // In addition to the requirements of selectVSplat(), this function returns
588 // true and sets Imm if:
589 // * The splat value is the same width as the elements of the vector
590 // * The splat value fits in an integer with the specified signed-ness and
591 // width.
592 //
593 // This function looks through ISD::BITCAST nodes.
594 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
595 // sometimes a shuffle in big-endian mode.
596 //
597 // It's worth noting that this function is not used as part of the selection
598 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
599 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
600 // MipsSEDAGToDAGISel::selectNode.
601 bool MipsSEDAGToDAGISel::
602 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
603  unsigned ImmBitSize) const {
604  APInt ImmValue;
605  EVT EltTy = N->getValueType(0).getVectorElementType();
606 
607  if (N->getOpcode() == ISD::BITCAST)
608  N = N->getOperand(0);
609 
610  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
611  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
612 
613  if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
614  (!Signed && ImmValue.isIntN(ImmBitSize))) {
615  Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
616  return true;
617  }
618  }
619 
620  return false;
621 }
622 
623 // Select constant vector splats.
624 bool MipsSEDAGToDAGISel::
625 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
626  return selectVSplatCommon(N, Imm, false, 1);
627 }
628 
629 bool MipsSEDAGToDAGISel::
630 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
631  return selectVSplatCommon(N, Imm, false, 2);
632 }
633 
634 bool MipsSEDAGToDAGISel::
635 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
636  return selectVSplatCommon(N, Imm, false, 3);
637 }
638 
639 // Select constant vector splats.
640 bool MipsSEDAGToDAGISel::
641 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
642  return selectVSplatCommon(N, Imm, false, 4);
643 }
644 
645 // Select constant vector splats.
646 bool MipsSEDAGToDAGISel::
647 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
648  return selectVSplatCommon(N, Imm, false, 5);
649 }
650 
651 // Select constant vector splats.
652 bool MipsSEDAGToDAGISel::
653 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
654  return selectVSplatCommon(N, Imm, false, 6);
655 }
656 
657 // Select constant vector splats.
658 bool MipsSEDAGToDAGISel::
659 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
660  return selectVSplatCommon(N, Imm, false, 8);
661 }
662 
663 // Select constant vector splats.
664 bool MipsSEDAGToDAGISel::
665 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
666  return selectVSplatCommon(N, Imm, true, 5);
667 }
668 
669 // Select constant vector splats whose value is a power of 2.
670 //
671 // In addition to the requirements of selectVSplat(), this function returns
672 // true and sets Imm if:
673 // * The splat value is the same width as the elements of the vector
674 // * The splat value is a power of two.
675 //
676 // This function looks through ISD::BITCAST nodes.
677 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
678 // sometimes a shuffle in big-endian mode.
679 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
680  APInt ImmValue;
681  EVT EltTy = N->getValueType(0).getVectorElementType();
682 
683  if (N->getOpcode() == ISD::BITCAST)
684  N = N->getOperand(0);
685 
686  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
687  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
688  int32_t Log2 = ImmValue.exactLogBase2();
689 
690  if (Log2 != -1) {
691  Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
692  return true;
693  }
694  }
695 
696  return false;
697 }
698 
699 // Select constant vector splats whose value only has a consecutive sequence
700 // of left-most bits set (e.g. 0b11...1100...00).
701 //
702 // In addition to the requirements of selectVSplat(), this function returns
703 // true and sets Imm if:
704 // * The splat value is the same width as the elements of the vector
705 // * The splat value is a consecutive sequence of left-most bits.
706 //
707 // This function looks through ISD::BITCAST nodes.
708 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
709 // sometimes a shuffle in big-endian mode.
710 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
711  APInt ImmValue;
712  EVT EltTy = N->getValueType(0).getVectorElementType();
713 
714  if (N->getOpcode() == ISD::BITCAST)
715  N = N->getOperand(0);
716 
717  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
718  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
719  // Extract the run of set bits starting with bit zero from the bitwise
720  // inverse of ImmValue, and test that the inverse of this is the same
721  // as the original value.
722  if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
723 
724  Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
725  EltTy);
726  return true;
727  }
728  }
729 
730  return false;
731 }
732 
733 // Select constant vector splats whose value only has a consecutive sequence
734 // of right-most bits set (e.g. 0b00...0011...11).
735 //
736 // In addition to the requirements of selectVSplat(), this function returns
737 // true and sets Imm if:
738 // * The splat value is the same width as the elements of the vector
739 // * The splat value is a consecutive sequence of right-most bits.
740 //
741 // This function looks through ISD::BITCAST nodes.
742 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
743 // sometimes a shuffle in big-endian mode.
744 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
745  APInt ImmValue;
746  EVT EltTy = N->getValueType(0).getVectorElementType();
747 
748  if (N->getOpcode() == ISD::BITCAST)
749  N = N->getOperand(0);
750 
751  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
752  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
753  // Extract the run of set bits starting with bit zero, and test that the
754  // result is the same as the original value
755  if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
756  Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
757  EltTy);
758  return true;
759  }
760  }
761 
762  return false;
763 }
764 
765 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
766  SDValue &Imm) const {
767  APInt ImmValue;
768  EVT EltTy = N->getValueType(0).getVectorElementType();
769 
770  if (N->getOpcode() == ISD::BITCAST)
771  N = N->getOperand(0);
772 
773  if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
774  ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
775  int32_t Log2 = (~ImmValue).exactLogBase2();
776 
777  if (Log2 != -1) {
778  Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
779  return true;
780  }
781  }
782 
783  return false;
784 }
785 
786 bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
787  unsigned Opcode = Node->getOpcode();
788  SDLoc DL(Node);
789 
790  ///
791  // Instruction Selection not handled by the auto-generated
792  // tablegen selection should be handled here.
793  ///
794  switch(Opcode) {
795  default: break;
796 
797  case Mips::PseudoD_SELECT_I:
798  case Mips::PseudoD_SELECT_I64: {
800  SDValue cond = Node->getOperand(0);
801  SDValue Hi1 = Node->getOperand(1);
802  SDValue Lo1 = Node->getOperand(2);
803  SDValue Hi2 = Node->getOperand(3);
804  SDValue Lo2 = Node->getOperand(4);
805 
806  SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2};
807  EVT NodeTys[] = {VT, VT};
809  ? Mips::PseudoD_SELECT_I64
810  : Mips::PseudoD_SELECT_I,
811  DL, NodeTys, ops));
812  return true;
813  }
814 
815  case ISD::ADDE: {
816  selectAddE(Node, DL);
817  return true;
818  }
819 
820  case ISD::ConstantFP: {
822  if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
823  if (Subtarget->isGP64bit()) {
825  Mips::ZERO_64, MVT::i64);
826  ReplaceNode(Node,
827  CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
828  } else if (Subtarget->isFP64bit()) {
830  Mips::ZERO, MVT::i32);
831  ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL,
832  MVT::f64, Zero, Zero));
833  } else {
835  Mips::ZERO, MVT::i32);
837  MVT::f64, Zero, Zero));
838  }
839  return true;
840  }
841  break;
842  }
843 
844  case ISD::Constant: {
845  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
846  int64_t Imm = CN->getSExtValue();
847  unsigned Size = CN->getValueSizeInBits(0);
848 
849  if (isInt<32>(Imm))
850  break;
851 
852  MipsAnalyzeImmediate AnalyzeImm;
853 
854  const MipsAnalyzeImmediate::InstSeq &Seq =
855  AnalyzeImm.Analyze(Imm, Size, false);
856 
858  SDLoc DL(CN);
859  SDNode *RegOpnd;
860  SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
861  DL, MVT::i64);
862 
863  // The first instruction can be a LUi which is different from other
864  // instructions (ADDiu, ORI and SLL) in that it does not have a register
865  // operand.
866  if (Inst->Opc == Mips::LUi64)
867  RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
868  else
869  RegOpnd =
870  CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
871  CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
872  ImmOpnd);
873 
874  // The remaining instructions in the sequence are handled here.
875  for (++Inst; Inst != Seq.end(); ++Inst) {
876  ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
877  MVT::i64);
878  RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
879  SDValue(RegOpnd, 0), ImmOpnd);
880  }
881 
882  ReplaceNode(Node, RegOpnd);
883  return true;
884  }
885 
886  case ISD::INTRINSIC_W_CHAIN: {
887  switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
888  default:
889  break;
890 
891  case Intrinsic::mips_cfcmsa: {
892  SDValue ChainIn = Node->getOperand(0);
893  SDValue RegIdx = Node->getOperand(2);
894  SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
895  getMSACtrlReg(RegIdx), MVT::i32);
896  ReplaceNode(Node, Reg.getNode());
897  return true;
898  }
899  }
900  break;
901  }
902 
904  switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
905  default:
906  break;
907 
908  case Intrinsic::mips_move_v:
909  // Like an assignment but will always produce a move.v even if
910  // unnecessary.
911  ReplaceNode(Node, CurDAG->getMachineNode(Mips::MOVE_V, DL,
912  Node->getValueType(0),
913  Node->getOperand(1)));
914  return true;
915  }
916  break;
917  }
918 
919  case ISD::INTRINSIC_VOID: {
920  switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
921  default:
922  break;
923 
924  case Intrinsic::mips_ctcmsa: {
925  SDValue ChainIn = Node->getOperand(0);
926  SDValue RegIdx = Node->getOperand(2);
927  SDValue Value = Node->getOperand(3);
928  SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
929  getMSACtrlReg(RegIdx), Value);
930  ReplaceNode(Node, ChainOut.getNode());
931  return true;
932  }
933  }
934  break;
935  }
936 
937  // Manually match MipsISD::Ins nodes to get the correct instruction. It has
938  // to be done in this fashion so that we respect the differences between
939  // dins and dinsm, as the difference is that the size operand has the range
940  // 0 < size <= 32 for dins while dinsm has the range 2 <= size <= 64 which
941  // means SelectionDAGISel would have to test all the operands at once to
942  // match the instruction.
943  case MipsISD::Ins: {
944 
945  // Sanity checking for the node operands.
946  if (Node->getValueType(0) != MVT::i32 && Node->getValueType(0) != MVT::i64)
947  return false;
948 
949  if (Node->getNumOperands() != 4)
950  return false;
951 
952  if (Node->getOperand(1)->getOpcode() != ISD::Constant ||
953  Node->getOperand(2)->getOpcode() != ISD::Constant)
954  return false;
955 
956  MVT ResTy = Node->getSimpleValueType(0);
957  uint64_t Pos = Node->getConstantOperandVal(1);
958  uint64_t Size = Node->getConstantOperandVal(2);
959 
960  // Size has to be >0 for 'ins', 'dins' and 'dinsu'.
961  if (!Size)
962  return false;
963 
964  if (Pos + Size > 64)
965  return false;
966 
967  if (ResTy != MVT::i32 && ResTy != MVT::i64)
968  return false;
969 
970  unsigned Opcode = 0;
971  if (ResTy == MVT::i32) {
972  if (Pos + Size <= 32)
973  Opcode = Mips::INS;
974  } else {
975  if (Pos + Size <= 32)
976  Opcode = Mips::DINS;
977  else if (Pos < 32 && 1 < Size)
978  Opcode = Mips::DINSM;
979  else
980  Opcode = Mips::DINSU;
981  }
982 
983  if (Opcode) {
984  SDValue Ops[4] = {
985  Node->getOperand(0), CurDAG->getTargetConstant(Pos, DL, MVT::i32),
986  CurDAG->getTargetConstant(Size, DL, MVT::i32), Node->getOperand(3)};
987 
988  ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, ResTy, Ops));
989  return true;
990  }
991 
992  return false;
993  }
994 
995  case MipsISD::ThreadPointer: {
997  unsigned RdhwrOpc, DestReg;
998 
999  if (PtrVT == MVT::i32) {
1000  RdhwrOpc = Mips::RDHWR;
1001  DestReg = Mips::V1;
1002  } else {
1003  RdhwrOpc = Mips::RDHWR64;
1004  DestReg = Mips::V1_64;
1005  }
1006 
1007  SDNode *Rdhwr =
1008  CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0),
1009  CurDAG->getRegister(Mips::HWR29, MVT::i32),
1010  CurDAG->getTargetConstant(0, DL, MVT::i32));
1011  SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
1012  SDValue(Rdhwr, 0));
1013  SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
1014  ReplaceNode(Node, ResNode.getNode());
1015  return true;
1016  }
1017 
1018  case ISD::BUILD_VECTOR: {
1019  // Select appropriate ldi.[bhwd] instructions for constant splats of
1020  // 128-bit when MSA is enabled. Fixup any register class mismatches that
1021  // occur as a result.
1022  //
1023  // This allows the compiler to use a wider range of immediates than would
1024  // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
1025  // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
1026  // 0x01010101 } without using a constant pool. This would be sub-optimal
1027  // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
1028  // same set/ of registers. Similarly, ldi.h isn't capable of producing {
1029  // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
1030 
1031  const MipsABIInfo &ABI =
1032  static_cast<const MipsTargetMachine &>(TM).getABI();
1033 
1034  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
1035  APInt SplatValue, SplatUndef;
1036  unsigned SplatBitSize;
1037  bool HasAnyUndefs;
1038  unsigned LdiOp;
1039  EVT ResVecTy = BVN->getValueType(0);
1040  EVT ViaVecTy;
1041 
1042  if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
1043  return false;
1044 
1045  if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1046  HasAnyUndefs, 8,
1047  !Subtarget->isLittle()))
1048  return false;
1049 
1050  switch (SplatBitSize) {
1051  default:
1052  return false;
1053  case 8:
1054  LdiOp = Mips::LDI_B;
1055  ViaVecTy = MVT::v16i8;
1056  break;
1057  case 16:
1058  LdiOp = Mips::LDI_H;
1059  ViaVecTy = MVT::v8i16;
1060  break;
1061  case 32:
1062  LdiOp = Mips::LDI_W;
1063  ViaVecTy = MVT::v4i32;
1064  break;
1065  case 64:
1066  LdiOp = Mips::LDI_D;
1067  ViaVecTy = MVT::v2i64;
1068  break;
1069  }
1070 
1071  SDNode *Res;
1072 
1073  // If we have a signed 10 bit integer, we can splat it directly.
1074  //
1075  // If we have something bigger we can synthesize the value into a GPR and
1076  // splat from there.
1077  if (SplatValue.isSignedIntN(10)) {
1078  SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
1079  ViaVecTy.getVectorElementType());
1080 
1081  Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
1082  } else if (SplatValue.isSignedIntN(16) &&
1083  ((ABI.IsO32() && SplatBitSize < 64) ||
1084  (ABI.IsN32() || ABI.IsN64()))) {
1085  // Only handle signed 16 bit values when the element size is GPR width.
1086  // MIPS64 can handle all the cases but MIPS32 would need to handle
1087  // negative cases specifically here. Instead, handle those cases as
1088  // 64bit values.
1089 
1090  bool Is32BitSplat = ABI.IsO32() || SplatBitSize < 64;
1091  const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
1092  const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64;
1093  SDValue ZeroVal = CurDAG->getRegister(
1094  Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT);
1095 
1096  const unsigned FILLOp =
1097  SplatBitSize == 16
1098  ? Mips::FILL_H
1099  : (SplatBitSize == 32 ? Mips::FILL_W
1100  : (SplatBitSize == 64 ? Mips::FILL_D : 0));
1101 
1102  assert(FILLOp != 0 && "Unknown FILL Op for splat synthesis!");
1103  assert((!ABI.IsO32() || (FILLOp != Mips::FILL_D)) &&
1104  "Attempting to use fill.d on MIPS32!");
1105 
1106  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1107  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, SplatMVT);
1108 
1109  Res = CurDAG->getMachineNode(ADDiuOp, DL, SplatMVT, ZeroVal, LoVal);
1110  Res = CurDAG->getMachineNode(FILLOp, DL, ViaVecTy, SDValue(Res, 0));
1111 
1112  } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 32) {
1113  // Only handle the cases where the splat size agrees with the size
1114  // of the SplatValue here.
1115  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1116  const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1117  SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1118 
1119  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1120  SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1121 
1122  if (Hi)
1123  Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1124 
1125  if (Lo)
1126  Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1127  Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1128 
1129  assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!");
1130  Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
1131 
1132  } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 64 &&
1133  (ABI.IsN32() || ABI.IsN64())) {
1134  // N32 and N64 can perform some tricks that O32 can't for signed 32 bit
1135  // integers due to having 64bit registers. lui will cause the necessary
1136  // zero/sign extension.
1137  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1138  const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1139  SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1140 
1141  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1142  SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1143 
1144  if (Hi)
1145  Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1146 
1147  if (Lo)
1148  Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1149  Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1150 
1151  Res = CurDAG->getMachineNode(
1152  Mips::SUBREG_TO_REG, DL, MVT::i64,
1153  CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1154  SDValue(Res, 0),
1155  CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1156 
1157  Res =
1158  CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1159 
1160  } else if (SplatValue.isSignedIntN(64)) {
1161  // If we have a 64 bit Splat value, we perform a similar sequence to the
1162  // above:
1163  //
1164  // MIPS32: MIPS64:
1165  // lui $res, %highest(val) lui $res, %highest(val)
1166  // ori $res, $res, %higher(val) ori $res, $res, %higher(val)
1167  // lui $res2, %hi(val) lui $res2, %hi(val)
1168  // ori $res2, %res2, %lo(val) ori $res2, %res2, %lo(val)
1169  // $res3 = fill $res2 dinsu $res, $res2, 0, 32
1170  // $res4 = insert.w $res3[1], $res fill.d $res
1171  // splat.d $res4, 0
1172  //
1173  // The ability to use dinsu is guaranteed as MSA requires MIPSR5. This saves
1174  // having to materialize the value by shifts and ors.
1175  //
1176  // FIXME: Implement the preferred sequence for MIPS64R6:
1177  //
1178  // MIPS64R6:
1179  // ori $res, $zero, %lo(val)
1180  // daui $res, $res, %hi(val)
1181  // dahi $res, $res, %higher(val)
1182  // dati $res, $res, %highest(cal)
1183  // fill.d $res
1184  //
1185 
1186  const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1187  const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1188  const unsigned Higher = SplatValue.lshr(32).getLoBits(16).getZExtValue();
1189  const unsigned Highest = SplatValue.lshr(48).getLoBits(16).getZExtValue();
1190 
1191  SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1192  SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1193  SDValue HigherVal = CurDAG->getTargetConstant(Higher, DL, MVT::i32);
1194  SDValue HighestVal = CurDAG->getTargetConstant(Highest, DL, MVT::i32);
1195  SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1196 
1197  // Independent of whether we're targeting MIPS64 or not, the basic
1198  // operations are the same. Also, directly use the $zero register if
1199  // the 16 bit chunk is zero.
1200  //
1201  // For optimization purposes we always synthesize the splat value as
1202  // an i32 value, then if we're targetting MIPS64, use SUBREG_TO_REG
1203  // just before combining the values with dinsu to produce an i64. This
1204  // enables SelectionDAG to aggressively share components of splat values
1205  // where possible.
1206  //
1207  // FIXME: This is the general constant synthesis problem. This code
1208  // should be factored out into a class shared between all the
1209  // classes that need it. Specifically, for a splat size of 64
1210  // bits that's a negative number we can do better than LUi/ORi
1211  // for the upper 32bits.
1212 
1213  if (Hi)
1214  Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1215 
1216  if (Lo)
1217  Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1218  Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1219 
1220  SDNode *HiRes;
1221  if (Highest)
1222  HiRes = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HighestVal);
1223 
1224  if (Higher)
1225  HiRes = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1226  Highest ? SDValue(HiRes, 0) : ZeroVal,
1227  HigherVal);
1228 
1229 
1230  if (ABI.IsO32()) {
1231  Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32,
1232  (Hi || Lo) ? SDValue(Res, 0) : ZeroVal);
1233 
1234  Res = CurDAG->getMachineNode(
1235  Mips::INSERT_W, DL, MVT::v4i32, SDValue(Res, 0),
1236  (Highest || Higher) ? SDValue(HiRes, 0) : ZeroVal,
1237  CurDAG->getTargetConstant(1, DL, MVT::i32));
1238 
1240  const TargetRegisterClass *RC =
1241  TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1242 
1243  Res = CurDAG->getMachineNode(
1244  Mips::COPY_TO_REGCLASS, DL, ViaVecTy, SDValue(Res, 0),
1245  CurDAG->getTargetConstant(RC->getID(), DL, MVT::i32));
1246 
1247  Res = CurDAG->getMachineNode(
1248  Mips::SPLATI_D, DL, MVT::v2i64, SDValue(Res, 0),
1249  CurDAG->getTargetConstant(0, DL, MVT::i32));
1250  } else if (ABI.IsN64() || ABI.IsN32()) {
1251 
1252  SDValue Zero64Val = CurDAG->getRegister(Mips::ZERO_64, MVT::i64);
1253  const bool HiResNonZero = Highest || Higher;
1254  const bool ResNonZero = Hi || Lo;
1255 
1256  if (HiResNonZero)
1257  HiRes = CurDAG->getMachineNode(
1258  Mips::SUBREG_TO_REG, DL, MVT::i64,
1259  CurDAG->getTargetConstant(((Highest >> 15) & 0x1), DL, MVT::i64),
1260  SDValue(HiRes, 0),
1261  CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1262 
1263  if (ResNonZero)
1264  Res = CurDAG->getMachineNode(
1265  Mips::SUBREG_TO_REG, DL, MVT::i64,
1266  CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1267  SDValue(Res, 0),
1268  CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1269 
1270  // We have 3 cases:
1271  // The HiRes is nonzero but Res is $zero => dsll32 HiRes, 0
1272  // The Res is nonzero but HiRes is $zero => dinsu Res, $zero, 32, 32
1273  // Both are non zero => dinsu Res, HiRes, 32, 32
1274  //
1275  // The obvious "missing" case is when both are zero, but that case is
1276  // handled by the ldi case.
1277  if (ResNonZero) {
1278  IntegerType *Int32Ty =
1280  const ConstantInt *Const32 = ConstantInt::get(Int32Ty, 32);
1281  SDValue Ops[4] = {HiResNonZero ? SDValue(HiRes, 0) : Zero64Val,
1282  CurDAG->getConstant(*Const32, DL, MVT::i32),
1283  CurDAG->getConstant(*Const32, DL, MVT::i32),
1284  SDValue(Res, 0)};
1285 
1286  Res = CurDAG->getMachineNode(Mips::DINSU, DL, MVT::i64, Ops);
1287  } else if (HiResNonZero) {
1288  Res = CurDAG->getMachineNode(
1289  Mips::DSLL32, DL, MVT::i64, SDValue(HiRes, 0),
1290  CurDAG->getTargetConstant(0, DL, MVT::i32));
1291  } else
1293  "Zero splat value handled by non-zero 64bit splat synthesis!");
1294 
1295  Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1296  } else
1297  llvm_unreachable("Unknown ABI in MipsISelDAGToDAG!");
1298 
1299  } else
1300  return false;
1301 
1302  if (ResVecTy != ViaVecTy) {
1303  // If LdiOp is writing to a different register class to ResVecTy, then
1304  // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
1305  // since the source and destination register sets contain the same
1306  // registers.
1308  MVT ResVecTySimple = ResVecTy.getSimpleVT();
1309  const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
1310  Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
1311  ResVecTy, SDValue(Res, 0),
1312  CurDAG->getTargetConstant(RC->getID(), DL,
1313  MVT::i32));
1314  }
1315 
1316  ReplaceNode(Node, Res);
1317  return true;
1318  }
1319 
1320  }
1321 
1322  return false;
1323 }
1324 
1325 bool MipsSEDAGToDAGISel::
1326 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
1327  std::vector<SDValue> &OutOps) {
1328  SDValue Base, Offset;
1329 
1330  switch(ConstraintID) {
1331  default:
1332  llvm_unreachable("Unexpected asm memory constraint");
1333  // All memory constraints can at least accept raw pointers.
1335  OutOps.push_back(Op);
1336  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1337  return false;
1339  if (selectAddrRegImm16(Op, Base, Offset)) {
1340  OutOps.push_back(Base);
1341  OutOps.push_back(Offset);
1342  return false;
1343  }
1344  OutOps.push_back(Op);
1345  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1346  return false;
1348  // The 'R' constraint is supposed to be much more complicated than this.
1349  // However, it's becoming less useful due to architectural changes and
1350  // ought to be replaced by other constraints such as 'ZC'.
1351  // For now, support 9-bit signed offsets which is supportable by all
1352  // subtargets for all instructions.
1353  if (selectAddrRegImm9(Op, Base, Offset)) {
1354  OutOps.push_back(Base);
1355  OutOps.push_back(Offset);
1356  return false;
1357  }
1358  OutOps.push_back(Op);
1359  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1360  return false;
1362  // ZC matches whatever the pref, ll, and sc instructions can handle for the
1363  // given subtarget.
1364  if (Subtarget->inMicroMipsMode()) {
1365  // On microMIPS, they can handle 12-bit offsets.
1366  if (selectAddrRegImm12(Op, Base, Offset)) {
1367  OutOps.push_back(Base);
1368  OutOps.push_back(Offset);
1369  return false;
1370  }
1371  } else if (Subtarget->hasMips32r6()) {
1372  // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
1373  if (selectAddrRegImm9(Op, Base, Offset)) {
1374  OutOps.push_back(Base);
1375  OutOps.push_back(Offset);
1376  return false;
1377  }
1378  } else if (selectAddrRegImm16(Op, Base, Offset)) {
1379  // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
1380  OutOps.push_back(Base);
1381  OutOps.push_back(Offset);
1382  return false;
1383  }
1384  // In all cases, 0-bit offsets are acceptable.
1385  OutOps.push_back(Op);
1386  OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1387  return false;
1388  }
1389  return true;
1390 }
1391 
1394  return new MipsSEDAGToDAGISel(TM, OptLevel);
1395 }
bool isABI_FPXX() const
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:570
SDNode * SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type...
EVT getValueType() const
Return the ValueType of the referenced return value.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool hasMTHC1() const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:320
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
FunctionPass * createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel)
bool inMips16Mode() const
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
const MipsInstrInfo * getInstrInfo() const override
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
Definition: ISDOpcodes.h:130
unsigned getValueSizeInBits(unsigned ResNo) const
Returns MVT::getSizeInBits(getValueType(ResNo)).
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
A debug info location.
Definition: DebugLoc.h:33
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
SDNode * getNode() const
get the SDNode which holds the desired result
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
bool isPHI() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineFunction * MF
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1508
return AArch64::GPR64RegClass contains(Reg)
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
AnalysisUsage & addRequired()
static use_iterator use_end()
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
bool inMicroMipsMode() const
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
const TargetLowering * TLI
bool isGP64bit() const
bool hasMips32r6() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:462
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:403
bool IsN32() const
Definition: MipsABIInfo.h:42
unsigned getID() const
Return the register class ID number.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:51
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
int64_t getSExtValue() const
bool IsN64() const
Definition: MipsABIInfo.h:43
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
SDValue getTargetFrameIndex(int FI, EVT VT)
Definition: SelectionDAG.h:633
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
int32_t exactLogBase2() const
Definition: APInt.h:1787
const InstSeq & Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu)
Analyze - Get an instruction sequence to load immediate Imm.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:581
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:150
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:326
TargetInstrInfo - Interface to description of machine instruction set.
MachineRegisterInfo * RegInfo
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:165
CodeGenOpt::Level OptLevel
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
unsigned countPopulation() const
Count the number of bits set.
Definition: APInt.h:1657
const MipsSubtarget * Subtarget
Keep a pointer to the MipsSubtarget around so that we can make the right decision when generating cod...
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn&#39;t correspond to a real machine instruction...
Definition: MachineInstr.h:618
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const SDValue & getOperand(unsigned Num) const
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
Represent the analysis usage information of a pass.
bool isExactlyValue(double V) const
We don&#39;t rely on operator== working on double values, as it returns true for things that are clearly ...
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool IsO32() const
Definition: MipsABIInfo.h:41
Class to represent integer types.
Definition: DerivedTypes.h:39
bool isIntN(unsigned N) const
Check if this APInt has an N-bits unsigned integer value.
Definition: APInt.h:449
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:192
Extended Value Type.
Definition: ValueTypes.h:33
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:397
const MachineBasicBlock & front() const
unsigned getNumOperands() const
Return the number of values used by this operation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:239
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:308
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isLittle() const
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
double Log2(double Value)
Return the log base 2 of the specified value.
Definition: MathExtras.h:527
MachineOperand class - Representation of each machine instruction operand.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:631
Represents one node in the SelectionDAG.
int64_t getImm() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:684
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Class for arbitrary precision integers.
Definition: APInt.h:69
A "pseudo-class" with methods for operating on BUILD_VECTORs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:710
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
use_iterator use_begin(unsigned RegNo) const
xray Insert XRay ops
bool is128BitVector() const
Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:181
bool isPositionIndependent() const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t Size
Definition: Profile.cpp:46
bool useOddSPReg() const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
unsigned getOpcode() const
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:455
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
const TargetLowering * getTargetLowering() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
SDValue getRegister(unsigned Reg, EVT VT)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align)
Returns the offset to the next integer (mod 2**64) that is greater than or equal to Value and is a mu...
Definition: MathExtras.h:726
IRTranslator LLVM IR MI
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
Legacy analysis pass which computes a DominatorTree.
Definition: Dominators.h:259
const SDValue & getOperand(unsigned i) const
uint64_t getZExtValue() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const TargetInstrInfo * TII
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool isFP64bit() const
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasMSA() const
IntegerType * Int32Ty