LLVM  10.0.0svn
RISCVInstructionSelector.cpp
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1 //===-- RISCVInstructionSelector.cpp -----------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the targeting of the InstructionSelector class for
10 /// RISCV.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "RISCVRegisterBankInfo.h"
15 #include "RISCVSubtarget.h"
16 #include "RISCVTargetMachine.h"
19 #include "llvm/Support/Debug.h"
20 
21 #define DEBUG_TYPE "riscv-isel"
22 
23 using namespace llvm;
24 
25 #define GET_GLOBALISEL_PREDICATE_BITSET
26 #include "RISCVGenGlobalISel.inc"
27 #undef GET_GLOBALISEL_PREDICATE_BITSET
28 
29 namespace {
30 
31 class RISCVInstructionSelector : public InstructionSelector {
32 public:
33  RISCVInstructionSelector(const RISCVTargetMachine &TM,
34  const RISCVSubtarget &STI,
35  const RISCVRegisterBankInfo &RBI);
36 
37  bool select(MachineInstr &I) override;
38  static const char *getName() { return DEBUG_TYPE; }
39 
40 private:
41  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
42 
43  const RISCVSubtarget &STI;
44  const RISCVInstrInfo &TII;
45  const RISCVRegisterInfo &TRI;
46  const RISCVRegisterBankInfo &RBI;
47 
48  // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
49  // uses "STI." in the code generated by TableGen. We need to unify the name of
50  // Subtarget variable.
51  const RISCVSubtarget *Subtarget = &STI;
52 
53 #define GET_GLOBALISEL_PREDICATES_DECL
54 #include "RISCVGenGlobalISel.inc"
55 #undef GET_GLOBALISEL_PREDICATES_DECL
56 
57 #define GET_GLOBALISEL_TEMPORARIES_DECL
58 #include "RISCVGenGlobalISel.inc"
59 #undef GET_GLOBALISEL_TEMPORARIES_DECL
60 };
61 
62 } // end anonymous namespace
63 
64 #define GET_GLOBALISEL_IMPL
65 #include "RISCVGenGlobalISel.inc"
66 #undef GET_GLOBALISEL_IMPL
67 
68 RISCVInstructionSelector::RISCVInstructionSelector(
69  const RISCVTargetMachine &TM, const RISCVSubtarget &STI,
70  const RISCVRegisterBankInfo &RBI)
71  : InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()),
72  TRI(*STI.getRegisterInfo()), RBI(RBI),
73 
75 #include "RISCVGenGlobalISel.inc"
78 #include "RISCVGenGlobalISel.inc"
80 {
81 }
82 
83 bool RISCVInstructionSelector::select(MachineInstr &I) {
84 
86  // Certain non-generic instructions also need some special handling.
87  return true;
88  }
89 
90  if (selectImpl(I, *CoverageInfo))
91  return true;
92 
93  return false;
94 }
95 
96 namespace llvm {
99  RISCVSubtarget &Subtarget,
100  RISCVRegisterBankInfo &RBI) {
101  return new RISCVInstructionSelector(TM, Subtarget, RBI);
102 }
103 } // end namespace llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static uint64_t selectImpl(uint64_t CandidateMask, uint64_t &NextInSequenceMask)
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &, RISCVSubtarget &, RISCVRegisterBankInfo &)
unsigned const TargetRegisterInfo * TRI
This class provides the information for the target register banks.
const HexagonInstrInfo * TII
static StringRef getName(Value *V)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
#define GET_GLOBALISEL_PREDICATES_INIT
#define GET_GLOBALISEL_TEMPORARIES_INIT
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:64
#define DEBUG_TYPE
#define I(x, y, z)
Definition: MD5.cpp:58
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:30
This file declares the targeting of the RegisterBankInfo class for RISCV.