85 if (&Subtarget == &NewSubtarget)
88 Names2InstrOpCodes.clear();
90 Names2RegMasks.clear();
91 Names2SubRegIndices.clear();
92 Names2TargetIndices.clear();
93 Names2DirectTargetFlags.clear();
94 Names2BitmaskTargetFlags.clear();
95 Names2MMOTargetFlags.clear();
97 initNames2RegClasses();
101void PerTargetMIParsingState::initNames2Regs() {
102 if (!Names2Regs.empty())
106 Names2Regs.insert(std::make_pair(
"noreg", 0));
108 assert(
TRI &&
"Expected target register info");
110 for (
unsigned I = 0, E =
TRI->getNumRegs();
I < E; ++
I) {
115 assert(WasInserted &&
"Expected registers to be unique case-insensitively");
122 auto RegInfo = Names2Regs.find(
RegName);
123 if (RegInfo == Names2Regs.end())
125 Reg = RegInfo->getValue();
131 const auto *
TRI = Subtarget.getRegisterInfo();
132 std::optional<uint8_t> FV =
TRI->getVRegFlagValue(FlagName);
139void PerTargetMIParsingState::initNames2InstrOpCodes() {
140 if (!Names2InstrOpCodes.
empty())
143 assert(
TII &&
"Expected target instruction info");
144 for (
unsigned I = 0, E =
TII->getNumOpcodes();
I < E; ++
I)
150 initNames2InstrOpCodes();
151 auto InstrInfo = Names2InstrOpCodes.find(InstrName);
152 if (InstrInfo == Names2InstrOpCodes.end())
154 OpCode = InstrInfo->getValue();
158void PerTargetMIParsingState::initNames2RegMasks() {
159 if (!Names2RegMasks.
empty())
162 assert(
TRI &&
"Expected target register info");
166 for (
size_t I = 0, E = RegMasks.
size();
I < E; ++
I)
168 std::make_pair(
StringRef(RegMaskNames[
I]).lower(), RegMasks[
I]));
172 initNames2RegMasks();
173 auto RegMaskInfo = Names2RegMasks.find(Identifier);
174 if (RegMaskInfo == Names2RegMasks.end())
176 return RegMaskInfo->getValue();
179void PerTargetMIParsingState::initNames2SubRegIndices() {
180 if (!Names2SubRegIndices.
empty())
183 for (
unsigned I = 1, E =
TRI->getNumSubRegIndices();
I < E; ++
I)
184 Names2SubRegIndices.
insert(
185 std::make_pair(
TRI->getSubRegIndexName(
I),
I));
189 initNames2SubRegIndices();
190 auto SubRegInfo = Names2SubRegIndices.find(Name);
191 if (SubRegInfo == Names2SubRegIndices.end())
193 return SubRegInfo->getValue();
196void PerTargetMIParsingState::initNames2TargetIndices() {
197 if (!Names2TargetIndices.
empty())
200 assert(
TII &&
"Expected target instruction info");
201 auto Indices =
TII->getSerializableTargetIndices();
202 for (
const auto &
I : Indices)
207 initNames2TargetIndices();
208 auto IndexInfo = Names2TargetIndices.find(Name);
209 if (IndexInfo == Names2TargetIndices.end())
211 Index = IndexInfo->second;
215void PerTargetMIParsingState::initNames2DirectTargetFlags() {
216 if (!Names2DirectTargetFlags.
empty())
220 assert(
TII &&
"Expected target instruction info");
221 auto Flags =
TII->getSerializableDirectMachineOperandTargetFlags();
222 for (
const auto &
I : Flags)
223 Names2DirectTargetFlags.
insert(
229 initNames2DirectTargetFlags();
230 auto FlagInfo = Names2DirectTargetFlags.find(Name);
231 if (FlagInfo == Names2DirectTargetFlags.end())
233 Flag = FlagInfo->second;
237void PerTargetMIParsingState::initNames2BitmaskTargetFlags() {
238 if (!Names2BitmaskTargetFlags.
empty())
242 assert(
TII &&
"Expected target instruction info");
243 auto Flags =
TII->getSerializableBitmaskMachineOperandTargetFlags();
244 for (
const auto &
I : Flags)
245 Names2BitmaskTargetFlags.
insert(
251 initNames2BitmaskTargetFlags();
252 auto FlagInfo = Names2BitmaskTargetFlags.find(Name);
253 if (FlagInfo == Names2BitmaskTargetFlags.end())
255 Flag = FlagInfo->second;
259void PerTargetMIParsingState::initNames2MMOTargetFlags() {
260 if (!Names2MMOTargetFlags.
empty())
264 assert(
TII &&
"Expected target instruction info");
265 auto Flags =
TII->getSerializableMachineMemOperandTargetFlags();
266 for (
const auto &
I : Flags)
272 initNames2MMOTargetFlags();
273 auto FlagInfo = Names2MMOTargetFlags.find(Name);
274 if (FlagInfo == Names2MMOTargetFlags.end())
276 Flag = FlagInfo->second;
280void PerTargetMIParsingState::initNames2RegClasses() {
281 if (!Names2RegClasses.
empty())
285 for (
unsigned I = 0, E =
TRI->getNumRegClasses();
I < E; ++
I) {
286 const auto *RC =
TRI->getRegClass(
I);
292void PerTargetMIParsingState::initNames2RegBanks() {
293 if (!Names2RegBanks.empty())
296 const RegisterBankInfo *RBI = Subtarget.getRegBankInfo();
304 Names2RegBanks.insert(
305 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank));
311 auto RegClassInfo = Names2RegClasses.find(Name);
312 if (RegClassInfo == Names2RegClasses.end())
314 return RegClassInfo->getValue();
318 auto RegBankInfo = Names2RegBanks.find(Name);
319 if (RegBankInfo == Names2RegBanks.end())
321 return RegBankInfo->getValue();
335 I.first->second = Info;
337 return *
I.first->second;
346 Info->
VReg =
MF.getRegInfo().createIncompleteVirtualRegister(
RegName);
347 I.first->second = Info;
349 return *
I.first->second;
357 Slots2Values.
insert(std::make_pair(
unsigned(Slot), V));
365 for (
const auto &Arg :
F.args())
367 for (
const auto &BB :
F) {
369 for (
const auto &
I : BB)
384struct ParsedMachineOperand {
388 std::optional<unsigned> TiedDefIdx;
392 std::optional<unsigned> &TiedDefIdx)
393 : Operand(Operand), Begin(Begin), End(End), TiedDefIdx(TiedDefIdx) {
396 "Only used register operands can be tied");
403 StringRef
Source, CurrentSource;
406 PerFunctionMIParsingState &PFS;
408 DenseMap<unsigned, const BasicBlock *> Slots2BasicBlocks;
411 MIParser(PerFunctionMIParsingState &PFS, SMDiagnostic &
Error,
413 MIParser(PerFunctionMIParsingState &PFS, SMDiagnostic &
Error,
414 StringRef Source, SMRange SourceRange);
418 void lex(
unsigned SkipChar = 0);
423 bool error(
const Twine &Msg);
431 parseBasicBlockDefinitions(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
432 bool parseBasicBlocks();
434 bool parseStandaloneMBB(MachineBasicBlock *&
MBB);
436 bool parseStandaloneVirtualRegister(VRegInfo *&Info);
438 bool parseStandaloneStackObject(
int &FI);
439 bool parseStandaloneMDNode(MDNode *&Node);
441 bool parseMDTuple(MDNode *&MD,
bool IsDistinct);
442 bool parseMDNodeVector(SmallVectorImpl<Metadata *> &Elts);
446 parseBasicBlockDefinition(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
447 bool parseBasicBlock(MachineBasicBlock &
MBB,
448 MachineBasicBlock *&AddFalthroughFrom);
449 bool parseBasicBlockLiveins(MachineBasicBlock &
MBB);
450 bool parseBasicBlockSuccessors(MachineBasicBlock &
MBB);
453 bool parseVirtualRegister(VRegInfo *&Info);
454 bool parseNamedVirtualRegister(VRegInfo *&Info);
455 bool parseRegister(
Register &
Reg, VRegInfo *&VRegInfo);
456 bool parseRegisterFlag(
RegState &Flags);
457 bool parseRegisterClassOrBank(VRegInfo &RegInfo);
458 bool parseSubRegisterIndex(
unsigned &SubReg);
459 bool parseRegisterTiedDefIndex(
unsigned &TiedDefIdx);
460 bool parseRegisterOperand(MachineOperand &Dest,
461 std::optional<unsigned> &TiedDefIdx,
463 bool parseImmediateOperand(MachineOperand &Dest);
464 bool parseInlineAsmOperand(MachineOperand &Dest);
469 bool parseTypedImmediateOperand(MachineOperand &Dest);
470 bool parseFPImmediateOperand(MachineOperand &Dest);
472 bool parseMBBOperand(MachineOperand &Dest);
473 bool parseStackFrameIndex(
int &FI);
474 bool parseStackObjectOperand(MachineOperand &Dest);
475 bool parseFixedStackFrameIndex(
int &FI);
476 bool parseFixedStackObjectOperand(MachineOperand &Dest);
478 bool parseGlobalAddressOperand(MachineOperand &Dest);
479 bool parseConstantPoolIndexOperand(MachineOperand &Dest);
480 bool parseSubRegisterIndexOperand(MachineOperand &Dest);
481 bool parseJumpTableIndexOperand(MachineOperand &Dest);
482 bool parseExternalSymbolOperand(MachineOperand &Dest);
483 bool parseMCSymbolOperand(MachineOperand &Dest);
485 bool parseDIExpression(MDNode *&Expr);
486 bool parseDILocation(MDNode *&Expr);
487 bool parseMetadataOperand(MachineOperand &Dest);
488 bool parseCFIOffset(
int &
Offset);
489 bool parseCFIRegister(
unsigned &
Reg);
491 bool parseCFIEscapeValues(std::string& Values);
492 bool parseCFIOperand(MachineOperand &Dest);
493 bool parseIRBlock(BasicBlock *&BB,
const Function &
F);
494 bool parseBlockAddressOperand(MachineOperand &Dest);
495 bool parseIntrinsicOperand(MachineOperand &Dest);
496 bool parsePredicateOperand(MachineOperand &Dest);
497 bool parseShuffleMaskOperand(MachineOperand &Dest);
498 bool parseTargetIndexOperand(MachineOperand &Dest);
499 bool parseDbgInstrRefOperand(MachineOperand &Dest);
500 bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
501 bool parseLaneMaskOperand(MachineOperand &Dest);
502 bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
503 bool parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
504 MachineOperand &Dest,
505 std::optional<unsigned> &TiedDefIdx);
506 bool parseMachineOperandAndTargetFlags(
const unsigned OpCode,
507 const unsigned OpIdx,
508 MachineOperand &Dest,
509 std::optional<unsigned> &TiedDefIdx);
510 bool parseOffset(int64_t &
Offset);
511 bool parseIRBlockAddressTaken(BasicBlock *&BB);
513 bool parseAddrspace(
unsigned &Addrspace);
514 bool parseSectionID(std::optional<MBBSectionID> &SID);
515 bool parseBBID(std::optional<UniqueBBID> &BBID);
516 bool parseCallFrameSize(
unsigned &CallFrameSize);
518 bool parseOperandsOffset(MachineOperand &
Op);
521 bool parseMemoryPseudoSourceValue(
const PseudoSourceValue *&PSV);
522 bool parseMachinePointerInfo(MachinePointerInfo &Dest);
525 bool parseMachineMemoryOperand(MachineMemOperand *&Dest);
526 bool parsePreOrPostInstrSymbol(MCSymbol *&Symbol);
527 bool parseHeapAllocMarker(MDNode *&Node);
528 bool parsePCSections(MDNode *&Node);
529 bool parseMMRA(MDNode *&Node);
531 bool parseTargetImmMnemonic(
const unsigned OpCode,
const unsigned OpIdx,
532 MachineOperand &Dest,
const MIRFormatter &MF);
543 bool getUint64(uint64_t &Result);
559 bool parseInstruction(
unsigned &OpCode,
unsigned &Flags);
561 bool assignRegisterTies(MachineInstr &
MI,
565 const MCInstrDesc &MCID);
568 const BasicBlock *getIRBlock(
unsigned Slot,
const Function &
F);
571 MCSymbol *getOrCreateMCSymbol(StringRef Name);
575 bool parseStringConstant(std::string &Result);
592 SourceRange(SourceRange), PFS(PFS) {}
594void MIParser::lex(
unsigned SkipChar) {
596 CurrentSource.substr(SkipChar), Token,
600bool MIParser::error(
const Twine &Msg) {
return error(Token.location(), Msg); }
620 assert(SourceRange.isValid() &&
"Invalid source range");
642 return "<unknown token>";
647 if (Token.isNot(TokenKind))
654 if (Token.isNot(TokenKind))
661bool MIParser::parseSectionID(std::optional<MBBSectionID> &SID) {
667 return error(
"Unknown Section ID");
670 const StringRef &S = Token.stringValue();
671 if (S ==
"Exception")
673 else if (S ==
"Cold")
676 return error(
"Unknown Section ID");
683bool MIParser::parseBBID(std::optional<UniqueBBID> &BBID) {
685 return error(
"expected 'bb_id'");
688 unsigned CloneID = 0;
691 auto Parts = S.
split(
'.');
692 if (Parts.first.getAsInteger(10, BaseID) ||
693 Parts.second.getAsInteger(10, CloneID))
694 return error(
"Unknown BB ID");
698 return error(
"Unknown BB ID");
703 return error(
"Unknown Clone ID");
707 return error(
"Unknown Clone ID");
711 BBID = {BaseID, CloneID};
716bool MIParser::parseCallFrameSize(
unsigned &CallFrameSize) {
721 return error(
"Unknown call frame size");
722 CallFrameSize =
Value;
729 std::optional<UniqueBBID> BBID;
738bool MIParser::parseBasicBlockDefinition(
744 auto Loc = Token.location();
745 auto Name = Token.stringValue();
747 bool MachineBlockAddressTaken =
false;
749 bool IsLandingPad =
false;
750 bool IsInlineAsmBrIndirectTarget =
false;
751 bool IsEHFuncletEntry =
false;
752 bool IsEHScopeEntry =
false;
753 std::optional<MBBSectionID> SectionID;
754 uint64_t Alignment = 0;
755 std::optional<UniqueBBID> BBID;
756 unsigned CallFrameSize = 0;
761 switch (Token.kind()) {
763 MachineBlockAddressTaken =
true;
767 if (parseIRBlockAddressTaken(AddressTakenIRBlock))
775 IsInlineAsmBrIndirectTarget =
true;
779 IsEHFuncletEntry =
true;
783 IsEHScopeEntry =
true;
793 if (parseIRBlock(BB, MF.getFunction()))
798 if (parseSectionID(SectionID))
806 if (parseCallFrameSize(CallFrameSize))
821 MF.getFunction().getValueSymbolTable()->lookup(Name));
824 "' is not defined in the function '" +
827 auto *
MBB = MF.CreateMachineBasicBlock(BB, BBID);
829 bool WasInserted = MBBSlots.
insert(std::make_pair(
ID,
MBB)).second;
831 return error(
Loc,
Twine(
"redefinition of machine basic block with id #") +
835 if (MachineBlockAddressTaken)
837 if (AddressTakenIRBlock)
851bool MIParser::parseBasicBlockDefinitions(
857 if (Token.isErrorOrEOF())
858 return Token.isError();
860 return error(
"expected a basic block definition before instructions");
861 unsigned BraceDepth = 0;
863 if (parseBasicBlockDefinition(MBBSlots))
865 bool IsAfterNewline =
false;
869 Token.isErrorOrEOF())
872 return error(
"basic block definition should be located at the start of "
875 IsAfterNewline =
true;
878 IsAfterNewline =
false;
883 return error(
"extraneous closing brace ('}')");
889 if (!Token.isError() && BraceDepth)
890 return error(
"expected '}'");
891 }
while (!Token.isErrorOrEOF());
892 return Token.isError();
900 if (Token.isNewlineOrEOF())
904 return error(
"expected a named register");
906 if (parseNamedRegister(
Reg))
914 return error(
"expected a lane mask");
916 "Use correct get-function for lane mask");
919 return error(
"invalid lane mask value");
933 if (Token.isNewlineOrEOF())
937 return error(
"expected a machine basic block reference");
946 return error(
"expected an integer literal after '('");
980 bool ExplicitSuccessors =
false;
983 if (parseBasicBlockSuccessors(
MBB))
985 ExplicitSuccessors =
true;
987 if (parseBasicBlockLiveins(
MBB))
994 if (!Token.isNewlineOrEOF())
995 return error(
"expected line break at the end of a list");
1000 bool IsInBundle =
false;
1024 return error(
"nested instruction bundles are not allowed");
1033 assert(Token.isNewlineOrEOF() &&
"MI is not fully parsed");
1038 if (!ExplicitSuccessors) {
1045 if (IsFallthrough) {
1046 AddFalthroughFrom = &
MBB;
1055bool MIParser::parseBasicBlocks() {
1060 if (Token.isErrorOrEOF())
1061 return Token.isError();
1070 if (AddFalthroughFrom) {
1074 AddFalthroughFrom =
nullptr;
1076 if (parseBasicBlock(*
MBB, AddFalthroughFrom))
1089 while (Token.isRegister() || Token.isRegisterFlag()) {
1090 auto Loc = Token.location();
1091 std::optional<unsigned> TiedDefIdx;
1092 if (parseRegisterOperand(MO, TiedDefIdx,
true))
1095 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1104 if (Token.isError() || parseInstruction(OpCode, Flags))
1117 auto Loc = Token.location();
1118 std::optional<unsigned> TiedDefIdx;
1119 if (parseMachineOperandAndTargetFlags(OpCode, Operands.
size(), MO, TiedDefIdx))
1122 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1127 return error(
"expected ',' before the next machine operand");
1131 MCSymbol *PreInstrSymbol =
nullptr;
1133 if (parsePreOrPostInstrSymbol(PreInstrSymbol))
1135 MCSymbol *PostInstrSymbol =
nullptr;
1137 if (parsePreOrPostInstrSymbol(PostInstrSymbol))
1139 MDNode *HeapAllocMarker =
nullptr;
1141 if (parseHeapAllocMarker(HeapAllocMarker))
1143 MDNode *PCSections =
nullptr;
1145 if (parsePCSections(PCSections))
1150 unsigned CFIType = 0;
1154 return error(
"expected an integer literal after 'cfi-type'");
1172 unsigned InstrNum = 0;
1176 return error(
"expected an integer literal after 'debug-instr-number'");
1193 if (parseDILocation(Node))
1196 return error(
"expected a metadata node after 'debug-location'");
1199 return error(
"referenced metadata is not a DILocation");
1207 while (!Token.isNewlineOrEOF()) {
1209 if (parseMachineMemoryOperand(
MemOp))
1212 if (Token.isNewlineOrEOF())
1217 return error(
"expected ',' before the next machine memory operand");
1222 const auto &
MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
1223 if (!
MCID.isVariadic()) {
1225 if (verifyImplicitOperands(Operands,
MCID))
1229 MI = MF.CreateMachineInstr(
MCID, DebugLocation,
true);
1230 MI->setFlags(Flags);
1234 for (
const auto &Operand : Operands)
1235 MI->addOperand(MF, Operand.Operand);
1237 if (assignRegisterTies(*
MI, Operands))
1240 MI->setPreInstrSymbol(MF, PreInstrSymbol);
1241 if (PostInstrSymbol)
1242 MI->setPostInstrSymbol(MF, PostInstrSymbol);
1243 if (HeapAllocMarker)
1244 MI->setHeapAllocMarker(MF, HeapAllocMarker);
1246 MI->setPCSections(MF, PCSections);
1248 MI->setMMRAMetadata(MF, MMRA);
1250 MI->setCFIType(MF, CFIType);
1252 MI->setDeactivationSymbol(MF, DS);
1253 if (!MemOperands.
empty())
1254 MI->setMemRefs(MF, MemOperands);
1256 MI->setDebugInstrNum(InstrNum);
1263 return error(
"expected a machine basic block reference");
1269 "expected end of string after the machine basic block reference");
1273bool MIParser::parseStandaloneNamedRegister(
Register &
Reg) {
1276 return error(
"expected a named register");
1277 if (parseNamedRegister(
Reg))
1281 return error(
"expected end of string after the register reference");
1285bool MIParser::parseStandaloneVirtualRegister(
VRegInfo *&Info) {
1288 return error(
"expected a virtual register");
1289 if (parseVirtualRegister(Info))
1293 return error(
"expected end of string after the register reference");
1297bool MIParser::parseStandaloneRegister(
Register &
Reg) {
1301 return error(
"expected either a named or virtual register");
1304 if (parseRegister(
Reg, Info))
1309 return error(
"expected end of string after the register reference");
1313bool MIParser::parseStandaloneStackObject(
int &FI) {
1316 return error(
"expected a stack object");
1317 if (parseStackFrameIndex(FI))
1320 return error(
"expected end of string after the stack object reference");
1324bool MIParser::parseStandaloneMDNode(
MDNode *&Node) {
1330 if (parseDIExpression(Node))
1333 if (parseDILocation(Node))
1336 return error(
"expected a metadata node");
1339 return error(
"expected end of string after the metadata node");
1343bool MIParser::parseMachineMetadata() {
1346 return error(
"expected a metadata node");
1350 return error(
"expected metadata id after '!'");
1361 return error(
"expected a metadata node");
1365 if (parseMDTuple(MD, IsDistinct))
1368 auto FI = PFS.MachineForwardRefMDNodes.find(
ID);
1369 if (FI != PFS.MachineForwardRefMDNodes.end()) {
1370 FI->second.first->replaceAllUsesWith(MD);
1371 PFS.MachineForwardRefMDNodes.erase(FI);
1373 assert(PFS.MachineMetadataNodes[
ID] == MD &&
"Tracking VH didn't work");
1375 auto [It,
Inserted] = PFS.MachineMetadataNodes.try_emplace(
ID);
1377 return error(
"Metadata id is already used");
1378 It->second.reset(MD);
1384bool MIParser::parseMDTuple(
MDNode *&MD,
bool IsDistinct) {
1386 if (parseMDNodeVector(Elts))
1395 return error(
"expected '{' here");
1416 return error(
"expected end of metadata node");
1424bool MIParser::parseMetadata(
Metadata *&MD) {
1426 return error(
"expected '!' here");
1431 if (parseStringConstant(Str))
1438 return error(
"expected metadata id after '!'");
1440 SMLoc Loc = mapSMLoc(Token.location());
1447 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
1448 if (NodeInfo != PFS.IRSlots.MetadataNodes.end()) {
1449 MD = NodeInfo->second.get();
1453 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
1454 if (NodeInfo != PFS.MachineMetadataNodes.end()) {
1455 MD = NodeInfo->second.get();
1459 auto &FwdRef = PFS.MachineForwardRefMDNodes[
ID];
1460 FwdRef = std::make_pair(
1462 PFS.MachineMetadataNodes[
ID].reset(FwdRef.first.get());
1463 MD = FwdRef.first.get();
1470 return MO.
isDef() ?
"implicit-def" :
"implicit";
1475 assert(
Reg.isPhysical() &&
"expected phys reg");
1482 for (
const auto &
I : Operands) {
1503 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
1504 assert(
TRI &&
"Expected target register info");
1505 for (
const auto &
I : ImplicitOperands) {
1508 return error(Operands.
empty() ? Token.location() : Operands.
back().End,
1509 Twine(
"missing implicit register operand '") +
1516bool MIParser::parseInstruction(
unsigned &OpCode,
unsigned &Flags) {
1585 return error(
"expected a machine instruction");
1586 StringRef InstrName = Token.stringValue();
1587 if (PFS.Target.parseInstrName(InstrName, OpCode))
1588 return error(
Twine(
"unknown machine instruction name '") + InstrName +
"'");
1596 if (PFS.Target.getRegisterByName(Name,
Reg))
1597 return error(
Twine(
"unknown register name '") + Name +
"'");
1601bool MIParser::parseNamedVirtualRegister(
VRegInfo *&Info) {
1606 Info = &PFS.getVRegInfoNamed(Name);
1610bool MIParser::parseVirtualRegister(
VRegInfo *&Info) {
1612 return parseNamedVirtualRegister(Info);
1617 Info = &PFS.getVRegInfo(
ID);
1622 switch (Token.kind()) {
1627 return parseNamedRegister(
Reg);
1630 if (parseVirtualRegister(Info))
1640bool MIParser::parseRegisterClassOrBank(
VRegInfo &RegInfo) {
1642 return error(
"expected '_', register class, or register bank name");
1651 switch (RegInfo.
Kind) {
1657 return error(
Loc,
Twine(
"conflicting register classes, previously: ") +
1666 return error(
Loc,
"register class specification on generic register");
1674 RegBank = PFS.Target.getRegBank(Name);
1676 return error(
Loc,
"expected '_', register class, or register bank name");
1681 switch (RegInfo.
Kind) {
1687 return error(
Loc,
"conflicting generic register banks");
1693 return error(
Loc,
"register bank specification on normal register");
1698bool MIParser::parseRegisterFlag(
RegState &Flags) {
1700 switch (Token.kind()) {
1734 if (OldFlags == Flags)
1737 return error(
"duplicate '" + Token.stringValue() +
"' register flag");
1742bool MIParser::parseSubRegisterIndex(
unsigned &SubReg) {
1746 return error(
"expected a subregister index after '.'");
1747 auto Name = Token.stringValue();
1748 SubReg = PFS.Target.getSubRegIndex(Name);
1750 return error(
Twine(
"use of unknown subregister index '") + Name +
"'");
1755bool MIParser::parseRegisterTiedDefIndex(
unsigned &TiedDefIdx) {
1759 return error(
"expected an integer literal after 'tied-def'");
1769 for (
unsigned I = 0,
E = Operands.
size();
I !=
E; ++
I) {
1770 if (!Operands[
I].TiedDefIdx)
1774 unsigned DefIdx = *Operands[
I].TiedDefIdx;
1776 return error(Operands[
I].Begin,
1777 Twine(
"use of invalid tied-def operand index '" +
1778 Twine(DefIdx) +
"'; instruction has only ") +
1780 const auto &DefOperand = Operands[DefIdx].Operand;
1781 if (!DefOperand.isReg() || !DefOperand.isDef())
1783 return error(Operands[
I].Begin,
1784 Twine(
"use of invalid tied-def operand index '") +
1785 Twine(DefIdx) +
"'; the operand #" +
Twine(DefIdx) +
1786 " isn't a defined register");
1788 for (
const auto &TiedPair : TiedRegisterPairs) {
1789 if (TiedPair.first == DefIdx)
1790 return error(Operands[
I].Begin,
1791 Twine(
"the tied-def operand #") +
Twine(DefIdx) +
1792 " is already tied with another register operand");
1794 TiedRegisterPairs.push_back(std::make_pair(DefIdx,
I));
1798 for (
const auto &TiedPair : TiedRegisterPairs)
1799 MI.tieOperands(TiedPair.first, TiedPair.second);
1804 std::optional<unsigned> &TiedDefIdx,
1807 while (Token.isRegisterFlag()) {
1808 if (parseRegisterFlag(Flags))
1813 if (!Token.isRegister())
1814 return error(
"expected a register after register flags");
1817 if (parseRegister(
Reg, RegInfo))
1820 unsigned SubReg = 0;
1822 if (parseSubRegisterIndex(SubReg))
1825 return error(
"subregister index expects a virtual register");
1829 return error(
"register class specification expects a virtual register");
1831 if (parseRegisterClassOrBank(*RegInfo))
1840 return error(
"tied-def not supported for defs");
1842 if (parseRegisterTiedDefIndex(Idx))
1847 return error(
"unexpected type on physical register");
1851 if (parseLowLevelType(Token.location(), Ty))
1853 :
error(
"expected tied-def or low-level type after '('");
1860 return error(
"inconsistent type for generic virtual register");
1870 return error(
"generic virtual registers must have a type");
1875 return error(
"cannot have a killed def operand");
1878 return error(
"cannot have a dead use operand");
1895 const APSInt &
Int = Token.integerValue();
1896 if (
auto SImm =
Int.trySExtValue();
Int.isSigned() && SImm.has_value())
1898 else if (
auto UImm =
Int.tryZExtValue(); !
Int.isSigned() && UImm.has_value())
1901 return error(
"integer literal is too large to be an immediate operand");
1909 StringRef KindStr = Token.stringValue();
1920 assert(K != InvalidKind &&
"unknown inline asm operand kind");
1931 return error(
"expected ':' after 'tiedto'");
1934 return error(
"expected '$N' operand number after 'tiedto:'");
1936 if (Token.stringValue().getAsInteger(10, OperandNo))
1937 return error(
"invalid operand number in tiedto constraint");
1940 F.setMatchingOp(OperandNo);
1955 return error(
"expected register class or memory constraint name after ':'");
1957 StringRef ConstraintStr = Token.stringValue();
1991 return error(
"unknown memory constraint '" + ConstraintStr +
"'");
1992 F.setMemConstraint(CC);
1996 PFS.Target.getRegClass(ConstraintStr.
lower());
1998 return error(
"unknown register class '" + ConstraintStr +
"'");
1999 F.setRegClass(RC->
getID());
2008bool MIParser::parseTargetImmMnemonic(
const unsigned OpCode,
2009 const unsigned OpIdx,
2013 auto Loc = Token.location();
2019 Len += Token.range().size();
2028 Src =
StringRef(
Loc, Len + Token.stringValue().size());
2033 ->
bool { return error(Loc, Msg); }))
2045 auto Source = StringValue.
str();
2050 return ErrCB(
Loc + Err.getColumnNo(), Err.getMessage());
2056 return ::parseIRConstant(
2057 Loc, StringValue, PFS,
C,
2084 if (Token.range().front() ==
's' || Token.range().front() ==
'p') {
2087 return error(
"expected integers after 's'/'p' type character");
2090 if (Token.range().front() ==
's') {
2094 return error(
"invalid size for scalar type");
2101 }
else if (Token.range().front() ==
'p') {
2105 return error(
"invalid address space number");
2114 return error(
Loc,
"expected sN, pA, <M x sN>, <M x pA>, <vscale x M x sN>, "
2115 "or <vscale x M x pA> for GlobalISel type");
2123 return error(
"expected <vscale x M x sN> or <vscale x M x pA>");
2127 auto GetError = [
this, &HasVScale,
Loc]() {
2130 Loc,
"expected <vscale x M x sN> or <vscale M x pA> for vector type");
2131 return error(
Loc,
"expected <M x sN> or <M x pA> for vector type");
2136 uint64_t NumElements = Token.integerValue().getZExtValue();
2138 return error(
"invalid number of vector elements");
2146 if (Token.range().front() !=
's' && Token.range().front() !=
'p')
2151 return error(
"expected integers after 's'/'p' type character");
2153 if (Token.range().front() ==
's') {
2156 return error(
"invalid size for scalar element in vector");
2158 }
else if (Token.range().front() ==
'p') {
2162 return error(
"invalid address space number");
2182 if (TypeStr.
front() !=
'i' && TypeStr.
front() !=
's' &&
2183 TypeStr.
front() !=
'p')
2185 "a typed immediate operand should start with one of 'i', 's', or 'p'");
2188 return error(
"expected integers after 'i'/'s'/'p' type character");
2190 auto Loc = Token.location();
2194 !(Token.range() ==
"true" || Token.range() ==
"false"))
2195 return error(
"expected an integer literal");
2205 auto Loc = Token.location();
2209 return error(
"expected a floating point literal");
2220 assert(S[0] ==
'0' && tolower(S[1]) ==
'x');
2222 if (!isxdigit(S[2]))
2225 APInt A(V.size()*4, V, 16);
2229 unsigned NumBits = (
A == 0) ? 32 :
A.getActiveBits();
2240 return ErrCB(Token.
location(),
"expected unsigned integer");
2243 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2251 if (
A.getBitWidth() > 32)
2252 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2253 Result =
A.getZExtValue();
2259bool MIParser::getUnsigned(
unsigned &Result) {
2260 return ::getUnsigned(
2272 auto MBBInfo = PFS.MBBSlots.find(
Number);
2273 if (MBBInfo == PFS.MBBSlots.end())
2274 return error(
Twine(
"use of undefined machine basic block #") +
2276 MBB = MBBInfo->second;
2279 if (!Token.stringValue().empty() && Token.stringValue() !=
MBB->
getName())
2281 " isn't '" + Token.stringValue() +
"'");
2294bool MIParser::parseStackFrameIndex(
int &FI) {
2299 auto ObjectInfo = PFS.StackObjectSlots.find(
ID);
2300 if (ObjectInfo == PFS.StackObjectSlots.end())
2304 if (
const auto *Alloca =
2305 MF.getFrameInfo().getObjectAllocation(ObjectInfo->second))
2306 Name = Alloca->getName();
2307 if (!Token.stringValue().empty() && Token.stringValue() != Name)
2309 "' isn't '" + Token.stringValue() +
"'");
2311 FI = ObjectInfo->second;
2317 if (parseStackFrameIndex(FI))
2323bool MIParser::parseFixedStackFrameIndex(
int &FI) {
2328 auto ObjectInfo = PFS.FixedStackObjectSlots.find(
ID);
2329 if (ObjectInfo == PFS.FixedStackObjectSlots.end())
2330 return error(
Twine(
"use of undefined fixed stack object '%fixed-stack.") +
2333 FI = ObjectInfo->second;
2337bool MIParser::parseFixedStackObjectOperand(
MachineOperand &Dest) {
2339 if (parseFixedStackFrameIndex(FI))
2348 switch (Token.
kind()) {
2353 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '") +
2354 Token.
range() +
"'");
2363 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '@") +
2364 Twine(GVIdx) +
"'");
2373bool MIParser::parseGlobalValue(
GlobalValue *&GV) {
2374 return ::parseGlobalValue(
2387 if (parseOperandsOffset(Dest))
2392bool MIParser::parseConstantPoolIndexOperand(
MachineOperand &Dest) {
2399 return error(
"use of undefined constant '%const." +
Twine(
ID) +
"'");
2402 if (parseOperandsOffset(Dest))
2412 auto JumpTableEntryInfo = PFS.JumpTableSlots.find(
ID);
2413 if (JumpTableEntryInfo == PFS.JumpTableSlots.end())
2414 return error(
"use of undefined jump table '%jump-table." +
Twine(
ID) +
"'");
2422 const char *
Symbol = MF.createExternalSymbolName(Token.stringValue());
2425 if (parseOperandsOffset(Dest))
2435 if (parseOperandsOffset(Dest))
2440bool MIParser::parseSubRegisterIndexOperand(
MachineOperand &Dest) {
2443 unsigned SubRegIndex = PFS.Target.getSubRegIndex(Token.stringValue());
2444 if (SubRegIndex == 0)
2445 return error(
Twine(
"unknown subregister index '") + Name +
"'");
2451bool MIParser::parseMDNode(
MDNode *&Node) {
2454 auto Loc = Token.location();
2457 return error(
"expected metadata id after '!'");
2461 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
2462 if (NodeInfo == PFS.IRSlots.MetadataNodes.end()) {
2463 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
2464 if (NodeInfo == PFS.MachineMetadataNodes.end())
2468 Node = NodeInfo->second.get();
2472bool MIParser::parseDIExpression(
MDNode *&Expr) {
2475 CurrentSource,
Read,
Error, *PFS.MF.getFunction().getParent(),
2477 CurrentSource = CurrentSource.substr(
Read);
2484bool MIParser::parseDILocation(
MDNode *&
Loc) {
2488 bool HaveLine =
false;
2490 unsigned Column = 0;
2492 MDNode *InlinedAt =
nullptr;
2493 bool ImplicitCode =
false;
2494 uint64_t AtomGroup = 0;
2495 uint64_t AtomRank = 0;
2503 if (Token.stringValue() ==
"line") {
2508 Token.integerValue().isSigned())
2509 return error(
"expected unsigned integer");
2510 Line = Token.integerValue().getZExtValue();
2515 if (Token.stringValue() ==
"column") {
2520 Token.integerValue().isSigned())
2521 return error(
"expected unsigned integer");
2522 Column = Token.integerValue().getZExtValue();
2526 if (Token.stringValue() ==
"scope") {
2531 return error(
"expected metadata node");
2533 return error(
"expected DIScope node");
2536 if (Token.stringValue() ==
"inlinedAt") {
2544 if (parseDILocation(InlinedAt))
2547 return error(
"expected metadata node");
2550 return error(
"expected DILocation node");
2553 if (Token.stringValue() ==
"isImplicitCode") {
2558 return error(
"expected true/false");
2562 if (Token.stringValue() ==
"true")
2563 ImplicitCode =
true;
2564 else if (Token.stringValue() ==
"false")
2565 ImplicitCode =
false;
2567 return error(
"expected true/false");
2571 if (Token.stringValue() ==
"atomGroup") {
2576 Token.integerValue().isSigned())
2577 return error(
"expected unsigned integer");
2578 AtomGroup = Token.integerValue().getZExtValue();
2582 if (Token.stringValue() ==
"atomRank") {
2587 Token.integerValue().isSigned())
2588 return error(
"expected unsigned integer");
2589 AtomRank = Token.integerValue().getZExtValue();
2594 return error(
Twine(
"invalid DILocation argument '") +
2595 Token.stringValue() +
"'");
2603 return error(
"DILocation requires line number");
2605 return error(
"DILocation requires a scope");
2608 InlinedAt, ImplicitCode, AtomGroup, AtomRank);
2618 if (parseDIExpression(Node))
2625bool MIParser::parseCFIOffset(
int &
Offset) {
2627 return error(
"expected a cfi offset");
2628 if (Token.integerValue().getSignificantBits() > 32)
2629 return error(
"expected a 32 bit integer (the cfi offset is too large)");
2630 Offset = (int)Token.integerValue().getExtValue();
2635bool MIParser::parseCFIRegister(
unsigned &
Reg) {
2637 return error(
"expected a cfi register");
2639 if (parseNamedRegister(LLVMReg))
2641 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
2642 assert(
TRI &&
"Expected target register info");
2643 int DwarfReg =
TRI->getDwarfRegNum(LLVMReg,
true);
2645 return error(
"invalid DWARF register");
2646 Reg = (unsigned)DwarfReg;
2651bool MIParser::parseCFIAddressSpace(
unsigned &
AddressSpace) {
2653 return error(
"expected a cfi address space literal");
2654 if (Token.integerValue().isSigned())
2655 return error(
"expected an unsigned integer (cfi address space)");
2661bool MIParser::parseCFIEscapeValues(std::string &Values) {
2664 return error(
"expected a hexadecimal literal");
2668 if (
Value > UINT8_MAX)
2669 return error(
"expected a 8-bit integer (too large)");
2670 Values.push_back(
static_cast<uint8_t
>(
Value));
2677 auto Kind = Token.kind();
2685 if (parseCFIRegister(
Reg))
2700 CFIIndex = MF.addFrameInst(
2704 if (parseCFIRegister(
Reg))
2710 if (parseCFIOffset(
Offset))
2716 if (parseCFIOffset(
Offset))
2718 CFIIndex = MF.addFrameInst(
2740 if (parseCFIRegister(
Reg))
2748 if (parseCFIRegister(
Reg))
2755 parseCFIRegister(Reg2))
2774 if (parseCFIEscapeValues(Values))
2788 switch (Token.kind()) {
2791 F.getValueSymbolTable()->lookup(Token.stringValue()));
2793 return error(
Twine(
"use of undefined IR block '") + Token.range() +
"'");
2797 unsigned SlotNumber = 0;
2800 BB =
const_cast<BasicBlock *
>(getIRBlock(SlotNumber,
F));
2802 return error(
Twine(
"use of undefined IR block '%ir-block.") +
2803 Twine(SlotNumber) +
"'");
2819 return error(
"expected a global value");
2825 return error(
"expected an IR function reference");
2831 return error(
"expected an IR block reference");
2832 if (parseIRBlock(BB, *
F))
2838 if (parseOperandsOffset(Dest))
2847 return error(
"expected syntax intrinsic(@llvm.whatever)");
2850 return error(
"expected syntax intrinsic(@llvm.whatever)");
2852 std::string
Name = std::string(Token.stringValue());
2856 return error(
"expected ')' to terminate intrinsic name");
2861 return error(
"unknown intrinsic name");
2873 return error(
"expected syntax intpred(whatever) or floatpred(whatever");
2876 return error(
"whatever");
2899 return error(
"invalid floating-point predicate");
2914 return error(
"invalid integer predicate");
2920 return error(
"predicate should be terminated by ')'.");
2930 return error(
"expected syntax shufflemask(<integer or undef>, ...)");
2937 const APSInt &
Int = Token.integerValue();
2940 return error(
"expected integer constant");
2947 return error(
"shufflemask should be terminated by ')'.");
2949 if (ShufMask.
size() < 2)
2950 return error(
"shufflemask should have > 1 element");
2962 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2965 return error(
"expected unsigned integer for instruction index");
2966 uint64_t InstrIdx = Token.integerValue().getZExtValue();
2967 assert(InstrIdx <= std::numeric_limits<unsigned>::max() &&
2968 "Instruction reference's instruction index is too large");
2972 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2975 return error(
"expected unsigned integer for operand index");
2976 uint64_t
OpIdx = Token.integerValue().getZExtValue();
2977 assert(
OpIdx <= std::numeric_limits<unsigned>::max() &&
2978 "Instruction reference's operand index is too large");
2982 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2994 return error(
"expected the name of the target index");
2996 if (PFS.Target.getTargetIndex(Token.stringValue(), Index))
2997 return error(
"use of undefined target index '" + Token.stringValue() +
"'");
3002 if (parseOperandsOffset(Dest))
3007bool MIParser::parseCustomRegisterMaskOperand(
MachineOperand &Dest) {
3008 assert(Token.stringValue() ==
"CustomRegMask" &&
"Expected a custom RegMask");
3013 uint32_t *
Mask = MF.allocateRegMask();
3017 return error(
"expected a named register");
3019 if (parseNamedRegister(
Reg))
3043 return error(
"expected a valid lane mask value");
3045 "Use correct get-function for lane mask.");
3059bool MIParser::parseLiveoutRegisterMaskOperand(
MachineOperand &Dest) {
3061 uint32_t *
Mask = MF.allocateRegMask();
3067 return error(
"expected a named register");
3069 if (parseNamedRegister(
Reg))
3084bool MIParser::parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
3086 std::optional<unsigned> &TiedDefIdx) {
3087 switch (Token.kind()) {
3102 return parseRegisterOperand(Dest, TiedDefIdx);
3106 return parseImmediateOperand(Dest);
3114 return parseFPImmediateOperand(Dest);
3116 return parseMBBOperand(Dest);
3118 return parseStackObjectOperand(Dest);
3120 return parseFixedStackObjectOperand(Dest);
3123 return parseGlobalAddressOperand(Dest);
3125 return parseConstantPoolIndexOperand(Dest);
3127 return parseJumpTableIndexOperand(Dest);
3129 return parseExternalSymbolOperand(Dest);
3131 return parseMCSymbolOperand(Dest);
3133 return parseSubRegisterIndexOperand(Dest);
3136 return parseMetadataOperand(Dest);
3154 return parseCFIOperand(Dest);
3156 return parseBlockAddressOperand(Dest);
3158 return parseIntrinsicOperand(Dest);
3160 return parseTargetIndexOperand(Dest);
3162 return parseLaneMaskOperand(Dest);
3164 return parseLiveoutRegisterMaskOperand(Dest);
3167 return parsePredicateOperand(Dest);
3169 return parseShuffleMaskOperand(Dest);
3171 return parseDbgInstrRefOperand(Dest);
3176 bool IsInlineAsmOperand = (
OpCode == TargetOpcode::INLINEASM ||
3177 OpCode == TargetOpcode::INLINEASM_BR) &&
3179 if (IsInlineAsmOperand &&
3180 (Id ==
"regdef" || Id ==
"reguse" || Id ==
"regdef-ec" ||
3181 Id ==
"clobber" || Id ==
"imm" || Id ==
"mem"))
3182 return parseInlineAsmOperand(Dest);
3183 if (
const auto *RegMask = PFS.Target.getRegMask(Id)) {
3187 }
else if (Id ==
"CustomRegMask") {
3188 return parseCustomRegisterMaskOperand(Dest);
3190 return parseTypedImmediateOperand(Dest);
3194 const auto *
TII = MF.getSubtarget().getInstrInfo();
3195 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3196 return parseTargetImmMnemonic(OpCode,
OpIdx, Dest, *Formatter);
3202 return error(
"expected a machine operand");
3207bool MIParser::parseMachineOperandAndTargetFlags(
3209 std::optional<unsigned> &TiedDefIdx) {
3211 bool HasTargetFlags =
false;
3213 HasTargetFlags =
true;
3218 return error(
"expected the name of the target flag");
3219 if (PFS.Target.getDirectTargetFlag(Token.stringValue(), TF)) {
3220 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), TF))
3221 return error(
"use of undefined target flag '" + Token.stringValue() +
3228 return error(
"expected the name of the target flag");
3229 unsigned BitFlag = 0;
3230 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), BitFlag))
3231 return error(
"use of undefined target flag '" + Token.stringValue() +
3240 auto Loc = Token.location();
3241 if (parseMachineOperand(OpCode,
OpIdx, Dest, TiedDefIdx))
3243 if (!HasTargetFlags)
3246 return error(
Loc,
"register operands can't have target flags");
3251bool MIParser::parseOffset(int64_t &
Offset) {
3258 return error(
"expected an integer literal after '" + Sign +
"'");
3259 if (Token.integerValue().getSignificantBits() > 64)
3260 return error(
"expected 64-bit integer (too large)");
3261 Offset = Token.integerValue().getExtValue();
3268bool MIParser::parseIRBlockAddressTaken(
BasicBlock *&BB) {
3272 return error(
"expected basic block after 'ir_block_address_taken'");
3274 if (parseIRBlock(BB, MF.getFunction()))
3281bool MIParser::parseAlignment(uint64_t &Alignment) {
3285 return error(
"expected an integer literal after 'align'");
3286 if (getUint64(Alignment))
3291 return error(
"expected a power-of-2 literal after 'align'");
3296bool MIParser::parseAddrspace(
unsigned &Addrspace) {
3300 return error(
"expected an integer literal after 'addrspace'");
3317 switch (Token.
kind()) {
3323 unsigned SlotNumber = 0;
3351 return ErrCB(Token.
location(),
Twine(
"use of undefined IR value '") + Token.
range() +
"'");
3355bool MIParser::parseIRValue(
const Value *&V) {
3356 return ::parseIRValue(
3362bool MIParser::getUint64(uint64_t &Result) {
3363 if (Token.hasIntegerValue()) {
3364 if (Token.integerValue().getActiveBits() > 64)
3365 return error(
"expected 64-bit integer (too large)");
3366 Result = Token.integerValue().getZExtValue();
3373 if (
A.getBitWidth() > 64)
3374 return error(
"expected 64-bit integer (too large)");
3381bool MIParser::getHexUint(
APInt &Result) {
3382 return ::getHexUint(Token, Result);
3386 const auto OldFlags =
Flags;
3387 switch (Token.kind()) {
3402 if (PFS.Target.getMMOTargetFlag(Token.stringValue(), TF))
3403 return error(
"use of undefined target MMO flag '" + Token.stringValue() +
3411 if (OldFlags == Flags)
3414 return error(
"duplicate '" + Token.stringValue() +
"' memory operand flag");
3420 switch (Token.kind()) {
3422 PSV = MF.getPSVManager().getStack();
3425 PSV = MF.getPSVManager().getGOT();
3428 PSV = MF.getPSVManager().getJumpTable();
3431 PSV = MF.getPSVManager().getConstantPool();
3435 if (parseFixedStackFrameIndex(FI))
3437 PSV = MF.getPSVManager().getFixedStack(FI);
3443 if (parseStackFrameIndex(FI))
3445 PSV = MF.getPSVManager().getFixedStack(FI);
3451 switch (Token.kind()) {
3457 PSV = MF.getPSVManager().getGlobalValueCallEntry(GV);
3461 PSV = MF.getPSVManager().getExternalSymbolCallEntry(
3462 MF.createExternalSymbolName(Token.stringValue()));
3466 "expected a global value or an external symbol after 'call-entry'");
3471 const auto *
TII = MF.getSubtarget().getInstrInfo();
3472 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3473 if (Formatter->parseCustomPseudoSourceValue(
3474 Token.stringValue(), MF, PFS, PSV,
3476 return error(Loc, Msg);
3480 return error(
"unable to parse target custom pseudo source value");
3497 if (parseMemoryPseudoSourceValue(PSV))
3510 return error(
"expected an IR value reference");
3511 const Value *
V =
nullptr;
3514 if (V && !
V->getType()->isPointerTy())
3515 return error(
"expected a pointer IR value");
3530 return error(
"expected '(' in syncscope");
3533 if (parseStringConstant(SSN))
3536 SSID =
Context.getOrInsertSyncScopeID(SSN);
3538 return error(
"expected ')' in syncscope");
3544bool MIParser::parseOptionalAtomicOrdering(
AtomicOrdering &Order) {
3563 return error(
"expected an atomic scope, ordering or a size specification");
3570 while (Token.isMemoryOperandFlag()) {
3571 if (parseMemoryOperandFlag(Flags))
3575 (Token.stringValue() !=
"load" && Token.stringValue() !=
"store"))
3576 return error(
"expected 'load' or 'store' memory operation");
3577 if (Token.stringValue() ==
"load")
3591 if (parseOptionalScope(MF.getFunction().getContext(), SSID))
3596 if (parseOptionalAtomicOrdering(Order))
3599 if (parseOptionalAtomicOrdering(FailureOrder))
3605 return error(
"expected memory LLT, the size integer literal or 'unknown-size' after "
3606 "memory operation");
3611 if (getUint64(
Size))
3622 if (parseLowLevelType(Token.location(), MemoryType))
3635 if (Token.stringValue() != Word)
3636 return error(
Twine(
"expected '") + Word +
"'");
3639 if (parseMachinePointerInfo(Ptr))
3642 uint64_t BaseAlignment =
3649 switch (Token.kind()) {
3655 if (Ptr.
Offset & (Alignment - 1)) {
3660 return error(
"specified alignment is more aligned than offset");
3662 BaseAlignment = Alignment;
3701 return error(
"expected 'align' or '!tbaa' or '!alias.scope' or "
3702 "'!noalias' or '!range' or '!noalias.addrspace'");
3707 Dest = MF.getMachineMemOperand(Ptr, Flags, MemoryType,
Align(BaseAlignment),
3708 AAInfo,
Range, SSID, Order, FailureOrder);
3712bool MIParser::parsePreOrPostInstrSymbol(
MCSymbol *&Symbol) {
3715 "Invalid token for a pre- post-instruction symbol!");
3718 return error(
"expected a symbol after 'pre-instr-symbol'");
3719 Symbol = getOrCreateMCSymbol(Token.stringValue());
3725 return error(
"expected ',' before the next machine operand");
3730bool MIParser::parseHeapAllocMarker(
MDNode *&Node) {
3732 "Invalid token for a heap alloc marker!");
3737 return error(
"expected a MDNode after 'heap-alloc-marker'");
3742 return error(
"expected ',' before the next machine operand");
3747bool MIParser::parsePCSections(
MDNode *&Node) {
3749 "Invalid token for a PC sections!");
3754 return error(
"expected a MDNode after 'pcsections'");
3759 return error(
"expected ',' before the next machine operand");
3764bool MIParser::parseMMRA(
MDNode *&Node) {
3773 return error(
"expected ',' before the next machine operand");
3783 for (
const auto &BB :
F) {
3789 Slots2BasicBlocks.
insert(std::make_pair(
unsigned(Slot), &BB));
3796 return Slots2BasicBlocks.
lookup(Slot);
3799const BasicBlock *MIParser::getIRBlock(
unsigned Slot) {
3800 if (Slots2BasicBlocks.empty())
3806 if (&
F == &MF.getFunction())
3807 return getIRBlock(Slot);
3819 return MF.getContext().getOrCreateSymbol(Name);
3822bool MIParser::parseStringConstant(std::string &Result) {
3824 return error(
"expected string constant");
3825 Result = std::string(Token.stringValue());
3833 return MIParser(PFS,
Error, Src).parseBasicBlockDefinitions(PFS.
MBBSlots);
3838 return MIParser(PFS,
Error, Src).parseBasicBlocks();
3844 return MIParser(PFS,
Error, Src).parseStandaloneMBB(
MBB);
3850 return MIParser(PFS,
Error, Src).parseStandaloneRegister(Reg);
3856 return MIParser(PFS,
Error, Src).parseStandaloneNamedRegister(Reg);
3862 return MIParser(PFS,
Error, Src).parseStandaloneVirtualRegister(Info);
3867 return MIParser(PFS,
Error, Src).parseStandaloneStackObject(FI);
3873 return MIParser(PFS,
Error, Src).parsePrefetchTarget(
Target);
3877 return MIParser(PFS,
Error, Src).parseStandaloneMDNode(
Node);
3882 return MIParser(PFS,
Error, Src, SrcRange).parseMachineMetadata();
3890 ErrorCallback(
Loc, Msg);
3894 return ::parseIRValue(Token, PFS, V, ErrorCallback);
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file defines the StringMap class.
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Atomic ordering constants.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static Error parseAlignment(StringRef Str, Align &Alignment, StringRef Name, bool AllowZero=false)
Attempts to parse an alignment component of a specification.
This file defines the DenseMap class.
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
A common definition of LaneBitmask for use in TableGen and CodeGen.
static llvm::Error parse(DataExtractor &Data, uint64_t BaseAddr, LineEntryCallback const &Callback)
Implement a low-level type suitable for MachineInstr level instruction selection.
static const char * printImplicitRegisterFlag(const MachineOperand &MO)
static const BasicBlock * getIRBlockFromSlot(unsigned Slot, const DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
static bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue, PerFunctionMIParsingState &PFS, const Constant *&C, ErrorCallbackType ErrCB)
static void initSlots2Values(const Function &F, DenseMap< unsigned, const Value * > &Slots2Values)
Creates the mapping from slot numbers to function's unnamed IR values.
static bool parseIRValue(const MIToken &Token, PerFunctionMIParsingState &PFS, const Value *&V, ErrorCallbackType ErrCB)
static bool verifyScalarSize(uint64_t Size)
static bool getUnsigned(const MIToken &Token, unsigned &Result, ErrorCallbackType ErrCB)
static bool getHexUint(const MIToken &Token, APInt &Result)
static bool verifyVectorElementCount(uint64_t NumElts)
static void mapValueToSlot(const Value *V, ModuleSlotTracker &MST, DenseMap< unsigned, const Value * > &Slots2Values)
static void initSlots2BasicBlocks(const Function &F, DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
function_ref< bool(StringRef::iterator Loc, const Twine &)> ErrorCallbackType
static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand, ArrayRef< ParsedMachineOperand > Operands)
Return true if the parsed machine operands contain a given machine operand.
static bool parseGlobalValue(const MIToken &Token, PerFunctionMIParsingState &PFS, GlobalValue *&GV, ErrorCallbackType ErrCB)
static bool verifyAddrSpace(uint64_t AddrSpace)
Register const TargetRegisterInfo * TRI
Promote Memory to Register
MachineInstr unsigned OpIdx
static constexpr unsigned SM(unsigned Version)
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
static bool parseMetadata(const StringRef &Input, uint64_t &FunctionHash, uint32_t &Attributes)
Parse Input that contains metadata.
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
An arbitrary precision integer that knows its signedness.
bool isNegative() const
Determine sign of this APSInt.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
const T & back() const
back - Get the last element.
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
LLVM Basic Block Representation.
static LLVM_ABI BlockAddress * get(Function *F, BasicBlock *BB)
Return a BlockAddress for the specified function and basic block.
static BranchProbability getRaw(uint32_t N)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
@ ICMP_SLT
signed less than
@ ICMP_SLE
signed less or equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_SGT
signed greater than
@ FCMP_ULT
1 1 0 0 True if unordered or less than
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
@ ICMP_ULT
unsigned less than
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
@ ICMP_SGE
signed greater or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
@ ICMP_ULE
unsigned less or equal
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
static bool isFPPredicate(Predicate P)
static bool isIntPredicate(Predicate P)
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Lightweight error class with error context and mandatory checking.
ValueSymbolTable * getValueSymbolTable()
getSymbolTable() - Return the symbol table if any, otherwise nullptr.
Module * getParent()
Get the module that this global value is contained inside of...
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT token()
Get a low-level token; just a scalar with zero bits (or no size).
This is an important class for using LLVM in a threaded context.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_undefined From now on the previous value of Register can't be restored anymore.
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
static MCCFIInstruction createLLVMDefAspaceCfa(MCSymbol *L, unsigned Register, int64_t Offset, unsigned AddressSpace, SMLoc Loc)
.cfi_llvm_def_aspace_cfa defines the rule for computing the CFA to be the result of evaluating the DW...
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2, SMLoc Loc={})
.cfi_register Previous value of Register1 is saved in register Register2.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction createNegateRAStateWithPC(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state_with_pc AArch64 negate RA state with PC.
static MCCFIInstruction createNegateRAState(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state AArch64 negate RA state.
static MCCFIInstruction createRememberState(MCSymbol *L, SMLoc Loc={})
.cfi_remember_state Save all current rules for all registers.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, SMLoc Loc={}, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
static MCCFIInstruction createWindowSave(MCSymbol *L, SMLoc Loc={})
.cfi_window_save SPARC register window is saved.
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int64_t Adjustment, SMLoc Loc={})
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
static MCCFIInstruction createRestoreState(MCSymbol *L, SMLoc Loc={})
.cfi_restore_state Restore the previously saved state.
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_same_value Current value of Register is the same as in the previous frame.
static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_rel_offset Previous value of Register is saved at offset Offset from the current CFA register.
Describe properties that are true of each instruction in the target description file.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static LLVM_ABI MDString * get(LLVMContext &Context, StringRef Str)
static MDTuple * getDistinct(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a distinct node.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static TempMDTuple getTemporary(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a temporary node.
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
void setAddressTakenIRBlock(BasicBlock *BB)
Set this block to reflect that it corresponds to an IR-level basic block with a BlockAddress.
LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
void setCallFrameSize(unsigned N)
Set the call frame size on entry to this basic block.
void setAlignment(Align A)
Set alignment of the basic block.
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void setSectionID(MBBSectionID V)
Sets the section ID for this basic block.
void setIsInlineAsmBrIndirectTarget(bool V=true)
Indicates if this is the indirect dest of an INLINEASM_BR.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
void setIsEHFuncletEntry(bool V=true)
Indicates if this is the entry block of an EH funclet.
LLVM_ABI bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
LLVM_ABI StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
void setIsEHScopeEntry(bool V=true)
Indicates if this is the entry block of an EH scope, i.e., the block that that used to have a catchpa...
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
void setFlag(MIFlag Flag)
Set a MI flag.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static MachineOperand CreateCImm(const ConstantInt *CI)
static MachineOperand CreateMetadata(const MDNode *Meta)
static MachineOperand CreatePredicate(unsigned Pred)
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
void setTargetFlags(unsigned F)
static MachineOperand CreateLaneMask(LaneBitmask LaneMask)
LLVM_ABI bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
LLVM_ABI Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
LLVM_ABI void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void noteNewVirtualRegister(Register Reg)
This interface provides simple read-only access to a block of memory, and provides simple methods for...
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
const char * getBufferEnd() const
const char * getBufferStart() const
Manage lifetime of a slot tracker for printing IR.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
void incorporateFunction(const Function &F)
Incorporate the given function.
A Module instance is used to store all the information related to an LLVM module.
Special value supplied for machine level alias analysis.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getNumRegBanks() const
Get the total number of register banks.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr unsigned id() const
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
Represents a range in source code.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This owns the files read by a parser, handles include stacks, and handles diagnostic wrangling.
bool insert(MapEntryTy *KeyValue)
insert - Insert the specified key/value pair into the map.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
std::string str() const
str - Get the contents as an std::string.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
StringRef drop_front(size_t N=1) const
Return a StringRef equal to 'this' but with the first N elements dropped.
constexpr size_t size() const
size - Get the string size.
char front() const
front - Get the first character in the string.
LLVM_ABI std::string lower() const
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
Target - Wrapper for Target specific information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM_ABI std::string str() const
Return the twine contents as a std::string.
Value * lookup(StringRef Name) const
This method finds the value with the given Name in the the symbol table.
LLVM Value Representation.
An efficient, type-erasing, non-owning reference to a callable.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
@ BasicBlock
Various leaf nodes.
LLVM_ABI ID lookupIntrinsicID(StringRef Name)
This does the actual lookup of an intrinsic ID which matches the given function name.
@ System
Synchronized with respect to all concurrently executing threads.
support::ulittle32_t Word
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
NodeAddr< NodeBase * > Node
This is an optimization pass for GlobalISel generic memory operations.
FunctionAddr VTableAddr Value
bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, StringRef Src, SMDiagnostic &Error)
bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, SMDiagnostic &Error)
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
RegState
Flags to represent properties of register accesses.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Kill
The last use of a register.
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Undef
Value of the register doesn't matter.
@ EarlyClobber
Register definition happens before uses.
@ Define
Register definition.
@ Renamable
Register that may be renamed.
@ Debug
Register 'use' is for debugging purpose.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
StringRef lexMIToken(StringRef Source, MIToken &Token, function_ref< void(StringRef::iterator, const Twine &)> ErrorCallback)
Consume a single machine instruction token in the given source and return the remaining source string...
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine basic block definitions, and skip the machine instructions.
bool parsePrefetchTarget(PerFunctionMIParsingState &PFS, CallsiteID &Target, StringRef Src, SMDiagnostic &Error)
LLVM_ABI void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl< MachineBasicBlock * > &Result, bool &IsFallthrough)
Determine a possible list of successors of a basic block based on the basic block machine operand bei...
bool parseMBBReference(PerFunctionMIParsingState &PFS, MachineBasicBlock *&MBB, StringRef Src, SMDiagnostic &Error)
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
auto dyn_cast_or_null(const Y &Val)
LLVM_ABI DIExpression * parseDIExpressionBodyAtBeginning(StringRef Asm, unsigned &Read, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots)
constexpr RegState getDefRegState(bool B)
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
constexpr bool hasRegState(RegState Value, RegState Test)
AtomicOrdering
Atomic ordering for LLVM's memory model.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
std::string toString(const APInt &I, unsigned Radix, bool Signed, bool formatAsCLiteral=false, bool UpperCase=true, bool InsertSeparators=false)
bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine instructions.
bool parseRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
LLVM_ABI Constant * parseConstantValue(StringRef Asm, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots=nullptr)
Parse a type and a constant value in the given string.
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
bool parseMachineMetadata(PerFunctionMIParsingState &PFS, StringRef Src, SMRange SourceRange, SMDiagnostic &Error)
bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, VRegInfo *&Info, StringRef Src, SMDiagnostic &Error)
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * NoAliasAddrSpace
The tag specifying the noalias address spaces.
MDNode * Scope
The tag for alias scope specification (used with noalias).
MDNode * TBAA
The tag for type-based alias analysis.
MDNode * NoAlias
The tag specifying the noalias scope.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static constexpr LaneBitmask getAll()
LLVM_ABI static const MBBSectionID ExceptionSectionID
LLVM_ABI static const MBBSectionID ColdSectionID
A token produced by the machine instruction lexer.
bool hasIntegerValue() const
bool is(TokenKind K) const
StringRef stringValue() const
Return the token's string value.
@ kw_cfi_aarch64_negate_ra_sign_state
@ kw_cfi_llvm_def_aspace_cfa
@ kw_inlineasm_br_indirect_target
@ kw_cfi_aarch64_negate_ra_sign_state_with_pc
@ kw_cfi_def_cfa_register
@ kw_cfi_adjust_cfa_offset
@ kw_machine_block_address_taken
@ kw_ir_block_address_taken
StringRef::iterator location() const
const APSInt & integerValue() const
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
VRegInfo & getVRegInfo(Register Num)
const SlotMapping & IRSlots
const Value * getIRValue(unsigned Slot)
DenseMap< unsigned, MachineBasicBlock * > MBBSlots
StringMap< VRegInfo * > VRegInfosNamed
DenseMap< unsigned, const Value * > Slots2Values
Maps from slot numbers to function's unnamed values.
PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, const SlotMapping &IRSlots, PerTargetMIParsingState &Target)
PerTargetMIParsingState & Target
DenseMap< Register, VRegInfo * > VRegInfos
VRegInfo & getVRegInfoNamed(StringRef RegName)
BumpPtrAllocator Allocator
bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const
bool getDirectTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a direct target flag to the corresponding target flag.
const RegisterBank * getRegBank(StringRef Name)
Check if the given identifier is a name of a register bank.
bool parseInstrName(StringRef InstrName, unsigned &OpCode)
Try to convert an instruction name to an opcode.
unsigned getSubRegIndex(StringRef Name)
Check if the given identifier is a name of a subregister index.
bool getTargetIndex(StringRef Name, int &Index)
Try to convert a name of target index to the corresponding target index.
void setTarget(const TargetSubtargetInfo &NewSubtarget)
bool getRegisterByName(StringRef RegName, Register &Reg)
Try to convert a register name to a register number.
bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag)
Try to convert a name of a MachineMemOperand target flag to the corresponding target flag.
bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a bitmask target flag to the corresponding target flag.
const TargetRegisterClass * getRegClass(StringRef Name)
Check if the given identifier is a name of a register class.
const uint32_t * getRegMask(StringRef Identifier)
Check if the given identifier is a name of a register mask.
This struct contains the mappings from the slot numbers to unnamed metadata nodes,...
NumberedValues< GlobalValue * > GlobalValues
const RegisterBank * RegBank
union llvm::VRegInfo::@127225073067155374133234315364317264041071000132 D
const TargetRegisterClass * RC
enum llvm::VRegInfo::@374354327266250320012227113300214031244227062232 Kind
bool Explicit
VReg was explicitly specified in the .mir file.