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15 #ifndef LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
16 #define LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
26 class MachineBasicBlock;
27 class MachineFunction;
30 class MachineRegisterInfo;
31 class RegisterClassInfo;
32 class TargetInstrInfo;
33 class TargetRegisterClass;
34 class TargetRegisterInfo;
53 std::vector<const TargetRegisterClass *> Classes;
56 std::multimap<unsigned, MachineOperand *> RegRefs;
59 std::multimap<unsigned, MachineOperand *>::const_iterator;
63 std::vector<unsigned> KillIndices;
67 std::vector<unsigned> DefIndices;
82 unsigned BreakAntiDependencies(
const std::vector<SUnit> &SUnits,
85 unsigned InsertPosIndex,
91 unsigned InsertPosIndex)
override;
94 void FinishBlock()
override;
99 bool isNewRegClobberedByRefs(RegRefIter RegRefBegin,
100 RegRefIter RegRefEnd,
102 unsigned findSuitableFreeRegister(RegRefIter RegRefBegin,
103 RegRefIter RegRefEnd,
112 #endif // LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
This is an optimization pass for GlobalISel generic memory operations.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned const TargetRegisterInfo * TRI
TargetInstrInfo - Interface to description of machine instruction set.
const HexagonInstrInfo * TII
Representation of each machine instruction.
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library,...
unsigned const MachineRegisterInfo * MRI
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector