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12 #ifndef LLVM_CODEGEN_RDFLIVENESS_H
13 #define LLVM_CODEGEN_RDFLIVENESS_H
21 #include <unordered_map>
22 #include <unordered_set>
27 class MachineBasicBlock;
28 class MachineDominanceFrontier;
29 class MachineDominatorTree;
30 class MachineRegisterInfo;
31 class TargetRegisterInfo;
39 using NodeRef = std::pair<NodeId, LaneBitmask>;
49 return std::hash<llvm::rdf::NodeId>{}(R.first) ^
50 std::hash<llvm::LaneBitmask::Type>{}(R.second.getAsInteger());
67 return Map.emplace(
B, Empty).first->second;
72 std::map<MachineBasicBlock*,RegisterAggr> Map;
77 using RefMap = std::unordered_map<RegisterId, NodeRefSet>;
80 : DFG(
g), TRI(
g.getTRI()), PRI(
g.getPRI()), MDT(
g.getDT()),
81 MDF(
g.getDF()), LiveMap(
g.getPRI()), Empty(), NoRegs(
g.getPRI()) {}
84 bool TopShadows,
bool FullChain,
const RegisterAggr &DefRRs);
112 auto F = RealUseMap.find(
P);
113 return F == RealUseMap.end() ? Empty :
F->second;
148 std::map<MachineBasicBlock*,std::set<MachineBasicBlock*>> IIDF;
151 std::map<MachineBasicBlock*,RefMap> PhiLON;
158 std::map<MachineBasicBlock*,RefMap> PhiLOX;
164 std::pair<NodeSet,bool> getAllReachingDefsRecImpl(
RegisterRef RefRR,
166 unsigned Nest,
unsigned MaxNest);
175 #endif // LLVM_CODEGEN_RDFLIVENESS_H
LiveMapType(const PhysicalRegisterInfo &pri)
This is an optimization pass for GlobalISel generic memory operations.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
std::unordered_map< RegisterId, NodeRefSet > RefMap
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr< DefNode * > DefA, const RegisterAggr &DefRRs)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
std::pair< NodeSet, bool > getAllReachingDefsRec(RegisterRef RefRR, NodeAddr< RefNode * > RefA, NodeSet &Visited, const NodeSet &Defs)
should just be implemented with a CLZ instruction Since there are other e g
Liveness(MachineRegisterInfo &mri, const DataFlowGraph &g)
NodeList getAllReachingDefs(NodeAddr< RefNode * > RefA)
NodeAddr< RefNode * > getNearestAliasedRef(RegisterRef RefRR, NodeAddr< InstrNode * > IA)
Find the nearest ref node aliased to RefRR, going upwards in the data flow, starting from the instruc...
const RefMap & getRealUses(NodeId P) const
NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr< DefNode * > DefA)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
std::pair< NodeId, LaneBitmask > NodeRef
This class implements an extremely fast bulk output stream that can only output to a stream.
RegisterAggr & operator[](MachineBasicBlock *B)
LiveMapType & getLiveMap()
raw_ostream & operator<<(raw_ostream &OS, const Print< RegisterRef > &P)
std::size_t operator()(llvm::rdf::detail::NodeRef R) const
std::set< NodeId > NodeSet
const LiveMapType & getLiveMap() const
NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr< RefNode * > RefA)
std::unordered_set< NodeRef > NodeRefSet
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR RN
NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr< RefNode * > RefA, bool TopShadows, bool FullChain, const RegisterAggr &DefRRs)
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...