12#ifndef LLVM_CODEGEN_RDFLIVENESS_H
13#define LLVM_CODEGEN_RDFLIVENESS_H
21#include <unordered_map>
22#include <unordered_set>
27class MachineBasicBlock;
28class MachineDominanceFrontier;
29class MachineDominatorTree;
30class MachineRegisterInfo;
31class TargetRegisterInfo;
39using NodeRef = std::pair<NodeId, LaneBitmask>;
47template <>
struct hash<
llvm::rdf::detail::NodeRef> {
49 return std::hash<llvm::rdf::NodeId>{}(R.first) ^
50 std::hash<llvm::LaneBitmask::Type>{}(R.second.getAsInteger());
67 return Map.emplace(
B, Empty).first->second;
72 std::map<MachineBasicBlock*,RegisterAggr> Map;
77 using RefMap = std::unordered_map<RegisterId, NodeRefSet>;
80 : DFG(
g), TRI(
g.getTRI()), PRI(
g.getPRI()), MDT(
g.getDT()),
81 MDF(
g.getDF()), LiveMap(
g.getPRI()), Empty(), NoRegs(
g.getPRI()) {}
84 bool TopShadows,
bool FullChain,
const RegisterAggr &DefRRs);
112 auto F = RealUseMap.find(
P);
113 return F == RealUseMap.end() ? Empty :
F->second;
148 std::map<MachineBasicBlock*,std::set<MachineBasicBlock*>> IIDF;
151 std::map<MachineBasicBlock*,RefMap> PhiLON;
158 std::map<MachineBasicBlock*,RefMap> PhiLOX;
164 std::pair<NodeSet,bool> getAllReachingDefsRecImpl(
RegisterRef RefRR,
166 unsigned Nest,
unsigned MaxNest);
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
This file defines the DenseMap class.
A common definition of LaneBitmask for use in TableGen and CodeGen.
INLINE void g(uint32_t *state, size_t a, size_t b, size_t c, size_t d, uint32_t x, uint32_t y)
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
std::pair< NodeId, LaneBitmask > NodeRef
raw_ostream & operator<<(raw_ostream &OS, const Print< RegisterRef > &P)
std::set< NodeId > NodeSet
This is an optimization pass for GlobalISel generic memory operations.
RegisterAggr & operator[](MachineBasicBlock *B)
LiveMapType(const PhysicalRegisterInfo &pri)
LiveMapType & getLiveMap()
std::unordered_set< NodeRef > NodeRefSet
const RefMap & getRealUses(NodeId P) const
NodeList getAllReachingDefs(NodeAddr< RefNode * > RefA)
NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr< RefNode * > RefA, bool TopShadows, bool FullChain, const RegisterAggr &DefRRs)
NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr< DefNode * > DefA, const RegisterAggr &DefRRs)
Liveness(MachineRegisterInfo &mri, const DataFlowGraph &g)
NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr< RefNode * > RefA)
NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr< DefNode * > DefA)
std::pair< NodeSet, bool > getAllReachingDefsRec(RegisterRef RefRR, NodeAddr< RefNode * > RefA, NodeSet &Visited, const NodeSet &Defs)
std::unordered_map< RegisterId, NodeRefSet > RefMap
const LiveMapType & getLiveMap() const
NodeAddr< RefNode * > getNearestAliasedRef(RegisterRef RefRR, NodeAddr< InstrNode * > IA)
Find the nearest ref node aliased to RefRR, going upwards in the data flow, starting from the instruc...
std::size_t operator()(llvm::rdf::detail::NodeRef R) const