LLVM  6.0.0svn
ARMAsmParser.cpp
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1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMFeatures.h"
11 #include "Utils/ARMBaseInfo.h"
14 #include "MCTargetDesc/ARMMCExpr.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/BinaryFormat/COFF.h"
22 #include "llvm/BinaryFormat/ELF.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/MC/MCAssembler.h"
25 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCELFStreamer.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCInstrInfo.h"
38 #include "llvm/MC/MCRegisterInfo.h"
39 #include "llvm/MC/MCSection.h"
40 #include "llvm/MC/MCStreamer.h"
42 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Support/ARMEHABI.h"
46 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/SourceMgr.h"
52 
53 using namespace llvm;
54 
55 namespace {
56 
57 enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
58 
59 static cl::opt<ImplicitItModeTy> ImplicitItMode(
60  "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
61  cl::desc("Allow conditional instructions outdside of an IT block"),
63  "Accept in both ISAs, emit implicit ITs in Thumb"),
65  "Warn in ARM, reject in Thumb"),
66  clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
67  "Accept in ARM, reject in Thumb"),
68  clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
69  "Warn in ARM, emit implicit ITs in Thumb")));
70 
71 static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
72  cl::init(false));
73 
74 class ARMOperand;
75 
76 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
77 
78 class UnwindContext {
79  MCAsmParser &Parser;
80 
81  typedef SmallVector<SMLoc, 4> Locs;
82 
83  Locs FnStartLocs;
84  Locs CantUnwindLocs;
85  Locs PersonalityLocs;
86  Locs PersonalityIndexLocs;
87  Locs HandlerDataLocs;
88  int FPReg;
89 
90 public:
91  UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
92 
93  bool hasFnStart() const { return !FnStartLocs.empty(); }
94  bool cantUnwind() const { return !CantUnwindLocs.empty(); }
95  bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
96  bool hasPersonality() const {
97  return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
98  }
99 
100  void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
101  void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
102  void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
103  void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
104  void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
105 
106  void saveFPReg(int Reg) { FPReg = Reg; }
107  int getFPReg() const { return FPReg; }
108 
109  void emitFnStartLocNotes() const {
110  for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
111  FI != FE; ++FI)
112  Parser.Note(*FI, ".fnstart was specified here");
113  }
114  void emitCantUnwindLocNotes() const {
115  for (Locs::const_iterator UI = CantUnwindLocs.begin(),
116  UE = CantUnwindLocs.end(); UI != UE; ++UI)
117  Parser.Note(*UI, ".cantunwind was specified here");
118  }
119  void emitHandlerDataLocNotes() const {
120  for (Locs::const_iterator HI = HandlerDataLocs.begin(),
121  HE = HandlerDataLocs.end(); HI != HE; ++HI)
122  Parser.Note(*HI, ".handlerdata was specified here");
123  }
124  void emitPersonalityLocNotes() const {
125  for (Locs::const_iterator PI = PersonalityLocs.begin(),
126  PE = PersonalityLocs.end(),
127  PII = PersonalityIndexLocs.begin(),
128  PIE = PersonalityIndexLocs.end();
129  PI != PE || PII != PIE;) {
130  if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
131  Parser.Note(*PI++, ".personality was specified here");
132  else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
133  Parser.Note(*PII++, ".personalityindex was specified here");
134  else
135  llvm_unreachable(".personality and .personalityindex cannot be "
136  "at the same location");
137  }
138  }
139 
140  void reset() {
141  FnStartLocs = Locs();
142  CantUnwindLocs = Locs();
143  PersonalityLocs = Locs();
144  HandlerDataLocs = Locs();
145  PersonalityIndexLocs = Locs();
146  FPReg = ARM::SP;
147  }
148 };
149 
150 class ARMAsmParser : public MCTargetAsmParser {
151  const MCInstrInfo &MII;
152  const MCRegisterInfo *MRI;
153  UnwindContext UC;
154 
155  ARMTargetStreamer &getTargetStreamer() {
156  assert(getParser().getStreamer().getTargetStreamer() &&
157  "do not have a target streamer");
158  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
159  return static_cast<ARMTargetStreamer &>(TS);
160  }
161 
162  // Map of register aliases registers via the .req directive.
163  StringMap<unsigned> RegisterReqs;
164 
165  bool NextSymbolIsThumb;
166 
167  bool useImplicitITThumb() const {
168  return ImplicitItMode == ImplicitItModeTy::Always ||
169  ImplicitItMode == ImplicitItModeTy::ThumbOnly;
170  }
171 
172  bool useImplicitITARM() const {
173  return ImplicitItMode == ImplicitItModeTy::Always ||
174  ImplicitItMode == ImplicitItModeTy::ARMOnly;
175  }
176 
177  struct {
178  ARMCC::CondCodes Cond; // Condition for IT block.
179  unsigned Mask:4; // Condition mask for instructions.
180  // Starting at first 1 (from lsb).
181  // '1' condition as indicated in IT.
182  // '0' inverse of condition (else).
183  // Count of instructions in IT block is
184  // 4 - trailingzeroes(mask)
185  // Note that this does not have the same encoding
186  // as in the IT instruction, which also depends
187  // on the low bit of the condition code.
188 
189  unsigned CurPosition; // Current position in parsing of IT
190  // block. In range [0,4], with 0 being the IT
191  // instruction itself. Initialized according to
192  // count of instructions in block. ~0U if no
193  // active IT block.
194 
195  bool IsExplicit; // true - The IT instruction was present in the
196  // input, we should not modify it.
197  // false - The IT instruction was added
198  // implicitly, we can extend it if that
199  // would be legal.
200  } ITState;
201 
202  llvm::SmallVector<MCInst, 4> PendingConditionalInsts;
203 
204  void flushPendingInstructions(MCStreamer &Out) override {
205  if (!inImplicitITBlock()) {
206  assert(PendingConditionalInsts.size() == 0);
207  return;
208  }
209 
210  // Emit the IT instruction
211  unsigned Mask = getITMaskEncoding();
212  MCInst ITInst;
213  ITInst.setOpcode(ARM::t2IT);
214  ITInst.addOperand(MCOperand::createImm(ITState.Cond));
215  ITInst.addOperand(MCOperand::createImm(Mask));
216  Out.EmitInstruction(ITInst, getSTI());
217 
218  // Emit the conditonal instructions
219  assert(PendingConditionalInsts.size() <= 4);
220  for (const MCInst &Inst : PendingConditionalInsts) {
221  Out.EmitInstruction(Inst, getSTI());
222  }
223  PendingConditionalInsts.clear();
224 
225  // Clear the IT state
226  ITState.Mask = 0;
227  ITState.CurPosition = ~0U;
228  }
229 
230  bool inITBlock() { return ITState.CurPosition != ~0U; }
231  bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
232  bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
233  bool lastInITBlock() {
234  return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
235  }
236  void forwardITPosition() {
237  if (!inITBlock()) return;
238  // Move to the next instruction in the IT block, if there is one. If not,
239  // mark the block as done, except for implicit IT blocks, which we leave
240  // open until we find an instruction that can't be added to it.
241  unsigned TZ = countTrailingZeros(ITState.Mask);
242  if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
243  ITState.CurPosition = ~0U; // Done with the IT block after this.
244  }
245 
246  // Rewind the state of the current IT block, removing the last slot from it.
247  void rewindImplicitITPosition() {
248  assert(inImplicitITBlock());
249  assert(ITState.CurPosition > 1);
250  ITState.CurPosition--;
251  unsigned TZ = countTrailingZeros(ITState.Mask);
252  unsigned NewMask = 0;
253  NewMask |= ITState.Mask & (0xC << TZ);
254  NewMask |= 0x2 << TZ;
255  ITState.Mask = NewMask;
256  }
257 
258  // Rewind the state of the current IT block, removing the last slot from it.
259  // If we were at the first slot, this closes the IT block.
260  void discardImplicitITBlock() {
261  assert(inImplicitITBlock());
262  assert(ITState.CurPosition == 1);
263  ITState.CurPosition = ~0U;
264  return;
265  }
266 
267  // Get the encoding of the IT mask, as it will appear in an IT instruction.
268  unsigned getITMaskEncoding() {
269  assert(inITBlock());
270  unsigned Mask = ITState.Mask;
271  unsigned TZ = countTrailingZeros(Mask);
272  if ((ITState.Cond & 1) == 0) {
273  assert(Mask && TZ <= 3 && "illegal IT mask value!");
274  Mask ^= (0xE << TZ) & 0xF;
275  }
276  return Mask;
277  }
278 
279  // Get the condition code corresponding to the current IT block slot.
280  ARMCC::CondCodes currentITCond() {
281  unsigned MaskBit;
282  if (ITState.CurPosition == 1)
283  MaskBit = 1;
284  else
285  MaskBit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
286 
287  return MaskBit ? ITState.Cond : ARMCC::getOppositeCondition(ITState.Cond);
288  }
289 
290  // Invert the condition of the current IT block slot without changing any
291  // other slots in the same block.
292  void invertCurrentITCondition() {
293  if (ITState.CurPosition == 1) {
294  ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
295  } else {
296  ITState.Mask ^= 1 << (5 - ITState.CurPosition);
297  }
298  }
299 
300  // Returns true if the current IT block is full (all 4 slots used).
301  bool isITBlockFull() {
302  return inITBlock() && (ITState.Mask & 1);
303  }
304 
305  // Extend the current implicit IT block to have one more slot with the given
306  // condition code.
307  void extendImplicitITBlock(ARMCC::CondCodes Cond) {
308  assert(inImplicitITBlock());
309  assert(!isITBlockFull());
310  assert(Cond == ITState.Cond ||
311  Cond == ARMCC::getOppositeCondition(ITState.Cond));
312  unsigned TZ = countTrailingZeros(ITState.Mask);
313  unsigned NewMask = 0;
314  // Keep any existing condition bits.
315  NewMask |= ITState.Mask & (0xE << TZ);
316  // Insert the new condition bit.
317  NewMask |= (Cond == ITState.Cond) << TZ;
318  // Move the trailing 1 down one bit.
319  NewMask |= 1 << (TZ - 1);
320  ITState.Mask = NewMask;
321  }
322 
323  // Create a new implicit IT block with a dummy condition code.
324  void startImplicitITBlock() {
325  assert(!inITBlock());
326  ITState.Cond = ARMCC::AL;
327  ITState.Mask = 8;
328  ITState.CurPosition = 1;
329  ITState.IsExplicit = false;
330  return;
331  }
332 
333  // Create a new explicit IT block with the given condition and mask. The mask
334  // should be in the parsed format, with a 1 implying 't', regardless of the
335  // low bit of the condition.
336  void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
337  assert(!inITBlock());
338  ITState.Cond = Cond;
339  ITState.Mask = Mask;
340  ITState.CurPosition = 0;
341  ITState.IsExplicit = true;
342  return;
343  }
344 
345  void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
346  return getParser().Note(L, Msg, Range);
347  }
348  bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
349  return getParser().Warning(L, Msg, Range);
350  }
351  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
352  return getParser().Error(L, Msg, Range);
353  }
354 
355  bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
356  unsigned ListNo, bool IsARPop = false);
357  bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
358  unsigned ListNo);
359 
360  int tryParseRegister();
361  bool tryParseRegisterWithWriteBack(OperandVector &);
362  int tryParseShiftRegister(OperandVector &);
363  bool parseRegisterList(OperandVector &);
364  bool parseMemory(OperandVector &);
365  bool parseOperand(OperandVector &, StringRef Mnemonic);
366  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
367  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
368  unsigned &ShiftAmount);
369  bool parseLiteralValues(unsigned Size, SMLoc L);
370  bool parseDirectiveThumb(SMLoc L);
371  bool parseDirectiveARM(SMLoc L);
372  bool parseDirectiveThumbFunc(SMLoc L);
373  bool parseDirectiveCode(SMLoc L);
374  bool parseDirectiveSyntax(SMLoc L);
375  bool parseDirectiveReq(StringRef Name, SMLoc L);
376  bool parseDirectiveUnreq(SMLoc L);
377  bool parseDirectiveArch(SMLoc L);
378  bool parseDirectiveEabiAttr(SMLoc L);
379  bool parseDirectiveCPU(SMLoc L);
380  bool parseDirectiveFPU(SMLoc L);
381  bool parseDirectiveFnStart(SMLoc L);
382  bool parseDirectiveFnEnd(SMLoc L);
383  bool parseDirectiveCantUnwind(SMLoc L);
384  bool parseDirectivePersonality(SMLoc L);
385  bool parseDirectiveHandlerData(SMLoc L);
386  bool parseDirectiveSetFP(SMLoc L);
387  bool parseDirectivePad(SMLoc L);
388  bool parseDirectiveRegSave(SMLoc L, bool IsVector);
389  bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
390  bool parseDirectiveLtorg(SMLoc L);
391  bool parseDirectiveEven(SMLoc L);
392  bool parseDirectivePersonalityIndex(SMLoc L);
393  bool parseDirectiveUnwindRaw(SMLoc L);
394  bool parseDirectiveTLSDescSeq(SMLoc L);
395  bool parseDirectiveMovSP(SMLoc L);
396  bool parseDirectiveObjectArch(SMLoc L);
397  bool parseDirectiveArchExtension(SMLoc L);
398  bool parseDirectiveAlign(SMLoc L);
399  bool parseDirectiveThumbSet(SMLoc L);
400 
401  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
402  bool &CarrySetting, unsigned &ProcessorIMod,
403  StringRef &ITMask);
404  void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
405  bool &CanAcceptCarrySet,
406  bool &CanAcceptPredicationCode);
407 
408  void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
409  OperandVector &Operands);
410  bool isThumb() const {
411  // FIXME: Can tablegen auto-generate this?
412  return getSTI().getFeatureBits()[ARM::ModeThumb];
413  }
414  bool isThumbOne() const {
415  return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
416  }
417  bool isThumbTwo() const {
418  return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
419  }
420  bool hasThumb() const {
421  return getSTI().getFeatureBits()[ARM::HasV4TOps];
422  }
423  bool hasThumb2() const {
424  return getSTI().getFeatureBits()[ARM::FeatureThumb2];
425  }
426  bool hasV6Ops() const {
427  return getSTI().getFeatureBits()[ARM::HasV6Ops];
428  }
429  bool hasV6T2Ops() const {
430  return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
431  }
432  bool hasV6MOps() const {
433  return getSTI().getFeatureBits()[ARM::HasV6MOps];
434  }
435  bool hasV7Ops() const {
436  return getSTI().getFeatureBits()[ARM::HasV7Ops];
437  }
438  bool hasV8Ops() const {
439  return getSTI().getFeatureBits()[ARM::HasV8Ops];
440  }
441  bool hasV8MBaseline() const {
442  return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
443  }
444  bool hasV8MMainline() const {
445  return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
446  }
447  bool has8MSecExt() const {
448  return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
449  }
450  bool hasARM() const {
451  return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
452  }
453  bool hasDSP() const {
454  return getSTI().getFeatureBits()[ARM::FeatureDSP];
455  }
456  bool hasD16() const {
457  return getSTI().getFeatureBits()[ARM::FeatureD16];
458  }
459  bool hasV8_1aOps() const {
460  return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
461  }
462  bool hasRAS() const {
463  return getSTI().getFeatureBits()[ARM::FeatureRAS];
464  }
465 
466  void SwitchMode() {
467  MCSubtargetInfo &STI = copySTI();
468  uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
469  setAvailableFeatures(FB);
470  }
471  void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
472  bool isMClass() const {
473  return getSTI().getFeatureBits()[ARM::FeatureMClass];
474  }
475 
476  /// @name Auto-generated Match Functions
477  /// {
478 
479 #define GET_ASSEMBLER_HEADER
480 #include "ARMGenAsmMatcher.inc"
481 
482  /// }
483 
484  OperandMatchResultTy parseITCondCode(OperandVector &);
485  OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
486  OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
487  OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
488  OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
489  OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
490  OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
491  OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
492  OperandMatchResultTy parseBankedRegOperand(OperandVector &);
493  OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
494  int High);
495  OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
496  return parsePKHImm(O, "lsl", 0, 31);
497  }
498  OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
499  return parsePKHImm(O, "asr", 1, 32);
500  }
501  OperandMatchResultTy parseSetEndImm(OperandVector &);
502  OperandMatchResultTy parseShifterImm(OperandVector &);
503  OperandMatchResultTy parseRotImm(OperandVector &);
504  OperandMatchResultTy parseModImm(OperandVector &);
505  OperandMatchResultTy parseBitfield(OperandVector &);
506  OperandMatchResultTy parsePostIdxReg(OperandVector &);
507  OperandMatchResultTy parseAM3Offset(OperandVector &);
508  OperandMatchResultTy parseFPImm(OperandVector &);
509  OperandMatchResultTy parseVectorList(OperandVector &);
510  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
511  SMLoc &EndLoc);
512 
513  // Asm Match Converter Methods
514  void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
515  void cvtThumbBranches(MCInst &Inst, const OperandVector &);
516 
517  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
518  bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
519  bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
520  bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
521  bool isITBlockTerminator(MCInst &Inst) const;
522 
523 public:
524  enum ARMMatchResultTy {
525  Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
526  Match_RequiresNotITBlock,
527  Match_RequiresV6,
528  Match_RequiresThumb2,
529  Match_RequiresV8,
530  Match_RequiresFlagSetting,
531 #define GET_OPERAND_DIAGNOSTIC_TYPES
532 #include "ARMGenAsmMatcher.inc"
533 
534  };
535 
536  ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
537  const MCInstrInfo &MII, const MCTargetOptions &Options)
538  : MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) {
540 
541  // Cache the MCRegisterInfo.
542  MRI = getContext().getRegisterInfo();
543 
544  // Initialize the set of available features.
545  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
546 
547  // Add build attributes based on the selected target.
548  if (AddBuildAttributes)
549  getTargetStreamer().emitTargetAttributes(STI);
550 
551  // Not in an ITBlock to start with.
552  ITState.CurPosition = ~0U;
553 
554  NextSymbolIsThumb = false;
555  }
556 
557  // Implementation of the MCTargetAsmParser interface:
558  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
559  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
560  SMLoc NameLoc, OperandVector &Operands) override;
561  bool ParseDirective(AsmToken DirectiveID) override;
562 
563  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
564  unsigned Kind) override;
565  unsigned checkTargetMatchPredicate(MCInst &Inst) override;
566 
567  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
568  OperandVector &Operands, MCStreamer &Out,
569  uint64_t &ErrorInfo,
570  bool MatchingInlineAsm) override;
571  unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
572  uint64_t &ErrorInfo, bool MatchingInlineAsm,
573  bool &EmitInITBlock, MCStreamer &Out);
574  void onLabelParsed(MCSymbol *Symbol) override;
575 };
576 } // end anonymous namespace
577 
578 namespace {
579 
580 /// ARMOperand - Instances of this class represent a parsed ARM machine
581 /// operand.
582 class ARMOperand : public MCParsedAsmOperand {
583  enum KindTy {
584  k_CondCode,
585  k_CCOut,
586  k_ITCondMask,
587  k_CoprocNum,
588  k_CoprocReg,
589  k_CoprocOption,
590  k_Immediate,
591  k_MemBarrierOpt,
592  k_InstSyncBarrierOpt,
593  k_Memory,
594  k_PostIndexRegister,
595  k_MSRMask,
596  k_BankedReg,
597  k_ProcIFlags,
598  k_VectorIndex,
599  k_Register,
600  k_RegisterList,
601  k_DPRRegisterList,
602  k_SPRRegisterList,
603  k_VectorList,
604  k_VectorListAllLanes,
605  k_VectorListIndexed,
606  k_ShiftedRegister,
607  k_ShiftedImmediate,
608  k_ShifterImmediate,
609  k_RotateImmediate,
610  k_ModifiedImmediate,
611  k_ConstantPoolImmediate,
612  k_BitfieldDescriptor,
613  k_Token,
614  } Kind;
615 
616  SMLoc StartLoc, EndLoc, AlignmentLoc;
617  SmallVector<unsigned, 8> Registers;
618 
619  struct CCOp {
620  ARMCC::CondCodes Val;
621  };
622 
623  struct CopOp {
624  unsigned Val;
625  };
626 
627  struct CoprocOptionOp {
628  unsigned Val;
629  };
630 
631  struct ITMaskOp {
632  unsigned Mask:4;
633  };
634 
635  struct MBOptOp {
636  ARM_MB::MemBOpt Val;
637  };
638 
639  struct ISBOptOp {
641  };
642 
643  struct IFlagsOp {
644  ARM_PROC::IFlags Val;
645  };
646 
647  struct MMaskOp {
648  unsigned Val;
649  };
650 
651  struct BankedRegOp {
652  unsigned Val;
653  };
654 
655  struct TokOp {
656  const char *Data;
657  unsigned Length;
658  };
659 
660  struct RegOp {
661  unsigned RegNum;
662  };
663 
664  // A vector register list is a sequential list of 1 to 4 registers.
665  struct VectorListOp {
666  unsigned RegNum;
667  unsigned Count;
668  unsigned LaneIndex;
669  bool isDoubleSpaced;
670  };
671 
672  struct VectorIndexOp {
673  unsigned Val;
674  };
675 
676  struct ImmOp {
677  const MCExpr *Val;
678  };
679 
680  /// Combined record for all forms of ARM address expressions.
681  struct MemoryOp {
682  unsigned BaseRegNum;
683  // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
684  // was specified.
685  const MCConstantExpr *OffsetImm; // Offset immediate value
686  unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
687  ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
688  unsigned ShiftImm; // shift for OffsetReg.
689  unsigned Alignment; // 0 = no alignment specified
690  // n = alignment in bytes (2, 4, 8, 16, or 32)
691  unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
692  };
693 
694  struct PostIdxRegOp {
695  unsigned RegNum;
696  bool isAdd;
697  ARM_AM::ShiftOpc ShiftTy;
698  unsigned ShiftImm;
699  };
700 
701  struct ShifterImmOp {
702  bool isASR;
703  unsigned Imm;
704  };
705 
706  struct RegShiftedRegOp {
707  ARM_AM::ShiftOpc ShiftTy;
708  unsigned SrcReg;
709  unsigned ShiftReg;
710  unsigned ShiftImm;
711  };
712 
713  struct RegShiftedImmOp {
714  ARM_AM::ShiftOpc ShiftTy;
715  unsigned SrcReg;
716  unsigned ShiftImm;
717  };
718 
719  struct RotImmOp {
720  unsigned Imm;
721  };
722 
723  struct ModImmOp {
724  unsigned Bits;
725  unsigned Rot;
726  };
727 
728  struct BitfieldOp {
729  unsigned LSB;
730  unsigned Width;
731  };
732 
733  union {
734  struct CCOp CC;
735  struct CopOp Cop;
736  struct CoprocOptionOp CoprocOption;
737  struct MBOptOp MBOpt;
738  struct ISBOptOp ISBOpt;
739  struct ITMaskOp ITMask;
740  struct IFlagsOp IFlags;
741  struct MMaskOp MMask;
742  struct BankedRegOp BankedReg;
743  struct TokOp Tok;
744  struct RegOp Reg;
745  struct VectorListOp VectorList;
746  struct VectorIndexOp VectorIndex;
747  struct ImmOp Imm;
748  struct MemoryOp Memory;
749  struct PostIdxRegOp PostIdxReg;
750  struct ShifterImmOp ShifterImm;
751  struct RegShiftedRegOp RegShiftedReg;
752  struct RegShiftedImmOp RegShiftedImm;
753  struct RotImmOp RotImm;
754  struct ModImmOp ModImm;
755  struct BitfieldOp Bitfield;
756  };
757 
758 public:
759  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
760 
761  /// getStartLoc - Get the location of the first token of this operand.
762  SMLoc getStartLoc() const override { return StartLoc; }
763  /// getEndLoc - Get the location of the last token of this operand.
764  SMLoc getEndLoc() const override { return EndLoc; }
765  /// getLocRange - Get the range between the first and last token of this
766  /// operand.
767  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
768 
769  /// getAlignmentLoc - Get the location of the Alignment token of this operand.
770  SMLoc getAlignmentLoc() const {
771  assert(Kind == k_Memory && "Invalid access!");
772  return AlignmentLoc;
773  }
774 
775  ARMCC::CondCodes getCondCode() const {
776  assert(Kind == k_CondCode && "Invalid access!");
777  return CC.Val;
778  }
779 
780  unsigned getCoproc() const {
781  assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
782  return Cop.Val;
783  }
784 
785  StringRef getToken() const {
786  assert(Kind == k_Token && "Invalid access!");
787  return StringRef(Tok.Data, Tok.Length);
788  }
789 
790  unsigned getReg() const override {
791  assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
792  return Reg.RegNum;
793  }
794 
795  const SmallVectorImpl<unsigned> &getRegList() const {
796  assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
797  Kind == k_SPRRegisterList) && "Invalid access!");
798  return Registers;
799  }
800 
801  const MCExpr *getImm() const {
802  assert(isImm() && "Invalid access!");
803  return Imm.Val;
804  }
805 
806  const MCExpr *getConstantPoolImm() const {
807  assert(isConstantPoolImm() && "Invalid access!");
808  return Imm.Val;
809  }
810 
811  unsigned getVectorIndex() const {
812  assert(Kind == k_VectorIndex && "Invalid access!");
813  return VectorIndex.Val;
814  }
815 
816  ARM_MB::MemBOpt getMemBarrierOpt() const {
817  assert(Kind == k_MemBarrierOpt && "Invalid access!");
818  return MBOpt.Val;
819  }
820 
821  ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
822  assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
823  return ISBOpt.Val;
824  }
825 
826  ARM_PROC::IFlags getProcIFlags() const {
827  assert(Kind == k_ProcIFlags && "Invalid access!");
828  return IFlags.Val;
829  }
830 
831  unsigned getMSRMask() const {
832  assert(Kind == k_MSRMask && "Invalid access!");
833  return MMask.Val;
834  }
835 
836  unsigned getBankedReg() const {
837  assert(Kind == k_BankedReg && "Invalid access!");
838  return BankedReg.Val;
839  }
840 
841  bool isCoprocNum() const { return Kind == k_CoprocNum; }
842  bool isCoprocReg() const { return Kind == k_CoprocReg; }
843  bool isCoprocOption() const { return Kind == k_CoprocOption; }
844  bool isCondCode() const { return Kind == k_CondCode; }
845  bool isCCOut() const { return Kind == k_CCOut; }
846  bool isITMask() const { return Kind == k_ITCondMask; }
847  bool isITCondCode() const { return Kind == k_CondCode; }
848  bool isImm() const override {
849  return Kind == k_Immediate;
850  }
851 
852  bool isARMBranchTarget() const {
853  if (!isImm()) return false;
854 
855  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
856  return CE->getValue() % 4 == 0;
857  return true;
858  }
859 
860 
861  bool isThumbBranchTarget() const {
862  if (!isImm()) return false;
863 
864  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
865  return CE->getValue() % 2 == 0;
866  return true;
867  }
868 
869  // checks whether this operand is an unsigned offset which fits is a field
870  // of specified width and scaled by a specific number of bits
871  template<unsigned width, unsigned scale>
872  bool isUnsignedOffset() const {
873  if (!isImm()) return false;
874  if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
875  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
876  int64_t Val = CE->getValue();
877  int64_t Align = 1LL << scale;
878  int64_t Max = Align * ((1LL << width) - 1);
879  return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
880  }
881  return false;
882  }
883  // checks whether this operand is an signed offset which fits is a field
884  // of specified width and scaled by a specific number of bits
885  template<unsigned width, unsigned scale>
886  bool isSignedOffset() const {
887  if (!isImm()) return false;
888  if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
889  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
890  int64_t Val = CE->getValue();
891  int64_t Align = 1LL << scale;
892  int64_t Max = Align * ((1LL << (width-1)) - 1);
893  int64_t Min = -Align * (1LL << (width-1));
894  return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
895  }
896  return false;
897  }
898 
899  // checks whether this operand is a memory operand computed as an offset
900  // applied to PC. the offset may have 8 bits of magnitude and is represented
901  // with two bits of shift. textually it may be either [pc, #imm], #imm or
902  // relocable expression...
903  bool isThumbMemPC() const {
904  int64_t Val = 0;
905  if (isImm()) {
906  if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
907  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
908  if (!CE) return false;
909  Val = CE->getValue();
910  }
911  else if (isMem()) {
912  if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
913  if(Memory.BaseRegNum != ARM::PC) return false;
914  Val = Memory.OffsetImm->getValue();
915  }
916  else return false;
917  return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
918  }
919  bool isFPImm() const {
920  if (!isImm()) return false;
921  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
922  if (!CE) return false;
923  int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
924  return Val != -1;
925  }
926 
927  template<int64_t N, int64_t M>
928  bool isImmediate() const {
929  if (!isImm()) return false;
930  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
931  if (!CE) return false;
932  int64_t Value = CE->getValue();
933  return Value >= N && Value <= M;
934  }
935  template<int64_t N, int64_t M>
936  bool isImmediateS4() const {
937  if (!isImm()) return false;
938  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
939  if (!CE) return false;
940  int64_t Value = CE->getValue();
941  return ((Value & 3) == 0) && Value >= N && Value <= M;
942  }
943  bool isFBits16() const {
944  return isImmediate<0, 17>();
945  }
946  bool isFBits32() const {
947  return isImmediate<1, 33>();
948  }
949  bool isImm8s4() const {
950  return isImmediateS4<-1020, 1020>();
951  }
952  bool isImm0_1020s4() const {
953  return isImmediateS4<0, 1020>();
954  }
955  bool isImm0_508s4() const {
956  return isImmediateS4<0, 508>();
957  }
958  bool isImm0_508s4Neg() const {
959  if (!isImm()) return false;
960  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
961  if (!CE) return false;
962  int64_t Value = -CE->getValue();
963  // explicitly exclude zero. we want that to use the normal 0_508 version.
964  return ((Value & 3) == 0) && Value > 0 && Value <= 508;
965  }
966  bool isImm0_4095Neg() const {
967  if (!isImm()) return false;
968  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
969  if (!CE) return false;
970  int64_t Value = -CE->getValue();
971  return Value > 0 && Value < 4096;
972  }
973  bool isImm0_7() const {
974  return isImmediate<0, 7>();
975  }
976  bool isImm1_16() const {
977  return isImmediate<1, 16>();
978  }
979  bool isImm1_32() const {
980  return isImmediate<1, 32>();
981  }
982  bool isImm8_255() const {
983  return isImmediate<8, 255>();
984  }
985  bool isImm256_65535Expr() const {
986  if (!isImm()) return false;
987  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
988  // If it's not a constant expression, it'll generate a fixup and be
989  // handled later.
990  if (!CE) return true;
991  int64_t Value = CE->getValue();
992  return Value >= 256 && Value < 65536;
993  }
994  bool isImm0_65535Expr() const {
995  if (!isImm()) return false;
996  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
997  // If it's not a constant expression, it'll generate a fixup and be
998  // handled later.
999  if (!CE) return true;
1000  int64_t Value = CE->getValue();
1001  return Value >= 0 && Value < 65536;
1002  }
1003  bool isImm24bit() const {
1004  return isImmediate<0, 0xffffff + 1>();
1005  }
1006  bool isImmThumbSR() const {
1007  return isImmediate<1, 33>();
1008  }
1009  bool isPKHLSLImm() const {
1010  return isImmediate<0, 32>();
1011  }
1012  bool isPKHASRImm() const {
1013  return isImmediate<0, 33>();
1014  }
1015  bool isAdrLabel() const {
1016  // If we have an immediate that's not a constant, treat it as a label
1017  // reference needing a fixup.
1018  if (isImm() && !isa<MCConstantExpr>(getImm()))
1019  return true;
1020 
1021  // If it is a constant, it must fit into a modified immediate encoding.
1022  if (!isImm()) return false;
1023  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1024  if (!CE) return false;
1025  int64_t Value = CE->getValue();
1026  return (ARM_AM::getSOImmVal(Value) != -1 ||
1027  ARM_AM::getSOImmVal(-Value) != -1);
1028  }
1029  bool isT2SOImm() const {
1030  // If we have an immediate that's not a constant, treat it as an expression
1031  // needing a fixup.
1032  if (isImm() && !isa<MCConstantExpr>(getImm())) {
1033  // We want to avoid matching :upper16: and :lower16: as we want these
1034  // expressions to match in isImm0_65535Expr()
1035  const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm());
1036  return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
1037  ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16));
1038  }
1039  if (!isImm()) return false;
1040  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1041  if (!CE) return false;
1042  int64_t Value = CE->getValue();
1043  return ARM_AM::getT2SOImmVal(Value) != -1;
1044  }
1045  bool isT2SOImmNot() const {
1046  if (!isImm()) return false;
1047  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1048  if (!CE) return false;
1049  int64_t Value = CE->getValue();
1050  return ARM_AM::getT2SOImmVal(Value) == -1 &&
1051  ARM_AM::getT2SOImmVal(~Value) != -1;
1052  }
1053  bool isT2SOImmNeg() const {
1054  if (!isImm()) return false;
1055  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1056  if (!CE) return false;
1057  int64_t Value = CE->getValue();
1058  // Only use this when not representable as a plain so_imm.
1059  return ARM_AM::getT2SOImmVal(Value) == -1 &&
1060  ARM_AM::getT2SOImmVal(-Value) != -1;
1061  }
1062  bool isSetEndImm() const {
1063  if (!isImm()) return false;
1064  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1065  if (!CE) return false;
1066  int64_t Value = CE->getValue();
1067  return Value == 1 || Value == 0;
1068  }
1069  bool isReg() const override { return Kind == k_Register; }
1070  bool isRegList() const { return Kind == k_RegisterList; }
1071  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1072  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1073  bool isToken() const override { return Kind == k_Token; }
1074  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1075  bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1076  bool isMem() const override { return Kind == k_Memory; }
1077  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1078  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1079  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1080  bool isRotImm() const { return Kind == k_RotateImmediate; }
1081  bool isModImm() const { return Kind == k_ModifiedImmediate; }
1082  bool isModImmNot() const {
1083  if (!isImm()) return false;
1084  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1085  if (!CE) return false;
1086  int64_t Value = CE->getValue();
1087  return ARM_AM::getSOImmVal(~Value) != -1;
1088  }
1089  bool isModImmNeg() const {
1090  if (!isImm()) return false;
1091  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1092  if (!CE) return false;
1093  int64_t Value = CE->getValue();
1094  return ARM_AM::getSOImmVal(Value) == -1 &&
1095  ARM_AM::getSOImmVal(-Value) != -1;
1096  }
1097  bool isThumbModImmNeg1_7() const {
1098  if (!isImm()) return false;
1099  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1100  if (!CE) return false;
1101  int32_t Value = -(int32_t)CE->getValue();
1102  return 0 < Value && Value < 8;
1103  }
1104  bool isThumbModImmNeg8_255() const {
1105  if (!isImm()) return false;
1106  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1107  if (!CE) return false;
1108  int32_t Value = -(int32_t)CE->getValue();
1109  return 7 < Value && Value < 256;
1110  }
1111  bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1112  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1113  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1114  bool isPostIdxReg() const {
1115  return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1116  }
1117  bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1118  if (!isMem())
1119  return false;
1120  // No offset of any kind.
1121  return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1122  (alignOK || Memory.Alignment == Alignment);
1123  }
1124  bool isMemPCRelImm12() const {
1125  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1126  return false;
1127  // Base register must be PC.
1128  if (Memory.BaseRegNum != ARM::PC)
1129  return false;
1130  // Immediate offset in range [-4095, 4095].
1131  if (!Memory.OffsetImm) return true;
1132  int64_t Val = Memory.OffsetImm->getValue();
1133  return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1134  }
1135  bool isAlignedMemory() const {
1136  return isMemNoOffset(true);
1137  }
1138  bool isAlignedMemoryNone() const {
1139  return isMemNoOffset(false, 0);
1140  }
1141  bool isDupAlignedMemoryNone() const {
1142  return isMemNoOffset(false, 0);
1143  }
1144  bool isAlignedMemory16() const {
1145  if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1146  return true;
1147  return isMemNoOffset(false, 0);
1148  }
1149  bool isDupAlignedMemory16() const {
1150  if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1151  return true;
1152  return isMemNoOffset(false, 0);
1153  }
1154  bool isAlignedMemory32() const {
1155  if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1156  return true;
1157  return isMemNoOffset(false, 0);
1158  }
1159  bool isDupAlignedMemory32() const {
1160  if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1161  return true;
1162  return isMemNoOffset(false, 0);
1163  }
1164  bool isAlignedMemory64() const {
1165  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1166  return true;
1167  return isMemNoOffset(false, 0);
1168  }
1169  bool isDupAlignedMemory64() const {
1170  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1171  return true;
1172  return isMemNoOffset(false, 0);
1173  }
1174  bool isAlignedMemory64or128() const {
1175  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1176  return true;
1177  if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1178  return true;
1179  return isMemNoOffset(false, 0);
1180  }
1181  bool isDupAlignedMemory64or128() const {
1182  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1183  return true;
1184  if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1185  return true;
1186  return isMemNoOffset(false, 0);
1187  }
1188  bool isAlignedMemory64or128or256() const {
1189  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1190  return true;
1191  if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1192  return true;
1193  if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1194  return true;
1195  return isMemNoOffset(false, 0);
1196  }
1197  bool isAddrMode2() const {
1198  if (!isMem() || Memory.Alignment != 0) return false;
1199  // Check for register offset.
1200  if (Memory.OffsetRegNum) return true;
1201  // Immediate offset in range [-4095, 4095].
1202  if (!Memory.OffsetImm) return true;
1203  int64_t Val = Memory.OffsetImm->getValue();
1204  return Val > -4096 && Val < 4096;
1205  }
1206  bool isAM2OffsetImm() const {
1207  if (!isImm()) return false;
1208  // Immediate offset in range [-4095, 4095].
1209  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1210  if (!CE) return false;
1211  int64_t Val = CE->getValue();
1212  return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1213  }
1214  bool isAddrMode3() const {
1215  // If we have an immediate that's not a constant, treat it as a label
1216  // reference needing a fixup. If it is a constant, it's something else
1217  // and we reject it.
1218  if (isImm() && !isa<MCConstantExpr>(getImm()))
1219  return true;
1220  if (!isMem() || Memory.Alignment != 0) return false;
1221  // No shifts are legal for AM3.
1222  if (Memory.ShiftType != ARM_AM::no_shift) return false;
1223  // Check for register offset.
1224  if (Memory.OffsetRegNum) return true;
1225  // Immediate offset in range [-255, 255].
1226  if (!Memory.OffsetImm) return true;
1227  int64_t Val = Memory.OffsetImm->getValue();
1228  // The #-0 offset is encoded as INT32_MIN, and we have to check
1229  // for this too.
1230  return (Val > -256 && Val < 256) || Val == INT32_MIN;
1231  }
1232  bool isAM3Offset() const {
1233  if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1234  return false;
1235  if (Kind == k_PostIndexRegister)
1236  return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1237  // Immediate offset in range [-255, 255].
1238  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1239  if (!CE) return false;
1240  int64_t Val = CE->getValue();
1241  // Special case, #-0 is INT32_MIN.
1242  return (Val > -256 && Val < 256) || Val == INT32_MIN;
1243  }
1244  bool isAddrMode5() const {
1245  // If we have an immediate that's not a constant, treat it as a label
1246  // reference needing a fixup. If it is a constant, it's something else
1247  // and we reject it.
1248  if (isImm() && !isa<MCConstantExpr>(getImm()))
1249  return true;
1250  if (!isMem() || Memory.Alignment != 0) return false;
1251  // Check for register offset.
1252  if (Memory.OffsetRegNum) return false;
1253  // Immediate offset in range [-1020, 1020] and a multiple of 4.
1254  if (!Memory.OffsetImm) return true;
1255  int64_t Val = Memory.OffsetImm->getValue();
1256  return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1257  Val == INT32_MIN;
1258  }
1259  bool isAddrMode5FP16() const {
1260  // If we have an immediate that's not a constant, treat it as a label
1261  // reference needing a fixup. If it is a constant, it's something else
1262  // and we reject it.
1263  if (isImm() && !isa<MCConstantExpr>(getImm()))
1264  return true;
1265  if (!isMem() || Memory.Alignment != 0) return false;
1266  // Check for register offset.
1267  if (Memory.OffsetRegNum) return false;
1268  // Immediate offset in range [-510, 510] and a multiple of 2.
1269  if (!Memory.OffsetImm) return true;
1270  int64_t Val = Memory.OffsetImm->getValue();
1271  return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) || Val == INT32_MIN;
1272  }
1273  bool isMemTBB() const {
1274  if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1275  Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1276  return false;
1277  return true;
1278  }
1279  bool isMemTBH() const {
1280  if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1281  Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1282  Memory.Alignment != 0 )
1283  return false;
1284  return true;
1285  }
1286  bool isMemRegOffset() const {
1287  if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1288  return false;
1289  return true;
1290  }
1291  bool isT2MemRegOffset() const {
1292  if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1293  Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1294  return false;
1295  // Only lsl #{0, 1, 2, 3} allowed.
1296  if (Memory.ShiftType == ARM_AM::no_shift)
1297  return true;
1298  if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1299  return false;
1300  return true;
1301  }
1302  bool isMemThumbRR() const {
1303  // Thumb reg+reg addressing is simple. Just two registers, a base and
1304  // an offset. No shifts, negations or any other complicating factors.
1305  if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1306  Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1307  return false;
1308  return isARMLowRegister(Memory.BaseRegNum) &&
1309  (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1310  }
1311  bool isMemThumbRIs4() const {
1312  if (!isMem() || Memory.OffsetRegNum != 0 ||
1313  !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1314  return false;
1315  // Immediate offset, multiple of 4 in range [0, 124].
1316  if (!Memory.OffsetImm) return true;
1317  int64_t Val = Memory.OffsetImm->getValue();
1318  return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1319  }
1320  bool isMemThumbRIs2() const {
1321  if (!isMem() || Memory.OffsetRegNum != 0 ||
1322  !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1323  return false;
1324  // Immediate offset, multiple of 4 in range [0, 62].
1325  if (!Memory.OffsetImm) return true;
1326  int64_t Val = Memory.OffsetImm->getValue();
1327  return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1328  }
1329  bool isMemThumbRIs1() const {
1330  if (!isMem() || Memory.OffsetRegNum != 0 ||
1331  !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1332  return false;
1333  // Immediate offset in range [0, 31].
1334  if (!Memory.OffsetImm) return true;
1335  int64_t Val = Memory.OffsetImm->getValue();
1336  return Val >= 0 && Val <= 31;
1337  }
1338  bool isMemThumbSPI() const {
1339  if (!isMem() || Memory.OffsetRegNum != 0 ||
1340  Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1341  return false;
1342  // Immediate offset, multiple of 4 in range [0, 1020].
1343  if (!Memory.OffsetImm) return true;
1344  int64_t Val = Memory.OffsetImm->getValue();
1345  return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1346  }
1347  bool isMemImm8s4Offset() const {
1348  // If we have an immediate that's not a constant, treat it as a label
1349  // reference needing a fixup. If it is a constant, it's something else
1350  // and we reject it.
1351  if (isImm() && !isa<MCConstantExpr>(getImm()))
1352  return true;
1353  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1354  return false;
1355  // Immediate offset a multiple of 4 in range [-1020, 1020].
1356  if (!Memory.OffsetImm) return true;
1357  int64_t Val = Memory.OffsetImm->getValue();
1358  // Special case, #-0 is INT32_MIN.
1359  return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1360  }
1361  bool isMemImm0_1020s4Offset() const {
1362  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1363  return false;
1364  // Immediate offset a multiple of 4 in range [0, 1020].
1365  if (!Memory.OffsetImm) return true;
1366  int64_t Val = Memory.OffsetImm->getValue();
1367  return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1368  }
1369  bool isMemImm8Offset() const {
1370  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1371  return false;
1372  // Base reg of PC isn't allowed for these encodings.
1373  if (Memory.BaseRegNum == ARM::PC) return false;
1374  // Immediate offset in range [-255, 255].
1375  if (!Memory.OffsetImm) return true;
1376  int64_t Val = Memory.OffsetImm->getValue();
1377  return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1378  }
1379  bool isMemPosImm8Offset() const {
1380  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1381  return false;
1382  // Immediate offset in range [0, 255].
1383  if (!Memory.OffsetImm) return true;
1384  int64_t Val = Memory.OffsetImm->getValue();
1385  return Val >= 0 && Val < 256;
1386  }
1387  bool isMemNegImm8Offset() const {
1388  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1389  return false;
1390  // Base reg of PC isn't allowed for these encodings.
1391  if (Memory.BaseRegNum == ARM::PC) return false;
1392  // Immediate offset in range [-255, -1].
1393  if (!Memory.OffsetImm) return false;
1394  int64_t Val = Memory.OffsetImm->getValue();
1395  return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1396  }
1397  bool isMemUImm12Offset() const {
1398  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1399  return false;
1400  // Immediate offset in range [0, 4095].
1401  if (!Memory.OffsetImm) return true;
1402  int64_t Val = Memory.OffsetImm->getValue();
1403  return (Val >= 0 && Val < 4096);
1404  }
1405  bool isMemImm12Offset() const {
1406  // If we have an immediate that's not a constant, treat it as a label
1407  // reference needing a fixup. If it is a constant, it's something else
1408  // and we reject it.
1409 
1410  if (isImm() && !isa<MCConstantExpr>(getImm()))
1411  return true;
1412 
1413  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1414  return false;
1415  // Immediate offset in range [-4095, 4095].
1416  if (!Memory.OffsetImm) return true;
1417  int64_t Val = Memory.OffsetImm->getValue();
1418  return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1419  }
1420  bool isConstPoolAsmImm() const {
1421  // Delay processing of Constant Pool Immediate, this will turn into
1422  // a constant. Match no other operand
1423  return (isConstantPoolImm());
1424  }
1425  bool isPostIdxImm8() const {
1426  if (!isImm()) return false;
1427  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1428  if (!CE) return false;
1429  int64_t Val = CE->getValue();
1430  return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1431  }
1432  bool isPostIdxImm8s4() const {
1433  if (!isImm()) return false;
1434  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1435  if (!CE) return false;
1436  int64_t Val = CE->getValue();
1437  return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1438  (Val == INT32_MIN);
1439  }
1440 
1441  bool isMSRMask() const { return Kind == k_MSRMask; }
1442  bool isBankedReg() const { return Kind == k_BankedReg; }
1443  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1444 
1445  // NEON operands.
1446  bool isSingleSpacedVectorList() const {
1447  return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1448  }
1449  bool isDoubleSpacedVectorList() const {
1450  return Kind == k_VectorList && VectorList.isDoubleSpaced;
1451  }
1452  bool isVecListOneD() const {
1453  if (!isSingleSpacedVectorList()) return false;
1454  return VectorList.Count == 1;
1455  }
1456 
1457  bool isVecListDPair() const {
1458  if (!isSingleSpacedVectorList()) return false;
1459  return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1460  .contains(VectorList.RegNum));
1461  }
1462 
1463  bool isVecListThreeD() const {
1464  if (!isSingleSpacedVectorList()) return false;
1465  return VectorList.Count == 3;
1466  }
1467 
1468  bool isVecListFourD() const {
1469  if (!isSingleSpacedVectorList()) return false;
1470  return VectorList.Count == 4;
1471  }
1472 
1473  bool isVecListDPairSpaced() const {
1474  if (Kind != k_VectorList) return false;
1475  if (isSingleSpacedVectorList()) return false;
1476  return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1477  .contains(VectorList.RegNum));
1478  }
1479 
1480  bool isVecListThreeQ() const {
1481  if (!isDoubleSpacedVectorList()) return false;
1482  return VectorList.Count == 3;
1483  }
1484 
1485  bool isVecListFourQ() const {
1486  if (!isDoubleSpacedVectorList()) return false;
1487  return VectorList.Count == 4;
1488  }
1489 
1490  bool isSingleSpacedVectorAllLanes() const {
1491  return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1492  }
1493  bool isDoubleSpacedVectorAllLanes() const {
1494  return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1495  }
1496  bool isVecListOneDAllLanes() const {
1497  if (!isSingleSpacedVectorAllLanes()) return false;
1498  return VectorList.Count == 1;
1499  }
1500 
1501  bool isVecListDPairAllLanes() const {
1502  if (!isSingleSpacedVectorAllLanes()) return false;
1503  return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1504  .contains(VectorList.RegNum));
1505  }
1506 
1507  bool isVecListDPairSpacedAllLanes() const {
1508  if (!isDoubleSpacedVectorAllLanes()) return false;
1509  return VectorList.Count == 2;
1510  }
1511 
1512  bool isVecListThreeDAllLanes() const {
1513  if (!isSingleSpacedVectorAllLanes()) return false;
1514  return VectorList.Count == 3;
1515  }
1516 
1517  bool isVecListThreeQAllLanes() const {
1518  if (!isDoubleSpacedVectorAllLanes()) return false;
1519  return VectorList.Count == 3;
1520  }
1521 
1522  bool isVecListFourDAllLanes() const {
1523  if (!isSingleSpacedVectorAllLanes()) return false;
1524  return VectorList.Count == 4;
1525  }
1526 
1527  bool isVecListFourQAllLanes() const {
1528  if (!isDoubleSpacedVectorAllLanes()) return false;
1529  return VectorList.Count == 4;
1530  }
1531 
1532  bool isSingleSpacedVectorIndexed() const {
1533  return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1534  }
1535  bool isDoubleSpacedVectorIndexed() const {
1536  return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1537  }
1538  bool isVecListOneDByteIndexed() const {
1539  if (!isSingleSpacedVectorIndexed()) return false;
1540  return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1541  }
1542 
1543  bool isVecListOneDHWordIndexed() const {
1544  if (!isSingleSpacedVectorIndexed()) return false;
1545  return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1546  }
1547 
1548  bool isVecListOneDWordIndexed() const {
1549  if (!isSingleSpacedVectorIndexed()) return false;
1550  return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1551  }
1552 
1553  bool isVecListTwoDByteIndexed() const {
1554  if (!isSingleSpacedVectorIndexed()) return false;
1555  return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1556  }
1557 
1558  bool isVecListTwoDHWordIndexed() const {
1559  if (!isSingleSpacedVectorIndexed()) return false;
1560  return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1561  }
1562 
1563  bool isVecListTwoQWordIndexed() const {
1564  if (!isDoubleSpacedVectorIndexed()) return false;
1565  return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1566  }
1567 
1568  bool isVecListTwoQHWordIndexed() const {
1569  if (!isDoubleSpacedVectorIndexed()) return false;
1570  return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1571  }
1572 
1573  bool isVecListTwoDWordIndexed() const {
1574  if (!isSingleSpacedVectorIndexed()) return false;
1575  return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1576  }
1577 
1578  bool isVecListThreeDByteIndexed() const {
1579  if (!isSingleSpacedVectorIndexed()) return false;
1580  return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1581  }
1582 
1583  bool isVecListThreeDHWordIndexed() const {
1584  if (!isSingleSpacedVectorIndexed()) return false;
1585  return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1586  }
1587 
1588  bool isVecListThreeQWordIndexed() const {
1589  if (!isDoubleSpacedVectorIndexed()) return false;
1590  return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1591  }
1592 
1593  bool isVecListThreeQHWordIndexed() const {
1594  if (!isDoubleSpacedVectorIndexed()) return false;
1595  return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1596  }
1597 
1598  bool isVecListThreeDWordIndexed() const {
1599  if (!isSingleSpacedVectorIndexed()) return false;
1600  return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1601  }
1602 
1603  bool isVecListFourDByteIndexed() const {
1604  if (!isSingleSpacedVectorIndexed()) return false;
1605  return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1606  }
1607 
1608  bool isVecListFourDHWordIndexed() const {
1609  if (!isSingleSpacedVectorIndexed()) return false;
1610  return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1611  }
1612 
1613  bool isVecListFourQWordIndexed() const {
1614  if (!isDoubleSpacedVectorIndexed()) return false;
1615  return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1616  }
1617 
1618  bool isVecListFourQHWordIndexed() const {
1619  if (!isDoubleSpacedVectorIndexed()) return false;
1620  return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1621  }
1622 
1623  bool isVecListFourDWordIndexed() const {
1624  if (!isSingleSpacedVectorIndexed()) return false;
1625  return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1626  }
1627 
1628  bool isVectorIndex8() const {
1629  if (Kind != k_VectorIndex) return false;
1630  return VectorIndex.Val < 8;
1631  }
1632  bool isVectorIndex16() const {
1633  if (Kind != k_VectorIndex) return false;
1634  return VectorIndex.Val < 4;
1635  }
1636  bool isVectorIndex32() const {
1637  if (Kind != k_VectorIndex) return false;
1638  return VectorIndex.Val < 2;
1639  }
1640 
1641  bool isNEONi8splat() const {
1642  if (!isImm()) return false;
1643  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1644  // Must be a constant.
1645  if (!CE) return false;
1646  int64_t Value = CE->getValue();
1647  // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1648  // value.
1649  return Value >= 0 && Value < 256;
1650  }
1651 
1652  bool isNEONi16splat() const {
1653  if (isNEONByteReplicate(2))
1654  return false; // Leave that for bytes replication and forbid by default.
1655  if (!isImm())
1656  return false;
1657  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1658  // Must be a constant.
1659  if (!CE) return false;
1660  unsigned Value = CE->getValue();
1661  return ARM_AM::isNEONi16splat(Value);
1662  }
1663 
1664  bool isNEONi16splatNot() const {
1665  if (!isImm())
1666  return false;
1667  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1668  // Must be a constant.
1669  if (!CE) return false;
1670  unsigned Value = CE->getValue();
1671  return ARM_AM::isNEONi16splat(~Value & 0xffff);
1672  }
1673 
1674  bool isNEONi32splat() const {
1675  if (isNEONByteReplicate(4))
1676  return false; // Leave that for bytes replication and forbid by default.
1677  if (!isImm())
1678  return false;
1679  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1680  // Must be a constant.
1681  if (!CE) return false;
1682  unsigned Value = CE->getValue();
1683  return ARM_AM::isNEONi32splat(Value);
1684  }
1685 
1686  bool isNEONi32splatNot() const {
1687  if (!isImm())
1688  return false;
1689  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1690  // Must be a constant.
1691  if (!CE) return false;
1692  unsigned Value = CE->getValue();
1693  return ARM_AM::isNEONi32splat(~Value);
1694  }
1695 
1696  bool isNEONByteReplicate(unsigned NumBytes) const {
1697  if (!isImm())
1698  return false;
1699  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1700  // Must be a constant.
1701  if (!CE)
1702  return false;
1703  int64_t Value = CE->getValue();
1704  if (!Value)
1705  return false; // Don't bother with zero.
1706 
1707  unsigned char B = Value & 0xff;
1708  for (unsigned i = 1; i < NumBytes; ++i) {
1709  Value >>= 8;
1710  if ((Value & 0xff) != B)
1711  return false;
1712  }
1713  return true;
1714  }
1715  bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1716  bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1717  bool isNEONi32vmov() const {
1718  if (isNEONByteReplicate(4))
1719  return false; // Let it to be classified as byte-replicate case.
1720  if (!isImm())
1721  return false;
1722  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1723  // Must be a constant.
1724  if (!CE)
1725  return false;
1726  int64_t Value = CE->getValue();
1727  // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1728  // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1729  // FIXME: This is probably wrong and a copy and paste from previous example
1730  return (Value >= 0 && Value < 256) ||
1731  (Value >= 0x0100 && Value <= 0xff00) ||
1732  (Value >= 0x010000 && Value <= 0xff0000) ||
1733  (Value >= 0x01000000 && Value <= 0xff000000) ||
1734  (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1735  (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1736  }
1737  bool isNEONi32vmovNeg() const {
1738  if (!isImm()) return false;
1739  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1740  // Must be a constant.
1741  if (!CE) return false;
1742  int64_t Value = ~CE->getValue();
1743  // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1744  // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1745  // FIXME: This is probably wrong and a copy and paste from previous example
1746  return (Value >= 0 && Value < 256) ||
1747  (Value >= 0x0100 && Value <= 0xff00) ||
1748  (Value >= 0x010000 && Value <= 0xff0000) ||
1749  (Value >= 0x01000000 && Value <= 0xff000000) ||
1750  (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1751  (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1752  }
1753 
1754  bool isNEONi64splat() const {
1755  if (!isImm()) return false;
1756  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1757  // Must be a constant.
1758  if (!CE) return false;
1759  uint64_t Value = CE->getValue();
1760  // i64 value with each byte being either 0 or 0xff.
1761  for (unsigned i = 0; i < 8; ++i, Value >>= 8)
1762  if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1763  return true;
1764  }
1765 
1766  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1767  // Add as immediates when possible. Null MCExpr = 0.
1768  if (!Expr)
1770  else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1771  Inst.addOperand(MCOperand::createImm(CE->getValue()));
1772  else
1773  Inst.addOperand(MCOperand::createExpr(Expr));
1774  }
1775 
1776  void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
1777  assert(N == 1 && "Invalid number of operands!");
1778  addExpr(Inst, getImm());
1779  }
1780 
1781  void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
1782  assert(N == 1 && "Invalid number of operands!");
1783  addExpr(Inst, getImm());
1784  }
1785 
1786  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1787  assert(N == 2 && "Invalid number of operands!");
1788  Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1789  unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1790  Inst.addOperand(MCOperand::createReg(RegNum));
1791  }
1792 
1793  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1794  assert(N == 1 && "Invalid number of operands!");
1795  Inst.addOperand(MCOperand::createImm(getCoproc()));
1796  }
1797 
1798  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1799  assert(N == 1 && "Invalid number of operands!");
1800  Inst.addOperand(MCOperand::createImm(getCoproc()));
1801  }
1802 
1803  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1804  assert(N == 1 && "Invalid number of operands!");
1805  Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
1806  }
1807 
1808  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1809  assert(N == 1 && "Invalid number of operands!");
1810  Inst.addOperand(MCOperand::createImm(ITMask.Mask));
1811  }
1812 
1813  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1814  assert(N == 1 && "Invalid number of operands!");
1815  Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1816  }
1817 
1818  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1819  assert(N == 1 && "Invalid number of operands!");
1821  }
1822 
1823  void addRegOperands(MCInst &Inst, unsigned N) const {
1824  assert(N == 1 && "Invalid number of operands!");
1826  }
1827 
1828  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1829  assert(N == 3 && "Invalid number of operands!");
1830  assert(isRegShiftedReg() &&
1831  "addRegShiftedRegOperands() on non-RegShiftedReg!");
1832  Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
1833  Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
1835  ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1836  }
1837 
1838  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1839  assert(N == 2 && "Invalid number of operands!");
1840  assert(isRegShiftedImm() &&
1841  "addRegShiftedImmOperands() on non-RegShiftedImm!");
1842  Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
1843  // Shift of #32 is encoded as 0 where permitted
1844  unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1846  ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1847  }
1848 
1849  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1850  assert(N == 1 && "Invalid number of operands!");
1851  Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
1852  ShifterImm.Imm));
1853  }
1854 
1855  void addRegListOperands(MCInst &Inst, unsigned N) const {
1856  assert(N == 1 && "Invalid number of operands!");
1857  const SmallVectorImpl<unsigned> &RegList = getRegList();
1859  I = RegList.begin(), E = RegList.end(); I != E; ++I)
1861  }
1862 
1863  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1864  addRegListOperands(Inst, N);
1865  }
1866 
1867  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1868  addRegListOperands(Inst, N);
1869  }
1870 
1871  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1872  assert(N == 1 && "Invalid number of operands!");
1873  // Encoded as val>>3. The printer handles display as 8, 16, 24.
1874  Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
1875  }
1876 
1877  void addModImmOperands(MCInst &Inst, unsigned N) const {
1878  assert(N == 1 && "Invalid number of operands!");
1879 
1880  // Support for fixups (MCFixup)
1881  if (isImm())
1882  return addImmOperands(Inst, N);
1883 
1884  Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
1885  }
1886 
1887  void addModImmNotOperands(MCInst &Inst, unsigned N) const {
1888  assert(N == 1 && "Invalid number of operands!");
1889  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1890  uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
1891  Inst.addOperand(MCOperand::createImm(Enc));
1892  }
1893 
1894  void addModImmNegOperands(MCInst &Inst, unsigned N) const {
1895  assert(N == 1 && "Invalid number of operands!");
1896  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1897  uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
1898  Inst.addOperand(MCOperand::createImm(Enc));
1899  }
1900 
1901  void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
1902  assert(N == 1 && "Invalid number of operands!");
1903  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1904  uint32_t Val = -CE->getValue();
1905  Inst.addOperand(MCOperand::createImm(Val));
1906  }
1907 
1908  void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
1909  assert(N == 1 && "Invalid number of operands!");
1910  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1911  uint32_t Val = -CE->getValue();
1912  Inst.addOperand(MCOperand::createImm(Val));
1913  }
1914 
1915  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1916  assert(N == 1 && "Invalid number of operands!");
1917  // Munge the lsb/width into a bitfield mask.
1918  unsigned lsb = Bitfield.LSB;
1919  unsigned width = Bitfield.Width;
1920  // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1921  uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1922  (32 - (lsb + width)));
1923  Inst.addOperand(MCOperand::createImm(Mask));
1924  }
1925 
1926  void addImmOperands(MCInst &Inst, unsigned N) const {
1927  assert(N == 1 && "Invalid number of operands!");
1928  addExpr(Inst, getImm());
1929  }
1930 
1931  void addFBits16Operands(MCInst &Inst, unsigned N) const {
1932  assert(N == 1 && "Invalid number of operands!");
1933  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1934  Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
1935  }
1936 
1937  void addFBits32Operands(MCInst &Inst, unsigned N) const {
1938  assert(N == 1 && "Invalid number of operands!");
1939  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1940  Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
1941  }
1942 
1943  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1944  assert(N == 1 && "Invalid number of operands!");
1945  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1946  int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1947  Inst.addOperand(MCOperand::createImm(Val));
1948  }
1949 
1950  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1951  assert(N == 1 && "Invalid number of operands!");
1952  // FIXME: We really want to scale the value here, but the LDRD/STRD
1953  // instruction don't encode operands that way yet.
1954  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1956  }
1957 
1958  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1959  assert(N == 1 && "Invalid number of operands!");
1960  // The immediate is scaled by four in the encoding and is stored
1961  // in the MCInst as such. Lop off the low two bits here.
1962  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1963  Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
1964  }
1965 
1966  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1967  assert(N == 1 && "Invalid number of operands!");
1968  // The immediate is scaled by four in the encoding and is stored
1969  // in the MCInst as such. Lop off the low two bits here.
1970  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1971  Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
1972  }
1973 
1974  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1975  assert(N == 1 && "Invalid number of operands!");
1976  // The immediate is scaled by four in the encoding and is stored
1977  // in the MCInst as such. Lop off the low two bits here.
1978  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1979  Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
1980  }
1981 
1982  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1983  assert(N == 1 && "Invalid number of operands!");
1984  // The constant encodes as the immediate-1, and we store in the instruction
1985  // the bits as encoded, so subtract off one here.
1986  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1987  Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
1988  }
1989 
1990  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1991  assert(N == 1 && "Invalid number of operands!");
1992  // The constant encodes as the immediate-1, and we store in the instruction
1993  // the bits as encoded, so subtract off one here.
1994  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1995  Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
1996  }
1997 
1998  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1999  assert(N == 1 && "Invalid number of operands!");
2000  // The constant encodes as the immediate, except for 32, which encodes as
2001  // zero.
2002  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2003  unsigned Imm = CE->getValue();
2004  Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2005  }
2006 
2007  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2008  assert(N == 1 && "Invalid number of operands!");
2009  // An ASR value of 32 encodes as 0, so that's how we want to add it to
2010  // the instruction as well.
2011  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2012  int Val = CE->getValue();
2013  Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2014  }
2015 
2016  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2017  assert(N == 1 && "Invalid number of operands!");
2018  // The operand is actually a t2_so_imm, but we have its bitwise
2019  // negation in the assembly source, so twiddle it here.
2020  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2022  }
2023 
2024  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2025  assert(N == 1 && "Invalid number of operands!");
2026  // The operand is actually a t2_so_imm, but we have its
2027  // negation in the assembly source, so twiddle it here.
2028  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2030  }
2031 
2032  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2033  assert(N == 1 && "Invalid number of operands!");
2034  // The operand is actually an imm0_4095, but we have its
2035  // negation in the assembly source, so twiddle it here.
2036  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2038  }
2039 
2040  void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2041  if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2042  Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2043  return;
2044  }
2045 
2046  const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2047  assert(SR && "Unknown value type!");
2049  }
2050 
2051  void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2052  assert(N == 1 && "Invalid number of operands!");
2053  if (isImm()) {
2054  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2055  if (CE) {
2057  return;
2058  }
2059 
2060  const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2061 
2062  assert(SR && "Unknown value type!");
2064  return;
2065  }
2066 
2067  assert(isMem() && "Unknown value type!");
2068  assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2069  Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
2070  }
2071 
2072  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2073  assert(N == 1 && "Invalid number of operands!");
2074  Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2075  }
2076 
2077  void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2078  assert(N == 1 && "Invalid number of operands!");
2079  Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2080  }
2081 
2082  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2083  assert(N == 1 && "Invalid number of operands!");
2084  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2085  }
2086 
2087  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2088  assert(N == 1 && "Invalid number of operands!");
2089  int32_t Imm = Memory.OffsetImm->getValue();
2090  Inst.addOperand(MCOperand::createImm(Imm));
2091  }
2092 
2093  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2094  assert(N == 1 && "Invalid number of operands!");
2095  assert(isImm() && "Not an immediate!");
2096 
2097  // If we have an immediate that's not a constant, treat it as a label
2098  // reference needing a fixup.
2099  if (!isa<MCConstantExpr>(getImm())) {
2100  Inst.addOperand(MCOperand::createExpr(getImm()));
2101  return;
2102  }
2103 
2104  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2105  int Val = CE->getValue();
2106  Inst.addOperand(MCOperand::createImm(Val));
2107  }
2108 
2109  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2110  assert(N == 2 && "Invalid number of operands!");
2111  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2112  Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2113  }
2114 
2115  void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2116  addAlignedMemoryOperands(Inst, N);
2117  }
2118 
2119  void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2120  addAlignedMemoryOperands(Inst, N);
2121  }
2122 
2123  void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2124  addAlignedMemoryOperands(Inst, N);
2125  }
2126 
2127  void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2128  addAlignedMemoryOperands(Inst, N);
2129  }
2130 
2131  void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2132  addAlignedMemoryOperands(Inst, N);
2133  }
2134 
2135  void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2136  addAlignedMemoryOperands(Inst, N);
2137  }
2138 
2139  void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2140  addAlignedMemoryOperands(Inst, N);
2141  }
2142 
2143  void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2144  addAlignedMemoryOperands(Inst, N);
2145  }
2146 
2147  void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2148  addAlignedMemoryOperands(Inst, N);
2149  }
2150 
2151  void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2152  addAlignedMemoryOperands(Inst, N);
2153  }
2154 
2155  void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2156  addAlignedMemoryOperands(Inst, N);
2157  }
2158 
2159  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2160  assert(N == 3 && "Invalid number of operands!");
2161  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2162  if (!Memory.OffsetRegNum) {
2163  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2164  // Special case for #-0
2165  if (Val == INT32_MIN) Val = 0;
2166  if (Val < 0) Val = -Val;
2167  Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2168  } else {
2169  // For register offset, we encode the shift type and negation flag
2170  // here.
2171  Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2172  Memory.ShiftImm, Memory.ShiftType);
2173  }
2174  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2175  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2176  Inst.addOperand(MCOperand::createImm(Val));
2177  }
2178 
2179  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2180  assert(N == 2 && "Invalid number of operands!");
2181  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2182  assert(CE && "non-constant AM2OffsetImm operand!");
2183  int32_t Val = CE->getValue();
2184  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2185  // Special case for #-0
2186  if (Val == INT32_MIN) Val = 0;
2187  if (Val < 0) Val = -Val;
2188  Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2190  Inst.addOperand(MCOperand::createImm(Val));
2191  }
2192 
2193  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2194  assert(N == 3 && "Invalid number of operands!");
2195  // If we have an immediate that's not a constant, treat it as a label
2196  // reference needing a fixup. If it is a constant, it's something else
2197  // and we reject it.
2198  if (isImm()) {
2199  Inst.addOperand(MCOperand::createExpr(getImm()));
2202  return;
2203  }
2204 
2205  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2206  if (!Memory.OffsetRegNum) {
2207  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2208  // Special case for #-0
2209  if (Val == INT32_MIN) Val = 0;
2210  if (Val < 0) Val = -Val;
2211  Val = ARM_AM::getAM3Opc(AddSub, Val);
2212  } else {
2213  // For register offset, we encode the shift type and negation flag
2214  // here.
2215  Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2216  }
2217  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2218  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2219  Inst.addOperand(MCOperand::createImm(Val));
2220  }
2221 
2222  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2223  assert(N == 2 && "Invalid number of operands!");
2224  if (Kind == k_PostIndexRegister) {
2225  int32_t Val =
2226  ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2227  Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2228  Inst.addOperand(MCOperand::createImm(Val));
2229  return;
2230  }
2231 
2232  // Constant offset.
2233  const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2234  int32_t Val = CE->getValue();
2235  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2236  // Special case for #-0
2237  if (Val == INT32_MIN) Val = 0;
2238  if (Val < 0) Val = -Val;
2239  Val = ARM_AM::getAM3Opc(AddSub, Val);
2241  Inst.addOperand(MCOperand::createImm(Val));
2242  }
2243 
2244  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2245  assert(N == 2 && "Invalid number of operands!");
2246  // If we have an immediate that's not a constant, treat it as a label
2247  // reference needing a fixup. If it is a constant, it's something else
2248  // and we reject it.
2249  if (isImm()) {
2250  Inst.addOperand(MCOperand::createExpr(getImm()));
2252  return;
2253  }
2254 
2255  // The lower two bits are always zero and as such are not encoded.
2256  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2257  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2258  // Special case for #-0
2259  if (Val == INT32_MIN) Val = 0;
2260  if (Val < 0) Val = -Val;
2261  Val = ARM_AM::getAM5Opc(AddSub, Val);
2262  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2263  Inst.addOperand(MCOperand::createImm(Val));
2264  }
2265 
2266  void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2267  assert(N == 2 && "Invalid number of operands!");
2268  // If we have an immediate that's not a constant, treat it as a label
2269  // reference needing a fixup. If it is a constant, it's something else
2270  // and we reject it.
2271  if (isImm()) {
2272  Inst.addOperand(MCOperand::createExpr(getImm()));
2274  return;
2275  }
2276 
2277  // The lower bit is always zero and as such is not encoded.
2278  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
2279  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2280  // Special case for #-0
2281  if (Val == INT32_MIN) Val = 0;
2282  if (Val < 0) Val = -Val;
2283  Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
2284  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2285  Inst.addOperand(MCOperand::createImm(Val));
2286  }
2287 
2288  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2289  assert(N == 2 && "Invalid number of operands!");
2290  // If we have an immediate that's not a constant, treat it as a label
2291  // reference needing a fixup. If it is a constant, it's something else
2292  // and we reject it.
2293  if (isImm()) {
2294  Inst.addOperand(MCOperand::createExpr(getImm()));
2296  return;
2297  }
2298 
2299  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2300  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2301  Inst.addOperand(MCOperand::createImm(Val));
2302  }
2303 
2304  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2305  assert(N == 2 && "Invalid number of operands!");
2306  // The lower two bits are always zero and as such are not encoded.
2307  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2308  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2309  Inst.addOperand(MCOperand::createImm(Val));
2310  }
2311 
2312  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2313  assert(N == 2 && "Invalid number of operands!");
2314  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2315  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2316  Inst.addOperand(MCOperand::createImm(Val));
2317  }
2318 
2319  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2320  addMemImm8OffsetOperands(Inst, N);
2321  }
2322 
2323  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2324  addMemImm8OffsetOperands(Inst, N);
2325  }
2326 
2327  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2328  assert(N == 2 && "Invalid number of operands!");
2329  // If this is an immediate, it's a label reference.
2330  if (isImm()) {
2331  addExpr(Inst, getImm());
2333  return;
2334  }
2335 
2336  // Otherwise, it's a normal memory reg+offset.
2337  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2338  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2339  Inst.addOperand(MCOperand::createImm(Val));
2340  }
2341 
2342  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2343  assert(N == 2 && "Invalid number of operands!");
2344  // If this is an immediate, it's a label reference.
2345  if (isImm()) {
2346  addExpr(Inst, getImm());
2348  return;
2349  }
2350 
2351  // Otherwise, it's a normal memory reg+offset.
2352  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2353  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2354  Inst.addOperand(MCOperand::createImm(Val));
2355  }
2356 
2357  void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
2358  assert(N == 1 && "Invalid number of operands!");
2359  // This is container for the immediate that we will create the constant
2360  // pool from
2361  addExpr(Inst, getConstantPoolImm());
2362  return;
2363  }
2364 
2365  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2366  assert(N == 2 && "Invalid number of operands!");
2367  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2368  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2369  }
2370 
2371  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2372  assert(N == 2 && "Invalid number of operands!");
2373  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2374  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2375  }
2376 
2377  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2378  assert(N == 3 && "Invalid number of operands!");
2379  unsigned Val =
2381  Memory.ShiftImm, Memory.ShiftType);
2382  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2383  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2384  Inst.addOperand(MCOperand::createImm(Val));
2385  }
2386 
2387  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2388  assert(N == 3 && "Invalid number of operands!");
2389  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2390  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2391  Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
2392  }
2393 
2394  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2395  assert(N == 2 && "Invalid number of operands!");
2396  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2397  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2398  }
2399 
2400  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2401  assert(N == 2 && "Invalid number of operands!");
2402  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2403  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2404  Inst.addOperand(MCOperand::createImm(Val));
2405  }
2406 
2407  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2408  assert(N == 2 && "Invalid number of operands!");
2409  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2410  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2411  Inst.addOperand(MCOperand::createImm(Val));
2412  }
2413 
2414  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2415  assert(N == 2 && "Invalid number of operands!");
2416  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2417  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2418  Inst.addOperand(MCOperand::createImm(Val));
2419  }
2420 
2421  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2422  assert(N == 2 && "Invalid number of operands!");
2423  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2424  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2425  Inst.addOperand(MCOperand::createImm(Val));
2426  }
2427 
2428  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2429  assert(N == 1 && "Invalid number of operands!");
2430  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2431  assert(CE && "non-constant post-idx-imm8 operand!");
2432  int Imm = CE->getValue();
2433  bool isAdd = Imm >= 0;
2434  if (Imm == INT32_MIN) Imm = 0;
2435  Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2436  Inst.addOperand(MCOperand::createImm(Imm));
2437  }
2438 
2439  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2440  assert(N == 1 && "Invalid number of operands!");
2441  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2442  assert(CE && "non-constant post-idx-imm8s4 operand!");
2443  int Imm = CE->getValue();
2444  bool isAdd = Imm >= 0;
2445  if (Imm == INT32_MIN) Imm = 0;
2446  // Immediate is scaled by 4.
2447  Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2448  Inst.addOperand(MCOperand::createImm(Imm));
2449  }
2450 
2451  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2452  assert(N == 2 && "Invalid number of operands!");
2453  Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2454  Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
2455  }
2456 
2457  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2458  assert(N == 2 && "Invalid number of operands!");
2459  Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2460  // The sign, shift type, and shift amount are encoded in a single operand
2461  // using the AM2 encoding helpers.
2462  ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2463  unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2464  PostIdxReg.ShiftTy);
2465  Inst.addOperand(MCOperand::createImm(Imm));
2466  }
2467 
2468  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2469  assert(N == 1 && "Invalid number of operands!");
2470  Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
2471  }
2472 
2473  void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2474  assert(N == 1 && "Invalid number of operands!");
2475  Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
2476  }
2477 
2478  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2479  assert(N == 1 && "Invalid number of operands!");
2480  Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
2481  }
2482 
2483  void addVecListOperands(MCInst &Inst, unsigned N) const {
2484  assert(N == 1 && "Invalid number of operands!");
2485  Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2486  }
2487 
2488  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2489  assert(N == 2 && "Invalid number of operands!");
2490  Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2491  Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
2492  }
2493 
2494  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2495  assert(N == 1 && "Invalid number of operands!");
2496  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2497  }
2498 
2499  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2500  assert(N == 1 && "Invalid number of operands!");
2501  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2502  }
2503 
2504  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2505  assert(N == 1 && "Invalid number of operands!");
2506  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2507  }
2508 
2509  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2510  assert(N == 1 && "Invalid number of operands!");
2511  // The immediate encodes the type of constant as well as the value.
2512  // Mask in that this is an i8 splat.
2513  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2514  Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
2515  }
2516 
2517  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2518  assert(N == 1 && "Invalid number of operands!");
2519  // The immediate encodes the type of constant as well as the value.
2520  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2521  unsigned Value = CE->getValue();
2522  Value = ARM_AM::encodeNEONi16splat(Value);
2523  Inst.addOperand(MCOperand::createImm(Value));
2524  }
2525 
2526  void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2527  assert(N == 1 && "Invalid number of operands!");
2528  // The immediate encodes the type of constant as well as the value.
2529  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2530  unsigned Value = CE->getValue();
2531  Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2532  Inst.addOperand(MCOperand::createImm(Value));
2533  }
2534 
2535  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2536  assert(N == 1 && "Invalid number of operands!");
2537  // The immediate encodes the type of constant as well as the value.
2538  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2539  unsigned Value = CE->getValue();
2540  Value = ARM_AM::encodeNEONi32splat(Value);
2541  Inst.addOperand(MCOperand::createImm(Value));
2542  }
2543 
2544  void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2545  assert(N == 1 && "Invalid number of operands!");
2546  // The immediate encodes the type of constant as well as the value.
2547  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2548  unsigned Value = CE->getValue();
2549  Value = ARM_AM::encodeNEONi32splat(~Value);
2550  Inst.addOperand(MCOperand::createImm(Value));
2551  }
2552 
2553  void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2554  assert(N == 1 && "Invalid number of operands!");
2555  // The immediate encodes the type of constant as well as the value.
2556  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2557  unsigned Value = CE->getValue();
2558  assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2559  Inst.getOpcode() == ARM::VMOVv16i8) &&
2560  "All vmvn instructions that wants to replicate non-zero byte "
2561  "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2562  unsigned B = ((~Value) & 0xff);
2563  B |= 0xe00; // cmode = 0b1110
2565  }
2566  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2567  assert(N == 1 && "Invalid number of operands!");
2568  // The immediate encodes the type of constant as well as the value.
2569  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2570  unsigned Value = CE->getValue();
2571  if (Value >= 256 && Value <= 0xffff)
2572  Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2573  else if (Value > 0xffff && Value <= 0xffffff)
2574  Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2575  else if (Value > 0xffffff)
2576  Value = (Value >> 24) | 0x600;
2577  Inst.addOperand(MCOperand::createImm(Value));
2578  }
2579 
2580  void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2581  assert(N == 1 && "Invalid number of operands!");
2582  // The immediate encodes the type of constant as well as the value.
2583  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2584  unsigned Value = CE->getValue();
2585  assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2586  Inst.getOpcode() == ARM::VMOVv16i8) &&
2587  "All instructions that wants to replicate non-zero byte "
2588  "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2589  unsigned B = Value & 0xff;
2590  B |= 0xe00; // cmode = 0b1110
2592  }
2593  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2594  assert(N == 1 && "Invalid number of operands!");
2595  // The immediate encodes the type of constant as well as the value.
2596  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2597  unsigned Value = ~CE->getValue();
2598  if (Value >= 256 && Value <= 0xffff)
2599  Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2600  else if (Value > 0xffff && Value <= 0xffffff)
2601  Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2602  else if (Value > 0xffffff)
2603  Value = (Value >> 24) | 0x600;
2604  Inst.addOperand(MCOperand::createImm(Value));
2605  }
2606 
2607  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2608  assert(N == 1 && "Invalid number of operands!");
2609  // The immediate encodes the type of constant as well as the value.
2610  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2611  uint64_t Value = CE->getValue();
2612  unsigned Imm = 0;
2613  for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2614  Imm |= (Value & 1) << i;
2615  }
2616  Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
2617  }
2618 
2619  void print(raw_ostream &OS) const override;
2620 
2621  static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2622  auto Op = make_unique<ARMOperand>(k_ITCondMask);
2623  Op->ITMask.Mask = Mask;
2624  Op->StartLoc = S;
2625  Op->EndLoc = S;
2626  return Op;
2627  }
2628 
2629  static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2630  SMLoc S) {
2631  auto Op = make_unique<ARMOperand>(k_CondCode);
2632  Op->CC.Val = CC;
2633  Op->StartLoc = S;
2634  Op->EndLoc = S;
2635  return Op;
2636  }
2637 
2638  static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2639  auto Op = make_unique<ARMOperand>(k_CoprocNum);
2640  Op->Cop.Val = CopVal;
2641  Op->StartLoc = S;
2642  Op->EndLoc = S;
2643  return Op;
2644  }
2645 
2646  static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2647  auto Op = make_unique<ARMOperand>(k_CoprocReg);
2648  Op->Cop.Val = CopVal;
2649  Op->StartLoc = S;
2650  Op->EndLoc = S;
2651  return Op;
2652  }
2653 
2654  static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2655  SMLoc E) {
2656  auto Op = make_unique<ARMOperand>(k_CoprocOption);
2657  Op->Cop.Val = Val;
2658  Op->StartLoc = S;
2659  Op->EndLoc = E;
2660  return Op;
2661  }
2662 
2663  static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2664  auto Op = make_unique<ARMOperand>(k_CCOut);
2665  Op->Reg.RegNum = RegNum;
2666  Op->StartLoc = S;
2667  Op->EndLoc = S;
2668  return Op;
2669  }
2670 
2671  static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2672  auto Op = make_unique<ARMOperand>(k_Token);
2673  Op->Tok.Data = Str.data();
2674  Op->Tok.Length = Str.size();
2675  Op->StartLoc = S;
2676  Op->EndLoc = S;
2677  return Op;
2678  }
2679 
2680  static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2681  SMLoc E) {
2682  auto Op = make_unique<ARMOperand>(k_Register);
2683  Op->Reg.RegNum = RegNum;
2684  Op->StartLoc = S;
2685  Op->EndLoc = E;
2686  return Op;
2687  }
2688 
2689  static std::unique_ptr<ARMOperand>
2690  CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2691  unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2692  SMLoc E) {
2693  auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2694  Op->RegShiftedReg.ShiftTy = ShTy;
2695  Op->RegShiftedReg.SrcReg = SrcReg;
2696  Op->RegShiftedReg.ShiftReg = ShiftReg;
2697  Op->RegShiftedReg.ShiftImm = ShiftImm;
2698  Op->StartLoc = S;
2699  Op->EndLoc = E;
2700  return Op;
2701  }
2702 
2703  static std::unique_ptr<ARMOperand>
2704  CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2705  unsigned ShiftImm, SMLoc S, SMLoc E) {
2706  auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2707  Op->RegShiftedImm.ShiftTy = ShTy;
2708  Op->RegShiftedImm.SrcReg = SrcReg;
2709  Op->RegShiftedImm.ShiftImm = ShiftImm;
2710  Op->StartLoc = S;
2711  Op->EndLoc = E;
2712  return Op;
2713  }
2714 
2715  static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2716  SMLoc S, SMLoc E) {
2717  auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2718  Op->ShifterImm.isASR = isASR;
2719  Op->ShifterImm.Imm = Imm;
2720  Op->StartLoc = S;
2721  Op->EndLoc = E;
2722  return Op;
2723  }
2724 
2725  static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2726  SMLoc E) {
2727  auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2728  Op->RotImm.Imm = Imm;
2729  Op->StartLoc = S;
2730  Op->EndLoc = E;
2731  return Op;
2732  }
2733 
2734  static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
2735  SMLoc S, SMLoc E) {
2736  auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
2737  Op->ModImm.Bits = Bits;
2738  Op->ModImm.Rot = Rot;
2739  Op->StartLoc = S;
2740  Op->EndLoc = E;
2741  return Op;
2742  }
2743 
2744  static std::unique_ptr<ARMOperand>
2745  CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2746  auto Op = make_unique<ARMOperand>(k_ConstantPoolImmediate);
2747  Op->Imm.Val = Val;
2748  Op->StartLoc = S;
2749  Op->EndLoc = E;
2750  return Op;
2751  }
2752 
2753  static std::unique_ptr<ARMOperand>
2754  CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2755  auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2756  Op->Bitfield.LSB = LSB;
2757  Op->Bitfield.Width = Width;
2758  Op->StartLoc = S;
2759  Op->EndLoc = E;
2760  return Op;
2761  }
2762 
2763  static std::unique_ptr<ARMOperand>
2764  CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2765  SMLoc StartLoc, SMLoc EndLoc) {
2766  assert (Regs.size() > 0 && "RegList contains no registers?");
2767  KindTy Kind = k_RegisterList;
2768 
2769  if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2770  Kind = k_DPRRegisterList;
2771  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2772  contains(Regs.front().second))
2773  Kind = k_SPRRegisterList;
2774 
2775  // Sort based on the register encoding values.
2776  array_pod_sort(Regs.begin(), Regs.end());
2777 
2778  auto Op = make_unique<ARMOperand>(Kind);
2779  for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2780  I = Regs.begin(), E = Regs.end(); I != E; ++I)
2781  Op->Registers.push_back(I->second);
2782  Op->StartLoc = StartLoc;
2783  Op->EndLoc = EndLoc;
2784  return Op;
2785  }
2786 
2787  static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2788  unsigned Count,
2789  bool isDoubleSpaced,
2790  SMLoc S, SMLoc E) {
2791  auto Op = make_unique<ARMOperand>(k_VectorList);
2792  Op->VectorList.RegNum = RegNum;
2793  Op->VectorList.Count = Count;
2794  Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2795  Op->StartLoc = S;
2796  Op->EndLoc = E;
2797  return Op;
2798  }
2799 
2800  static std::unique_ptr<ARMOperand>
2801  CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2802  SMLoc S, SMLoc E) {
2803  auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2804  Op->VectorList.RegNum = RegNum;
2805  Op->VectorList.Count = Count;
2806  Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2807  Op->StartLoc = S;
2808  Op->EndLoc = E;
2809  return Op;
2810  }
2811 
2812  static std::unique_ptr<ARMOperand>
2813  CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2814  bool isDoubleSpaced, SMLoc S, SMLoc E) {
2815  auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2816  Op->VectorList.RegNum = RegNum;
2817  Op->VectorList.Count = Count;
2818  Op->VectorList.LaneIndex = Index;
2819  Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2820  Op->StartLoc = S;
2821  Op->EndLoc = E;
2822  return Op;
2823  }
2824 
2825  static std::unique_ptr<ARMOperand>
2826  CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2827  auto Op = make_unique<ARMOperand>(k_VectorIndex);
2828  Op->VectorIndex.Val = Idx;
2829  Op->StartLoc = S;
2830  Op->EndLoc = E;
2831  return Op;
2832  }
2833 
2834  static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2835  SMLoc E) {
2836  auto Op = make_unique<ARMOperand>(k_Immediate);
2837  Op->Imm.Val = Val;
2838  Op->StartLoc = S;
2839  Op->EndLoc = E;
2840  return Op;
2841  }
2842 
2843  static std::unique_ptr<ARMOperand>
2844  CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2845  unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2846  unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2847  SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2848  auto Op = make_unique<ARMOperand>(k_Memory);
2849  Op->Memory.BaseRegNum = BaseRegNum;
2850  Op->Memory.OffsetImm = OffsetImm;
2851  Op->Memory.OffsetRegNum = OffsetRegNum;
2852  Op->Memory.ShiftType = ShiftType;
2853  Op->Memory.ShiftImm = ShiftImm;
2854  Op->Memory.Alignment = Alignment;
2855  Op->Memory.isNegative = isNegative;
2856  Op->StartLoc = S;
2857  Op->EndLoc = E;
2858  Op->AlignmentLoc = AlignmentLoc;
2859  return Op;
2860  }
2861 
2862  static std::unique_ptr<ARMOperand>
2863  CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2864  unsigned ShiftImm, SMLoc S, SMLoc E) {
2865  auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2866  Op->PostIdxReg.RegNum = RegNum;
2867  Op->PostIdxReg.isAdd = isAdd;
2868  Op->PostIdxReg.ShiftTy = ShiftTy;
2869  Op->PostIdxReg.ShiftImm = ShiftImm;
2870  Op->StartLoc = S;
2871  Op->EndLoc = E;
2872  return Op;
2873  }
2874 
2875  static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2876  SMLoc S) {
2877  auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2878  Op->MBOpt.Val = Opt;
2879  Op->StartLoc = S;
2880  Op->EndLoc = S;
2881  return Op;
2882  }
2883 
2884  static std::unique_ptr<ARMOperand>
2885  CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2886  auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2887  Op->ISBOpt.Val = Opt;
2888  Op->StartLoc = S;
2889  Op->EndLoc = S;
2890  return Op;
2891  }
2892 
2893  static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2894  SMLoc S) {
2895  auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2896  Op->IFlags.Val = IFlags;
2897  Op->StartLoc = S;
2898  Op->EndLoc = S;
2899  return Op;
2900  }
2901 
2902  static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2903  auto Op = make_unique<ARMOperand>(k_MSRMask);
2904  Op->MMask.Val = MMask;
2905  Op->StartLoc = S;
2906  Op->EndLoc = S;
2907  return Op;
2908  }
2909 
2910  static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
2911  auto Op = make_unique<ARMOperand>(k_BankedReg);
2912  Op->BankedReg.Val = Reg;
2913  Op->StartLoc = S;
2914  Op->EndLoc = S;
2915  return Op;
2916  }
2917 };
2918 
2919 } // end anonymous namespace.
2920 
2921 void ARMOperand::print(raw_ostream &OS) const {
2922  switch (Kind) {
2923  case k_CondCode:
2924  OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2925  break;
2926  case k_CCOut:
2927  OS << "<ccout " << getReg() << ">";
2928  break;
2929  case k_ITCondMask: {
2930  static const char *const MaskStr[] = {
2931  "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2932  "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2933  };
2934  assert((ITMask.Mask & 0xf) == ITMask.Mask);
2935  OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2936  break;
2937  }
2938  case k_CoprocNum:
2939  OS << "<coprocessor number: " << getCoproc() << ">";
2940  break;
2941  case k_CoprocReg:
2942  OS << "<coprocessor register: " << getCoproc() << ">";
2943  break;
2944  case k_CoprocOption:
2945  OS << "<coprocessor option: " << CoprocOption.Val << ">";
2946  break;
2947  case k_MSRMask:
2948  OS << "<mask: " << getMSRMask() << ">";
2949  break;
2950  case k_BankedReg:
2951  OS << "<banked reg: " << getBankedReg() << ">";
2952  break;
2953  case k_Immediate:
2954  OS << *getImm();
2955  break;
2956  case k_MemBarrierOpt:
2957  OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2958  break;
2959  case k_InstSyncBarrierOpt:
2960  OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2961  break;
2962  case k_Memory:
2963  OS << "<memory "
2964  << " base:" << Memory.BaseRegNum;
2965  OS << ">";
2966  break;
2967  case k_PostIndexRegister:
2968  OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2969  << PostIdxReg.RegNum;
2970  if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2971  OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2972  << PostIdxReg.ShiftImm;
2973  OS << ">";
2974  break;
2975  case k_ProcIFlags: {
2976  OS << "<ARM_PROC::";
2977  unsigned IFlags = getProcIFlags();
2978  for (int i=2; i >= 0; --i)
2979  if (IFlags & (1 << i))
2980  OS << ARM_PROC::IFlagsToString(1 << i);
2981  OS << ">";
2982  break;
2983  }
2984  case k_Register:
2985  OS << "<register " << getReg() << ">";
2986  break;
2987  case k_ShifterImmediate:
2988  OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2989  << " #" << ShifterImm.Imm << ">";
2990  break;
2991  case k_ShiftedRegister:
2992  OS << "<so_reg_reg "
2993  << RegShiftedReg.SrcReg << " "
2994  << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2995  << " " << RegShiftedReg.ShiftReg << ">";
2996  break;
2997  case k_ShiftedImmediate:
2998  OS << "<so_reg_imm "
2999  << RegShiftedImm.SrcReg << " "
3000  << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
3001  << " #" << RegShiftedImm.ShiftImm << ">";
3002  break;
3003  case k_RotateImmediate:
3004  OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
3005  break;
3006  case k_ModifiedImmediate:
3007  OS << "<mod_imm #" << ModImm.Bits << ", #"
3008  << ModImm.Rot << ")>";
3009  break;
3010  case k_ConstantPoolImmediate:
3011  OS << "<constant_pool_imm #" << *getConstantPoolImm();
3012  break;
3013  case k_BitfieldDescriptor:
3014  OS << "<bitfield " << "lsb: " << Bitfield.LSB
3015  << ", width: " << Bitfield.Width << ">";
3016  break;
3017  case k_RegisterList:
3018  case k_DPRRegisterList:
3019  case k_SPRRegisterList: {
3020  OS << "<register_list ";
3021 
3022  const SmallVectorImpl<unsigned> &RegList = getRegList();
3024  I = RegList.begin(), E = RegList.end(); I != E; ) {
3025  OS << *I;
3026  if (++I < E) OS << ", ";
3027  }
3028 
3029  OS << ">";
3030  break;
3031  }
3032  case k_VectorList:
3033  OS << "<vector_list " << VectorList.Count << " * "
3034  << VectorList.RegNum << ">";
3035  break;
3036  case k_VectorListAllLanes:
3037  OS << "<vector_list(all lanes) " << VectorList.Count << " * "
3038  << VectorList.RegNum << ">";
3039  break;
3040  case k_VectorListIndexed:
3041  OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
3042  << VectorList.Count << " * " << VectorList.RegNum << ">";
3043  break;
3044  case k_Token:
3045  OS << "'" << getToken() << "'";
3046  break;
3047  case k_VectorIndex:
3048  OS << "<vectorindex " << getVectorIndex() << ">";
3049  break;
3050  }
3051 }
3052 
3053 /// @name Auto-generated Match Functions
3054 /// {
3055 
3056 static unsigned MatchRegisterName(StringRef Name);
3057 
3058 /// }
3059 
3060 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
3061  SMLoc &StartLoc, SMLoc &EndLoc) {
3062  const AsmToken &Tok = getParser().getTok();
3063  StartLoc = Tok.getLoc();
3064  EndLoc = Tok.getEndLoc();
3065  RegNo = tryParseRegister();
3066 
3067  return (RegNo == (unsigned)-1);
3068 }
3069 
3070 /// Try to parse a register name. The token must be an Identifier when called,
3071 /// and if it is a register name the token is eaten and the register number is
3072 /// returned. Otherwise return -1.
3073 ///
3074 int ARMAsmParser::tryParseRegister() {
3075  MCAsmParser &Parser = getParser();
3076  const AsmToken &Tok = Parser.getTok();
3077  if (Tok.isNot(AsmToken::Identifier)) return -1;
3078 
3079  std::string lowerCase = Tok.getString().lower();
3080  unsigned RegNum = MatchRegisterName(lowerCase);
3081  if (!RegNum) {
3082  RegNum = StringSwitch<unsigned>(lowerCase)
3083  .Case("r13", ARM::SP)
3084  .Case("r14", ARM::LR)
3085  .Case("r15", ARM::PC)
3086  .Case("ip", ARM::R12)
3087  // Additional register name aliases for 'gas' compatibility.
3088  .Case("a1", ARM::R0)
3089  .Case("a2", ARM::R1)
3090  .Case("a3", ARM::R2)
3091  .Case("a4", ARM::R3)
3092  .Case("v1", ARM::R4)
3093  .Case("v2", ARM::R5)
3094  .Case("v3", ARM::R6)
3095  .Case("v4", ARM::R7)
3096  .Case("v5", ARM::R8)
3097  .Case("v6", ARM::R9)
3098  .Case("v7", ARM::R10)
3099  .Case("v8", ARM::R11)
3100  .Case("sb", ARM::R9)
3101  .Case("sl", ARM::R10)
3102  .Case("fp", ARM::R11)
3103  .Default(0);
3104  }
3105  if (!RegNum) {
3106  // Check for aliases registered via .req. Canonicalize to lower case.
3107  // That's more consistent since register names are case insensitive, and
3108  // it's how the original entry was passed in from MC/MCParser/AsmParser.
3109  StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3110  // If no match, return failure.
3111  if (Entry == RegisterReqs.end())
3112  return -1;
3113  Parser.Lex(); // Eat identifier token.
3114  return Entry->getValue();
3115  }
3116 
3117  // Some FPUs only have 16 D registers, so D16-D31 are invalid
3118  if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3119  return -1;
3120 
3121  Parser.Lex(); // Eat identifier token.
3122 
3123  return RegNum;
3124 }
3125 
3126 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
3127 // If a recoverable error occurs, return 1. If an irrecoverable error
3128 // occurs, return -1. An irrecoverable error is one where tokens have been
3129 // consumed in the process of trying to parse the shifter (i.e., when it is
3130 // indeed a shifter operand, but malformed).
3131 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3132  MCAsmParser &Parser = getParser();
3133  SMLoc S = Parser.getTok().getLoc();
3134  const AsmToken &Tok = Parser.getTok();
3135  if (Tok.isNot(AsmToken::Identifier))
3136  return -1;
3137 
3138  std::string lowerCase = Tok.getString().lower();
3140  .Case("asl", ARM_AM::lsl)
3141  .Case("lsl", ARM_AM::lsl)
3142  .Case("lsr", ARM_AM::lsr)
3143  .Case("asr", ARM_AM::asr)
3144  .Case("ror", ARM_AM::ror)
3145  .Case("rrx", ARM_AM::rrx)
3147 
3148  if (ShiftTy == ARM_AM::no_shift)
3149  return 1;
3150 
3151  Parser.Lex(); // Eat the operator.
3152 
3153  // The source register for the shift has already been added to the
3154  // operand list, so we need to pop it off and combine it into the shifted
3155  // register operand instead.
3156  std::unique_ptr<ARMOperand> PrevOp(
3157  (ARMOperand *)Operands.pop_back_val().release());
3158  if (!PrevOp->isReg())
3159  return Error(PrevOp->getStartLoc(), "shift must be of a register");
3160  int SrcReg = PrevOp->getReg();
3161 
3162  SMLoc EndLoc;
3163  int64_t Imm = 0;
3164  int ShiftReg = 0;
3165  if (ShiftTy == ARM_AM::rrx) {
3166  // RRX Doesn't have an explicit shift amount. The encoder expects
3167  // the shift register to be the same as the source register. Seems odd,
3168  // but OK.
3169  ShiftReg = SrcReg;
3170  } else {
3171  // Figure out if this is shifted by a constant or a register (for non-RRX).
3172  if (Parser.getTok().is(AsmToken::Hash) ||
3173  Parser.getTok().is(AsmToken::Dollar)) {
3174  Parser.Lex(); // Eat hash.
3175  SMLoc ImmLoc = Parser.getTok().getLoc();
3176  const MCExpr *ShiftExpr = nullptr;
3177  if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3178  Error(ImmLoc, "invalid immediate shift value");
3179  return -1;
3180  }
3181  // The expression must be evaluatable as an immediate.
3182  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3183  if (!CE) {
3184  Error(ImmLoc, "invalid immediate shift value");
3185  return -1;
3186  }
3187  // Range check the immediate.
3188  // lsl, ror: 0 <= imm <= 31
3189  // lsr, asr: 0 <= imm <= 32
3190  Imm = CE->getValue();
3191  if (Imm < 0 ||
3192  ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3193  ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3194  Error(ImmLoc, "immediate shift value out of range");
3195  return -1;
3196  }
3197  // shift by zero is a nop. Always send it through as lsl.
3198  // ('as' compatibility)
3199  if (Imm == 0)
3200  ShiftTy = ARM_AM::lsl;
3201  } else if (Parser.getTok().is(AsmToken::Identifier)) {
3202  SMLoc L = Parser.getTok().getLoc();
3203  EndLoc = Parser.getTok().getEndLoc();
3204  ShiftReg = tryParseRegister();
3205  if (ShiftReg == -1) {
3206  Error(L, "expected immediate or register in shift operand");
3207  return -1;
3208  }
3209  } else {
3210  Error(Parser.getTok().getLoc(),
3211  "expected immediate or register in shift operand");
3212  return -1;
3213  }
3214  }
3215 
3216  if (ShiftReg && ShiftTy != ARM_AM::rrx)
3217  Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3218  ShiftReg, Imm,
3219  S, EndLoc));
3220  else
3221  Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3222  S, EndLoc));
3223 
3224  return 0;
3225 }
3226 
3227 
3228 /// Try to parse a register name. The token must be an Identifier when called.
3229 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3230 /// if there is a "writeback". 'true' if it's not a register.
3231 ///
3232 /// TODO this is likely to change to allow different register types and or to
3233 /// parse for a specific register type.
3234 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3235  MCAsmParser &Parser = getParser();
3236  const AsmToken &RegTok = Parser.getTok();
3237  int RegNo = tryParseRegister();
3238  if (RegNo == -1)
3239  return true;
3240 
3241  Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3242  RegTok.getEndLoc()));
3243 
3244  const AsmToken &ExclaimTok = Parser.getTok();
3245  if (ExclaimTok.is(AsmToken::Exclaim)) {
3246  Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3247  ExclaimTok.getLoc()));
3248  Parser.Lex(); // Eat exclaim token
3249  return false;
3250  }
3251 
3252  // Also check for an index operand. This is only legal for vector registers,
3253  // but that'll get caught OK in operand matching, so we don't need to
3254  // explicitly filter everything else out here.
3255  if (Parser.getTok().is(AsmToken::LBrac)) {
3256  SMLoc SIdx = Parser.getTok().getLoc();
3257  Parser.Lex(); // Eat left bracket token.
3258 
3259  const MCExpr *ImmVal;
3260  if (getParser().parseExpression(ImmVal))
3261  return true;
3262  const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3263  if (!MCE)
3264  return TokError("immediate value expected for vector index");
3265 
3266  if (Parser.getTok().isNot(AsmToken::RBrac))
3267  return Error(Parser.getTok().getLoc(), "']' expected");
3268 
3269  SMLoc E = Parser.getTok().getEndLoc();
3270  Parser.Lex(); // Eat right bracket token.
3271 
3272  Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3273  SIdx, E,
3274  getContext()));
3275  }
3276 
3277  return false;
3278 }
3279 
3280 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3281 /// instruction with a symbolic operand name.
3282 /// We accept "crN" syntax for GAS compatibility.
3283 /// <operand-name> ::= <prefix><number>
3284 /// If CoprocOp is 'c', then:
3285 /// <prefix> ::= c | cr
3286 /// If CoprocOp is 'p', then :
3287 /// <prefix> ::= p
3288 /// <number> ::= integer in range [0, 15]
3289 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3290  // Use the same layout as the tablegen'erated register name matcher. Ugly,
3291  // but efficient.
3292  if (Name.size() < 2 || Name[0] != CoprocOp)
3293  return -1;
3294  Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3295 
3296  switch (Name.size()) {
3297  default: return -1;
3298  case 1:
3299  switch (Name[0]) {
3300  default: return -1;
3301  case '0': return 0;
3302  case '1': return 1;
3303  case '2': return 2;
3304  case '3': return 3;
3305  case '4': return 4;
3306  case '5': return 5;
3307  case '6': return 6;
3308  case '7': return 7;
3309  case '8': return 8;
3310  case '9': return 9;
3311  }
3312  case 2:
3313  if (Name[0] != '1')
3314  return -1;
3315  switch (Name[1]) {
3316  default: return -1;
3317  // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3318  // However, old cores (v5/v6) did use them in that way.
3319  case '0': return 10;
3320  case '1': return 11;
3321  case '2': return 12;
3322  case '3': return 13;
3323  case '4': return 14;
3324  case '5': return 15;
3325  }
3326  }
3327 }
3328 
3329 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3331 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3332  MCAsmParser &Parser = getParser();
3333  SMLoc S = Parser.getTok().getLoc();
3334  const AsmToken &Tok = Parser.getTok();
3335  if (!Tok.is(AsmToken::Identifier))
3336  return MatchOperand_NoMatch;
3337  unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3338  .Case("eq", ARMCC::EQ)
3339  .Case("ne", ARMCC::NE)
3340  .Case("hs", ARMCC::HS)
3341  .Case("cs", ARMCC::HS)
3342  .Case("lo", ARMCC::LO)
3343  .Case("cc", ARMCC::LO)
3344  .Case("mi", ARMCC::MI)
3345  .Case("pl", ARMCC::PL)
3346  .Case("vs", ARMCC::VS)
3347  .Case("vc", ARMCC::VC)
3348  .Case("hi", ARMCC::HI)
3349  .Case("ls", ARMCC::LS)
3350  .Case("ge", ARMCC::GE)
3351  .Case("lt", ARMCC::LT)
3352  .Case("gt", ARMCC::GT)
3353  .Case("le", ARMCC::LE)
3354  .Case("al", ARMCC::AL)
3355  .Default(~0U);
3356  if (CC == ~0U)
3357  return MatchOperand_NoMatch;
3358  Parser.Lex(); // Eat the token.
3359 
3360  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3361 
3362  return MatchOperand_Success;
3363 }
3364 
3365 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3366 /// token must be an Identifier when called, and if it is a coprocessor
3367 /// number, the token is eaten and the operand is added to the operand list.
3369 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3370  MCAsmParser &Parser = getParser();
3371  SMLoc S = Parser.getTok().getLoc();
3372  const AsmToken &Tok = Parser.getTok();
3373  if (Tok.isNot(AsmToken::Identifier))
3374  return MatchOperand_NoMatch;
3375 
3376  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3377  if (Num == -1)
3378  return MatchOperand_NoMatch;
3379  // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3380  if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3381  return MatchOperand_NoMatch;
3382 
3383  Parser.Lex(); // Eat identifier token.
3384  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3385  return MatchOperand_Success;
3386 }
3387 
3388 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3389 /// token must be an Identifier when called, and if it is a coprocessor
3390 /// number, the token is eaten and the operand is added to the operand list.
3392 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3393  MCAsmParser &Parser = getParser();
3394  SMLoc S = Parser.getTok().getLoc();
3395  const AsmToken &Tok = Parser.getTok();
3396  if (Tok.isNot(AsmToken::Identifier))
3397  return MatchOperand_NoMatch;
3398 
3399  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3400  if (Reg == -1)
3401  return MatchOperand_NoMatch;
3402 
3403  Parser.Lex(); // Eat identifier token.
3404  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3405  return MatchOperand_Success;
3406 }
3407 
3408 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3409 /// coproc_option : '{' imm0_255 '}'
3411 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3412  MCAsmParser &Parser = getParser();
3413  SMLoc S = Parser.getTok().getLoc();
3414 
3415  // If this isn't a '{', this isn't a coprocessor immediate operand.
3416  if (Parser.getTok().isNot(AsmToken::LCurly))
3417  return MatchOperand_NoMatch;
3418  Parser.Lex(); // Eat the '{'
3419 
3420  const MCExpr *Expr;
3421  SMLoc Loc = Parser.getTok().getLoc();
3422  if (getParser().parseExpression(Expr)) {
3423  Error(Loc, "illegal expression");
3424  return MatchOperand_ParseFail;
3425  }
3426  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3427  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3428  Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3429  return MatchOperand_ParseFail;
3430  }
3431  int Val = CE->getValue();
3432 
3433  // Check for and consume the closing '}'
3434  if (Parser.getTok().isNot(AsmToken::RCurly))
3435  return MatchOperand_ParseFail;
3436  SMLoc E = Parser.getTok().getEndLoc();
3437  Parser.Lex(); // Eat the '}'
3438 
3439  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3440  return MatchOperand_Success;
3441 }
3442 
3443 // For register list parsing, we need to map from raw GPR register numbering
3444 // to the enumeration values. The enumeration values aren't sorted by
3445 // register number due to our using "sp", "lr" and "pc" as canonical names.
3446 static unsigned getNextRegister(unsigned Reg) {
3447  // If this is a GPR, we need to do it manually, otherwise we can rely
3448  // on the sort ordering of the enumeration since the other reg-classes
3449  // are sane.
3450  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3451  return Reg + 1;
3452  switch(Reg) {
3453  default: llvm_unreachable("Invalid GPR number!");
3454  case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3455  case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3456  case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3457  case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3458  case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3459  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3460  case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3461  case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3462  }
3463 }
3464 
3465 // Return the low-subreg of a given Q register.
3466 static unsigned getDRegFromQReg(unsigned QReg) {
3467  switch (QReg) {
3468  default: llvm_unreachable("expected a Q register!");
3469  case ARM::Q0: return ARM::D0;
3470  case ARM::Q1: return ARM::D2;
3471  case ARM::Q2: return ARM::D4;
3472  case ARM::Q3: return ARM::D6;
3473  case ARM::Q4: return ARM::D8;
3474  case ARM::Q5: return ARM::D10;
3475  case ARM::Q6: return ARM::D12;
3476  case ARM::Q7: return ARM::D14;
3477  case ARM::Q8: return ARM::D16;
3478  case ARM::Q9: return ARM::D18;
3479  case ARM::Q10: return ARM::D20;
3480  case ARM::Q11: return ARM::D22;
3481  case ARM::Q12: return ARM::D24;
3482  case ARM::Q13: return ARM::D26;
3483  case ARM::Q14: return ARM::D28;
3484  case ARM::Q15: return ARM::D30;
3485  }
3486 }
3487 
3488 /// Parse a register list.
3489 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3490  MCAsmParser &Parser = getParser();
3491  if (Parser.getTok().isNot(AsmToken::LCurly))
3492  return TokError("Token is not a Left Curly Brace");
3493  SMLoc S = Parser.getTok().getLoc();
3494  Parser.Lex(); // Eat '{' token.
3495  SMLoc RegLoc = Parser.getTok().getLoc();
3496 
3497  // Check the first register in the list to see what register class
3498  // this is a list of.
3499  int Reg = tryParseRegister();
3500  if (Reg == -1)
3501  return Error(RegLoc, "register expected");
3502 
3503  // The reglist instructions have at most 16 registers, so reserve
3504  // space for that many.
3505  int EReg = 0;
3507 
3508  // Allow Q regs and just interpret them as the two D sub-registers.
3509  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3510  Reg = getDRegFromQReg(Reg);
3511  EReg = MRI->getEncodingValue(Reg);
3512  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3513  ++Reg;
3514  }
3515  const MCRegisterClass *RC;
3516  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3517  RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3518  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3519  RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3520  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3521  RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3522  else
3523  return Error(RegLoc, "invalid register in register list");
3524 
3525  // Store the register.
3526  EReg = MRI->getEncodingValue(Reg);
3527  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3528 
3529  // This starts immediately after the first register token in the list,
3530  // so we can see either a comma or a minus (range separator) as a legal
3531  // next token.
3532  while (Parser.getTok().is(AsmToken::Comma) ||
3533  Parser.getTok().is(AsmToken::Minus)) {
3534  if (Parser.getTok().is(AsmToken::Minus)) {
3535  Parser.Lex(); // Eat the minus.
3536  SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3537  int EndReg = tryParseRegister();
3538  if (EndReg == -1)
3539  return Error(AfterMinusLoc, "register expected");
3540  // Allow Q regs and just interpret them as the two D sub-registers.
3541  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3542  EndReg = getDRegFromQReg(EndReg) + 1;
3543  // If the register is the same as the start reg, there's nothing
3544  // more to do.
3545  if (Reg == EndReg)
3546  continue;
3547  // The register must be in the same register class as the first.
3548  if (!RC->contains(EndReg))
3549  return Error(AfterMinusLoc, "invalid register in register list");
3550  // Ranges must go from low to high.
3551  if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3552  return Error(AfterMinusLoc, "bad range in register list");
3553 
3554  // Add all the registers in the range to the register list.
3555  while (Reg != EndReg) {
3556  Reg = getNextRegister(Reg);
3557  EReg = MRI->getEncodingValue(Reg);
3558  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3559  }
3560  continue;
3561  }
3562  Parser.Lex(); // Eat the comma.
3563  RegLoc = Parser.getTok().getLoc();
3564  int OldReg = Reg;
3565  const AsmToken RegTok = Parser.getTok();
3566  Reg = tryParseRegister();
3567  if (Reg == -1)
3568  return Error(RegLoc, "register expected");
3569  // Allow Q regs and just interpret them as the two D sub-registers.
3570  bool isQReg = false;
3571  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3572  Reg = getDRegFromQReg(Reg);
3573  isQReg = true;
3574  }
3575  // The register must be in the same register class as the first.
3576  if (!RC->contains(Reg))
3577  return Error(RegLoc, "invalid register in register list");
3578  // List must be monotonically increasing.
3579  if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3580  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3581  Warning(RegLoc, "register list not in ascending order");
3582  else
3583  return Error(RegLoc, "register list not in ascending order");
3584  }
3585  if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3586  Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3587  ") in register list");
3588  continue;
3589  }
3590  // VFP register lists must also be contiguous.
3591  if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3592  Reg != OldReg + 1)
3593  return Error(RegLoc, "non-contiguous register range");
3594  EReg = MRI->getEncodingValue(Reg);
3595  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3596  if (isQReg) {
3597  EReg = MRI->getEncodingValue(++Reg);
3598  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3599  }
3600  }
3601 
3602  if (Parser.getTok().isNot(AsmToken::RCurly))
3603  return Error(Parser.getTok().getLoc(), "'}' expected");
3604  SMLoc E = Parser.getTok().getEndLoc();
3605  Parser.Lex(); // Eat '}' token.
3606 
3607  // Push the register list operand.
3608  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3609 
3610  // The ARM system instruction variants for LDM/STM have a '^' token here.
3611  if (Parser.getTok().is(AsmToken::Caret)) {
3612  Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3613  Parser.Lex(); // Eat '^' token.
3614  }
3615 
3616  return false;
3617 }
3618 
3619 // Helper function to parse the lane index for vector lists.
3620 OperandMatchResultTy ARMAsmParser::
3621 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3622  MCAsmParser &Parser = getParser();
3623  Index = 0; // Always return a defined index value.
3624  if (Parser.getTok().is(AsmToken::LBrac)) {
3625  Parser.Lex(); // Eat the '['.
3626  if (Parser.getTok().is(AsmToken::RBrac)) {
3627  // "Dn[]" is the 'all lanes' syntax.
3628  LaneKind = AllLanes;
3629  EndLoc = Parser.getTok().getEndLoc();
3630  Parser.Lex(); // Eat the ']'.
3631  return MatchOperand_Success;
3632  }
3633 
3634  // There's an optional '#' token here. Normally there wouldn't be, but
3635  // inline assemble puts one in, and it's friendly to accept that.
3636  if (Parser.getTok().is(AsmToken::Hash))
3637  Parser.Lex(); // Eat '#' or '$'.
3638 
3639  const MCExpr *LaneIndex;
3640  SMLoc Loc = Parser.getTok().getLoc();
3641  if (getParser().parseExpression(LaneIndex)) {
3642  Error(Loc, "illegal expression");
3643  return MatchOperand_ParseFail;
3644  }
3645  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3646  if (!CE) {
3647  Error(Loc, "lane index must be empty or an integer");
3648  return MatchOperand_ParseFail;
3649  }
3650  if (Parser.getTok().isNot(AsmToken::RBrac)) {
3651  Error(Parser.getTok().getLoc(), "']' expected");
3652  return MatchOperand_ParseFail;
3653  }
3654  EndLoc = Parser.getTok().getEndLoc();
3655  Parser.Lex(); // Eat the ']'.
3656  int64_t Val = CE->getValue();
3657 
3658  // FIXME: Make this range check context sensitive for .8, .16, .32.
3659  if (Val < 0 || Val > 7) {
3660  Error(Parser.getTok().getLoc(), "lane index out of range");
3661  return MatchOperand_ParseFail;
3662  }
3663  Index = Val;
3664  LaneKind = IndexedLane;
3665  return MatchOperand_Success;
3666  }
3667  LaneKind = NoLanes;
3668  return MatchOperand_Success;
3669 }
3670 
3671 // parse a vector register list
3673 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3674  MCAsmParser &Parser = getParser();
3675  VectorLaneTy LaneKind;
3676  unsigned LaneIndex;
3677  SMLoc S = Parser.getTok().getLoc();
3678  // As an extension (to match gas), support a plain D register or Q register
3679  // (without encosing curly braces) as a single or double entry list,
3680  // respectively.
3681  if (Parser.getTok().is(AsmToken::Identifier)) {
3682  SMLoc E = Parser.getTok().getEndLoc();
3683  int Reg = tryParseRegister();
3684  if (Reg == -1)
3685  return MatchOperand_NoMatch;
3686  if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3687  OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3688  if (Res != MatchOperand_Success)
3689  return Res;
3690  switch (LaneKind) {
3691  case NoLanes:
3692  Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3693  break;
3694  case AllLanes:
3695  Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3696  S, E));
3697  break;
3698  case IndexedLane:
3699  Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3700  LaneIndex,
3701  false, S, E));
3702  break;
3703  }
3704  return MatchOperand_Success;
3705  }
3706  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3707  Reg = getDRegFromQReg(Reg);
3708  OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3709  if (Res != MatchOperand_Success)
3710  return Res;
3711  switch (LaneKind) {
3712  case NoLanes:
3713  Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3714  &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3715  Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3716  break;
3717  case AllLanes:
3718  Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3719  &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3720  Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3721  S, E));
3722  break;
3723  case IndexedLane:
3724  Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3725  LaneIndex,
3726  false, S, E));
3727  break;
3728  }
3729  return MatchOperand_Success;
3730  }
3731  Error(S, "vector register expected");
3732  return MatchOperand_ParseFail;
3733  }
3734 
3735  if (Parser.getTok().isNot(AsmToken::LCurly))
3736  return MatchOperand_NoMatch;
3737 
3738  Parser.Lex(); // Eat '{' token.
3739  SMLoc RegLoc = Parser.getTok().getLoc();
3740 
3741  int Reg = tryParseRegister();
3742  if (Reg == -1) {
3743  Error(RegLoc, "register expected");
3744  return MatchOperand_ParseFail;
3745  }
3746  unsigned Count = 1;
3747  int Spacing = 0;
3748  unsigned FirstReg = Reg;
3749  // The list is of D registers, but we also allow Q regs and just interpret
3750  // them as the two D sub-registers.
3751  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3752  FirstReg = Reg = getDRegFromQReg(Reg);
3753  Spacing = 1; // double-spacing requires explicit D registers, otherwise
3754  // it's ambiguous with four-register single spaced.
3755  ++Reg;
3756  ++Count;
3757  }
3758 
3759  SMLoc E;
3760  if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3761  return MatchOperand_ParseFail;
3762 
3763  while (Parser.getTok().is(AsmToken::Comma) ||
3764  Parser.getTok().is(AsmToken::Minus)) {
3765  if (Parser.getTok().is(AsmToken::Minus)) {
3766  if (!Spacing)
3767  Spacing = 1; // Register range implies a single spaced list.
3768  else if (Spacing == 2) {
3769  Error(Parser.getTok().getLoc(),
3770  "sequential registers in double spaced list");
3771  return MatchOperand_ParseFail;
3772  }
3773  Parser.Lex(); // Eat the minus.
3774  SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3775  int EndReg = tryParseRegister();
3776  if (EndReg == -1) {
3777  Error(AfterMinusLoc, "register expected");
3778  return MatchOperand_ParseFail;
3779  }
3780  // Allow Q regs and just interpret them as the two D sub-registers.
3781  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3782  EndReg = getDRegFromQReg(EndReg) + 1;
3783  // If the register is the same as the start reg, there's nothing
3784  // more to do.
3785  if (Reg == EndReg)
3786  continue;
3787  // The register must be in the same register class as the first.
3788  if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3789  Error(AfterMinusLoc, "invalid register in register list");
3790  return MatchOperand_ParseFail;
3791  }
3792  // Ranges must go from low to high.
3793  if (Reg > EndReg) {
3794  Error(AfterMinusLoc, "bad range in register list");
3795  return MatchOperand_ParseFail;
3796  }
3797  // Parse the lane specifier if present.
3798  VectorLaneTy NextLaneKind;
3799  unsigned NextLaneIndex;
3800  if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3802  return MatchOperand_ParseFail;
3803  if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3804  Error(AfterMinusLoc, "mismatched lane index in register list");
3805  return MatchOperand_ParseFail;
3806  }
3807 
3808  // Add all the registers in the range to the register list.
3809  Count += EndReg - Reg;
3810  Reg = EndReg;
3811  continue;
3812  }
3813  Parser.Lex(); // Eat the comma.
3814  RegLoc = Parser.getTok().getLoc();
3815  int OldReg = Reg;
3816  Reg = tryParseRegister();
3817  if (Reg == -1) {
3818  Error(RegLoc, "register expected");
3819  return MatchOperand_ParseFail;
3820  }
3821  // vector register lists must be contiguous.
3822  // It's OK to use the enumeration values directly here rather, as the
3823  // VFP register classes have the enum sorted properly.
3824  //
3825  // The list is of D registers, but we also allow Q regs and just interpret
3826  // them as the two D sub-registers.
3827  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3828  if (!Spacing)
3829  Spacing = 1; // Register range implies a single spaced list.
3830  else if (Spacing == 2) {
3831  Error(RegLoc,
3832  "invalid register in double-spaced list (must be 'D' register')");
3833  return MatchOperand_ParseFail;
3834  }
3835  Reg = getDRegFromQReg(Reg);
3836  if (Reg != OldReg + 1) {
3837  Error(RegLoc, "non-contiguous register range");
3838  return MatchOperand_ParseFail;
3839  }
3840  ++Reg;
3841  Count += 2;
3842  // Parse the lane specifier if present.
3843  VectorLaneTy NextLaneKind;
3844  unsigned NextLaneIndex;
3845  SMLoc LaneLoc = Parser.getTok().getLoc();
3846  if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3848  return MatchOperand_ParseFail;
3849  if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3850  Error(LaneLoc, "mismatched lane index in register list");
3851  return MatchOperand_ParseFail;
3852  }
3853  continue;
3854  }
3855  // Normal D register.
3856  // Figure out the register spacing (single or double) of the list if
3857  // we don't know it already.
3858  if (!Spacing)
3859  Spacing = 1 + (Reg == OldReg + 2);
3860 
3861  // Just check that it's contiguous and keep going.
3862  if (Reg != OldReg + Spacing) {
3863  Error(RegLoc, "non-contiguous register range");
3864  return MatchOperand_ParseFail;
3865  }
3866  ++Count;
3867  // Parse the lane specifier if present.
3868  VectorLaneTy NextLaneKind;
3869  unsigned NextLaneIndex;
3870  SMLoc EndLoc = Parser.getTok().getLoc();
3871  if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3872  return MatchOperand_ParseFail;
3873  if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3874  Error(EndLoc, "mismatched lane index in register list");
3875  return MatchOperand_ParseFail;
3876  }
3877  }
3878 
3879  if (Parser.getTok().isNot(AsmToken::RCurly)) {
3880  Error(Parser.getTok().getLoc(), "'}' expected");
3881  return MatchOperand_ParseFail;
3882  }
3883  E = Parser.getTok().getEndLoc();
3884  Parser.Lex(); // Eat '}' token.
3885 
3886  switch (LaneKind) {
3887  case NoLanes:
3888  // Two-register operands have been converted to the
3889  // composite register classes.
3890  if (Count == 2) {
3891  const MCRegisterClass *RC = (Spacing == 1) ?
3892  &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3893  &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3894  FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3895  }
3896 
3897  Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3898  (Spacing == 2), S, E));
3899  break;
3900  case AllLanes:
3901  // Two-register operands have been converted to the
3902  // composite register classes.
3903  if (Count == 2) {
3904  const MCRegisterClass *RC = (Spacing == 1) ?
3905  &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3906  &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3907  FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3908  }
3909  Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3910  (Spacing == 2),
3911  S, E));
3912  break;
3913  case IndexedLane:
3914  Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3915  LaneIndex,
3916  (Spacing == 2),
3917  S, E));
3918  break;
3919  }
3920  return MatchOperand_Success;
3921 }
3922 
3923 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3925 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3926  MCAsmParser &Parser = getParser();
3927  SMLoc S = Parser.getTok().getLoc();
3928  const AsmToken &Tok = Parser.getTok();
3929  unsigned Opt;
3930 
3931  if (Tok.is(AsmToken::Identifier)) {
3932  StringRef OptStr = Tok.getString();
3933 
3934  Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3935  .Case("sy", ARM_MB::SY)
3936  .Case("st", ARM_MB::ST)
3937  .Case("ld", ARM_MB::LD)
3938  .Case("sh", ARM_MB::ISH)
3939  .Case("ish", ARM_MB::ISH)
3940  .Case("shst", ARM_MB::ISHST)
3941  .Case("ishst", ARM_MB::ISHST)
3942  .Case("ishld", ARM_MB::ISHLD)
3943  .Case("nsh", ARM_MB::NSH)
3944  .Case("un", ARM_MB::NSH)
3945  .Case("nshst", ARM_MB::NSHST)
3946  .Case("nshld", ARM_MB::NSHLD)
3947  .Case("unst", ARM_MB::NSHST)
3948  .Case("osh", ARM_MB::OSH)
3949  .Case("oshst", ARM_MB::OSHST)
3950  .Case("oshld", ARM_MB::OSHLD)
3951  .Default(~0U);
3952 
3953  // ishld, oshld, nshld and ld are only available from ARMv8.
3954  if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3955  Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3956  Opt = ~0U;
3957 
3958  if (Opt == ~0U)
3959  return MatchOperand_NoMatch;
3960 
3961  Parser.Lex(); // Eat identifier token.
3962  } else if (Tok.is(AsmToken::Hash) ||
3963  Tok.is(AsmToken::Dollar) ||
3964  Tok.is(AsmToken::Integer)) {
3965  if (Parser.getTok().isNot(AsmToken::Integer))
3966  Parser.Lex(); // Eat '#' or '$'.
3967  SMLoc Loc = Parser.getTok().getLoc();
3968 
3969  const MCExpr *MemBarrierID;
3970  if (getParser().parseExpression(MemBarrierID)) {
3971  Error(Loc, "illegal expression");
3972  return MatchOperand_ParseFail;
3973  }
3974 
3975  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3976  if (!CE) {
3977  Error(Loc, "constant expression expected");
3978  return MatchOperand_ParseFail;
3979  }
3980 
3981  int Val = CE->getValue();
3982  if (Val & ~0xf) {
3983  Error(Loc, "immediate value out of range");
3984  return MatchOperand_ParseFail;
3985  }
3986 
3987  Opt = ARM_MB::RESERVED_0 + Val;
3988  } else
3989  return MatchOperand_ParseFail;
3990 
3991  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3992  return MatchOperand_Success;
3993 }
3994 
3995 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3997 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3998  MCAsmParser &Parser = getParser();
3999  SMLoc S = Parser.getTok().getLoc();
4000  const AsmToken &Tok = Parser.getTok();
4001  unsigned Opt;
4002 
4003  if (Tok.is(AsmToken::Identifier)) {
4004  StringRef OptStr = Tok.getString();
4005 
4006  if (OptStr.equals_lower("sy"))
4007  Opt = ARM_ISB::SY;
4008  else
4009  return MatchOperand_NoMatch;
4010 
4011  Parser.Lex(); // Eat identifier token.
4012  } else if (Tok.is(AsmToken::Hash) ||
4013  Tok.is(AsmToken::Dollar) ||
4014  Tok.is(AsmToken::Integer)) {
4015  if (Parser.getTok().isNot(AsmToken::Integer))
4016  Parser.Lex(); // Eat '#' or '$'.
4017  SMLoc Loc = Parser.getTok().getLoc();
4018 
4019  const MCExpr *ISBarrierID;
4020  if (getParser().parseExpression(ISBarrierID)) {
4021  Error(Loc, "illegal expression");
4022  return MatchOperand_ParseFail;
4023  }
4024 
4025  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
4026  if (!CE) {
4027  Error(Loc, "constant expression expected");
4028  return MatchOperand_ParseFail;
4029  }
4030 
4031  int Val = CE->getValue();
4032  if (Val & ~0xf) {
4033  Error(Loc, "immediate value out of range");
4034  return MatchOperand_ParseFail;
4035  }
4036 
4037  Opt = ARM_ISB::RESERVED_0 + Val;
4038  } else
4039  return MatchOperand_ParseFail;
4040 
4041  Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
4042  (ARM_ISB::InstSyncBOpt)Opt, S));
4043  return MatchOperand_Success;
4044 }
4045 
4046 
4047 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
4049 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
4050  MCAsmParser &Parser = getParser();
4051  SMLoc S = Parser.getTok().getLoc();
4052  const AsmToken &Tok = Parser.getTok();
4053  if (!Tok.is(AsmToken::Identifier))
4054  return MatchOperand_NoMatch;
4055  StringRef IFlagsStr = Tok.getString();
4056 
4057  // An iflags string of "none" is interpreted to mean that none of the AIF
4058  // bits are set. Not a terribly useful instruction, but a valid encoding.
4059  unsigned IFlags = 0;
4060  if (IFlagsStr != "none") {
4061  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
4062  unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
4063  .Case("a", ARM_PROC::A)
4064  .Case("i", ARM_PROC::I)
4065  .Case("f", ARM_PROC::F)
4066  .Default(~0U);
4067 
4068  // If some specific iflag is already set, it means that some letter is
4069  // present more than once, this is not acceptable.
4070  if (Flag == ~0U || (IFlags & Flag))
4071  return MatchOperand_NoMatch;
4072 
4073  IFlags |= Flag;
4074  }
4075  }
4076 
4077  Parser.Lex(); // Eat identifier token.
4078  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
4079  return MatchOperand_Success;
4080 }
4081 
4082 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4084 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
4085  MCAsmParser &Parser = getParser();
4086  SMLoc S = Parser.getTok().getLoc();
4087  const AsmToken &Tok = Parser.getTok();
4088  if (!Tok.is(AsmToken::Identifier))
4089  return MatchOperand_NoMatch;
4090  StringRef Mask = Tok.getString();
4091 
4092  if (isMClass()) {
4093  auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
4094  if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
4095  return MatchOperand_NoMatch;
4096 
4097  unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
4098 
4099  Parser.Lex(); // Eat identifier token.
4100  Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4101  return MatchOperand_Success;
4102  }
4103 
4104  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4105  size_t Start = 0, Next = Mask.find('_');
4106  StringRef Flags = "";
4107  std::string SpecReg = Mask.slice(Start, Next).lower();
4108  if (Next != StringRef::npos)
4109  Flags = Mask.slice(Next+1, Mask.size());
4110 
4111  // FlagsVal contains the complete mask:
4112  // 3-0: Mask
4113  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4114  unsigned FlagsVal = 0;
4115 
4116  if (SpecReg == "apsr") {
4117  FlagsVal = StringSwitch<unsigned>(Flags)
4118  .Case("nzcvq", 0x8) // same as CPSR_f
4119  .Case("g", 0x4) // same as CPSR_s
4120  .Case("nzcvqg", 0xc) // same as CPSR_fs
4121  .Default(~0U);
4122 
4123  if (FlagsVal == ~0U) {
4124  if (!Flags.empty())
4125  return MatchOperand_NoMatch;
4126  else
4127  FlagsVal = 8; // No flag
4128  }
4129  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4130  // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4131  if (Flags == "all" || Flags == "")
4132  Flags = "fc";
4133  for (int i = 0, e = Flags.size(); i != e; ++i) {
4134  unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4135  .Case("c", 1)
4136  .Case("x", 2)
4137  .Case("s", 4)
4138  .Case("f", 8)
4139  .Default(~0U);
4140 
4141  // If some specific flag is already set, it means that some letter is
4142  // present more than once, this is not acceptable.
4143  if (Flag == ~0U || (FlagsVal & Flag))
4144  return MatchOperand_NoMatch;
4145  FlagsVal |= Flag;
4146  }
4147  } else // No match for special register.
4148  return MatchOperand_NoMatch;
4149 
4150  // Special register without flags is NOT equivalent to "fc" flags.
4151  // NOTE: This is a divergence from gas' behavior. Uncommenting the following
4152  // two lines would enable gas compatibility at the expense of breaking
4153  // round-tripping.
4154  //
4155  // if (!FlagsVal)
4156  // FlagsVal = 0x9;
4157 
4158  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4159  if (SpecReg == "spsr")
4160  FlagsVal |= 16;
4161 
4162  Parser.Lex(); // Eat identifier token.
4163  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4164  return MatchOperand_Success;
4165 }
4166 
4167 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4168 /// use in the MRS/MSR instructions added to support virtualization.
4170 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4171  MCAsmParser &Parser = getParser();
4172  SMLoc S = Parser.getTok().getLoc();
4173  const AsmToken &Tok = Parser.getTok();
4174  if (!Tok.is(AsmToken::Identifier))
4175  return MatchOperand_NoMatch;
4176  StringRef RegName = Tok.getString();
4177 
4178  // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4179  // and bit 5 is R.
4180  unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4181  .Case("r8_usr", 0x00)
4182  .Case("r9_usr", 0x01)
4183  .Case("r10_usr", 0x02)
4184  .Case("r11_usr", 0x03)
4185  .Case("r12_usr", 0x04)
4186  .Case("sp_usr", 0x05)
4187  .Case("lr_usr", 0x06)
4188  .Case("r8_fiq", 0x08)
4189  .Case("r9_fiq", 0x09)
4190  .Case("r10_fiq", 0x0a)
4191  .Case("r11_fiq", 0x0b)
4192  .Case("r12_fiq", 0x0c)
4193  .Case("sp_fiq", 0x0d)
4194  .Case("lr_fiq", 0x0e)
4195  .Case("lr_irq", 0x10)
4196  .Case("sp_irq", 0x11)
4197  .Case("lr_svc", 0x12)
4198  .Case("sp_svc", 0x13)
4199  .Case("lr_abt", 0x14)
4200  .Case("sp_abt", 0x15)
4201  .Case("lr_und", 0x16)
4202  .Case("sp_und", 0x17)
4203  .Case("lr_mon", 0x1c)
4204  .Case("sp_mon", 0x1d)
4205  .Case("elr_hyp", 0x1e)
4206  .Case("sp_hyp", 0x1f)
4207  .Case("spsr_fiq", 0x2e)
4208  .Case("spsr_irq", 0x30)
4209  .Case("spsr_svc", 0x32)
4210  .Case("spsr_abt", 0x34)
4211  .Case("spsr_und", 0x36)
4212  .Case("spsr_mon", 0x3c)
4213  .Case("spsr_hyp", 0x3e)
4214  .Default(~0U);
4215 
4216  if (Encoding == ~0U)
4217  return MatchOperand_NoMatch;
4218 
4219  Parser.Lex(); // Eat identifier token.
4220  Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4221  return MatchOperand_Success;
4222 }
4223 
4225 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4226  int High) {
4227  MCAsmParser &Parser = getParser();
4228  const AsmToken &Tok = Parser.getTok();
4229  if (Tok.isNot(AsmToken::Identifier)) {
4230  Error(Parser.getTok().getLoc(), Op + " operand expected.");
4231  return MatchOperand_ParseFail;
4232  }
4233  StringRef ShiftName = Tok.getString();
4234  std::string LowerOp = Op.lower();
4235  std::string UpperOp = Op.upper();
4236  if (ShiftName != LowerOp && ShiftName != UpperOp) {
4237  Error(Parser.getTok().getLoc(), Op + " operand expected.");
4238  return MatchOperand_ParseFail;
4239  }
4240  Parser.Lex(); // Eat shift type token.
4241 
4242  // There must be a '#' and a shift amount.
4243  if (Parser.getTok().isNot(AsmToken::Hash) &&
4244  Parser.getTok().isNot(AsmToken::Dollar)) {
4245  Error(Parser.getTok().getLoc(), "'#' expected");
4246  return MatchOperand_ParseFail;
4247  }
4248  Parser.Lex(); // Eat hash token.
4249 
4250  const MCExpr *ShiftAmount;
4251  SMLoc Loc = Parser.getTok().getLoc();
4252  SMLoc EndLoc;
4253  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4254  Error(Loc, "illegal expression");
4255  return MatchOperand_ParseFail;
4256  }
4257  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4258  if (!CE) {
4259  Error(Loc, "constant expression expected");
4260  return MatchOperand_ParseFail;
4261  }
4262  int Val = CE->getValue();
4263  if (Val < Low || Val > High) {
4264  Error(Loc, "immediate value out of range");
4265  return MatchOperand_ParseFail;
4266  }
4267 
4268  Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4269 
4270  return MatchOperand_Success;
4271 }
4272 
4274 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4275  MCAsmParser &Parser = getParser();
4276  const AsmToken &Tok = Parser.getTok();
4277  SMLoc S = Tok.getLoc();
4278  if (Tok.isNot(AsmToken::Identifier)) {
4279  Error(S, "'be' or 'le' operand expected");
4280  return MatchOperand_ParseFail;
4281  }
4282  int Val = StringSwitch<int>(Tok.getString().lower())
4283  .Case("be", 1)
4284  .Case("le", 0)
4285  .Default(-1);
4286  Parser.Lex(); // Eat the token.
4287 
4288  if (Val == -1) {
4289  Error(S, "'be' or 'le' operand expected");
4290  return MatchOperand_ParseFail;
4291  }
4292  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
4293  getContext()),
4294  S, Tok.getEndLoc()));
4295  return MatchOperand_Success;
4296 }
4297 
4298 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4299 /// instructions. Legal values are:
4300 /// lsl #n 'n' in [0,31]
4301 /// asr #n 'n' in [1,32]
4302 /// n == 32 encoded as n == 0.
4304 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4305  MCAsmParser &Parser = getParser();
4306  const AsmToken &Tok = Parser.getTok();
4307  SMLoc S = Tok.getLoc();
4308  if (Tok.isNot(AsmToken::Identifier)) {
4309  Error(S, "shift operator 'asr' or 'lsl' expected");
4310  return MatchOperand_ParseFail;
4311  }
4312  StringRef ShiftName = Tok.getString();
4313  bool isASR;
4314  if (ShiftName == "lsl" || ShiftName == "LSL")
4315  isASR = false;
4316  else if (ShiftName == "asr" || ShiftName == "ASR")
4317  isASR = true;
4318  else {
4319  Error(S, "shift operator 'asr' or 'lsl' expected");
4320  return MatchOperand_ParseFail;
4321  }
4322  Parser.Lex(); // Eat the operator.
4323 
4324  // A '#' and a shift amount.
4325  if (Parser.getTok().isNot(AsmToken::Hash) &&
4326  Parser.getTok().isNot(AsmToken::Dollar)) {
4327  Error(Parser.getTok().getLoc(), "'#' expected");
4328  return MatchOperand_ParseFail;
4329  }
4330  Parser.Lex(); // Eat hash token.
4331  SMLoc ExLoc = Parser.getTok().getLoc();
4332 
4333  const MCExpr *ShiftAmount;
4334  SMLoc EndLoc;
4335  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4336  Error(ExLoc, "malformed shift expression");
4337  return MatchOperand_ParseFail;
4338  }
4339  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4340  if (!CE) {
4341  Error(ExLoc, "shift amount must be an immediate");
4342  return MatchOperand_ParseFail;
4343  }
4344 
4345  int64_t Val = CE->getValue();
4346  if (isASR) {
4347  // Shift amount must be in [1,32]
4348  if (Val < 1 || Val > 32) {
4349  Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4350  return MatchOperand_ParseFail;
4351  }
4352  // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4353  if (isThumb() && Val == 32) {
4354  Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4355  return MatchOperand_ParseFail;
4356  }
4357  if (Val == 32) Val = 0;
4358  } else {
4359  // Shift amount must be in [1,32]
4360  if (Val < 0 || Val > 31) {
4361  Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4362  return MatchOperand_ParseFail;
4363  }
4364  }
4365 
4366  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4367 
4368  return MatchOperand_Success;
4369 }
4370 
4371 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4372 /// of instructions. Legal values are:
4373 /// ror #n 'n' in {0, 8, 16, 24}
4375 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4376  MCAsmParser &Parser = getParser();
4377  const AsmToken &Tok = Parser.getTok();
4378  SMLoc S = Tok.getLoc();
4379  if (Tok.isNot(AsmToken::Identifier))
4380  return MatchOperand_NoMatch;
4381  StringRef ShiftName = Tok.getString();
4382  if (ShiftName != "ror" && ShiftName != "ROR")
4383  return MatchOperand_NoMatch;
4384  Parser.Lex(); // Eat the operator.
4385 
4386  // A '#' and a rotate amount.
4387  if (Parser.getTok().isNot(AsmToken::Hash) &&
4388  Parser.getTok().isNot(AsmToken::Dollar)) {
4389  Error(Parser.getTok().getLoc(), "'#' expected");
4390  return MatchOperand_ParseFail;
4391  }
4392  Parser.Lex(); // Eat hash token.
4393  SMLoc ExLoc = Parser.getTok().getLoc();
4394 
4395  const MCExpr *ShiftAmount;
4396  SMLoc EndLoc;
4397  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4398  Error(ExLoc, "malformed rotate expression");
4399  return MatchOperand_ParseFail;
4400  }
4401  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4402  if (!CE) {
4403  Error(ExLoc, "rotate amount must be an immediate");
4404  return MatchOperand_ParseFail;
4405  }
4406 
4407  int64_t Val = CE->getValue();
4408  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4409  // normally, zero is represented in asm by omitting the rotate operand
4410  // entirely.
4411  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4412  Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4413  return MatchOperand_ParseFail;
4414  }
4415 
4416  Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4417 
4418  return MatchOperand_Success;
4419 }
4420 
4422 ARMAsmParser::parseModImm(OperandVector &Operands) {
4423  MCAsmParser &Parser = getParser();
4424  MCAsmLexer &Lexer = getLexer();
4425  int64_t Imm1, Imm2;
4426 
4427  SMLoc S = Parser.getTok().getLoc();
4428 
4429  // 1) A mod_imm operand can appear in the place of a register name:
4430  // add r0, #mod_imm
4431  // add r0, r0, #mod_imm
4432  // to correctly handle the latter, we bail out as soon as we see an
4433  // identifier.
4434  //
4435  // 2) Similarly, we do not want to parse into complex operands:
4436  // mov r0, #mod_imm
4437  // mov r0, :lower16:(_foo)
4438  if (Parser.getTok().is(AsmToken::Identifier) ||
4439  Parser.getTok().is(AsmToken::Colon))
4440  return MatchOperand_NoMatch;
4441 
4442  // Hash (dollar) is optional as per the ARMARM
4443  if (Parser.getTok().is(AsmToken::Hash) ||
4444  Parser.getTok().is(AsmToken::Dollar)) {
4445  // Avoid parsing into complex operands (#:)
4446  if (Lexer.peekTok().is(AsmToken::Colon))
4447  return MatchOperand_NoMatch;
4448 
4449  // Eat the hash (dollar)
4450  Parser.Lex();
4451  }
4452 
4453  SMLoc Sx1, Ex1;
4454  Sx1 = Parser.getTok().getLoc();
4455  const MCExpr *Imm1Exp;
4456  if (getParser().parseExpression(Imm1Exp, Ex1)) {
4457  Error(Sx1, "malformed expression");
4458  return MatchOperand_ParseFail;
4459  }
4460 
4461  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4462 
4463  if (CE) {
4464  // Immediate must fit within 32-bits
4465  Imm1 = CE->getValue();
4466  int Enc = ARM_AM::getSOImmVal(Imm1);
4467  if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4468  // We have a match!
4469  Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4470  (Enc & 0xF00) >> 7,
4471  Sx1, Ex1));
4472  return MatchOperand_Success;
4473  }
4474 
4475  // We have parsed an immediate which is not for us, fallback to a plain
4476  // immediate. This can happen for instruction aliases. For an example,
4477  // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4478  // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4479  // instruction with a mod_imm operand. The alias is defined such that the
4480  // parser method is shared, that's why we have to do this here.
4481  if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4482  Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4483  return MatchOperand_Success;
4484  }
4485  } else {
4486  // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4487  // MCFixup). Fallback to a plain immediate.
4488  Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4489  return MatchOperand_Success;
4490  }
4491 
4492  // From this point onward, we expect the input to be a (#bits, #rot) pair
4493  if (Parser.getTok().isNot(AsmToken::Comma)) {
4494  Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4495  return MatchOperand_ParseFail;
4496  }
4497 
4498  if (Imm1 & ~0xFF) {
4499  Error(Sx1, "immediate operand must a number in the range [0, 255]");
4500  return MatchOperand_ParseFail;
4501  }
4502 
4503  // Eat the comma
4504  Parser.Lex();
4505 
4506  // Repeat for #rot
4507  SMLoc Sx2, Ex2;
4508  Sx2 = Parser.getTok().getLoc();
4509 
4510  // Eat the optional hash (dollar)
4511  if (Parser.getTok().is(AsmToken::Hash) ||
4512  Parser.getTok().is(AsmToken::Dollar))
4513  Parser.Lex();
4514 
4515  const MCExpr *Imm2Exp;
4516  if (getParser().parseExpression(Imm2Exp, Ex2)) {
4517  Error(Sx2, "malformed expression");
4518  return MatchOperand_ParseFail;
4519  }
4520 
4521  CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4522 
4523  if (CE) {
4524  Imm2 = CE->getValue();
4525  if (!(Imm2 & ~0x1E)) {
4526  // We have a match!
4527  Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4528  return MatchOperand_Success;
4529  }
4530  Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4531  return MatchOperand_ParseFail;
4532  } else {
4533  Error(Sx2, "constant expression expected");
4534  return MatchOperand_ParseFail;
4535  }
4536 }
4537 
4539 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4540  MCAsmParser &Parser = getParser();
4541  SMLoc S = Parser.getTok().getLoc();
4542  // The bitfield descriptor is really two operands, the LSB and the width.
4543  if (Parser.getTok().isNot(AsmToken::Hash) &&
4544  Parser.getTok().isNot(AsmToken::Dollar)) {
4545  Error(Parser.getTok().getLoc(), "'#' expected");
4546  return MatchOperand_ParseFail;
4547  }
4548  Parser.Lex(); // Eat hash token.
4549 
4550  const MCExpr *LSBExpr;
4551  SMLoc E = Parser.getTok().getLoc();
4552  if (getParser().parseExpression(LSBExpr)) {
4553  Error(E, "malformed immediate expression");
4554  return MatchOperand_ParseFail;
4555  }
4556  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4557  if (!CE) {
4558  Error(E, "'lsb' operand must be an immediate");
4559  return MatchOperand_ParseFail;
4560  }
4561 
4562  int64_t LSB = CE->getValue();
4563  // The LSB must be in the range [0,31]
4564  if (LSB < 0 || LSB > 31) {
4565  Error(E, "'lsb' operand must be in the range [0,31]");
4566  return MatchOperand_ParseFail;
4567  }
4568  E = Parser.getTok().getLoc();
4569 
4570  // Expect another immediate operand.
4571  if (Parser.getTok().isNot(AsmToken::Comma)) {
4572  Error(Parser.getTok().getLoc(), "too few operands");
4573  return MatchOperand_ParseFail;
4574  }
4575  Parser.Lex(); // Eat hash token.
4576  if (Parser.getTok().isNot(AsmToken::Hash) &&
4577  Parser.getTok().isNot(AsmToken::Dollar)) {
4578  Error(Parser.getTok().getLoc(), "'#' expected");
4579  return MatchOperand_ParseFail;
4580  }
4581  Parser.Lex(); // Eat hash token.
4582 
4583  const MCExpr *WidthExpr;
4584  SMLoc EndLoc;
4585  if (getParser().parseExpression(WidthExpr, EndLoc)) {
4586  Error(E, "malformed immediate expression");
4587  return MatchOperand_ParseFail;
4588  }
4589  CE = dyn_cast<MCConstantExpr>(WidthExpr);
4590  if (!CE) {
4591  Error(E, "'width' operand must be an immediate");
4592  return MatchOperand_ParseFail;
4593  }
4594 
4595  int64_t Width = CE->getValue();
4596  // The LSB must be in the range [1,32-lsb]
4597  if (Width < 1 || Width > 32 - LSB) {
4598  Error(E, "'width' operand must be in the range [1,32-lsb]");
4599  return MatchOperand_ParseFail;
4600  }
4601 
4602  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4603 
4604  return MatchOperand_Success;
4605 }
4606 
4608 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4609  // Check for a post-index addressing register operand. Specifically:
4610  // postidx_reg := '+' register {, shift}
4611  // | '-' register {, shift}
4612  // | register {, shift}
4613 
4614  // This method must return MatchOperand_NoMatch without consuming any tokens
4615  // in the case where there is no match, as other alternatives take other
4616  // parse methods.
4617  MCAsmParser &Parser = getParser();
4618  AsmToken Tok = Parser.getTok();
4619  SMLoc S = Tok.getLoc();
4620  bool haveEaten = false;
4621  bool isAdd = true;
4622  if (Tok.is(AsmToken::Plus)) {
4623  Parser.Lex(); // Eat the '+' token.
4624  haveEaten = true;
4625  } else if (Tok.is(AsmToken::Minus)) {
4626  Parser.Lex(); // Eat the '-' token.
4627  isAdd = false;
4628  haveEaten = true;
4629  }
4630 
4631  SMLoc E = Parser.getTok().getEndLoc();
4632  int Reg = tryParseRegister();
4633  if (Reg == -1) {
4634  if (!haveEaten)
4635  return MatchOperand_NoMatch;
4636  Error(Parser.getTok().getLoc(), "register expected");
4637  return MatchOperand_ParseFail;
4638  }
4639 
4641  unsigned ShiftImm = 0;
4642  if (Parser.getTok().is(AsmToken::Comma)) {
4643  Parser.Lex(); // Eat the ','.
4644  if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4645  return MatchOperand_ParseFail;
4646 
4647  // FIXME: Only approximates end...may include intervening whitespace.
4648  E = Parser.getTok().getLoc();
4649  }
4650 
4651  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4652  ShiftImm, S, E));
4653 
4654  return MatchOperand_Success;
4655 }
4656 
4658 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4659  // Check for a post-index addressing register operand. Specifically:
4660  // am3offset := '+' register
4661  // | '-' register
4662  // | register
4663  // | # imm
4664  // | # + imm
4665  // | # - imm
4666 
4667  // This method must return MatchOperand_NoMatch without consuming any tokens
4668  // in the case where there is no match, as other alternatives take other
4669  // parse methods.
4670  MCAsmParser &Parser = getParser();
4671  AsmToken Tok = Parser.getTok();
4672  SMLoc S = Tok.getLoc();
4673 
4674  // Do immediates first, as we always parse those if we have a '#'.
4675  if (Parser.getTok().is(AsmToken::Hash) ||
4676  Parser.getTok().is(AsmToken::Dollar)) {
4677  Parser.Lex(); // Eat '#' or '$'.
4678  // Explicitly look for a '-', as we need to encode negative zero
4679  // differently.
4680  bool isNegative = Parser.getTok().is(AsmToken::Minus);
4681  const MCExpr *Offset;
4682  SMLoc E;
4683  if (getParser().parseExpression(Offset, E))
4684  return MatchOperand_ParseFail;
4686  if (!CE) {
4687  Error(S, "constant expression expected");
4688  return MatchOperand_ParseFail;
4689  }
4690  // Negative zero is encoded as the flag value INT32_MIN.
4691  int32_t Val = CE->getValue();
4692  if (isNegative && Val == 0)
4693  Val = INT32_MIN;
4694 
4695  Operands.push_back(
4696  ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
4697 
4698  return MatchOperand_Success;
4699  }
4700 
4701 
4702  bool haveEaten = false;
4703  bool isAdd = true;
4704  if (Tok.is(AsmToken::Plus)) {
4705  Parser.Lex(); // Eat the '+' token.
4706  haveEaten = true;
4707  } else if (Tok.is(AsmToken::Minus)) {
4708  Parser.Lex(); // Eat the '-' token.
4709  isAdd = false;
4710  haveEaten = true;
4711  }
4712 
4713  Tok = Parser.getTok();
4714  int Reg = tryParseRegister();
4715  if (Reg == -1) {
4716  if (!haveEaten)
4717  return MatchOperand_NoMatch;
4718  Error(Tok.getLoc(), "register expected");
4719  return MatchOperand_ParseFail;
4720  }
4721 
4722  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4723  0, S, Tok.getEndLoc()));
4724 
4725  return MatchOperand_Success;
4726 }
4727 
4728 /// Convert parsed operands to MCInst. Needed here because this instruction
4729 /// only has two register operands, but multiplication is commutative so
4730 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4731 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4732  const OperandVector &Operands) {
4733  ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4734  ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4735  // If we have a three-operand form, make sure to set Rn to be the operand
4736  // that isn't the same as Rd.
4737  unsigned RegOp = 4;
4738  if (Operands.size() == 6 &&
4739  ((ARMOperand &)*Operands[4]).getReg() ==
4740  ((ARMOperand &)*Operands[3]).getReg())
4741  RegOp = 5;
4742  ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4743  Inst.addOperand(Inst.getOperand(0));
4744  ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4745 }
4746 
4747 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4748  const OperandVector &Operands) {
4749  int CondOp = -1, ImmOp = -1;
4750  switch(Inst.getOpcode()) {
4751  case ARM::tB:
4752  case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4753 
4754  case ARM::t2B:
4755  case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4756 
4757  default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4758  }
4759  // first decide whether or not the branch should be conditional
4760  // by looking at it's location relative to an IT block
4761  if(inITBlock()) {
4762  // inside an IT block we cannot have any conditional branches. any
4763  // such instructions needs to be converted to unconditional form
4764  switch(Inst.getOpcode()) {
4765  case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4766  case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4767  }
4768  } else {
4769  // outside IT blocks we can only have unconditional branches with AL
4770  // condition code or conditional branches with non-AL condition code
4771  unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4772  switch(Inst.getOpcode()) {
4773  case ARM::tB:
4774  case ARM::tBcc:
4775  Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4776  break;
4777  case ARM::t2B:
4778  case ARM::t2Bcc:
4779  Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4780  break;
4781  }
4782  }
4783 
4784  // now decide on encoding size based on branch target range
4785  switch(Inst.getOpcode()) {
4786  // classify tB as either t2B or t1B based on range of immediate operand
4787  case ARM::tB: {
4788  ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4789  if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
4790  Inst.setOpcode(ARM::t2B);
4791  break;
4792  }
4793  // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4794  case ARM::tBcc: {
4795  ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4796  if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
4797  Inst.setOpcode(ARM::t2Bcc);
4798  break;
4799  }
4800  }
4801  ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4802  ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4803 }
4804 
4805 /// Parse an ARM memory expression, return false if successful else return true
4806 /// or an error. The first token must be a '[' when called.
4807 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4808  MCAsmParser &Parser = getParser();
4809  SMLoc S, E;
4810  if (Parser.getTok().isNot(AsmToken::LBrac))
4811  return TokError("Token is not a Left Bracket");
4812  S = Parser.getTok().getLoc();
4813  Parser.Lex(); // Eat left bracket token.
4814 
4815  const AsmToken &BaseRegTok = Parser.getTok();
4816  int BaseRegNum = tryParseRegister();
4817  if (BaseRegNum == -1)
4818  return Error(BaseRegTok.getLoc(), "register expected");
4819 
4820  // The next token must either be a comma, a colon or a closing bracket.
4821  const AsmToken &Tok = Parser.getTok();
4822  if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4823  !Tok.is(AsmToken::RBrac))
4824  return Error(Tok.getLoc(), "malformed memory operand");
4825 
4826  if (Tok.is(AsmToken::RBrac)) {
4827  E = Tok.getEndLoc();
4828  Parser.Lex(); // Eat right bracket token.
4829 
4830  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4831  ARM_AM::no_shift, 0, 0, false,
4832  S, E));
4833 
4834  // If there's a pre-indexing writeback marker, '!', just add it as a token
4835  // operand. It's rather odd, but syntactically valid.
4836  if (Parser.getTok().is(AsmToken::Exclaim)) {
4837  Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4838  Parser.Lex(); // Eat the '!'.
4839  }
4840 
4841  return false;
4842  }
4843 
4844  assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4845  "Lost colon or comma in memory operand?!");
4846  if (Tok.is(AsmToken::Comma)) {
4847  Parser.Lex(); // Eat the comma.
4848  }
4849 
4850  // If we have a ':', it's an alignment specifier.
4851  if (Parser.getTok().is(AsmToken::Colon)) {
4852  Parser.Lex(); // Eat the ':'.
4853  E = Parser.getTok().getLoc();
4854  SMLoc AlignmentLoc = Tok.getLoc();
4855 
4856  const MCExpr *Expr;
4857  if (getParser().parseExpression(Expr))
4858  return true;
4859 
4860  // The expression has to be a constant. Memory references with relocations
4861  // don't come through here, as they use the <label> forms of the relevant
4862  // instructions.
4863  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4864  if (!CE)
4865  return Error (E, "constant expression expected");
4866 
4867  unsigned Align = 0;
4868  switch (CE->getValue()) {
4869  default:
4870  return Error(E,
4871  "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4872  case 16: Align = 2; break;
4873  case 32: Align = 4; break;
4874  case 64: Align = 8; break;
4875  case 128: Align = 16; break;
4876  case 256: Align = 32; break;
4877  }
4878 
4879  // Now we should have the closing ']'
4880  if (Parser.getTok().isNot(AsmToken::RBrac))
4881  return Error(Parser.getTok().getLoc(), "']' expected");
4882  E = Parser.getTok().getEndLoc();
4883  Parser.Lex(); // Eat right bracket token.
4884 
4885  // Don't worry about range checking the value here. That's handled by
4886  // the is*() predicates.
4887  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4888  ARM_AM::no_shift, 0, Align,
4889  false, S, E, AlignmentLoc));
4890 
4891  // If there's a pre-indexing writeback marker, '!', just add it as a token
4892  // operand.
4893  if (Parser.getTok().is(AsmToken::Exclaim)) {
4894  Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4895  Parser.Lex(); // Eat the '!'.
4896  }
4897 
4898  return false;
4899  }
4900 
4901  // If we have a '#', it's an immediate offset, else assume it's a register
4902  // offset. Be friendly and also accept a plain integer (without a leading
4903  // hash) for gas compatibility.
4904  if (Parser.getTok().is(AsmToken::Hash) ||
4905  Parser.getTok().is(AsmToken::Dollar) ||
4906  Parser.getTok().is(AsmToken::Integer)) {
4907  if (Parser.getTok().isNot(AsmToken::Integer))
4908  Parser.Lex(); // Eat '#' or '$'.
4909  E = Parser.getTok().getLoc();
4910 
4911  bool isNegative = getParser().getTok().is(AsmToken::Minus);
4912  const MCExpr *Offset;
4913  if (getParser().parseExpression(Offset))
4914  return true;
4915 
4916  // The expression has to be a constant. Memory references with relocations
4917  // don't come through here, as they use the <label> forms of the relevant
4918  // instructions.
4920  if (!CE)
4921  return Error (E, "constant expression expected");
4922 
4923  // If the constant was #-0, represent it as INT32_MIN.
4924  int32_t Val = CE->getValue();
4925  if (isNegative && Val == 0)
4926  CE = MCConstantExpr::create(INT32_MIN, getContext());
4927 
4928  // Now we should have the closing ']'
4929  if (Parser.getTok().isNot(AsmToken::RBrac))
4930  return Error(Parser.getTok().getLoc(), "']' expected");
4931  E = Parser.getTok().getEndLoc();
4932  Parser.Lex(); // Eat right bracket token.
4933 
4934  // Don't worry about range checking the value here. That's handled by
4935  // the is*() predicates.
4936  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4937  ARM_AM::no_shift, 0, 0,
4938  false, S, E));
4939 
4940  // If there's a pre-indexing writeback marker, '!', just add it as a token
4941  // operand.
4942  if (Parser.getTok().is(AsmToken::Exclaim)) {
4943  Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4944  Parser.Lex(); // Eat the '!'.
4945  }
4946 
4947  return false;
4948  }
4949 
4950  // The register offset is optionally preceded by a '+' or '-'
4951  bool isNegative = false;
4952  if (Parser.getTok().is(AsmToken::Minus)) {
4953  isNegative = true;
4954  Parser.Lex(); // Eat the '-'.
4955  } else if (Parser.getTok().is(AsmToken::Plus)) {
4956  // Nothing to do.
4957  Parser.Lex(); // Eat the '+'.
4958  }
4959 
4960  E = Parser.getTok().getLoc();
4961  int OffsetRegNum = tryParseRegister();
4962  if (OffsetRegNum == -1)
4963  return Error(E, "register expected");
4964 
4965  // If there's a shift operator, handle it.
4966  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4967  unsigned ShiftImm = 0;
4968  if (Parser.getTok().is(AsmToken::Comma)) {
4969  Parser.Lex(); // Eat the ','.
4970  if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4971  return true;
4972  }
4973 
4974  // Now we should have the closing ']'
4975  if (Parser.getTok().isNot(AsmToken::RBrac))
4976  return Error(Parser.getTok().getLoc(), "']' expected");
4977  E = Parser.getTok().getEndLoc();
4978  Parser.Lex(); // Eat right bracket token.
4979 
4980  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4981  ShiftType, ShiftImm, 0, isNegative,
4982  S, E));
4983 
4984  // If there's a pre-indexing writeback marker, '!', just add it as a token
4985  // operand.
4986  if (Parser.getTok().is(AsmToken::Exclaim)) {
4987  Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4988  Parser.Lex(); // Eat the '!'.
4989  }
4990 
4991  return false;
4992 }
4993 
4994 /// parseMemRegOffsetShift - one of these two:
4995 /// ( lsl | lsr | asr | ror ) , # shift_amount
4996 /// rrx
4997 /// return true if it parses a shift otherwise it returns false.
4998 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4999  unsigned &Amount) {
5000  MCAsmParser &Parser = getParser();
5001  SMLoc Loc = Parser.getTok().getLoc();
5002  const AsmToken &Tok = Parser.getTok();
5003  if (Tok.isNot(AsmToken::Identifier))
5004  return true;
5005  StringRef ShiftName = Tok.getString();
5006  if (ShiftName == "lsl" || ShiftName == "LSL" ||
5007  ShiftName == "asl" || ShiftName == "ASL")
5008  St = ARM_AM::lsl;
5009  else if (ShiftName == "lsr" || ShiftName == "LSR")
5010  St = ARM_AM::lsr;
5011  else if (ShiftName == "asr" || ShiftName == "ASR")
5012  St = ARM_AM::asr;
5013  else if (ShiftName == "ror" || ShiftName == "ROR")
5014  St = ARM_AM::ror;
5015  else if (ShiftName == "rrx" || ShiftName == "RRX")
5016  St = ARM_AM::rrx;
5017  else
5018  return Error(Loc, "illegal shift operator");
5019  Parser.Lex(); // Eat shift type token.
5020 
5021  // rrx stands alone.
5022  Amount = 0;
5023  if (St != ARM_AM::rrx) {
5024  Loc = Parser.getTok().getLoc();
5025  // A '#' and a shift amount.
5026  const AsmToken &HashTok = Parser.getTok();
5027  if (HashTok.isNot(AsmToken::Hash) &&
5028  HashTok.isNot(AsmToken::Dollar))
5029  return Error(HashTok.getLoc(), "'#' expected");
5030  Parser.Lex(); // Eat hash token.
5031 
5032  const MCExpr *Expr;
5033  if (getParser().parseExpression(Expr))
5034  return true;
5035  // Range check the immediate.
5036  // lsl, ror: 0 <= imm <= 31
5037  // lsr, asr: 0 <= imm <= 32
5038  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5039  if (!CE)
5040  return Error(Loc, "shift amount must be an immediate");
5041  int64_t Imm = CE->getValue();
5042  if (Imm < 0 ||
5043  ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5044  ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5045  return Error(Loc, "immediate shift value out of range");
5046  // If <ShiftTy> #0, turn it into a no_shift.
5047  if (Imm == 0)
5048  St = ARM_AM::lsl;
5049  // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5050  if (Imm == 32)
5051  Imm = 0;
5052  Amount = Imm;
5053  }
5054 
5055  return false;
5056 }
5057 
5058 /// parseFPImm - A floating point immediate expression operand.
5060 ARMAsmParser::parseFPImm(OperandVector &Operands) {
5061  MCAsmParser &Parser = getParser();
5062  // Anything that can accept a floating point constant as an operand
5063  // needs to go through here, as the regular parseExpression is
5064  // integer only.
5065  //
5066  // This routine still creates a generic Immediate operand, containing
5067  // a bitcast of the 64-bit floating point value. The various operands
5068  // that accept floats can check whether the value is valid for them
5069  // via the standard is*() predicates.
5070 
5071  SMLoc S = Parser.getTok().getLoc();
5072 
5073  if (Parser.getTok().isNot(AsmToken::Hash) &&
5074  Parser.getTok().isNot(AsmToken::Dollar))
5075  return MatchOperand_NoMatch;
5076 
5077  // Disambiguate the VMOV forms that can accept an FP immediate.
5078  // vmov.f32 <sreg>, #imm
5079  // vmov.f64 <dreg>, #imm
5080  // vmov.f32 <dreg>, #imm @ vector f32x2
5081  // vmov.f32 <qreg>, #imm @ vector f32x4
5082  //
5083  // There are also the NEON VMOV instructions which expect an
5084  // integer constant. Make sure we don't try to parse an FPImm
5085  // for these:
5086  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5087  ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5088  bool isVmovf = TyOp.isToken() &&
5089  (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
5090  TyOp.getToken() == ".f16");
5091  ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5092  bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5093  Mnemonic.getToken() == "fconsts");
5094  if (!(isVmovf || isFconst))
5095  return MatchOperand_NoMatch;
5096 
5097  Parser.Lex(); // Eat '#' or '$'.
5098 
5099  // Handle negation, as that still comes through as a separate token.
5100  bool isNegative = false;
5101  if (Parser.getTok().is(AsmToken::Minus)) {
5102  isNegative = true;
5103  Parser.Lex();
5104  }
5105  const AsmToken &Tok = Parser.getTok();
5106  SMLoc Loc = Tok.getLoc();
5107  if (Tok.is(AsmToken::Real) && isVmovf) {
5108  APFloat RealVal(APFloat::IEEEsingle(), Tok.getString());
5109  uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5110  // If we had a '-' in front, toggle the sign bit.
5111  IntVal ^= (uint64_t)isNegative << 31;
5112  Parser.Lex(); // Eat the token.
5113  Operands.push_back(ARMOperand::CreateImm(
5114  MCConstantExpr::create(IntVal, getContext()),
5115  S, Parser.getTok().getLoc()));
5116  return MatchOperand_Success;
5117  }
5118  // Also handle plain integers. Instructions which allow floating point
5119  // immediates also allow a raw encoded 8-bit value.
5120  if (Tok.is(AsmToken::Integer) && isFconst) {
5121  int64_t Val = Tok.getIntVal();
5122  Parser.Lex(); // Eat the token.
5123  if (Val > 255 || Val < 0) {
5124  Error(Loc, "encoded floating point value out of range");
5125  return MatchOperand_ParseFail;
5126  }
5127  float RealVal = ARM_AM::getFPImmFloat(Val);
5128  Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5129 
5130  Operands.push_back(ARMOperand::CreateImm(
5131  MCConstantExpr::create(Val, getContext()), S,
5132  Parser.getTok().getLoc()));
5133  return MatchOperand_Success;
5134  }
5135 
5136  Error(Loc, "invalid floating point immediate");
5137  return MatchOperand_ParseFail;
5138 }
5139 
5140 /// Parse a arm instruction operand. For now this parses the operand regardless
5141 /// of the mnemonic.
5142 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5143  MCAsmParser &Parser = getParser();
5144  SMLoc S, E;
5145 
5146  // Check if the current operand has a custom associated parser, if so, try to
5147  // custom parse the operand, or fallback to the general approach.
5148  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5149  if (ResTy == MatchOperand_Success)
5150  return false;
5151  // If there wasn't a custom match, try the generic matcher below. Otherwise,
5152  // there was a match, but an error occurred, in which case, just return that
5153  // the operand parsing failed.
5154  if (ResTy == MatchOperand_ParseFail)
5155  return true;
5156 
5157  switch (getLexer().getKind()) {
5158  default:
5159  Error(Parser.getTok().getLoc(), "unexpected token in operand");
5160  return true;
5161  case AsmToken::Identifier: {
5162  // If we've seen a branch mnemonic, the next operand must be a label. This
5163  // is true even if the label is a register name. So "br r1" means branch to
5164  // label "r1".
5165  bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
5166  if (!ExpectLabel) {
5167  if (!tryParseRegisterWithWriteBack(Operands))
5168  return false;
5169  int Res = tryParseShiftRegister(Operands);
5170  if (Res == 0) // success
5171  return false;
5172  else if (Res == -1) // irrecoverable error
5173  return true;
5174  // If this is VMRS, check for the apsr_nzcv operand.
5175  if (Mnemonic == "vmrs" &&
5176  Parser.getTok().getString().equals_lower("apsr_nzcv")) {
5177  S = Parser.getTok().getLoc();
5178  Parser.Lex();
5179  Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
5180  return false;
5181  }
5182  }
5183 
5184  // Fall though for the Identifier case that is not a register or a
5185  // special name.
5187  }
5188  case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
5189  case AsmToken::Integer: // things like 1f and 2b as a branch targets
5190  case AsmToken::String: // quoted label names.
5191  case AsmToken::Dot: { // . as a branch target
5192  // This was not a register so parse other operands that start with an
5193  // identifier (like labels) as expressions and create them as immediates.
5194  const MCExpr *IdVal;
5195  S = Parser.getTok().getLoc();
5196  if (getParser().parseExpression(IdVal))
5197  return true;
5198  E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5199  Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
5200  return false;
5201  }
5202  case AsmToken::LBrac:
5203  return parseMemory(Operands);