LLVM  7.0.0svn
ARMAsmParser.cpp
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1 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMFeatures.h"
11 #include "Utils/ARMBaseInfo.h"
14 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/APFloat.h"
17 #include "llvm/ADT/APInt.h"
18 #include "llvm/ADT/None.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringMap.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/ADT/Twine.h"
27 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCInstrInfo.h"
39 #include "llvm/MC/MCRegisterInfo.h"
40 #include "llvm/MC/MCSection.h"
41 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/ARMEHABI.h"
47 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/Compiler.h"
52 #include "llvm/Support/SMLoc.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <cstddef>
59 #include <cstdint>
60 #include <iterator>
61 #include <limits>
62 #include <memory>
63 #include <string>
64 #include <utility>
65 #include <vector>
66 
67 #define DEBUG_TYPE "asm-parser"
68 
69 using namespace llvm;
70 
71 namespace {
72 
73 enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
74 
75 static cl::opt<ImplicitItModeTy> ImplicitItMode(
76  "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
77  cl::desc("Allow conditional instructions outdside of an IT block"),
78  cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
79  "Accept in both ISAs, emit implicit ITs in Thumb"),
80  clEnumValN(ImplicitItModeTy::Never, "never",
81  "Warn in ARM, reject in Thumb"),
82  clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
83  "Accept in ARM, reject in Thumb"),
84  clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
85  "Warn in ARM, emit implicit ITs in Thumb")));
86 
87 static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
88  cl::init(false));
89 
90 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
91 
92 class UnwindContext {
93  using Locs = SmallVector<SMLoc, 4>;
94 
95  MCAsmParser &Parser;
96  Locs FnStartLocs;
97  Locs CantUnwindLocs;
98  Locs PersonalityLocs;
99  Locs PersonalityIndexLocs;
100  Locs HandlerDataLocs;
101  int FPReg;
102 
103 public:
104  UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
105 
106  bool hasFnStart() const { return !FnStartLocs.empty(); }
107  bool cantUnwind() const { return !CantUnwindLocs.empty(); }
108  bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
109 
110  bool hasPersonality() const {
111  return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
112  }
113 
114  void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
115  void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
116  void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
117  void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
118  void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
119 
120  void saveFPReg(int Reg) { FPReg = Reg; }
121  int getFPReg() const { return FPReg; }
122 
123  void emitFnStartLocNotes() const {
124  for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
125  FI != FE; ++FI)
126  Parser.Note(*FI, ".fnstart was specified here");
127  }
128 
129  void emitCantUnwindLocNotes() const {
130  for (Locs::const_iterator UI = CantUnwindLocs.begin(),
131  UE = CantUnwindLocs.end(); UI != UE; ++UI)
132  Parser.Note(*UI, ".cantunwind was specified here");
133  }
134 
135  void emitHandlerDataLocNotes() const {
136  for (Locs::const_iterator HI = HandlerDataLocs.begin(),
137  HE = HandlerDataLocs.end(); HI != HE; ++HI)
138  Parser.Note(*HI, ".handlerdata was specified here");
139  }
140 
141  void emitPersonalityLocNotes() const {
142  for (Locs::const_iterator PI = PersonalityLocs.begin(),
143  PE = PersonalityLocs.end(),
144  PII = PersonalityIndexLocs.begin(),
145  PIE = PersonalityIndexLocs.end();
146  PI != PE || PII != PIE;) {
147  if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
148  Parser.Note(*PI++, ".personality was specified here");
149  else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
150  Parser.Note(*PII++, ".personalityindex was specified here");
151  else
152  llvm_unreachable(".personality and .personalityindex cannot be "
153  "at the same location");
154  }
155  }
156 
157  void reset() {
158  FnStartLocs = Locs();
159  CantUnwindLocs = Locs();
160  PersonalityLocs = Locs();
161  HandlerDataLocs = Locs();
162  PersonalityIndexLocs = Locs();
163  FPReg = ARM::SP;
164  }
165 };
166 
167 class ARMAsmParser : public MCTargetAsmParser {
168  const MCRegisterInfo *MRI;
169  UnwindContext UC;
170 
171  ARMTargetStreamer &getTargetStreamer() {
172  assert(getParser().getStreamer().getTargetStreamer() &&
173  "do not have a target streamer");
174  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
175  return static_cast<ARMTargetStreamer &>(TS);
176  }
177 
178  // Map of register aliases registers via the .req directive.
179  StringMap<unsigned> RegisterReqs;
180 
181  bool NextSymbolIsThumb;
182 
183  bool useImplicitITThumb() const {
184  return ImplicitItMode == ImplicitItModeTy::Always ||
185  ImplicitItMode == ImplicitItModeTy::ThumbOnly;
186  }
187 
188  bool useImplicitITARM() const {
189  return ImplicitItMode == ImplicitItModeTy::Always ||
190  ImplicitItMode == ImplicitItModeTy::ARMOnly;
191  }
192 
193  struct {
194  ARMCC::CondCodes Cond; // Condition for IT block.
195  unsigned Mask:4; // Condition mask for instructions.
196  // Starting at first 1 (from lsb).
197  // '1' condition as indicated in IT.
198  // '0' inverse of condition (else).
199  // Count of instructions in IT block is
200  // 4 - trailingzeroes(mask)
201  // Note that this does not have the same encoding
202  // as in the IT instruction, which also depends
203  // on the low bit of the condition code.
204 
205  unsigned CurPosition; // Current position in parsing of IT
206  // block. In range [0,4], with 0 being the IT
207  // instruction itself. Initialized according to
208  // count of instructions in block. ~0U if no
209  // active IT block.
210 
211  bool IsExplicit; // true - The IT instruction was present in the
212  // input, we should not modify it.
213  // false - The IT instruction was added
214  // implicitly, we can extend it if that
215  // would be legal.
216  } ITState;
217 
218  SmallVector<MCInst, 4> PendingConditionalInsts;
219 
220  void flushPendingInstructions(MCStreamer &Out) override {
221  if (!inImplicitITBlock()) {
222  assert(PendingConditionalInsts.size() == 0);
223  return;
224  }
225 
226  // Emit the IT instruction
227  unsigned Mask = getITMaskEncoding();
228  MCInst ITInst;
229  ITInst.setOpcode(ARM::t2IT);
230  ITInst.addOperand(MCOperand::createImm(ITState.Cond));
231  ITInst.addOperand(MCOperand::createImm(Mask));
232  Out.EmitInstruction(ITInst, getSTI());
233 
234  // Emit the conditonal instructions
235  assert(PendingConditionalInsts.size() <= 4);
236  for (const MCInst &Inst : PendingConditionalInsts) {
237  Out.EmitInstruction(Inst, getSTI());
238  }
239  PendingConditionalInsts.clear();
240 
241  // Clear the IT state
242  ITState.Mask = 0;
243  ITState.CurPosition = ~0U;
244  }
245 
246  bool inITBlock() { return ITState.CurPosition != ~0U; }
247  bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
248  bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
249 
250  bool lastInITBlock() {
251  return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
252  }
253 
254  void forwardITPosition() {
255  if (!inITBlock()) return;
256  // Move to the next instruction in the IT block, if there is one. If not,
257  // mark the block as done, except for implicit IT blocks, which we leave
258  // open until we find an instruction that can't be added to it.
259  unsigned TZ = countTrailingZeros(ITState.Mask);
260  if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
261  ITState.CurPosition = ~0U; // Done with the IT block after this.
262  }
263 
264  // Rewind the state of the current IT block, removing the last slot from it.
265  void rewindImplicitITPosition() {
266  assert(inImplicitITBlock());
267  assert(ITState.CurPosition > 1);
268  ITState.CurPosition--;
269  unsigned TZ = countTrailingZeros(ITState.Mask);
270  unsigned NewMask = 0;
271  NewMask |= ITState.Mask & (0xC << TZ);
272  NewMask |= 0x2 << TZ;
273  ITState.Mask = NewMask;
274  }
275 
276  // Rewind the state of the current IT block, removing the last slot from it.
277  // If we were at the first slot, this closes the IT block.
278  void discardImplicitITBlock() {
279  assert(inImplicitITBlock());
280  assert(ITState.CurPosition == 1);
281  ITState.CurPosition = ~0U;
282  }
283 
284  // Return the low-subreg of a given Q register.
285  unsigned getDRegFromQReg(unsigned QReg) const {
286  return MRI->getSubReg(QReg, ARM::dsub_0);
287  }
288 
289  // Get the encoding of the IT mask, as it will appear in an IT instruction.
290  unsigned getITMaskEncoding() {
291  assert(inITBlock());
292  unsigned Mask = ITState.Mask;
293  unsigned TZ = countTrailingZeros(Mask);
294  if ((ITState.Cond & 1) == 0) {
295  assert(Mask && TZ <= 3 && "illegal IT mask value!");
296  Mask ^= (0xE << TZ) & 0xF;
297  }
298  return Mask;
299  }
300 
301  // Get the condition code corresponding to the current IT block slot.
302  ARMCC::CondCodes currentITCond() {
303  unsigned MaskBit;
304  if (ITState.CurPosition == 1)
305  MaskBit = 1;
306  else
307  MaskBit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
308 
309  return MaskBit ? ITState.Cond : ARMCC::getOppositeCondition(ITState.Cond);
310  }
311 
312  // Invert the condition of the current IT block slot without changing any
313  // other slots in the same block.
314  void invertCurrentITCondition() {
315  if (ITState.CurPosition == 1) {
316  ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
317  } else {
318  ITState.Mask ^= 1 << (5 - ITState.CurPosition);
319  }
320  }
321 
322  // Returns true if the current IT block is full (all 4 slots used).
323  bool isITBlockFull() {
324  return inITBlock() && (ITState.Mask & 1);
325  }
326 
327  // Extend the current implicit IT block to have one more slot with the given
328  // condition code.
329  void extendImplicitITBlock(ARMCC::CondCodes Cond) {
330  assert(inImplicitITBlock());
331  assert(!isITBlockFull());
332  assert(Cond == ITState.Cond ||
333  Cond == ARMCC::getOppositeCondition(ITState.Cond));
334  unsigned TZ = countTrailingZeros(ITState.Mask);
335  unsigned NewMask = 0;
336  // Keep any existing condition bits.
337  NewMask |= ITState.Mask & (0xE << TZ);
338  // Insert the new condition bit.
339  NewMask |= (Cond == ITState.Cond) << TZ;
340  // Move the trailing 1 down one bit.
341  NewMask |= 1 << (TZ - 1);
342  ITState.Mask = NewMask;
343  }
344 
345  // Create a new implicit IT block with a dummy condition code.
346  void startImplicitITBlock() {
347  assert(!inITBlock());
348  ITState.Cond = ARMCC::AL;
349  ITState.Mask = 8;
350  ITState.CurPosition = 1;
351  ITState.IsExplicit = false;
352  }
353 
354  // Create a new explicit IT block with the given condition and mask. The mask
355  // should be in the parsed format, with a 1 implying 't', regardless of the
356  // low bit of the condition.
357  void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
358  assert(!inITBlock());
359  ITState.Cond = Cond;
360  ITState.Mask = Mask;
361  ITState.CurPosition = 0;
362  ITState.IsExplicit = true;
363  }
364 
365  void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
366  return getParser().Note(L, Msg, Range);
367  }
368 
369  bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
370  return getParser().Warning(L, Msg, Range);
371  }
372 
373  bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
374  return getParser().Error(L, Msg, Range);
375  }
376 
377  bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
378  unsigned ListNo, bool IsARPop = false);
379  bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
380  unsigned ListNo);
381 
382  int tryParseRegister();
383  bool tryParseRegisterWithWriteBack(OperandVector &);
384  int tryParseShiftRegister(OperandVector &);
385  bool parseRegisterList(OperandVector &);
386  bool parseMemory(OperandVector &);
387  bool parseOperand(OperandVector &, StringRef Mnemonic);
388  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
389  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
390  unsigned &ShiftAmount);
391  bool parseLiteralValues(unsigned Size, SMLoc L);
392  bool parseDirectiveThumb(SMLoc L);
393  bool parseDirectiveARM(SMLoc L);
394  bool parseDirectiveThumbFunc(SMLoc L);
395  bool parseDirectiveCode(SMLoc L);
396  bool parseDirectiveSyntax(SMLoc L);
397  bool parseDirectiveReq(StringRef Name, SMLoc L);
398  bool parseDirectiveUnreq(SMLoc L);
399  bool parseDirectiveArch(SMLoc L);
400  bool parseDirectiveEabiAttr(SMLoc L);
401  bool parseDirectiveCPU(SMLoc L);
402  bool parseDirectiveFPU(SMLoc L);
403  bool parseDirectiveFnStart(SMLoc L);
404  bool parseDirectiveFnEnd(SMLoc L);
405  bool parseDirectiveCantUnwind(SMLoc L);
406  bool parseDirectivePersonality(SMLoc L);
407  bool parseDirectiveHandlerData(SMLoc L);
408  bool parseDirectiveSetFP(SMLoc L);
409  bool parseDirectivePad(SMLoc L);
410  bool parseDirectiveRegSave(SMLoc L, bool IsVector);
411  bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
412  bool parseDirectiveLtorg(SMLoc L);
413  bool parseDirectiveEven(SMLoc L);
414  bool parseDirectivePersonalityIndex(SMLoc L);
415  bool parseDirectiveUnwindRaw(SMLoc L);
416  bool parseDirectiveTLSDescSeq(SMLoc L);
417  bool parseDirectiveMovSP(SMLoc L);
418  bool parseDirectiveObjectArch(SMLoc L);
419  bool parseDirectiveArchExtension(SMLoc L);
420  bool parseDirectiveAlign(SMLoc L);
421  bool parseDirectiveThumbSet(SMLoc L);
422 
423  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
424  bool &CarrySetting, unsigned &ProcessorIMod,
425  StringRef &ITMask);
426  void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
427  bool &CanAcceptCarrySet,
428  bool &CanAcceptPredicationCode);
429 
430  void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
431  OperandVector &Operands);
432  bool isThumb() const {
433  // FIXME: Can tablegen auto-generate this?
434  return getSTI().getFeatureBits()[ARM::ModeThumb];
435  }
436 
437  bool isThumbOne() const {
438  return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
439  }
440 
441  bool isThumbTwo() const {
442  return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
443  }
444 
445  bool hasThumb() const {
446  return getSTI().getFeatureBits()[ARM::HasV4TOps];
447  }
448 
449  bool hasThumb2() const {
450  return getSTI().getFeatureBits()[ARM::FeatureThumb2];
451  }
452 
453  bool hasV6Ops() const {
454  return getSTI().getFeatureBits()[ARM::HasV6Ops];
455  }
456 
457  bool hasV6T2Ops() const {
458  return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
459  }
460 
461  bool hasV6MOps() const {
462  return getSTI().getFeatureBits()[ARM::HasV6MOps];
463  }
464 
465  bool hasV7Ops() const {
466  return getSTI().getFeatureBits()[ARM::HasV7Ops];
467  }
468 
469  bool hasV8Ops() const {
470  return getSTI().getFeatureBits()[ARM::HasV8Ops];
471  }
472 
473  bool hasV8MBaseline() const {
474  return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
475  }
476 
477  bool hasV8MMainline() const {
478  return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
479  }
480 
481  bool has8MSecExt() const {
482  return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
483  }
484 
485  bool hasARM() const {
486  return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
487  }
488 
489  bool hasDSP() const {
490  return getSTI().getFeatureBits()[ARM::FeatureDSP];
491  }
492 
493  bool hasD16() const {
494  return getSTI().getFeatureBits()[ARM::FeatureD16];
495  }
496 
497  bool hasV8_1aOps() const {
498  return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
499  }
500 
501  bool hasRAS() const {
502  return getSTI().getFeatureBits()[ARM::FeatureRAS];
503  }
504 
505  void SwitchMode() {
506  MCSubtargetInfo &STI = copySTI();
507  uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
508  setAvailableFeatures(FB);
509  }
510 
511  void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
512 
513  bool isMClass() const {
514  return getSTI().getFeatureBits()[ARM::FeatureMClass];
515  }
516 
517  /// @name Auto-generated Match Functions
518  /// {
519 
520 #define GET_ASSEMBLER_HEADER
521 #include "ARMGenAsmMatcher.inc"
522 
523  /// }
524 
525  OperandMatchResultTy parseITCondCode(OperandVector &);
526  OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
527  OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
528  OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
529  OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
530  OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
531  OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
532  OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
533  OperandMatchResultTy parseBankedRegOperand(OperandVector &);
534  OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
535  int High);
536  OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
537  return parsePKHImm(O, "lsl", 0, 31);
538  }
539  OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
540  return parsePKHImm(O, "asr", 1, 32);
541  }
542  OperandMatchResultTy parseSetEndImm(OperandVector &);
543  OperandMatchResultTy parseShifterImm(OperandVector &);
544  OperandMatchResultTy parseRotImm(OperandVector &);
545  OperandMatchResultTy parseModImm(OperandVector &);
546  OperandMatchResultTy parseBitfield(OperandVector &);
547  OperandMatchResultTy parsePostIdxReg(OperandVector &);
548  OperandMatchResultTy parseAM3Offset(OperandVector &);
549  OperandMatchResultTy parseFPImm(OperandVector &);
550  OperandMatchResultTy parseVectorList(OperandVector &);
551  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
552  SMLoc &EndLoc);
553 
554  // Asm Match Converter Methods
555  void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
556  void cvtThumbBranches(MCInst &Inst, const OperandVector &);
557 
558  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
559  bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
560  bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
561  bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
562  bool isITBlockTerminator(MCInst &Inst) const;
563  void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
564 
565 public:
566  enum ARMMatchResultTy {
567  Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
568  Match_RequiresNotITBlock,
569  Match_RequiresV6,
570  Match_RequiresThumb2,
571  Match_RequiresV8,
572  Match_RequiresFlagSetting,
573 #define GET_OPERAND_DIAGNOSTIC_TYPES
574 #include "ARMGenAsmMatcher.inc"
575 
576  };
577 
578  ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
579  const MCInstrInfo &MII, const MCTargetOptions &Options)
580  : MCTargetAsmParser(Options, STI, MII), UC(Parser) {
582 
583  // Cache the MCRegisterInfo.
584  MRI = getContext().getRegisterInfo();
585 
586  // Initialize the set of available features.
587  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
588 
589  // Add build attributes based on the selected target.
590  if (AddBuildAttributes)
591  getTargetStreamer().emitTargetAttributes(STI);
592 
593  // Not in an ITBlock to start with.
594  ITState.CurPosition = ~0U;
595 
596  NextSymbolIsThumb = false;
597  }
598 
599  // Implementation of the MCTargetAsmParser interface:
600  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
601  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
602  SMLoc NameLoc, OperandVector &Operands) override;
603  bool ParseDirective(AsmToken DirectiveID) override;
604 
605  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
606  unsigned Kind) override;
607  unsigned checkTargetMatchPredicate(MCInst &Inst) override;
608 
609  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
610  OperandVector &Operands, MCStreamer &Out,
611  uint64_t &ErrorInfo,
612  bool MatchingInlineAsm) override;
613  unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
614  SmallVectorImpl<NearMissInfo> &NearMisses,
615  bool MatchingInlineAsm, bool &EmitInITBlock,
616  MCStreamer &Out);
617 
618  struct NearMissMessage {
619  SMLoc Loc;
620  SmallString<128> Message;
621  };
622 
623  const char *getCustomOperandDiag(ARMMatchResultTy MatchError);
624 
625  void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
626  SmallVectorImpl<NearMissMessage> &NearMissesOut,
627  SMLoc IDLoc, OperandVector &Operands);
628  void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc,
629  OperandVector &Operands);
630 
631  void onLabelParsed(MCSymbol *Symbol) override;
632 };
633 
634 /// ARMOperand - Instances of this class represent a parsed ARM machine
635 /// operand.
636 class ARMOperand : public MCParsedAsmOperand {
637  enum KindTy {
638  k_CondCode,
639  k_CCOut,
640  k_ITCondMask,
641  k_CoprocNum,
642  k_CoprocReg,
643  k_CoprocOption,
644  k_Immediate,
645  k_MemBarrierOpt,
646  k_InstSyncBarrierOpt,
647  k_Memory,
648  k_PostIndexRegister,
649  k_MSRMask,
650  k_BankedReg,
651  k_ProcIFlags,
652  k_VectorIndex,
653  k_Register,
654  k_RegisterList,
655  k_DPRRegisterList,
656  k_SPRRegisterList,
657  k_VectorList,
658  k_VectorListAllLanes,
659  k_VectorListIndexed,
660  k_ShiftedRegister,
661  k_ShiftedImmediate,
662  k_ShifterImmediate,
663  k_RotateImmediate,
664  k_ModifiedImmediate,
665  k_ConstantPoolImmediate,
666  k_BitfieldDescriptor,
667  k_Token,
668  } Kind;
669 
670  SMLoc StartLoc, EndLoc, AlignmentLoc;
671  SmallVector<unsigned, 8> Registers;
672 
673  struct CCOp {
674  ARMCC::CondCodes Val;
675  };
676 
677  struct CopOp {
678  unsigned Val;
679  };
680 
681  struct CoprocOptionOp {
682  unsigned Val;
683  };
684 
685  struct ITMaskOp {
686  unsigned Mask:4;
687  };
688 
689  struct MBOptOp {
690  ARM_MB::MemBOpt Val;
691  };
692 
693  struct ISBOptOp {
695  };
696 
697  struct IFlagsOp {
698  ARM_PROC::IFlags Val;
699  };
700 
701  struct MMaskOp {
702  unsigned Val;
703  };
704 
705  struct BankedRegOp {
706  unsigned Val;
707  };
708 
709  struct TokOp {
710  const char *Data;
711  unsigned Length;
712  };
713 
714  struct RegOp {
715  unsigned RegNum;
716  };
717 
718  // A vector register list is a sequential list of 1 to 4 registers.
719  struct VectorListOp {
720  unsigned RegNum;
721  unsigned Count;
722  unsigned LaneIndex;
723  bool isDoubleSpaced;
724  };
725 
726  struct VectorIndexOp {
727  unsigned Val;
728  };
729 
730  struct ImmOp {
731  const MCExpr *Val;
732  };
733 
734  /// Combined record for all forms of ARM address expressions.
735  struct MemoryOp {
736  unsigned BaseRegNum;
737  // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
738  // was specified.
739  const MCConstantExpr *OffsetImm; // Offset immediate value
740  unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
741  ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
742  unsigned ShiftImm; // shift for OffsetReg.
743  unsigned Alignment; // 0 = no alignment specified
744  // n = alignment in bytes (2, 4, 8, 16, or 32)
745  unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
746  };
747 
748  struct PostIdxRegOp {
749  unsigned RegNum;
750  bool isAdd;
751  ARM_AM::ShiftOpc ShiftTy;
752  unsigned ShiftImm;
753  };
754 
755  struct ShifterImmOp {
756  bool isASR;
757  unsigned Imm;
758  };
759 
760  struct RegShiftedRegOp {
761  ARM_AM::ShiftOpc ShiftTy;
762  unsigned SrcReg;
763  unsigned ShiftReg;
764  unsigned ShiftImm;
765  };
766 
767  struct RegShiftedImmOp {
768  ARM_AM::ShiftOpc ShiftTy;
769  unsigned SrcReg;
770  unsigned ShiftImm;
771  };
772 
773  struct RotImmOp {
774  unsigned Imm;
775  };
776 
777  struct ModImmOp {
778  unsigned Bits;
779  unsigned Rot;
780  };
781 
782  struct BitfieldOp {
783  unsigned LSB;
784  unsigned Width;
785  };
786 
787  union {
788  struct CCOp CC;
789  struct CopOp Cop;
790  struct CoprocOptionOp CoprocOption;
791  struct MBOptOp MBOpt;
792  struct ISBOptOp ISBOpt;
793  struct ITMaskOp ITMask;
794  struct IFlagsOp IFlags;
795  struct MMaskOp MMask;
796  struct BankedRegOp BankedReg;
797  struct TokOp Tok;
798  struct RegOp Reg;
799  struct VectorListOp VectorList;
800  struct VectorIndexOp VectorIndex;
801  struct ImmOp Imm;
802  struct MemoryOp Memory;
803  struct PostIdxRegOp PostIdxReg;
804  struct ShifterImmOp ShifterImm;
805  struct RegShiftedRegOp RegShiftedReg;
806  struct RegShiftedImmOp RegShiftedImm;
807  struct RotImmOp RotImm;
808  struct ModImmOp ModImm;
809  struct BitfieldOp Bitfield;
810  };
811 
812 public:
813  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
814 
815  /// getStartLoc - Get the location of the first token of this operand.
816  SMLoc getStartLoc() const override { return StartLoc; }
817 
818  /// getEndLoc - Get the location of the last token of this operand.
819  SMLoc getEndLoc() const override { return EndLoc; }
820 
821  /// getLocRange - Get the range between the first and last token of this
822  /// operand.
823  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
824 
825  /// getAlignmentLoc - Get the location of the Alignment token of this operand.
826  SMLoc getAlignmentLoc() const {
827  assert(Kind == k_Memory && "Invalid access!");
828  return AlignmentLoc;
829  }
830 
831  ARMCC::CondCodes getCondCode() const {
832  assert(Kind == k_CondCode && "Invalid access!");
833  return CC.Val;
834  }
835 
836  unsigned getCoproc() const {
837  assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
838  return Cop.Val;
839  }
840 
841  StringRef getToken() const {
842  assert(Kind == k_Token && "Invalid access!");
843  return StringRef(Tok.Data, Tok.Length);
844  }
845 
846  unsigned getReg() const override {
847  assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
848  return Reg.RegNum;
849  }
850 
851  const SmallVectorImpl<unsigned> &getRegList() const {
852  assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
853  Kind == k_SPRRegisterList) && "Invalid access!");
854  return Registers;
855  }
856 
857  const MCExpr *getImm() const {
858  assert(isImm() && "Invalid access!");
859  return Imm.Val;
860  }
861 
862  const MCExpr *getConstantPoolImm() const {
863  assert(isConstantPoolImm() && "Invalid access!");
864  return Imm.Val;
865  }
866 
867  unsigned getVectorIndex() const {
868  assert(Kind == k_VectorIndex && "Invalid access!");
869  return VectorIndex.Val;
870  }
871 
872  ARM_MB::MemBOpt getMemBarrierOpt() const {
873  assert(Kind == k_MemBarrierOpt && "Invalid access!");
874  return MBOpt.Val;
875  }
876 
877  ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
878  assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
879  return ISBOpt.Val;
880  }
881 
882  ARM_PROC::IFlags getProcIFlags() const {
883  assert(Kind == k_ProcIFlags && "Invalid access!");
884  return IFlags.Val;
885  }
886 
887  unsigned getMSRMask() const {
888  assert(Kind == k_MSRMask && "Invalid access!");
889  return MMask.Val;
890  }
891 
892  unsigned getBankedReg() const {
893  assert(Kind == k_BankedReg && "Invalid access!");
894  return BankedReg.Val;
895  }
896 
897  bool isCoprocNum() const { return Kind == k_CoprocNum; }
898  bool isCoprocReg() const { return Kind == k_CoprocReg; }
899  bool isCoprocOption() const { return Kind == k_CoprocOption; }
900  bool isCondCode() const { return Kind == k_CondCode; }
901  bool isCCOut() const { return Kind == k_CCOut; }
902  bool isITMask() const { return Kind == k_ITCondMask; }
903  bool isITCondCode() const { return Kind == k_CondCode; }
904  bool isImm() const override {
905  return Kind == k_Immediate;
906  }
907 
908  bool isARMBranchTarget() const {
909  if (!isImm()) return false;
910 
911  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
912  return CE->getValue() % 4 == 0;
913  return true;
914  }
915 
916 
917  bool isThumbBranchTarget() const {
918  if (!isImm()) return false;
919 
920  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
921  return CE->getValue() % 2 == 0;
922  return true;
923  }
924 
925  // checks whether this operand is an unsigned offset which fits is a field
926  // of specified width and scaled by a specific number of bits
927  template<unsigned width, unsigned scale>
928  bool isUnsignedOffset() const {
929  if (!isImm()) return false;
930  if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
931  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
932  int64_t Val = CE->getValue();
933  int64_t Align = 1LL << scale;
934  int64_t Max = Align * ((1LL << width) - 1);
935  return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
936  }
937  return false;
938  }
939 
940  // checks whether this operand is an signed offset which fits is a field
941  // of specified width and scaled by a specific number of bits
942  template<unsigned width, unsigned scale>
943  bool isSignedOffset() const {
944  if (!isImm()) return false;
945  if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
946  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
947  int64_t Val = CE->getValue();
948  int64_t Align = 1LL << scale;
949  int64_t Max = Align * ((1LL << (width-1)) - 1);
950  int64_t Min = -Align * (1LL << (width-1));
951  return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
952  }
953  return false;
954  }
955 
956  // checks whether this operand is a memory operand computed as an offset
957  // applied to PC. the offset may have 8 bits of magnitude and is represented
958  // with two bits of shift. textually it may be either [pc, #imm], #imm or
959  // relocable expression...
960  bool isThumbMemPC() const {
961  int64_t Val = 0;
962  if (isImm()) {
963  if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
964  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
965  if (!CE) return false;
966  Val = CE->getValue();
967  }
968  else if (isMem()) {
969  if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
970  if(Memory.BaseRegNum != ARM::PC) return false;
971  Val = Memory.OffsetImm->getValue();
972  }
973  else return false;
974  return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
975  }
976 
977  bool isFPImm() const {
978  if (!isImm()) return false;
979  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
980  if (!CE) return false;
981  int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
982  return Val != -1;
983  }
984 
985  template<int64_t N, int64_t M>
986  bool isImmediate() const {
987  if (!isImm()) return false;
988  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
989  if (!CE) return false;
990  int64_t Value = CE->getValue();
991  return Value >= N && Value <= M;
992  }
993 
994  template<int64_t N, int64_t M>
995  bool isImmediateS4() const {
996  if (!isImm()) return false;
997  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
998  if (!CE) return false;
999  int64_t Value = CE->getValue();
1000  return ((Value & 3) == 0) && Value >= N && Value <= M;
1001  }
1002 
1003  bool isFBits16() const {
1004  return isImmediate<0, 17>();
1005  }
1006  bool isFBits32() const {
1007  return isImmediate<1, 33>();
1008  }
1009  bool isImm8s4() const {
1010  return isImmediateS4<-1020, 1020>();
1011  }
1012  bool isImm0_1020s4() const {
1013  return isImmediateS4<0, 1020>();
1014  }
1015  bool isImm0_508s4() const {
1016  return isImmediateS4<0, 508>();
1017  }
1018  bool isImm0_508s4Neg() const {
1019  if (!isImm()) return false;
1020  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1021  if (!CE) return false;
1022  int64_t Value = -CE->getValue();
1023  // explicitly exclude zero. we want that to use the normal 0_508 version.
1024  return ((Value & 3) == 0) && Value > 0 && Value <= 508;
1025  }
1026 
1027  bool isImm0_4095Neg() const {
1028  if (!isImm()) return false;
1029  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1030  if (!CE) return false;
1031  int64_t Value = -CE->getValue();
1032  return Value > 0 && Value < 4096;
1033  }
1034 
1035  bool isImm0_7() const {
1036  return isImmediate<0, 7>();
1037  }
1038 
1039  bool isImm1_16() const {
1040  return isImmediate<1, 16>();
1041  }
1042 
1043  bool isImm1_32() const {
1044  return isImmediate<1, 32>();
1045  }
1046 
1047  bool isImm8_255() const {
1048  return isImmediate<8, 255>();
1049  }
1050 
1051  bool isImm256_65535Expr() const {
1052  if (!isImm()) return false;
1053  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1054  // If it's not a constant expression, it'll generate a fixup and be
1055  // handled later.
1056  if (!CE) return true;
1057  int64_t Value = CE->getValue();
1058  return Value >= 256 && Value < 65536;
1059  }
1060 
1061  bool isImm0_65535Expr() const {
1062  if (!isImm()) return false;
1063  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1064  // If it's not a constant expression, it'll generate a fixup and be
1065  // handled later.
1066  if (!CE) return true;
1067  int64_t Value = CE->getValue();
1068  return Value >= 0 && Value < 65536;
1069  }
1070 
1071  bool isImm24bit() const {
1072  return isImmediate<0, 0xffffff + 1>();
1073  }
1074 
1075  bool isImmThumbSR() const {
1076  return isImmediate<1, 33>();
1077  }
1078 
1079  bool isPKHLSLImm() const {
1080  return isImmediate<0, 32>();
1081  }
1082 
1083  bool isPKHASRImm() const {
1084  return isImmediate<0, 33>();
1085  }
1086 
1087  bool isAdrLabel() const {
1088  // If we have an immediate that's not a constant, treat it as a label
1089  // reference needing a fixup.
1090  if (isImm() && !isa<MCConstantExpr>(getImm()))
1091  return true;
1092 
1093  // If it is a constant, it must fit into a modified immediate encoding.
1094  if (!isImm()) return false;
1095  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1096  if (!CE) return false;
1097  int64_t Value = CE->getValue();
1098  return (ARM_AM::getSOImmVal(Value) != -1 ||
1099  ARM_AM::getSOImmVal(-Value) != -1);
1100  }
1101 
1102  bool isT2SOImm() const {
1103  // If we have an immediate that's not a constant, treat it as an expression
1104  // needing a fixup.
1105  if (isImm() && !isa<MCConstantExpr>(getImm())) {
1106  // We want to avoid matching :upper16: and :lower16: as we want these
1107  // expressions to match in isImm0_65535Expr()
1108  const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm());
1109  return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
1110  ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16));
1111  }
1112  if (!isImm()) return false;
1113  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1114  if (!CE) return false;
1115  int64_t Value = CE->getValue();
1116  return ARM_AM::getT2SOImmVal(Value) != -1;
1117  }
1118 
1119  bool isT2SOImmNot() const {
1120  if (!isImm()) return false;
1121  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1122  if (!CE) return false;
1123  int64_t Value = CE->getValue();
1124  return ARM_AM::getT2SOImmVal(Value) == -1 &&
1125  ARM_AM::getT2SOImmVal(~Value) != -1;
1126  }
1127 
1128  bool isT2SOImmNeg() const {
1129  if (!isImm()) return false;
1130  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1131  if (!CE) return false;
1132  int64_t Value = CE->getValue();
1133  // Only use this when not representable as a plain so_imm.
1134  return ARM_AM::getT2SOImmVal(Value) == -1 &&
1135  ARM_AM::getT2SOImmVal(-Value) != -1;
1136  }
1137 
1138  bool isSetEndImm() const {
1139  if (!isImm()) return false;
1140  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1141  if (!CE) return false;
1142  int64_t Value = CE->getValue();
1143  return Value == 1 || Value == 0;
1144  }
1145 
1146  bool isReg() const override { return Kind == k_Register; }
1147  bool isRegList() const { return Kind == k_RegisterList; }
1148  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1149  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1150  bool isToken() const override { return Kind == k_Token; }
1151  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1152  bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1153  bool isMem() const override {
1154  if (Kind != k_Memory)
1155  return false;
1156  if (Memory.BaseRegNum &&
1157  !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum))
1158  return false;
1159  if (Memory.OffsetRegNum &&
1160  !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum))
1161  return false;
1162  return true;
1163  }
1164  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1165  bool isRegShiftedReg() const {
1166  return Kind == k_ShiftedRegister &&
1167  ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1168  RegShiftedReg.SrcReg) &&
1169  ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1170  RegShiftedReg.ShiftReg);
1171  }
1172  bool isRegShiftedImm() const {
1173  return Kind == k_ShiftedImmediate &&
1174  ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1175  RegShiftedImm.SrcReg);
1176  }
1177  bool isRotImm() const { return Kind == k_RotateImmediate; }
1178  bool isModImm() const { return Kind == k_ModifiedImmediate; }
1179 
1180  bool isModImmNot() const {
1181  if (!isImm()) return false;
1182  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1183  if (!CE) return false;
1184  int64_t Value = CE->getValue();
1185  return ARM_AM::getSOImmVal(~Value) != -1;
1186  }
1187 
1188  bool isModImmNeg() const {
1189  if (!isImm()) return false;
1190  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1191  if (!CE) return false;
1192  int64_t Value = CE->getValue();
1193  return ARM_AM::getSOImmVal(Value) == -1 &&
1194  ARM_AM::getSOImmVal(-Value) != -1;
1195  }
1196 
1197  bool isThumbModImmNeg1_7() const {
1198  if (!isImm()) return false;
1199  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1200  if (!CE) return false;
1201  int32_t Value = -(int32_t)CE->getValue();
1202  return 0 < Value && Value < 8;
1203  }
1204 
1205  bool isThumbModImmNeg8_255() const {
1206  if (!isImm()) return false;
1207  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1208  if (!CE) return false;
1209  int32_t Value = -(int32_t)CE->getValue();
1210  return 7 < Value && Value < 256;
1211  }
1212 
1213  bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1214  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1215  bool isPostIdxRegShifted() const {
1216  return Kind == k_PostIndexRegister &&
1217  ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
1218  }
1219  bool isPostIdxReg() const {
1220  return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1221  }
1222  bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1223  if (!isMem())
1224  return false;
1225  // No offset of any kind.
1226  return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1227  (alignOK || Memory.Alignment == Alignment);
1228  }
1229  bool isMemPCRelImm12() const {
1230  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1231  return false;
1232  // Base register must be PC.
1233  if (Memory.BaseRegNum != ARM::PC)
1234  return false;
1235  // Immediate offset in range [-4095, 4095].
1236  if (!Memory.OffsetImm) return true;
1237  int64_t Val = Memory.OffsetImm->getValue();
1238  return (Val > -4096 && Val < 4096) ||
1239  (Val == std::numeric_limits<int32_t>::min());
1240  }
1241 
1242  bool isAlignedMemory() const {
1243  return isMemNoOffset(true);
1244  }
1245 
1246  bool isAlignedMemoryNone() const {
1247  return isMemNoOffset(false, 0);
1248  }
1249 
1250  bool isDupAlignedMemoryNone() const {
1251  return isMemNoOffset(false, 0);
1252  }
1253 
1254  bool isAlignedMemory16() const {
1255  if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1256  return true;
1257  return isMemNoOffset(false, 0);
1258  }
1259 
1260  bool isDupAlignedMemory16() const {
1261  if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1262  return true;
1263  return isMemNoOffset(false, 0);
1264  }
1265 
1266  bool isAlignedMemory32() const {
1267  if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1268  return true;
1269  return isMemNoOffset(false, 0);
1270  }
1271 
1272  bool isDupAlignedMemory32() const {
1273  if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1274  return true;
1275  return isMemNoOffset(false, 0);
1276  }
1277 
1278  bool isAlignedMemory64() const {
1279  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1280  return true;
1281  return isMemNoOffset(false, 0);
1282  }
1283 
1284  bool isDupAlignedMemory64() const {
1285  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1286  return true;
1287  return isMemNoOffset(false, 0);
1288  }
1289 
1290  bool isAlignedMemory64or128() const {
1291  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1292  return true;
1293  if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1294  return true;
1295  return isMemNoOffset(false, 0);
1296  }
1297 
1298  bool isDupAlignedMemory64or128() const {
1299  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1300  return true;
1301  if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1302  return true;
1303  return isMemNoOffset(false, 0);
1304  }
1305 
1306  bool isAlignedMemory64or128or256() const {
1307  if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1308  return true;
1309  if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1310  return true;
1311  if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1312  return true;
1313  return isMemNoOffset(false, 0);
1314  }
1315 
1316  bool isAddrMode2() const {
1317  if (!isMem() || Memory.Alignment != 0) return false;
1318  // Check for register offset.
1319  if (Memory.OffsetRegNum) return true;
1320  // Immediate offset in range [-4095, 4095].
1321  if (!Memory.OffsetImm) return true;
1322  int64_t Val = Memory.OffsetImm->getValue();
1323  return Val > -4096 && Val < 4096;
1324  }
1325 
1326  bool isAM2OffsetImm() const {
1327  if (!isImm()) return false;
1328  // Immediate offset in range [-4095, 4095].
1329  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1330  if (!CE) return false;
1331  int64_t Val = CE->getValue();
1332  return (Val == std::numeric_limits<int32_t>::min()) ||
1333  (Val > -4096 && Val < 4096);
1334  }
1335 
1336  bool isAddrMode3() const {
1337  // If we have an immediate that's not a constant, treat it as a label
1338  // reference needing a fixup. If it is a constant, it's something else
1339  // and we reject it.
1340  if (isImm() && !isa<MCConstantExpr>(getImm()))
1341  return true;
1342  if (!isMem() || Memory.Alignment != 0) return false;
1343  // No shifts are legal for AM3.
1344  if (Memory.ShiftType != ARM_AM::no_shift) return false;
1345  // Check for register offset.
1346  if (Memory.OffsetRegNum) return true;
1347  // Immediate offset in range [-255, 255].
1348  if (!Memory.OffsetImm) return true;
1349  int64_t Val = Memory.OffsetImm->getValue();
1350  // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and we
1351  // have to check for this too.
1352  return (Val > -256 && Val < 256) ||
1353  Val == std::numeric_limits<int32_t>::min();
1354  }
1355 
1356  bool isAM3Offset() const {
1357  if (isPostIdxReg())
1358  return true;
1359  if (!isImm())
1360  return false;
1361  // Immediate offset in range [-255, 255].
1362  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1363  if (!CE) return false;
1364  int64_t Val = CE->getValue();
1365  // Special case, #-0 is std::numeric_limits<int32_t>::min().
1366  return (Val > -256 && Val < 256) ||
1367  Val == std::numeric_limits<int32_t>::min();
1368  }
1369 
1370  bool isAddrMode5() const {
1371  // If we have an immediate that's not a constant, treat it as a label
1372  // reference needing a fixup. If it is a constant, it's something else
1373  // and we reject it.
1374  if (isImm() && !isa<MCConstantExpr>(getImm()))
1375  return true;
1376  if (!isMem() || Memory.Alignment != 0) return false;
1377  // Check for register offset.
1378  if (Memory.OffsetRegNum) return false;
1379  // Immediate offset in range [-1020, 1020] and a multiple of 4.
1380  if (!Memory.OffsetImm) return true;
1381  int64_t Val = Memory.OffsetImm->getValue();
1382  return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1383  Val == std::numeric_limits<int32_t>::min();
1384  }
1385 
1386  bool isAddrMode5FP16() const {
1387  // If we have an immediate that's not a constant, treat it as a label
1388  // reference needing a fixup. If it is a constant, it's something else
1389  // and we reject it.
1390  if (isImm() && !isa<MCConstantExpr>(getImm()))
1391  return true;
1392  if (!isMem() || Memory.Alignment != 0) return false;
1393  // Check for register offset.
1394  if (Memory.OffsetRegNum) return false;
1395  // Immediate offset in range [-510, 510] and a multiple of 2.
1396  if (!Memory.OffsetImm) return true;
1397  int64_t Val = Memory.OffsetImm->getValue();
1398  return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
1399  Val == std::numeric_limits<int32_t>::min();
1400  }
1401 
1402  bool isMemTBB() const {
1403  if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1404  Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1405  return false;
1406  return true;
1407  }
1408 
1409  bool isMemTBH() const {
1410  if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1411  Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1412  Memory.Alignment != 0 )
1413  return false;
1414  return true;
1415  }
1416 
1417  bool isMemRegOffset() const {
1418  if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1419  return false;
1420  return true;
1421  }
1422 
1423  bool isT2MemRegOffset() const {
1424  if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1425  Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1426  return false;
1427  // Only lsl #{0, 1, 2, 3} allowed.
1428  if (Memory.ShiftType == ARM_AM::no_shift)
1429  return true;
1430  if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1431  return false;
1432  return true;
1433  }
1434 
1435  bool isMemThumbRR() const {
1436  // Thumb reg+reg addressing is simple. Just two registers, a base and
1437  // an offset. No shifts, negations or any other complicating factors.
1438  if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1439  Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1440  return false;
1441  return isARMLowRegister(Memory.BaseRegNum) &&
1442  (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1443  }
1444 
1445  bool isMemThumbRIs4() const {
1446  if (!isMem() || Memory.OffsetRegNum != 0 ||
1447  !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1448  return false;
1449  // Immediate offset, multiple of 4 in range [0, 124].
1450  if (!Memory.OffsetImm) return true;
1451  int64_t Val = Memory.OffsetImm->getValue();
1452  return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1453  }
1454 
1455  bool isMemThumbRIs2() const {
1456  if (!isMem() || Memory.OffsetRegNum != 0 ||
1457  !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1458  return false;
1459  // Immediate offset, multiple of 4 in range [0, 62].
1460  if (!Memory.OffsetImm) return true;
1461  int64_t Val = Memory.OffsetImm->getValue();
1462  return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1463  }
1464 
1465  bool isMemThumbRIs1() const {
1466  if (!isMem() || Memory.OffsetRegNum != 0 ||
1467  !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1468  return false;
1469  // Immediate offset in range [0, 31].
1470  if (!Memory.OffsetImm) return true;
1471  int64_t Val = Memory.OffsetImm->getValue();
1472  return Val >= 0 && Val <= 31;
1473  }
1474 
1475  bool isMemThumbSPI() const {
1476  if (!isMem() || Memory.OffsetRegNum != 0 ||
1477  Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1478  return false;
1479  // Immediate offset, multiple of 4 in range [0, 1020].
1480  if (!Memory.OffsetImm) return true;
1481  int64_t Val = Memory.OffsetImm->getValue();
1482  return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1483  }
1484 
1485  bool isMemImm8s4Offset() const {
1486  // If we have an immediate that's not a constant, treat it as a label
1487  // reference needing a fixup. If it is a constant, it's something else
1488  // and we reject it.
1489  if (isImm() && !isa<MCConstantExpr>(getImm()))
1490  return true;
1491  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1492  return false;
1493  // Immediate offset a multiple of 4 in range [-1020, 1020].
1494  if (!Memory.OffsetImm) return true;
1495  int64_t Val = Memory.OffsetImm->getValue();
1496  // Special case, #-0 is std::numeric_limits<int32_t>::min().
1497  return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
1498  Val == std::numeric_limits<int32_t>::min();
1499  }
1500 
1501  bool isMemImm0_1020s4Offset() const {
1502  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1503  return false;
1504  // Immediate offset a multiple of 4 in range [0, 1020].
1505  if (!Memory.OffsetImm) return true;
1506  int64_t Val = Memory.OffsetImm->getValue();
1507  return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1508  }
1509 
1510  bool isMemImm8Offset() const {
1511  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1512  return false;
1513  // Base reg of PC isn't allowed for these encodings.
1514  if (Memory.BaseRegNum == ARM::PC) return false;
1515  // Immediate offset in range [-255, 255].
1516  if (!Memory.OffsetImm) return true;
1517  int64_t Val = Memory.OffsetImm->getValue();
1518  return (Val == std::numeric_limits<int32_t>::min()) ||
1519  (Val > -256 && Val < 256);
1520  }
1521 
1522  bool isMemPosImm8Offset() const {
1523  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1524  return false;
1525  // Immediate offset in range [0, 255].
1526  if (!Memory.OffsetImm) return true;
1527  int64_t Val = Memory.OffsetImm->getValue();
1528  return Val >= 0 && Val < 256;
1529  }
1530 
1531  bool isMemNegImm8Offset() const {
1532  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1533  return false;
1534  // Base reg of PC isn't allowed for these encodings.
1535  if (Memory.BaseRegNum == ARM::PC) return false;
1536  // Immediate offset in range [-255, -1].
1537  if (!Memory.OffsetImm) return false;
1538  int64_t Val = Memory.OffsetImm->getValue();
1539  return (Val == std::numeric_limits<int32_t>::min()) ||
1540  (Val > -256 && Val < 0);
1541  }
1542 
1543  bool isMemUImm12Offset() const {
1544  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1545  return false;
1546  // Immediate offset in range [0, 4095].
1547  if (!Memory.OffsetImm) return true;
1548  int64_t Val = Memory.OffsetImm->getValue();
1549  return (Val >= 0 && Val < 4096);
1550  }
1551 
1552  bool isMemImm12Offset() const {
1553  // If we have an immediate that's not a constant, treat it as a label
1554  // reference needing a fixup. If it is a constant, it's something else
1555  // and we reject it.
1556 
1557  if (isImm() && !isa<MCConstantExpr>(getImm()))
1558  return true;
1559 
1560  if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1561  return false;
1562  // Immediate offset in range [-4095, 4095].
1563  if (!Memory.OffsetImm) return true;
1564  int64_t Val = Memory.OffsetImm->getValue();
1565  return (Val > -4096 && Val < 4096) ||
1566  (Val == std::numeric_limits<int32_t>::min());
1567  }
1568 
1569  bool isConstPoolAsmImm() const {
1570  // Delay processing of Constant Pool Immediate, this will turn into
1571  // a constant. Match no other operand
1572  return (isConstantPoolImm());
1573  }
1574 
1575  bool isPostIdxImm8() const {
1576  if (!isImm()) return false;
1577  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1578  if (!CE) return false;
1579  int64_t Val = CE->getValue();
1580  return (Val > -256 && Val < 256) ||
1581  (Val == std::numeric_limits<int32_t>::min());
1582  }
1583 
1584  bool isPostIdxImm8s4() const {
1585  if (!isImm()) return false;
1586  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1587  if (!CE) return false;
1588  int64_t Val = CE->getValue();
1589  return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1590  (Val == std::numeric_limits<int32_t>::min());
1591  }
1592 
1593  bool isMSRMask() const { return Kind == k_MSRMask; }
1594  bool isBankedReg() const { return Kind == k_BankedReg; }
1595  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1596 
1597  // NEON operands.
1598  bool isSingleSpacedVectorList() const {
1599  return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1600  }
1601 
1602  bool isDoubleSpacedVectorList() const {
1603  return Kind == k_VectorList && VectorList.isDoubleSpaced;
1604  }
1605 
1606  bool isVecListOneD() const {
1607  if (!isSingleSpacedVectorList()) return false;
1608  return VectorList.Count == 1;
1609  }
1610 
1611  bool isVecListDPair() const {
1612  if (!isSingleSpacedVectorList()) return false;
1613  return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1614  .contains(VectorList.RegNum));
1615  }
1616 
1617  bool isVecListThreeD() const {
1618  if (!isSingleSpacedVectorList()) return false;
1619  return VectorList.Count == 3;
1620  }
1621 
1622  bool isVecListFourD() const {
1623  if (!isSingleSpacedVectorList()) return false;
1624  return VectorList.Count == 4;
1625  }
1626 
1627  bool isVecListDPairSpaced() const {
1628  if (Kind != k_VectorList) return false;
1629  if (isSingleSpacedVectorList()) return false;
1630  return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1631  .contains(VectorList.RegNum));
1632  }
1633 
1634  bool isVecListThreeQ() const {
1635  if (!isDoubleSpacedVectorList()) return false;
1636  return VectorList.Count == 3;
1637  }
1638 
1639  bool isVecListFourQ() const {
1640  if (!isDoubleSpacedVectorList()) return false;
1641  return VectorList.Count == 4;
1642  }
1643 
1644  bool isSingleSpacedVectorAllLanes() const {
1645  return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1646  }
1647 
1648  bool isDoubleSpacedVectorAllLanes() const {
1649  return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1650  }
1651 
1652  bool isVecListOneDAllLanes() const {
1653  if (!isSingleSpacedVectorAllLanes()) return false;
1654  return VectorList.Count == 1;
1655  }
1656 
1657  bool isVecListDPairAllLanes() const {
1658  if (!isSingleSpacedVectorAllLanes()) return false;
1659  return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1660  .contains(VectorList.RegNum));
1661  }
1662 
1663  bool isVecListDPairSpacedAllLanes() const {
1664  if (!isDoubleSpacedVectorAllLanes()) return false;
1665  return VectorList.Count == 2;
1666  }
1667 
1668  bool isVecListThreeDAllLanes() const {
1669  if (!isSingleSpacedVectorAllLanes()) return false;
1670  return VectorList.Count == 3;
1671  }
1672 
1673  bool isVecListThreeQAllLanes() const {
1674  if (!isDoubleSpacedVectorAllLanes()) return false;
1675  return VectorList.Count == 3;
1676  }
1677 
1678  bool isVecListFourDAllLanes() const {
1679  if (!isSingleSpacedVectorAllLanes()) return false;
1680  return VectorList.Count == 4;
1681  }
1682 
1683  bool isVecListFourQAllLanes() const {
1684  if (!isDoubleSpacedVectorAllLanes()) return false;
1685  return VectorList.Count == 4;
1686  }
1687 
1688  bool isSingleSpacedVectorIndexed() const {
1689  return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1690  }
1691 
1692  bool isDoubleSpacedVectorIndexed() const {
1693  return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1694  }
1695 
1696  bool isVecListOneDByteIndexed() const {
1697  if (!isSingleSpacedVectorIndexed()) return false;
1698  return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1699  }
1700 
1701  bool isVecListOneDHWordIndexed() const {
1702  if (!isSingleSpacedVectorIndexed()) return false;
1703  return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1704  }
1705 
1706  bool isVecListOneDWordIndexed() const {
1707  if (!isSingleSpacedVectorIndexed()) return false;
1708  return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1709  }
1710 
1711  bool isVecListTwoDByteIndexed() const {
1712  if (!isSingleSpacedVectorIndexed()) return false;
1713  return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1714  }
1715 
1716  bool isVecListTwoDHWordIndexed() const {
1717  if (!isSingleSpacedVectorIndexed()) return false;
1718  return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1719  }
1720 
1721  bool isVecListTwoQWordIndexed() const {
1722  if (!isDoubleSpacedVectorIndexed()) return false;
1723  return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1724  }
1725 
1726  bool isVecListTwoQHWordIndexed() const {
1727  if (!isDoubleSpacedVectorIndexed()) return false;
1728  return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1729  }
1730 
1731  bool isVecListTwoDWordIndexed() const {
1732  if (!isSingleSpacedVectorIndexed()) return false;
1733  return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1734  }
1735 
1736  bool isVecListThreeDByteIndexed() const {
1737  if (!isSingleSpacedVectorIndexed()) return false;
1738  return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1739  }
1740 
1741  bool isVecListThreeDHWordIndexed() const {
1742  if (!isSingleSpacedVectorIndexed()) return false;
1743  return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1744  }
1745 
1746  bool isVecListThreeQWordIndexed() const {
1747  if (!isDoubleSpacedVectorIndexed()) return false;
1748  return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1749  }
1750 
1751  bool isVecListThreeQHWordIndexed() const {
1752  if (!isDoubleSpacedVectorIndexed()) return false;
1753  return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1754  }
1755 
1756  bool isVecListThreeDWordIndexed() const {
1757  if (!isSingleSpacedVectorIndexed()) return false;
1758  return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1759  }
1760 
1761  bool isVecListFourDByteIndexed() const {
1762  if (!isSingleSpacedVectorIndexed()) return false;
1763  return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1764  }
1765 
1766  bool isVecListFourDHWordIndexed() const {
1767  if (!isSingleSpacedVectorIndexed()) return false;
1768  return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1769  }
1770 
1771  bool isVecListFourQWordIndexed() const {
1772  if (!isDoubleSpacedVectorIndexed()) return false;
1773  return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1774  }
1775 
1776  bool isVecListFourQHWordIndexed() const {
1777  if (!isDoubleSpacedVectorIndexed()) return false;
1778  return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1779  }
1780 
1781  bool isVecListFourDWordIndexed() const {
1782  if (!isSingleSpacedVectorIndexed()) return false;
1783  return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1784  }
1785 
1786  bool isVectorIndex8() const {
1787  if (Kind != k_VectorIndex) return false;
1788  return VectorIndex.Val < 8;
1789  }
1790 
1791  bool isVectorIndex16() const {
1792  if (Kind != k_VectorIndex) return false;
1793  return VectorIndex.Val < 4;
1794  }
1795 
1796  bool isVectorIndex32() const {
1797  if (Kind != k_VectorIndex) return false;
1798  return VectorIndex.Val < 2;
1799  }
1800  bool isVectorIndex64() const {
1801  if (Kind != k_VectorIndex) return false;
1802  return VectorIndex.Val < 1;
1803  }
1804 
1805  bool isNEONi8splat() const {
1806  if (!isImm()) return false;
1807  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1808  // Must be a constant.
1809  if (!CE) return false;
1810  int64_t Value = CE->getValue();
1811  // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1812  // value.
1813  return Value >= 0 && Value < 256;
1814  }
1815 
1816  bool isNEONi16splat() const {
1817  if (isNEONByteReplicate(2))
1818  return false; // Leave that for bytes replication and forbid by default.
1819  if (!isImm())
1820  return false;
1821  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1822  // Must be a constant.
1823  if (!CE) return false;
1824  unsigned Value = CE->getValue();
1825  return ARM_AM::isNEONi16splat(Value);
1826  }
1827 
1828  bool isNEONi16splatNot() const {
1829  if (!isImm())
1830  return false;
1831  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1832  // Must be a constant.
1833  if (!CE) return false;
1834  unsigned Value = CE->getValue();
1835  return ARM_AM::isNEONi16splat(~Value & 0xffff);
1836  }
1837 
1838  bool isNEONi32splat() const {
1839  if (isNEONByteReplicate(4))
1840  return false; // Leave that for bytes replication and forbid by default.
1841  if (!isImm())
1842  return false;
1843  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1844  // Must be a constant.
1845  if (!CE) return false;
1846  unsigned Value = CE->getValue();
1847  return ARM_AM::isNEONi32splat(Value);
1848  }
1849 
1850  bool isNEONi32splatNot() const {
1851  if (!isImm())
1852  return false;
1853  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1854  // Must be a constant.
1855  if (!CE) return false;
1856  unsigned Value = CE->getValue();
1857  return ARM_AM::isNEONi32splat(~Value);
1858  }
1859 
1860  bool isNEONByteReplicate(unsigned NumBytes) const {
1861  if (!isImm())
1862  return false;
1863  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1864  // Must be a constant.
1865  if (!CE)
1866  return false;
1867  int64_t Value = CE->getValue();
1868  if (!Value)
1869  return false; // Don't bother with zero.
1870 
1871  unsigned char B = Value & 0xff;
1872  for (unsigned i = 1; i < NumBytes; ++i) {
1873  Value >>= 8;
1874  if ((Value & 0xff) != B)
1875  return false;
1876  }
1877  return true;
1878  }
1879 
1880  bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1881  bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1882 
1883  bool isNEONi32vmov() const {
1884  if (isNEONByteReplicate(4))
1885  return false; // Let it to be classified as byte-replicate case.
1886  if (!isImm())
1887  return false;
1888  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1889  // Must be a constant.
1890  if (!CE)
1891  return false;
1892  int64_t Value = CE->getValue();
1893  // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1894  // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1895  // FIXME: This is probably wrong and a copy and paste from previous example
1896  return (Value >= 0 && Value < 256) ||
1897  (Value >= 0x0100 && Value <= 0xff00) ||
1898  (Value >= 0x010000 && Value <= 0xff0000) ||
1899  (Value >= 0x01000000 && Value <= 0xff000000) ||
1900  (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1901  (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1902  }
1903 
1904  bool isNEONi32vmovNeg() const {
1905  if (!isImm()) return false;
1906  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1907  // Must be a constant.
1908  if (!CE) return false;
1909  int64_t Value = ~CE->getValue();
1910  // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1911  // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1912  // FIXME: This is probably wrong and a copy and paste from previous example
1913  return (Value >= 0 && Value < 256) ||
1914  (Value >= 0x0100 && Value <= 0xff00) ||
1915  (Value >= 0x010000 && Value <= 0xff0000) ||
1916  (Value >= 0x01000000 && Value <= 0xff000000) ||
1917  (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1918  (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1919  }
1920 
1921  bool isNEONi64splat() const {
1922  if (!isImm()) return false;
1923  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1924  // Must be a constant.
1925  if (!CE) return false;
1926  uint64_t Value = CE->getValue();
1927  // i64 value with each byte being either 0 or 0xff.
1928  for (unsigned i = 0; i < 8; ++i, Value >>= 8)
1929  if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1930  return true;
1931  }
1932 
1933  template<int64_t Angle, int64_t Remainder>
1934  bool isComplexRotation() const {
1935  if (!isImm()) return false;
1936 
1937  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1938  if (!CE) return false;
1939  uint64_t Value = CE->getValue();
1940 
1941  return (Value % Angle == Remainder && Value <= 270);
1942  }
1943 
1944  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1945  // Add as immediates when possible. Null MCExpr = 0.
1946  if (!Expr)
1948  else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1949  Inst.addOperand(MCOperand::createImm(CE->getValue()));
1950  else
1951  Inst.addOperand(MCOperand::createExpr(Expr));
1952  }
1953 
1954  void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
1955  assert(N == 1 && "Invalid number of operands!");
1956  addExpr(Inst, getImm());
1957  }
1958 
1959  void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
1960  assert(N == 1 && "Invalid number of operands!");
1961  addExpr(Inst, getImm());
1962  }
1963 
1964  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1965  assert(N == 2 && "Invalid number of operands!");
1966  Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1967  unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1968  Inst.addOperand(MCOperand::createReg(RegNum));
1969  }
1970 
1971  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1972  assert(N == 1 && "Invalid number of operands!");
1973  Inst.addOperand(MCOperand::createImm(getCoproc()));
1974  }
1975 
1976  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1977  assert(N == 1 && "Invalid number of operands!");
1978  Inst.addOperand(MCOperand::createImm(getCoproc()));
1979  }
1980 
1981  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1982  assert(N == 1 && "Invalid number of operands!");
1983  Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
1984  }
1985 
1986  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1987  assert(N == 1 && "Invalid number of operands!");
1988  Inst.addOperand(MCOperand::createImm(ITMask.Mask));
1989  }
1990 
1991  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1992  assert(N == 1 && "Invalid number of operands!");
1993  Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1994  }
1995 
1996  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1997  assert(N == 1 && "Invalid number of operands!");
1999  }
2000 
2001  void addRegOperands(MCInst &Inst, unsigned N) const {
2002  assert(N == 1 && "Invalid number of operands!");
2004  }
2005 
2006  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
2007  assert(N == 3 && "Invalid number of operands!");
2008  assert(isRegShiftedReg() &&
2009  "addRegShiftedRegOperands() on non-RegShiftedReg!");
2010  Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
2011  Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
2013  ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2014  }
2015 
2016  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
2017  assert(N == 2 && "Invalid number of operands!");
2018  assert(isRegShiftedImm() &&
2019  "addRegShiftedImmOperands() on non-RegShiftedImm!");
2020  Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
2021  // Shift of #32 is encoded as 0 where permitted
2022  unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2024  ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2025  }
2026 
2027  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
2028  assert(N == 1 && "Invalid number of operands!");
2029  Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
2030  ShifterImm.Imm));
2031  }
2032 
2033  void addRegListOperands(MCInst &Inst, unsigned N) const {
2034  assert(N == 1 && "Invalid number of operands!");
2035  const SmallVectorImpl<unsigned> &RegList = getRegList();
2037  I = RegList.begin(), E = RegList.end(); I != E; ++I)
2039  }
2040 
2041  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2042  addRegListOperands(Inst, N);
2043  }
2044 
2045  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2046  addRegListOperands(Inst, N);
2047  }
2048 
2049  void addRotImmOperands(MCInst &Inst, unsigned N) const {
2050  assert(N == 1 && "Invalid number of operands!");
2051  // Encoded as val>>3. The printer handles display as 8, 16, 24.
2052  Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
2053  }
2054 
2055  void addModImmOperands(MCInst &Inst, unsigned N) const {
2056  assert(N == 1 && "Invalid number of operands!");
2057 
2058  // Support for fixups (MCFixup)
2059  if (isImm())
2060  return addImmOperands(Inst, N);
2061 
2062  Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
2063  }
2064 
2065  void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2066  assert(N == 1 && "Invalid number of operands!");
2067  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2068  uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2069  Inst.addOperand(MCOperand::createImm(Enc));
2070  }
2071 
2072  void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2073  assert(N == 1 && "Invalid number of operands!");
2074  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2075  uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2076  Inst.addOperand(MCOperand::createImm(Enc));
2077  }
2078 
2079  void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
2080  assert(N == 1 && "Invalid number of operands!");
2081  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2082  uint32_t Val = -CE->getValue();
2083  Inst.addOperand(MCOperand::createImm(Val));
2084  }
2085 
2086  void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
2087  assert(N == 1 && "Invalid number of operands!");
2088  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2089  uint32_t Val = -CE->getValue();
2090  Inst.addOperand(MCOperand::createImm(Val));
2091  }
2092 
2093  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2094  assert(N == 1 && "Invalid number of operands!");
2095  // Munge the lsb/width into a bitfield mask.
2096  unsigned lsb = Bitfield.LSB;
2097  unsigned width = Bitfield.Width;
2098  // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
2099  uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2100  (32 - (lsb + width)));
2101  Inst.addOperand(MCOperand::createImm(Mask));
2102  }
2103 
2104  void addImmOperands(MCInst &Inst, unsigned N) const {
2105  assert(N == 1 && "Invalid number of operands!");
2106  addExpr(Inst, getImm());
2107  }
2108 
2109  void addFBits16Operands(MCInst &Inst, unsigned N) const {
2110  assert(N == 1 && "Invalid number of operands!");
2111  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2112  Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
2113  }
2114 
2115  void addFBits32Operands(MCInst &Inst, unsigned N) const {
2116  assert(N == 1 && "Invalid number of operands!");
2117  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2118  Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
2119  }
2120 
2121  void addFPImmOperands(MCInst &Inst, unsigned N) const {
2122  assert(N == 1 && "Invalid number of operands!");
2123  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2124  int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2125  Inst.addOperand(MCOperand::createImm(Val));
2126  }
2127 
2128  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2129  assert(N == 1 && "Invalid number of operands!");
2130  // FIXME: We really want to scale the value here, but the LDRD/STRD
2131  // instruction don't encode operands that way yet.
2132  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2134  }
2135 
2136  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2137  assert(N == 1 && "Invalid number of operands!");
2138  // The immediate is scaled by four in the encoding and is stored
2139  // in the MCInst as such. Lop off the low two bits here.
2140  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2141  Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2142  }
2143 
2144  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2145  assert(N == 1 && "Invalid number of operands!");
2146  // The immediate is scaled by four in the encoding and is stored
2147  // in the MCInst as such. Lop off the low two bits here.
2148  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2149  Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
2150  }
2151 
2152  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2153  assert(N == 1 && "Invalid number of operands!");
2154  // The immediate is scaled by four in the encoding and is stored
2155  // in the MCInst as such. Lop off the low two bits here.
2156  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2157  Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2158  }
2159 
2160  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2161  assert(N == 1 && "Invalid number of operands!");
2162  // The constant encodes as the immediate-1, and we store in the instruction
2163  // the bits as encoded, so subtract off one here.
2164  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2165  Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2166  }
2167 
2168  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2169  assert(N == 1 && "Invalid number of operands!");
2170  // The constant encodes as the immediate-1, and we store in the instruction
2171  // the bits as encoded, so subtract off one here.
2172  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2173  Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2174  }
2175 
2176  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2177  assert(N == 1 && "Invalid number of operands!");
2178  // The constant encodes as the immediate, except for 32, which encodes as
2179  // zero.
2180  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2181  unsigned Imm = CE->getValue();
2182  Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2183  }
2184 
2185  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2186  assert(N == 1 && "Invalid number of operands!");
2187  // An ASR value of 32 encodes as 0, so that's how we want to add it to
2188  // the instruction as well.
2189  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2190  int Val = CE->getValue();
2191  Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2192  }
2193 
2194  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2195  assert(N == 1 && "Invalid number of operands!");
2196  // The operand is actually a t2_so_imm, but we have its bitwise
2197  // negation in the assembly source, so twiddle it here.
2198  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2200  }
2201 
2202  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2203  assert(N == 1 && "Invalid number of operands!");
2204  // The operand is actually a t2_so_imm, but we have its
2205  // negation in the assembly source, so twiddle it here.
2206  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2208  }
2209 
2210  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2211  assert(N == 1 && "Invalid number of operands!");
2212  // The operand is actually an imm0_4095, but we have its
2213  // negation in the assembly source, so twiddle it here.
2214  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2216  }
2217 
2218  void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2219  if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2220  Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2221  return;
2222  }
2223 
2224  const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2225  assert(SR && "Unknown value type!");
2227  }
2228 
2229  void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2230  assert(N == 1 && "Invalid number of operands!");
2231  if (isImm()) {
2232  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2233  if (CE) {
2235  return;
2236  }
2237 
2238  const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2239 
2240  assert(SR && "Unknown value type!");
2242  return;
2243  }
2244 
2245  assert(isMem() && "Unknown value type!");
2246  assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2247  Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
2248  }
2249 
2250  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2251  assert(N == 1 && "Invalid number of operands!");
2252  Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2253  }
2254 
2255  void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2256  assert(N == 1 && "Invalid number of operands!");
2257  Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2258  }
2259 
2260  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2261  assert(N == 1 && "Invalid number of operands!");
2262  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2263  }
2264 
2265  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2266  assert(N == 1 && "Invalid number of operands!");
2267  int32_t Imm = Memory.OffsetImm->getValue();
2268  Inst.addOperand(MCOperand::createImm(Imm));
2269  }
2270 
2271  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2272  assert(N == 1 && "Invalid number of operands!");
2273  assert(isImm() && "Not an immediate!");
2274 
2275  // If we have an immediate that's not a constant, treat it as a label
2276  // reference needing a fixup.
2277  if (!isa<MCConstantExpr>(getImm())) {
2278  Inst.addOperand(MCOperand::createExpr(getImm()));
2279  return;
2280  }
2281 
2282  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2283  int Val = CE->getValue();
2284  Inst.addOperand(MCOperand::createImm(Val));
2285  }
2286 
2287  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2288  assert(N == 2 && "Invalid number of operands!");
2289  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2290  Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2291  }
2292 
2293  void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2294  addAlignedMemoryOperands(Inst, N);
2295  }
2296 
2297  void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2298  addAlignedMemoryOperands(Inst, N);
2299  }
2300 
2301  void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2302  addAlignedMemoryOperands(Inst, N);
2303  }
2304 
2305  void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2306  addAlignedMemoryOperands(Inst, N);
2307  }
2308 
2309  void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2310  addAlignedMemoryOperands(Inst, N);
2311  }
2312 
2313  void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2314  addAlignedMemoryOperands(Inst, N);
2315  }
2316 
2317  void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2318  addAlignedMemoryOperands(Inst, N);
2319  }
2320 
2321  void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2322  addAlignedMemoryOperands(Inst, N);
2323  }
2324 
2325  void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2326  addAlignedMemoryOperands(Inst, N);
2327  }
2328 
2329  void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2330  addAlignedMemoryOperands(Inst, N);
2331  }
2332 
2333  void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2334  addAlignedMemoryOperands(Inst, N);
2335  }
2336 
2337  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2338  assert(N == 3 && "Invalid number of operands!");
2339  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2340  if (!Memory.OffsetRegNum) {
2341  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2342  // Special case for #-0
2343  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2344  if (Val < 0) Val = -Val;
2345  Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2346  } else {
2347  // For register offset, we encode the shift type and negation flag
2348  // here.
2349  Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2350  Memory.ShiftImm, Memory.ShiftType);
2351  }
2352  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2353  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2354  Inst.addOperand(MCOperand::createImm(Val));
2355  }
2356 
2357  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2358  assert(N == 2 && "Invalid number of operands!");
2359  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2360  assert(CE && "non-constant AM2OffsetImm operand!");
2361  int32_t Val = CE->getValue();
2362  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2363  // Special case for #-0
2364  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2365  if (Val < 0) Val = -Val;
2366  Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2368  Inst.addOperand(MCOperand::createImm(Val));
2369  }
2370 
2371  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2372  assert(N == 3 && "Invalid number of operands!");
2373  // If we have an immediate that's not a constant, treat it as a label
2374  // reference needing a fixup. If it is a constant, it's something else
2375  // and we reject it.
2376  if (isImm()) {
2377  Inst.addOperand(MCOperand::createExpr(getImm()));
2380  return;
2381  }
2382 
2383  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2384  if (!Memory.OffsetRegNum) {
2385  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2386  // Special case for #-0
2387  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2388  if (Val < 0) Val = -Val;
2389  Val = ARM_AM::getAM3Opc(AddSub, Val);
2390  } else {
2391  // For register offset, we encode the shift type and negation flag
2392  // here.
2393  Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2394  }
2395  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2396  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2397  Inst.addOperand(MCOperand::createImm(Val));
2398  }
2399 
2400  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2401  assert(N == 2 && "Invalid number of operands!");
2402  if (Kind == k_PostIndexRegister) {
2403  int32_t Val =
2404  ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2405  Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2406  Inst.addOperand(MCOperand::createImm(Val));
2407  return;
2408  }
2409 
2410  // Constant offset.
2411  const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2412  int32_t Val = CE->getValue();
2413  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2414  // Special case for #-0
2415  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2416  if (Val < 0) Val = -Val;
2417  Val = ARM_AM::getAM3Opc(AddSub, Val);
2419  Inst.addOperand(MCOperand::createImm(Val));
2420  }
2421 
2422  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2423  assert(N == 2 && "Invalid number of operands!");
2424  // If we have an immediate that's not a constant, treat it as a label
2425  // reference needing a fixup. If it is a constant, it's something else
2426  // and we reject it.
2427  if (isImm()) {
2428  Inst.addOperand(MCOperand::createExpr(getImm()));
2430  return;
2431  }
2432 
2433  // The lower two bits are always zero and as such are not encoded.
2434  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2435  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2436  // Special case for #-0
2437  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2438  if (Val < 0) Val = -Val;
2439  Val = ARM_AM::getAM5Opc(AddSub, Val);
2440  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2441  Inst.addOperand(MCOperand::createImm(Val));
2442  }
2443 
2444  void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2445  assert(N == 2 && "Invalid number of operands!");
2446  // If we have an immediate that's not a constant, treat it as a label
2447  // reference needing a fixup. If it is a constant, it's something else
2448  // and we reject it.
2449  if (isImm()) {
2450  Inst.addOperand(MCOperand::createExpr(getImm()));
2452  return;
2453  }
2454 
2455  // The lower bit is always zero and as such is not encoded.
2456  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
2457  ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2458  // Special case for #-0
2459  if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2460  if (Val < 0) Val = -Val;
2461  Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
2462  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2463  Inst.addOperand(MCOperand::createImm(Val));
2464  }
2465 
2466  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2467  assert(N == 2 && "Invalid number of operands!");
2468  // If we have an immediate that's not a constant, treat it as a label
2469  // reference needing a fixup. If it is a constant, it's something else
2470  // and we reject it.
2471  if (isImm()) {
2472  Inst.addOperand(MCOperand::createExpr(getImm()));
2474  return;
2475  }
2476 
2477  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2478  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2479  Inst.addOperand(MCOperand::createImm(Val));
2480  }
2481 
2482  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2483  assert(N == 2 && "Invalid number of operands!");
2484  // The lower two bits are always zero and as such are not encoded.
2485  int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2486  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2487  Inst.addOperand(MCOperand::createImm(Val));
2488  }
2489 
2490  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2491  assert(N == 2 && "Invalid number of operands!");
2492  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2493  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2494  Inst.addOperand(MCOperand::createImm(Val));
2495  }
2496 
2497  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2498  addMemImm8OffsetOperands(Inst, N);
2499  }
2500 
2501  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2502  addMemImm8OffsetOperands(Inst, N);
2503  }
2504 
2505  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2506  assert(N == 2 && "Invalid number of operands!");
2507  // If this is an immediate, it's a label reference.
2508  if (isImm()) {
2509  addExpr(Inst, getImm());
2511  return;
2512  }
2513 
2514  // Otherwise, it's a normal memory reg+offset.
2515  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2516  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2517  Inst.addOperand(MCOperand::createImm(Val));
2518  }
2519 
2520  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2521  assert(N == 2 && "Invalid number of operands!");
2522  // If this is an immediate, it's a label reference.
2523  if (isImm()) {
2524  addExpr(Inst, getImm());
2526  return;
2527  }
2528 
2529  // Otherwise, it's a normal memory reg+offset.
2530  int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2531  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2532  Inst.addOperand(MCOperand::createImm(Val));
2533  }
2534 
2535  void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
2536  assert(N == 1 && "Invalid number of operands!");
2537  // This is container for the immediate that we will create the constant
2538  // pool from
2539  addExpr(Inst, getConstantPoolImm());
2540  return;
2541  }
2542 
2543  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2544  assert(N == 2 && "Invalid number of operands!");
2545  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2546  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2547  }
2548 
2549  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2550  assert(N == 2 && "Invalid number of operands!");
2551  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2552  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2553  }
2554 
2555  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2556  assert(N == 3 && "Invalid number of operands!");
2557  unsigned Val =
2559  Memory.ShiftImm, Memory.ShiftType);
2560  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2561  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2562  Inst.addOperand(MCOperand::createImm(Val));
2563  }
2564 
2565  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2566  assert(N == 3 && "Invalid number of operands!");
2567  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2568  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2569  Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
2570  }
2571 
2572  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2573  assert(N == 2 && "Invalid number of operands!");
2574  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2575  Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2576  }
2577 
2578  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2579  assert(N == 2 && "Invalid number of operands!");
2580  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2581  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2582  Inst.addOperand(MCOperand::createImm(Val));
2583  }
2584 
2585  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2586  assert(N == 2 && "Invalid number of operands!");
2587  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2588  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2589  Inst.addOperand(MCOperand::createImm(Val));
2590  }
2591 
2592  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2593  assert(N == 2 && "Invalid number of operands!");
2594  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2595  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2596  Inst.addOperand(MCOperand::createImm(Val));
2597  }
2598 
2599  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2600  assert(N == 2 && "Invalid number of operands!");
2601  int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2602  Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2603  Inst.addOperand(MCOperand::createImm(Val));
2604  }
2605 
2606  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2607  assert(N == 1 && "Invalid number of operands!");
2608  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2609  assert(CE && "non-constant post-idx-imm8 operand!");
2610  int Imm = CE->getValue();
2611  bool isAdd = Imm >= 0;
2612  if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
2613  Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2614  Inst.addOperand(MCOperand::createImm(Imm));
2615  }
2616 
2617  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2618  assert(N == 1 && "Invalid number of operands!");
2619  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2620  assert(CE && "non-constant post-idx-imm8s4 operand!");
2621  int Imm = CE->getValue();
2622  bool isAdd = Imm >= 0;
2623  if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
2624  // Immediate is scaled by 4.
2625  Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2626  Inst.addOperand(MCOperand::createImm(Imm));
2627  }
2628 
2629  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2630  assert(N == 2 && "Invalid number of operands!");
2631  Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2632  Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
2633  }
2634 
2635  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2636  assert(N == 2 && "Invalid number of operands!");
2637  Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2638  // The sign, shift type, and shift amount are encoded in a single operand
2639  // using the AM2 encoding helpers.
2640  ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2641  unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2642  PostIdxReg.ShiftTy);
2643  Inst.addOperand(MCOperand::createImm(Imm));
2644  }
2645 
2646  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2647  assert(N == 1 && "Invalid number of operands!");
2648  Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
2649  }
2650 
2651  void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2652  assert(N == 1 && "Invalid number of operands!");
2653  Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
2654  }
2655 
2656  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2657  assert(N == 1 && "Invalid number of operands!");
2658  Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
2659  }
2660 
2661  void addVecListOperands(MCInst &Inst, unsigned N) const {
2662  assert(N == 1 && "Invalid number of operands!");
2663  Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2664  }
2665 
2666  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2667  assert(N == 2 && "Invalid number of operands!");
2668  Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2669  Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
2670  }
2671 
2672  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2673  assert(N == 1 && "Invalid number of operands!");
2674  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2675  }
2676 
2677  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2678  assert(N == 1 && "Invalid number of operands!");
2679  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2680  }
2681 
2682  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2683  assert(N == 1 && "Invalid number of operands!");
2684  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2685  }
2686 
2687  void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
2688  assert(N == 1 && "Invalid number of operands!");
2689  Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2690  }
2691 
2692  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2693  assert(N == 1 && "Invalid number of operands!");
2694  // The immediate encodes the type of constant as well as the value.
2695  // Mask in that this is an i8 splat.
2696  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2697  Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
2698  }
2699 
2700  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2701  assert(N == 1 && "Invalid number of operands!");
2702  // The immediate encodes the type of constant as well as the value.
2703  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2704  unsigned Value = CE->getValue();
2705  Value = ARM_AM::encodeNEONi16splat(Value);
2706  Inst.addOperand(MCOperand::createImm(Value));
2707  }
2708 
2709  void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2710  assert(N == 1 && "Invalid number of operands!");
2711  // The immediate encodes the type of constant as well as the value.
2712  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2713  unsigned Value = CE->getValue();
2714  Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2715  Inst.addOperand(MCOperand::createImm(Value));
2716  }
2717 
2718  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2719  assert(N == 1 && "Invalid number of operands!");
2720  // The immediate encodes the type of constant as well as the value.
2721  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2722  unsigned Value = CE->getValue();
2723  Value = ARM_AM::encodeNEONi32splat(Value);
2724  Inst.addOperand(MCOperand::createImm(Value));
2725  }
2726 
2727  void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2728  assert(N == 1 && "Invalid number of operands!");
2729  // The immediate encodes the type of constant as well as the value.
2730  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2731  unsigned Value = CE->getValue();
2732  Value = ARM_AM::encodeNEONi32splat(~Value);
2733  Inst.addOperand(MCOperand::createImm(Value));
2734  }
2735 
2736  void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2737  assert(N == 1 && "Invalid number of operands!");
2738  // The immediate encodes the type of constant as well as the value.
2739  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2740  unsigned Value = CE->getValue();
2741  assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2742  Inst.getOpcode() == ARM::VMOVv16i8) &&
2743  "All vmvn instructions that wants to replicate non-zero byte "
2744  "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2745  unsigned B = ((~Value) & 0xff);
2746  B |= 0xe00; // cmode = 0b1110
2748  }
2749 
2750  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2751  assert(N == 1 && "Invalid number of operands!");
2752  // The immediate encodes the type of constant as well as the value.
2753  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2754  unsigned Value = CE->getValue();
2755  if (Value >= 256 && Value <= 0xffff)
2756  Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2757  else if (Value > 0xffff && Value <= 0xffffff)
2758  Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2759  else if (Value > 0xffffff)
2760  Value = (Value >> 24) | 0x600;
2761  Inst.addOperand(MCOperand::createImm(Value));
2762  }
2763 
2764  void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2765  assert(N == 1 && "Invalid number of operands!");
2766  // The immediate encodes the type of constant as well as the value.
2767  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2768  unsigned Value = CE->getValue();
2769  assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2770  Inst.getOpcode() == ARM::VMOVv16i8) &&
2771  "All instructions that wants to replicate non-zero byte "
2772  "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2773  unsigned B = Value & 0xff;
2774  B |= 0xe00; // cmode = 0b1110
2776  }
2777 
2778  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2779  assert(N == 1 && "Invalid number of operands!");
2780  // The immediate encodes the type of constant as well as the value.
2781  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2782  unsigned Value = ~CE->getValue();
2783  if (Value >= 256 && Value <= 0xffff)
2784  Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2785  else if (Value > 0xffff && Value <= 0xffffff)
2786  Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2787  else if (Value > 0xffffff)
2788  Value = (Value >> 24) | 0x600;
2789  Inst.addOperand(MCOperand::createImm(Value));
2790  }
2791 
2792  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2793  assert(N == 1 && "Invalid number of operands!");
2794  // The immediate encodes the type of constant as well as the value.
2795  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2796  uint64_t Value = CE->getValue();
2797  unsigned Imm = 0;
2798  for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2799  Imm |= (Value & 1) << i;
2800  }
2801  Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
2802  }
2803 
2804  void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
2805  assert(N == 1 && "Invalid number of operands!");
2806  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2807  Inst.addOperand(MCOperand::createImm(CE->getValue() / 90));
2808  }
2809 
2810  void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
2811  assert(N == 1 && "Invalid number of operands!");
2812  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2813  Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180));
2814  }
2815 
2816  void print(raw_ostream &OS) const override;
2817 
2818  static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2819  auto Op = make_unique<ARMOperand>(k_ITCondMask);
2820  Op->ITMask.Mask = Mask;
2821  Op->StartLoc = S;
2822  Op->EndLoc = S;
2823  return Op;
2824  }
2825 
2826  static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2827  SMLoc S) {
2828  auto Op = make_unique<ARMOperand>(k_CondCode);
2829  Op->CC.Val = CC;
2830  Op->StartLoc = S;
2831  Op->EndLoc = S;
2832  return Op;
2833  }
2834 
2835  static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2836  auto Op = make_unique<ARMOperand>(k_CoprocNum);
2837  Op->Cop.Val = CopVal;
2838  Op->StartLoc = S;
2839  Op->EndLoc = S;
2840  return Op;
2841  }
2842 
2843  static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2844  auto Op = make_unique<ARMOperand>(k_CoprocReg);
2845  Op->Cop.Val = CopVal;
2846  Op->StartLoc = S;
2847  Op->EndLoc = S;
2848  return Op;
2849  }
2850 
2851  static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2852  SMLoc E) {
2853  auto Op = make_unique<ARMOperand>(k_CoprocOption);
2854  Op->Cop.Val = Val;
2855  Op->StartLoc = S;
2856  Op->EndLoc = E;
2857  return Op;
2858  }
2859 
2860  static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2861  auto Op = make_unique<ARMOperand>(k_CCOut);
2862  Op->Reg.RegNum = RegNum;
2863  Op->StartLoc = S;
2864  Op->EndLoc = S;
2865  return Op;
2866  }
2867 
2868  static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2869  auto Op = make_unique<ARMOperand>(k_Token);
2870  Op->Tok.Data = Str.data();
2871  Op->Tok.Length = Str.size();
2872  Op->StartLoc = S;
2873  Op->EndLoc = S;
2874  return Op;
2875  }
2876 
2877  static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2878  SMLoc E) {
2879  auto Op = make_unique<ARMOperand>(k_Register);
2880  Op->Reg.RegNum = RegNum;
2881  Op->StartLoc = S;
2882  Op->EndLoc = E;
2883  return Op;
2884  }
2885 
2886  static std::unique_ptr<ARMOperand>
2887  CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2888  unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2889  SMLoc E) {
2890  auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2891  Op->RegShiftedReg.ShiftTy = ShTy;
2892  Op->RegShiftedReg.SrcReg = SrcReg;
2893  Op->RegShiftedReg.ShiftReg = ShiftReg;
2894  Op->RegShiftedReg.ShiftImm = ShiftImm;
2895  Op->StartLoc = S;
2896  Op->EndLoc = E;
2897  return Op;
2898  }
2899 
2900  static std::unique_ptr<ARMOperand>
2901  CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2902  unsigned ShiftImm, SMLoc S, SMLoc E) {
2903  auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2904  Op->RegShiftedImm.ShiftTy = ShTy;
2905  Op->RegShiftedImm.SrcReg = SrcReg;
2906  Op->RegShiftedImm.ShiftImm = ShiftImm;
2907  Op->StartLoc = S;
2908  Op->EndLoc = E;
2909  return Op;
2910  }
2911 
2912  static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2913  SMLoc S, SMLoc E) {
2914  auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2915  Op->ShifterImm.isASR = isASR;
2916  Op->ShifterImm.Imm = Imm;
2917  Op->StartLoc = S;
2918  Op->EndLoc = E;
2919  return Op;
2920  }
2921 
2922  static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2923  SMLoc E) {
2924  auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2925  Op->RotImm.Imm = Imm;
2926  Op->StartLoc = S;
2927  Op->EndLoc = E;
2928  return Op;
2929  }
2930 
2931  static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
2932  SMLoc S, SMLoc E) {
2933  auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
2934  Op->ModImm.Bits = Bits;
2935  Op->ModImm.Rot = Rot;
2936  Op->StartLoc = S;
2937  Op->EndLoc = E;
2938  return Op;
2939  }
2940 
2941  static std::unique_ptr<ARMOperand>
2942  CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2943  auto Op = make_unique<ARMOperand>(k_ConstantPoolImmediate);
2944  Op->Imm.Val = Val;
2945  Op->StartLoc = S;
2946  Op->EndLoc = E;
2947  return Op;
2948  }
2949 
2950  static std::unique_ptr<ARMOperand>
2951  CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2952  auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2953  Op->Bitfield.LSB = LSB;
2954  Op->Bitfield.Width = Width;
2955  Op->StartLoc = S;
2956  Op->EndLoc = E;
2957  return Op;
2958  }
2959 
2960  static std::unique_ptr<ARMOperand>
2961  CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2962  SMLoc StartLoc, SMLoc EndLoc) {
2963  assert(Regs.size() > 0 && "RegList contains no registers?");
2964  KindTy Kind = k_RegisterList;
2965 
2966  if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2967  Kind = k_DPRRegisterList;
2968  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2969  contains(Regs.front().second))
2970  Kind = k_SPRRegisterList;
2971 
2972  // Sort based on the register encoding values.
2973  array_pod_sort(Regs.begin(), Regs.end());
2974 
2975  auto Op = make_unique<ARMOperand>(Kind);
2976  for (SmallVectorImpl<std::pair<unsigned, unsigned>>::const_iterator
2977  I = Regs.begin(), E = Regs.end(); I != E; ++I)
2978  Op->Registers.push_back(I->second);
2979  Op->StartLoc = StartLoc;
2980  Op->EndLoc = EndLoc;
2981  return Op;
2982  }
2983 
2984  static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2985  unsigned Count,
2986  bool isDoubleSpaced,
2987  SMLoc S, SMLoc E) {
2988  auto Op = make_unique<ARMOperand>(k_VectorList);
2989  Op->VectorList.RegNum = RegNum;
2990  Op->VectorList.Count = Count;
2991  Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2992  Op->StartLoc = S;
2993  Op->EndLoc = E;
2994  return Op;
2995  }
2996 
2997  static std::unique_ptr<ARMOperand>
2998  CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2999  SMLoc S, SMLoc E) {
3000  auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
3001  Op->VectorList.RegNum = RegNum;
3002  Op->VectorList.Count = Count;
3003  Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3004  Op->StartLoc = S;
3005  Op->EndLoc = E;
3006  return Op;
3007  }
3008 
3009  static std::unique_ptr<ARMOperand>
3010  CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
3011  bool isDoubleSpaced, SMLoc S, SMLoc E) {
3012  auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
3013  Op->VectorList.RegNum = RegNum;
3014  Op->VectorList.Count = Count;
3015  Op->VectorList.LaneIndex = Index;
3016  Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3017  Op->StartLoc = S;
3018  Op->EndLoc = E;
3019  return Op;
3020  }
3021 
3022  static std::unique_ptr<ARMOperand>
3023  CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
3024  auto Op = make_unique<ARMOperand>(k_VectorIndex);
3025  Op->VectorIndex.Val = Idx;
3026  Op->StartLoc = S;
3027  Op->EndLoc = E;
3028  return Op;
3029  }
3030 
3031  static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
3032  SMLoc E) {
3033  auto Op = make_unique<ARMOperand>(k_Immediate);
3034  Op->Imm.Val = Val;
3035  Op->StartLoc = S;
3036  Op->EndLoc = E;
3037  return Op;
3038  }
3039 
3040  static std::unique_ptr<ARMOperand>
3041  CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
3042  unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
3043  unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
3044  SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
3045  auto Op = make_unique<ARMOperand>(k_Memory);
3046  Op->Memory.BaseRegNum = BaseRegNum;
3047  Op->Memory.OffsetImm = OffsetImm;
3048  Op->Memory.OffsetRegNum = OffsetRegNum;
3049  Op->Memory.ShiftType = ShiftType;
3050  Op->Memory.ShiftImm = ShiftImm;
3051  Op->Memory.Alignment = Alignment;
3052  Op->Memory.isNegative = isNegative;
3053  Op->StartLoc = S;
3054  Op->EndLoc = E;
3055  Op->AlignmentLoc = AlignmentLoc;
3056  return Op;
3057  }
3058 
3059  static std::unique_ptr<ARMOperand>
3060  CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3061  unsigned ShiftImm, SMLoc S, SMLoc E) {
3062  auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
3063  Op->PostIdxReg.RegNum = RegNum;
3064  Op->PostIdxReg.isAdd = isAdd;
3065  Op->PostIdxReg.ShiftTy = ShiftTy;
3066  Op->PostIdxReg.ShiftImm = ShiftImm;
3067  Op->StartLoc = S;
3068  Op->EndLoc = E;
3069  return Op;
3070  }
3071 
3072  static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
3073  SMLoc S) {
3074  auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
3075  Op->MBOpt.Val = Opt;
3076  Op->StartLoc = S;
3077  Op->EndLoc = S;
3078  return Op;
3079  }
3080 
3081  static std::unique_ptr<ARMOperand>
3082  CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
3083  auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
3084  Op->ISBOpt.Val = Opt;
3085  Op->StartLoc = S;
3086  Op->EndLoc = S;
3087  return Op;
3088  }
3089 
3090  static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
3091  SMLoc S) {
3092  auto Op = make_unique<ARMOperand>(k_ProcIFlags);
3093  Op->IFlags.Val = IFlags;
3094  Op->StartLoc = S;
3095  Op->EndLoc = S;
3096  return Op;
3097  }
3098 
3099  static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
3100  auto Op = make_unique<ARMOperand>(k_MSRMask);
3101  Op->MMask.Val = MMask;
3102  Op->StartLoc = S;
3103  Op->EndLoc = S;
3104  return Op;
3105  }
3106 
3107  static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
3108  auto Op = make_unique<ARMOperand>(k_BankedReg);
3109  Op->BankedReg.Val = Reg;
3110  Op->StartLoc = S;
3111  Op->EndLoc = S;
3112  return Op;
3113  }
3114 };
3115 
3116 } // end anonymous namespace.
3117 
3118 void ARMOperand::print(raw_ostream &OS) const {
3119  switch (Kind) {
3120  case k_CondCode:
3121  OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
3122  break;
3123  case k_CCOut:
3124  OS << "<ccout " << getReg() << ">";
3125  break;
3126  case k_ITCondMask: {
3127  static const char *const MaskStr[] = {
3128  "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
3129  "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
3130  };
3131  assert((ITMask.Mask & 0xf) == ITMask.Mask);
3132  OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
3133  break;
3134  }
3135  case k_CoprocNum:
3136  OS << "<coprocessor number: " << getCoproc() << ">";
3137  break;
3138  case k_CoprocReg:
3139  OS << "<coprocessor register: " << getCoproc() << ">";
3140  break;
3141  case k_CoprocOption:
3142  OS << "<coprocessor option: " << CoprocOption.Val << ">";
3143  break;
3144  case k_MSRMask:
3145  OS << "<mask: " << getMSRMask() << ">";
3146  break;
3147  case k_BankedReg:
3148  OS << "<banked reg: " << getBankedReg() << ">";
3149  break;
3150  case k_Immediate:
3151  OS << *getImm();
3152  break;
3153  case k_MemBarrierOpt:
3154  OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
3155  break;
3156  case k_InstSyncBarrierOpt:
3157  OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
3158  break;
3159  case k_Memory:
3160  OS << "<memory "
3161  << " base:" << Memory.BaseRegNum;
3162  OS << ">";
3163  break;
3164  case k_PostIndexRegister:
3165  OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
3166  << PostIdxReg.RegNum;
3167  if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3168  OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3169  << PostIdxReg.ShiftImm;
3170  OS << ">";
3171  break;
3172  case k_ProcIFlags: {
3173  OS << "<ARM_PROC::";
3174  unsigned IFlags = getProcIFlags();
3175  for (int i=2; i >= 0; --i)
3176  if (IFlags & (1 << i))
3177  OS << ARM_PROC::IFlagsToString(1 << i);
3178  OS << ">";
3179  break;
3180  }
3181  case k_Register:
3182  OS << "<register " << getReg() << ">";
3183  break;
3184  case k_ShifterImmediate:
3185  OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
3186  << " #" << ShifterImm.Imm << ">";
3187  break;
3188  case k_ShiftedRegister:
3189  OS << "<so_reg_reg "
3190  << RegShiftedReg.SrcReg << " "
3191  << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
3192  << " " << RegShiftedReg.ShiftReg << ">";
3193  break;
3194  case k_ShiftedImmediate:
3195  OS << "<so_reg_imm "
3196  << RegShiftedImm.SrcReg << " "
3197  << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
3198  << " #" << RegShiftedImm.ShiftImm << ">";
3199  break;
3200  case k_RotateImmediate:
3201  OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
3202  break;
3203  case k_ModifiedImmediate:
3204  OS << "<mod_imm #" << ModImm.Bits << ", #"
3205  << ModImm.Rot << ")>";
3206  break;
3207  case k_ConstantPoolImmediate:
3208  OS << "<constant_pool_imm #" << *getConstantPoolImm();
3209  break;
3210  case k_BitfieldDescriptor:
3211  OS << "<bitfield " << "lsb: " << Bitfield.LSB
3212  << ", width: " << Bitfield.Width << ">";
3213  break;
3214  case k_RegisterList:
3215  case k_DPRRegisterList:
3216  case k_SPRRegisterList: {
3217  OS << "<register_list ";
3218 
3219  const SmallVectorImpl<unsigned> &RegList = getRegList();
3221  I = RegList.begin(), E = RegList.end(); I != E; ) {
3222  OS << *I;
3223  if (++I < E) OS << ", ";
3224  }
3225 
3226  OS << ">";
3227  break;
3228  }
3229  case k_VectorList:
3230  OS << "<vector_list " << VectorList.Count << " * "
3231  << VectorList.RegNum << ">";
3232  break;
3233  case k_VectorListAllLanes:
3234  OS << "<vector_list(all lanes) " << VectorList.Count << " * "
3235  << VectorList.RegNum << ">";
3236  break;
3237  case k_VectorListIndexed:
3238  OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
3239  << VectorList.Count << " * " << VectorList.RegNum << ">";
3240  break;
3241  case k_Token:
3242  OS << "'" << getToken() << "'";
3243  break;
3244  case k_VectorIndex:
3245  OS << "<vectorindex " << getVectorIndex() << ">";
3246  break;
3247  }
3248 }
3249 
3250 /// @name Auto-generated Match Functions
3251 /// {
3252 
3253 static unsigned MatchRegisterName(StringRef Name);
3254 
3255 /// }
3256 
3257 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
3258  SMLoc &StartLoc, SMLoc &EndLoc) {
3259  const AsmToken &Tok = getParser().getTok();
3260  StartLoc = Tok.getLoc();
3261  EndLoc = Tok.getEndLoc();
3262  RegNo = tryParseRegister();
3263 
3264  return (RegNo == (unsigned)-1);
3265 }
3266 
3267 /// Try to parse a register name. The token must be an Identifier when called,
3268 /// and if it is a register name the token is eaten and the register number is
3269 /// returned. Otherwise return -1.
3270 int ARMAsmParser::tryParseRegister() {
3271  MCAsmParser &Parser = getParser();
3272  const AsmToken &Tok = Parser.getTok();
3273  if (Tok.isNot(AsmToken::Identifier)) return -1;
3274 
3275  std::string lowerCase = Tok.getString().lower();
3276  unsigned RegNum = MatchRegisterName(lowerCase);
3277  if (!RegNum) {
3278  RegNum = StringSwitch<unsigned>(lowerCase)
3279  .Case("r13", ARM::SP)
3280  .Case("r14", ARM::LR)
3281  .Case("r15", ARM::PC)
3282  .Case("ip", ARM::R12)
3283  // Additional register name aliases for 'gas' compatibility.
3284  .Case("a1", ARM::R0)
3285  .Case("a2", ARM::R1)
3286  .Case("a3", ARM::R2)
3287  .Case("a4", ARM::R3)
3288  .Case("v1", ARM::R4)
3289  .Case("v2", ARM::R5)
3290  .Case("v3", ARM::R6)
3291  .Case("v4", ARM::R7)
3292  .Case("v5", ARM::R8)
3293  .Case("v6", ARM::R9)
3294  .Case("v7", ARM::R10)
3295  .Case("v8", ARM::R11)
3296  .Case("sb", ARM::R9)
3297  .Case("sl", ARM::R10)
3298  .Case("fp", ARM::R11)
3299  .Default(0);
3300  }
3301  if (!RegNum) {
3302  // Check for aliases registered via .req. Canonicalize to lower case.
3303  // That's more consistent since register names are case insensitive, and
3304  // it's how the original entry was passed in from MC/MCParser/AsmParser.
3305  StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3306  // If no match, return failure.
3307  if (Entry == RegisterReqs.end())
3308  return -1;
3309  Parser.Lex(); // Eat identifier token.
3310  return Entry->getValue();
3311  }
3312 
3313  // Some FPUs only have 16 D registers, so D16-D31 are invalid
3314  if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3315  return -1;
3316 
3317  Parser.Lex(); // Eat identifier token.
3318 
3319  return RegNum;
3320 }
3321 
3322 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
3323 // If a recoverable error occurs, return 1. If an irrecoverable error
3324 // occurs, return -1. An irrecoverable error is one where tokens have been
3325 // consumed in the process of trying to parse the shifter (i.e., when it is
3326 // indeed a shifter operand, but malformed).
3327 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3328  MCAsmParser &Parser = getParser();
3329  SMLoc S = Parser.getTok().getLoc();
3330  const AsmToken &Tok = Parser.getTok();
3331  if (Tok.isNot(AsmToken::Identifier))
3332  return -1;
3333 
3334  std::string lowerCase = Tok.getString().lower();
3336  .Case("asl", ARM_AM::lsl)
3337  .Case("lsl", ARM_AM::lsl)
3338  .Case("lsr", ARM_AM::lsr)
3339  .Case("asr", ARM_AM::asr)
3340  .Case("ror", ARM_AM::ror)
3341  .Case("rrx", ARM_AM::rrx)
3343 
3344  if (ShiftTy == ARM_AM::no_shift)
3345  return 1;
3346 
3347  Parser.Lex(); // Eat the operator.
3348 
3349  // The source register for the shift has already been added to the
3350  // operand list, so we need to pop it off and combine it into the shifted
3351  // register operand instead.
3352  std::unique_ptr<ARMOperand> PrevOp(
3353  (ARMOperand *)Operands.pop_back_val().release());
3354  if (!PrevOp->isReg())
3355  return Error(PrevOp->getStartLoc(), "shift must be of a register");
3356  int SrcReg = PrevOp->getReg();
3357 
3358  SMLoc EndLoc;
3359  int64_t Imm = 0;
3360  int ShiftReg = 0;
3361  if (ShiftTy == ARM_AM::rrx) {
3362  // RRX Doesn't have an explicit shift amount. The encoder expects
3363  // the shift register to be the same as the source register. Seems odd,
3364  // but OK.
3365  ShiftReg = SrcReg;
3366  } else {
3367  // Figure out if this is shifted by a constant or a register (for non-RRX).
3368  if (Parser.getTok().is(AsmToken::Hash) ||
3369  Parser.getTok().is(AsmToken::Dollar)) {
3370  Parser.Lex(); // Eat hash.
3371  SMLoc ImmLoc = Parser.getTok().getLoc();
3372  const MCExpr *ShiftExpr = nullptr;
3373  if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3374  Error(ImmLoc, "invalid immediate shift value");
3375  return -1;
3376  }
3377  // The expression must be evaluatable as an immediate.
3378  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3379  if (!CE) {
3380  Error(ImmLoc, "invalid immediate shift value");
3381  return -1;
3382  }
3383  // Range check the immediate.
3384  // lsl, ror: 0 <= imm <= 31
3385  // lsr, asr: 0 <= imm <= 32
3386  Imm = CE->getValue();
3387  if (Imm < 0 ||
3388  ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3389  ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3390  Error(ImmLoc, "immediate shift value out of range");
3391  return -1;
3392  }
3393  // shift by zero is a nop. Always send it through as lsl.
3394  // ('as' compatibility)
3395  if (Imm == 0)
3396  ShiftTy = ARM_AM::lsl;
3397  } else if (Parser.getTok().is(AsmToken::Identifier)) {
3398  SMLoc L = Parser.getTok().getLoc();
3399  EndLoc = Parser.getTok().getEndLoc();
3400  ShiftReg = tryParseRegister();
3401  if (ShiftReg == -1) {
3402  Error(L, "expected immediate or register in shift operand");
3403  return -1;
3404  }
3405  } else {
3406  Error(Parser.getTok().getLoc(),
3407  "expected immediate or register in shift operand");
3408  return -1;
3409  }
3410  }
3411 
3412  if (ShiftReg && ShiftTy != ARM_AM::rrx)
3413  Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3414  ShiftReg, Imm,
3415  S, EndLoc));
3416  else
3417  Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3418  S, EndLoc));
3419 
3420  return 0;
3421 }
3422 
3423 /// Try to parse a register name. The token must be an Identifier when called.
3424 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3425 /// if there is a "writeback". 'true' if it's not a register.
3426 ///
3427 /// TODO this is likely to change to allow different register types and or to
3428 /// parse for a specific register type.
3429 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3430  MCAsmParser &Parser = getParser();
3431  SMLoc RegStartLoc = Parser.getTok().getLoc();
3432  SMLoc RegEndLoc = Parser.getTok().getEndLoc();
3433  int RegNo = tryParseRegister();
3434  if (RegNo == -1)
3435  return true;
3436 
3437  Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc));
3438 
3439  const AsmToken &ExclaimTok = Parser.getTok();
3440  if (ExclaimTok.is(AsmToken::Exclaim)) {
3441  Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3442  ExclaimTok.getLoc()));
3443  Parser.Lex(); // Eat exclaim token
3444  return false;
3445  }
3446 
3447  // Also check for an index operand. This is only legal for vector registers,
3448  // but that'll get caught OK in operand matching, so we don't need to
3449  // explicitly filter everything else out here.
3450  if (Parser.getTok().is(AsmToken::LBrac)) {
3451  SMLoc SIdx = Parser.getTok().getLoc();
3452  Parser.Lex(); // Eat left bracket token.
3453 
3454  const MCExpr *ImmVal;
3455  if (getParser().parseExpression(ImmVal))
3456  return true;
3457  const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3458  if (!MCE)
3459  return TokError("immediate value expected for vector index");
3460 
3461  if (Parser.getTok().isNot(AsmToken::RBrac))
3462  return Error(Parser.getTok().getLoc(), "']' expected");
3463 
3464  SMLoc E = Parser.getTok().getEndLoc();
3465  Parser.Lex(); // Eat right bracket token.
3466 
3467  Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3468  SIdx, E,
3469  getContext()));
3470  }
3471 
3472  return false;
3473 }
3474 
3475 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3476 /// instruction with a symbolic operand name.
3477 /// We accept "crN" syntax for GAS compatibility.
3478 /// <operand-name> ::= <prefix><number>
3479 /// If CoprocOp is 'c', then:
3480 /// <prefix> ::= c | cr
3481 /// If CoprocOp is 'p', then :
3482 /// <prefix> ::= p
3483 /// <number> ::= integer in range [0, 15]
3484 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3485  // Use the same layout as the tablegen'erated register name matcher. Ugly,
3486  // but efficient.
3487  if (Name.size() < 2 || Name[0] != CoprocOp)
3488  return -1;
3489  Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3490 
3491  switch (Name.size()) {
3492  default: return -1;
3493  case 1:
3494  switch (Name[0]) {
3495  default: return -1;
3496  case '0': return 0;
3497  case '1': return 1;
3498  case '2': return 2;
3499  case '3': return 3;
3500  case '4': return 4;
3501  case '5': return 5;
3502  case '6': return 6;
3503  case '7': return 7;
3504  case '8': return 8;
3505  case '9': return 9;
3506  }
3507  case 2:
3508  if (Name[0] != '1')
3509  return -1;
3510  switch (Name[1]) {
3511  default: return -1;
3512  // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3513  // However, old cores (v5/v6) did use them in that way.
3514  case '0': return 10;
3515  case '1': return 11;
3516  case '2': return 12;
3517  case '3': return 13;
3518  case '4': return 14;
3519  case '5': return 15;
3520  }
3521  }
3522 }
3523 
3524 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3526 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3527  MCAsmParser &Parser = getParser();
3528  SMLoc S = Parser.getTok().getLoc();
3529  const AsmToken &Tok = Parser.getTok();
3530  if (!Tok.is(AsmToken::Identifier))
3531  return MatchOperand_NoMatch;
3532  unsigned CC = ARMCondCodeFromString(Tok.getString());
3533  if (CC == ~0U)
3534  return MatchOperand_NoMatch;
3535  Parser.Lex(); // Eat the token.
3536 
3537  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3538 
3539  return MatchOperand_Success;
3540 }
3541 
3542 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3543 /// token must be an Identifier when called, and if it is a coprocessor
3544 /// number, the token is eaten and the operand is added to the operand list.
3546 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3547  MCAsmParser &Parser = getParser();
3548  SMLoc S = Parser.getTok().getLoc();
3549  const AsmToken &Tok = Parser.getTok();
3550  if (Tok.isNot(AsmToken::Identifier))
3551  return MatchOperand_NoMatch;
3552 
3553  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3554  if (Num == -1)
3555  return MatchOperand_NoMatch;
3556  // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3557  if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3558  return MatchOperand_NoMatch;
3559 
3560  Parser.Lex(); // Eat identifier token.
3561  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3562  return MatchOperand_Success;
3563 }
3564 
3565 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3566 /// token must be an Identifier when called, and if it is a coprocessor
3567 /// number, the token is eaten and the operand is added to the operand list.
3569 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3570  MCAsmParser &Parser = getParser();
3571  SMLoc S = Parser.getTok().getLoc();
3572  const AsmToken &Tok = Parser.getTok();
3573  if (Tok.isNot(AsmToken::Identifier))
3574  return MatchOperand_NoMatch;
3575 
3576  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3577  if (Reg == -1)
3578  return MatchOperand_NoMatch;
3579 
3580  Parser.Lex(); // Eat identifier token.
3581  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3582  return MatchOperand_Success;
3583 }
3584 
3585 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3586 /// coproc_option : '{' imm0_255 '}'
3588 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3589  MCAsmParser &Parser = getParser();
3590  SMLoc S = Parser.getTok().getLoc();
3591 
3592  // If this isn't a '{', this isn't a coprocessor immediate operand.
3593  if (Parser.getTok().isNot(AsmToken::LCurly))
3594  return MatchOperand_NoMatch;
3595  Parser.Lex(); // Eat the '{'
3596 
3597  const MCExpr *Expr;
3598  SMLoc Loc = Parser.getTok().getLoc();
3599  if (getParser().parseExpression(Expr)) {
3600  Error(Loc, "illegal expression");
3601  return MatchOperand_ParseFail;
3602  }
3603  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3604  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3605  Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3606  return MatchOperand_ParseFail;
3607  }
3608  int Val = CE->getValue();
3609 
3610  // Check for and consume the closing '}'
3611  if (Parser.getTok().isNot(AsmToken::RCurly))
3612  return MatchOperand_ParseFail;
3613  SMLoc E = Parser.getTok().getEndLoc();
3614  Parser.Lex(); // Eat the '}'
3615 
3616  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3617  return MatchOperand_Success;
3618 }
3619 
3620 // For register list parsing, we need to map from raw GPR register numbering
3621 // to the enumeration values. The enumeration values aren't sorted by
3622 // register number due to our using "sp", "lr" and "pc" as canonical names.
3623 static unsigned getNextRegister(unsigned Reg) {
3624  // If this is a GPR, we need to do it manually, otherwise we can rely
3625  // on the sort ordering of the enumeration since the other reg-classes
3626  // are sane.
3627  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3628  return Reg + 1;
3629  switch(Reg) {
3630  default: llvm_unreachable("Invalid GPR number!");
3631  case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3632  case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3633  case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3634  case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3635  case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3636  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3637  case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3638  case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3639  }
3640 }
3641 
3642 /// Parse a register list.
3643 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3644  MCAsmParser &Parser = getParser();
3645  if (Parser.getTok().isNot(AsmToken::LCurly))
3646  return TokError("Token is not a Left Curly Brace");
3647  SMLoc S = Parser.getTok().getLoc();
3648  Parser.Lex(); // Eat '{' token.
3649  SMLoc RegLoc = Parser.getTok().getLoc();
3650 
3651  // Check the first register in the list to see what register class
3652  // this is a list of.
3653  int Reg = tryParseRegister();
3654  if (Reg == -1)
3655  return Error(RegLoc, "register expected");
3656 
3657  // The reglist instructions have at most 16 registers, so reserve
3658  // space for that many.
3659  int EReg = 0;
3661 
3662  // Allow Q regs and just interpret them as the two D sub-registers.
3663  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3664  Reg = getDRegFromQReg(Reg);
3665  EReg = MRI->getEncodingValue(Reg);
3666  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3667  ++Reg;
3668  }
3669  const MCRegisterClass *RC;
3670  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3671  RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3672  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3673  RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3674  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3675  RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3676  else
3677  return Error(RegLoc, "invalid register in register list");
3678 
3679  // Store the register.
3680  EReg = MRI->getEncodingValue(Reg);
3681  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3682 
3683  // This starts immediately after the first register token in the list,
3684  // so we can see either a comma or a minus (range separator) as a legal
3685  // next token.
3686  while (Parser.getTok().is(AsmToken::Comma) ||
3687  Parser.getTok().is(AsmToken::Minus)) {
3688  if (Parser.getTok().is(AsmToken::Minus)) {
3689  Parser.Lex(); // Eat the minus.
3690  SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3691  int EndReg = tryParseRegister();
3692  if (EndReg == -1)
3693  return Error(AfterMinusLoc, "register expected");
3694  // Allow Q regs and just interpret them as the two D sub-registers.
3695  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3696  EndReg = getDRegFromQReg(EndReg) + 1;
3697  // If the register is the same as the start reg, there's nothing
3698  // more to do.
3699  if (Reg == EndReg)
3700  continue;
3701  // The register must be in the same register class as the first.
3702  if (!RC->contains(EndReg))
3703  return Error(AfterMinusLoc, "invalid register in register list");
3704  // Ranges must go from low to high.
3705  if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3706  return Error(AfterMinusLoc, "bad range in register list");
3707 
3708  // Add all the registers in the range to the register list.
3709  while (Reg != EndReg) {
3710  Reg = getNextRegister(Reg);
3711  EReg = MRI->getEncodingValue(Reg);
3712  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3713  }
3714  continue;
3715  }
3716  Parser.Lex(); // Eat the comma.
3717  RegLoc = Parser.getTok().getLoc();
3718  int OldReg = Reg;
3719  const AsmToken RegTok = Parser.getTok();
3720  Reg = tryParseRegister();
3721  if (Reg == -1)
3722  return Error(RegLoc, "register expected");
3723  // Allow Q regs and just interpret them as the two D sub-registers.
3724  bool isQReg = false;
3725  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3726  Reg = getDRegFromQReg(Reg);
3727  isQReg = true;
3728  }
3729  // The register must be in the same register class as the first.
3730  if (!RC->contains(Reg))
3731  return Error(RegLoc, "invalid register in register list");
3732  // List must be monotonically increasing.
3733  if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3734  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3735  Warning(RegLoc, "register list not in ascending order");
3736  else
3737  return Error(RegLoc, "register list not in ascending order");
3738  }
3739  if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3740  Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3741  ") in register list");
3742  continue;
3743  }
3744  // VFP register lists must also be contiguous.
3745  if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3746  Reg != OldReg + 1)
3747  return Error(RegLoc, "non-contiguous register range");
3748  EReg = MRI->getEncodingValue(Reg);
3749  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3750  if (isQReg) {
3751  EReg = MRI->getEncodingValue(++Reg);
3752  Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3753  }
3754  }
3755 
3756  if (Parser.getTok().isNot(AsmToken::RCurly))
3757  return Error(Parser.getTok().getLoc(), "'}' expected");
3758  SMLoc E = Parser.getTok().getEndLoc();
3759  Parser.Lex(); // Eat '}' token.
3760 
3761  // Push the register list operand.
3762  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3763 
3764  // The ARM system instruction variants for LDM/STM have a '^' token here.
3765  if (Parser.getTok().is(AsmToken::Caret)) {
3766  Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3767  Parser.Lex(); // Eat '^' token.
3768  }
3769 
3770  return false;
3771 }
3772 
3773 // Helper function to parse the lane index for vector lists.
3774 OperandMatchResultTy ARMAsmParser::
3775 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3776  MCAsmParser &Parser = getParser();
3777  Index = 0; // Always return a defined index value.
3778  if (Parser.getTok().is(AsmToken::LBrac)) {
3779  Parser.Lex(); // Eat the '['.
3780  if (Parser.getTok().is(AsmToken::RBrac)) {
3781  // "Dn[]" is the 'all lanes' syntax.
3782  LaneKind = AllLanes;
3783  EndLoc = Parser.getTok().getEndLoc();
3784  Parser.Lex(); // Eat the ']'.
3785  return MatchOperand_Success;
3786  }
3787 
3788  // There's an optional '#' token here. Normally there wouldn't be, but
3789  // inline assemble puts one in, and it's friendly to accept that.
3790  if (Parser.getTok().is(AsmToken::Hash))
3791  Parser.Lex(); // Eat '#' or '$'.
3792 
3793  const MCExpr *LaneIndex;
3794  SMLoc Loc = Parser.getTok().getLoc();
3795  if (getParser().parseExpression(LaneIndex)) {
3796  Error(Loc, "illegal expression");
3797  return MatchOperand_ParseFail;
3798  }
3799  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3800  if (!CE) {
3801  Error(Loc, "lane index must be empty or an integer");
3802  return MatchOperand_ParseFail;
3803  }
3804  if (Parser.getTok().isNot(AsmToken::RBrac)) {
3805  Error(Parser.getTok().getLoc(), "']' expected");
3806  return MatchOperand_ParseFail;
3807  }
3808  EndLoc = Parser.getTok().getEndLoc();
3809  Parser.Lex(); // Eat the ']'.
3810  int64_t Val = CE->getValue();
3811 
3812  // FIXME: Make this range check context sensitive for .8, .16, .32.
3813  if (Val < 0 || Val > 7) {
3814  Error(Parser.getTok().getLoc(), "lane index out of range");
3815  return MatchOperand_ParseFail;
3816  }
3817  Index = Val;
3818  LaneKind = IndexedLane;
3819  return MatchOperand_Success;
3820  }
3821  LaneKind = NoLanes;
3822  return MatchOperand_Success;
3823 }
3824 
3825 // parse a vector register list
3827 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3828  MCAsmParser &Parser = getParser();
3829  VectorLaneTy LaneKind;
3830  unsigned LaneIndex;
3831  SMLoc S = Parser.getTok().getLoc();
3832  // As an extension (to match gas), support a plain D register or Q register
3833  // (without encosing curly braces) as a single or double entry list,
3834  // respectively.
3835  if (Parser.getTok().is(AsmToken::Identifier)) {
3836  SMLoc E = Parser.getTok().getEndLoc();
3837  int Reg = tryParseRegister();
3838  if (Reg == -1)
3839  return MatchOperand_NoMatch;
3840  if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3841  OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3842  if (Res != MatchOperand_Success)
3843  return Res;
3844  switch (LaneKind) {
3845  case NoLanes:
3846  Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3847  break;
3848  case AllLanes:
3849  Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3850  S, E));
3851  break;
3852  case IndexedLane:
3853  Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3854  LaneIndex,
3855  false, S, E));
3856  break;
3857  }
3858  return MatchOperand_Success;
3859  }
3860  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3861  Reg = getDRegFromQReg(Reg);
3862  OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3863  if (Res != MatchOperand_Success)
3864  return Res;
3865  switch (LaneKind) {
3866  case NoLanes:
3867  Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3868  &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3869  Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3870  break;
3871  case AllLanes:
3872  Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3873  &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3874  Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3875  S, E));
3876  break;
3877  case IndexedLane:
3878  Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3879  LaneIndex,
3880  false, S, E));
3881  break;
3882  }
3883  return MatchOperand_Success;
3884  }
3885  Error(S, "vector register expected");
3886  return MatchOperand_ParseFail;
3887  }
3888 
3889  if (Parser.getTok().isNot(AsmToken::LCurly))
3890  return MatchOperand_NoMatch;
3891 
3892  Parser.Lex(); // Eat '{' token.
3893  SMLoc RegLoc = Parser.getTok().getLoc();
3894 
3895  int Reg = tryParseRegister();
3896  if (Reg == -1) {
3897  Error(RegLoc, "register expected");
3898  return MatchOperand_ParseFail;
3899  }
3900  unsigned Count = 1;
3901  int Spacing = 0;
3902  unsigned FirstReg = Reg;
3903  // The list is of D registers, but we also allow Q regs and just interpret
3904  // them as the two D sub-registers.
3905  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3906  FirstReg = Reg = getDRegFromQReg(Reg);
3907  Spacing = 1; // double-spacing requires explicit D registers, otherwise
3908  // it's ambiguous with four-register single spaced.
3909  ++Reg;
3910  ++Count;
3911  }
3912 
3913  SMLoc E;
3914  if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3915  return MatchOperand_ParseFail;
3916 
3917  while (Parser.getTok().is(AsmToken::Comma) ||
3918  Parser.getTok().is(AsmToken::Minus)) {
3919  if (Parser.getTok().is(AsmToken::Minus)) {
3920  if (!Spacing)
3921  Spacing = 1; // Register range implies a single spaced list.
3922  else if (Spacing == 2) {
3923  Error(Parser.getTok().getLoc(),
3924  "sequential registers in double spaced list");
3925  return MatchOperand_ParseFail;
3926  }
3927  Parser.Lex(); // Eat the minus.
3928  SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3929  int EndReg = tryParseRegister();
3930  if (EndReg == -1) {
3931  Error(AfterMinusLoc, "register expected");
3932  return MatchOperand_ParseFail;
3933  }
3934  // Allow Q regs and just interpret them as the two D sub-registers.
3935  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3936  EndReg = getDRegFromQReg(EndReg) + 1;
3937  // If the register is the same as the start reg, there's nothing
3938  // more to do.
3939  if (Reg == EndReg)
3940  continue;
3941  // The register must be in the same register class as the first.
3942  if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3943  Error(AfterMinusLoc, "invalid register in register list");
3944  return MatchOperand_ParseFail;
3945  }
3946  // Ranges must go from low to high.
3947  if (Reg > EndReg) {
3948  Error(AfterMinusLoc, "bad range in register list");
3949  return MatchOperand_ParseFail;
3950  }
3951  // Parse the lane specifier if present.
3952  VectorLaneTy NextLaneKind;
3953  unsigned NextLaneIndex;
3954  if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3956  return MatchOperand_ParseFail;
3957  if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3958  Error(AfterMinusLoc, "mismatched lane index in register list");
3959  return MatchOperand_ParseFail;
3960  }
3961 
3962  // Add all the registers in the range to the register list.
3963  Count += EndReg - Reg;
3964  Reg = EndReg;
3965  continue;
3966  }
3967  Parser.Lex(); // Eat the comma.
3968  RegLoc = Parser.getTok().getLoc();
3969  int OldReg = Reg;
3970  Reg = tryParseRegister();
3971  if (Reg == -1) {
3972  Error(RegLoc, "register expected");
3973  return MatchOperand_ParseFail;
3974  }
3975  // vector register lists must be contiguous.
3976  // It's OK to use the enumeration values directly here rather, as the
3977  // VFP register classes have the enum sorted properly.
3978  //
3979  // The list is of D registers, but we also allow Q regs and just interpret
3980  // them as the two D sub-registers.
3981  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3982  if (!Spacing)
3983  Spacing = 1; // Register range implies a single spaced list.
3984  else if (Spacing == 2) {
3985  Error(RegLoc,
3986  "invalid register in double-spaced list (must be 'D' register')");
3987  return MatchOperand_ParseFail;
3988  }
3989  Reg = getDRegFromQReg(Reg);
3990  if (Reg != OldReg + 1) {
3991  Error(RegLoc, "non-contiguous register range");
3992  return MatchOperand_ParseFail;
3993  }
3994  ++Reg;
3995  Count += 2;
3996  // Parse the lane specifier if present.
3997  VectorLaneTy NextLaneKind;
3998  unsigned NextLaneIndex;
3999  SMLoc LaneLoc = Parser.getTok().getLoc();
4000  if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4002  return MatchOperand_ParseFail;
4003  if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4004  Error(LaneLoc, "mismatched lane index in register list");
4005  return MatchOperand_ParseFail;
4006  }
4007  continue;
4008  }
4009  // Normal D register.
4010  // Figure out the register spacing (single or double) of the list if
4011  // we don't know it already.
4012  if (!Spacing)
4013  Spacing = 1 + (Reg == OldReg + 2);
4014 
4015  // Just check that it's contiguous and keep going.
4016  if (Reg != OldReg + Spacing) {
4017  Error(RegLoc, "non-contiguous register range");
4018  return MatchOperand_ParseFail;
4019  }
4020  ++Count;
4021  // Parse the lane specifier if present.
4022  VectorLaneTy NextLaneKind;
4023  unsigned NextLaneIndex;
4024  SMLoc EndLoc = Parser.getTok().getLoc();
4025  if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
4026  return MatchOperand_ParseFail;
4027  if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4028  Error(EndLoc, "mismatched lane index in register list");
4029  return MatchOperand_ParseFail;
4030  }
4031  }
4032 
4033  if (Parser.getTok().isNot(AsmToken::RCurly)) {
4034  Error(Parser.getTok().getLoc(), "'}' expected");
4035  return MatchOperand_ParseFail;
4036  }
4037  E = Parser.getTok().getEndLoc();
4038  Parser.Lex(); // Eat '}' token.
4039 
4040  switch (LaneKind) {
4041  case NoLanes:
4042  // Two-register operands have been converted to the
4043  // composite register classes.
4044  if (Count == 2) {
4045  const MCRegisterClass *RC = (Spacing == 1) ?
4046  &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4047  &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4048  FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4049  }
4050  Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
4051  (Spacing == 2), S, E));
4052  break;
4053  case AllLanes:
4054  // Two-register operands have been converted to the
4055  // composite register classes.
4056  if (Count == 2) {
4057  const MCRegisterClass *RC = (Spacing == 1) ?
4058  &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4059  &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4060  FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4061  }
4062  Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
4063  (Spacing == 2),
4064  S, E));
4065  break;
4066  case IndexedLane:
4067  Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
4068  LaneIndex,
4069  (Spacing == 2),
4070  S, E));
4071  break;
4072  }
4073  return MatchOperand_Success;
4074 }
4075 
4076 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
4078 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
4079  MCAsmParser &Parser = getParser();
4080  SMLoc S = Parser.getTok().getLoc();
4081  const AsmToken &Tok = Parser.getTok();
4082  unsigned Opt;
4083 
4084  if (Tok.is(AsmToken::Identifier)) {
4085  StringRef OptStr = Tok.getString();
4086 
4087  Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
4088  .Case("sy", ARM_MB::SY)
4089  .Case("st", ARM_MB::ST)
4090  .Case("ld", ARM_MB::LD)
4091  .Case("sh", ARM_MB::ISH)
4092  .Case("ish", ARM_MB::ISH)
4093  .Case("shst", ARM_MB::ISHST)
4094  .Case("ishst", ARM_MB::ISHST)
4095  .Case("ishld", ARM_MB::ISHLD)
4096  .Case("nsh", ARM_MB::NSH)
4097  .Case("un", ARM_MB::NSH)
4098  .Case("nshst", ARM_MB::NSHST)
4099  .Case("nshld", ARM_MB::NSHLD)
4100  .Case("unst", ARM_MB::NSHST)
4101  .Case("osh", ARM_MB::OSH)
4102  .Case("oshst", ARM_MB::OSHST)
4103  .Case("oshld", ARM_MB::OSHLD)
4104  .Default(~0U);
4105 
4106  // ishld, oshld, nshld and ld are only available from ARMv8.
4107  if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
4108  Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
4109  Opt = ~0U;
4110 
4111  if (Opt == ~0U)
4112  return MatchOperand_NoMatch;
4113 
4114  Parser.Lex(); // Eat identifier token.
4115  } else if (Tok.is(AsmToken::Hash) ||
4116  Tok.is(AsmToken::Dollar) ||
4117  Tok.is(AsmToken::Integer)) {
4118  if (Parser.getTok().isNot(AsmToken::Integer))
4119  Parser.Lex(); // Eat '#' or '$'.
4120  SMLoc Loc = Parser.getTok().getLoc();
4121 
4122  const MCExpr *MemBarrierID;
4123  if (getParser().parseExpression(MemBarrierID)) {
4124  Error(Loc, "illegal expression");
4125  return MatchOperand_ParseFail;
4126  }
4127 
4128  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
4129  if (!CE) {
4130  Error(Loc, "constant expression expected");
4131  return MatchOperand_ParseFail;
4132  }
4133 
4134  int Val = CE->getValue();
4135  if (Val & ~0xf) {
4136  Error(Loc, "immediate value out of range");
4137  return MatchOperand_ParseFail;
4138  }
4139 
4140  Opt = ARM_MB::RESERVED_0 + Val;
4141  } else
4142  return MatchOperand_ParseFail;
4143 
4144  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
4145  return MatchOperand_Success;
4146 }
4147 
4148 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
4150 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
4151  MCAsmParser &Parser = getParser();
4152  SMLoc S = Parser.getTok().getLoc();
4153  const AsmToken &Tok = Parser.getTok();
4154  unsigned Opt;
4155 
4156  if (Tok.is(AsmToken::Identifier)) {
4157  StringRef OptStr = Tok.getString();
4158 
4159  if (OptStr.equals_lower("sy"))
4160  Opt = ARM_ISB::SY;
4161  else
4162  return MatchOperand_NoMatch;
4163 
4164  Parser.Lex(); // Eat identifier token.
4165  } else if (Tok.is(AsmToken::Hash) ||
4166  Tok.is(AsmToken::Dollar) ||
4167  Tok.is(AsmToken::Integer)) {
4168  if (Parser.getTok().isNot(AsmToken::Integer))
4169  Parser.Lex(); // Eat '#' or '$'.
4170  SMLoc Loc = Parser.getTok().getLoc();
4171 
4172  const MCExpr *ISBarrierID;
4173  if (getParser().parseExpression(ISBarrierID)) {
4174  Error(Loc, "illegal expression");
4175  return MatchOperand_ParseFail;
4176  }
4177 
4178  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
4179  if (!CE) {
4180  Error(Loc, "constant expression expected");
4181  return MatchOperand_ParseFail;
4182  }
4183 
4184  int Val = CE->getValue();
4185  if (Val & ~0xf) {
4186  Error(Loc, "immediate value out of range");
4187  return MatchOperand_ParseFail;
4188  }
4189 
4190  Opt = ARM_ISB::RESERVED_0 + Val;
4191  } else
4192  return MatchOperand_ParseFail;
4193 
4194  Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
4195  (ARM_ISB::InstSyncBOpt)Opt, S));
4196  return MatchOperand_Success;
4197 }
4198 
4199 
4200 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
4202 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
4203  MCAsmParser &Parser = getParser();
4204  SMLoc S = Parser.getTok().getLoc();
4205  const AsmToken &Tok = Parser.getTok();
4206  if (!Tok.is(AsmToken::Identifier))
4207  return MatchOperand_NoMatch;
4208  StringRef IFlagsStr = Tok.getString();
4209 
4210  // An iflags string of "none" is interpreted to mean that none of the AIF
4211  // bits are set. Not a terribly useful instruction, but a valid encoding.
4212  unsigned IFlags = 0;
4213  if (IFlagsStr != "none") {
4214  for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
4215  unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1).lower())
4216  .Case("a", ARM_PROC::A)
4217  .Case("i", ARM_PROC::I)
4218  .Case("f", ARM_PROC::F)
4219  .Default(~0U);
4220 
4221  // If some specific iflag is already set, it means that some letter is
4222  // present more than once, this is not acceptable.
4223  if (Flag == ~0U || (IFlags & Flag))
4224  return MatchOperand_NoMatch;
4225 
4226  IFlags |= Flag;
4227  }
4228  }
4229 
4230  Parser.Lex(); // Eat identifier token.
4231  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
4232  return MatchOperand_Success;
4233 }
4234 
4235 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4237 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
4238  MCAsmParser &Parser = getParser();
4239  SMLoc S = Parser.getTok().getLoc();
4240  const AsmToken &Tok = Parser.getTok();
4241  if (!Tok.is(AsmToken::Identifier))
4242  return MatchOperand_NoMatch;
4243  StringRef Mask = Tok.getString();
4244 
4245  if (isMClass()) {
4246  auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
4247  if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
4248  return MatchOperand_NoMatch;
4249 
4250  unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
4251 
4252  Parser.Lex(); // Eat identifier token.
4253  Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4254  return MatchOperand_Success;
4255  }
4256 
4257  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4258  size_t Start = 0, Next = Mask.find('_');
4259  StringRef Flags = "";
4260  std::string SpecReg = Mask.slice(Start, Next).lower();
4261  if (Next != StringRef::npos)
4262  Flags = Mask.slice(Next+1, Mask.size());
4263 
4264  // FlagsVal contains the complete mask:
4265  // 3-0: Mask
4266  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4267  unsigned FlagsVal = 0;
4268 
4269  if (SpecReg == "apsr") {
4270  FlagsVal = StringSwitch<unsigned>(Flags)
4271  .Case("nzcvq", 0x8) // same as CPSR_f
4272  .Case("g", 0x4) // same as CPSR_s
4273  .Case("nzcvqg", 0xc) // same as CPSR_fs
4274  .Default(~0U);
4275 
4276  if (FlagsVal == ~0U) {
4277  if (!Flags.empty())
4278  return MatchOperand_NoMatch;
4279  else
4280  FlagsVal = 8; // No flag
4281  }
4282  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4283  // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4284  if (Flags == "all" || Flags == "")
4285  Flags = "fc";
4286  for (int i = 0, e = Flags.size(); i != e; ++i) {
4287  unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4288  .Case("c", 1)
4289  .Case("x", 2)
4290  .Case("s", 4)
4291  .Case("f", 8)
4292  .Default(~0U);
4293 
4294  // If some specific flag is already set, it means that some letter is
4295  // present more than once, this is not acceptable.
4296  if (Flag == ~0U || (FlagsVal & Flag))
4297  return MatchOperand_NoMatch;
4298  FlagsVal |= Flag;
4299  }
4300  } else // No match for special register.
4301  return MatchOperand_NoMatch;
4302 
4303  // Special register without flags is NOT equivalent to "fc" flags.
4304  // NOTE: This is a divergence from gas' behavior. Uncommenting the following
4305  // two lines would enable gas compatibility at the expense of breaking
4306  // round-tripping.
4307  //
4308  // if (!FlagsVal)
4309  // FlagsVal = 0x9;
4310 
4311  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4312  if (SpecReg == "spsr")
4313  FlagsVal |= 16;
4314 
4315  Parser.Lex(); // Eat identifier token.
4316  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4317  return MatchOperand_Success;
4318 }
4319 
4320 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4321 /// use in the MRS/MSR instructions added to support virtualization.
4323 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4324  MCAsmParser &Parser = getParser();
4325  SMLoc S = Parser.getTok().getLoc();
4326  const AsmToken &Tok = Parser.getTok();
4327  if (!Tok.is(AsmToken::Identifier))
4328  return MatchOperand_NoMatch;
4329  StringRef RegName = Tok.getString();
4330 
4331  auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower());
4332  if (!TheReg)
4333  return MatchOperand_NoMatch;
4334  unsigned Encoding = TheReg->Encoding;
4335 
4336  Parser.Lex(); // Eat identifier token.
4337  Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4338  return MatchOperand_Success;
4339 }
4340 
4342 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4343  int High) {
4344  MCAsmParser &Parser = getParser();
4345  const AsmToken &Tok = Parser.getTok();
4346  if (Tok.isNot(AsmToken::Identifier)) {
4347  Error(Parser.getTok().getLoc(), Op + " operand expected.");
4348  return MatchOperand_ParseFail;
4349  }
4350  StringRef ShiftName = Tok.getString();
4351  std::string LowerOp = Op.lower();
4352  std::string UpperOp = Op.upper();
4353  if (ShiftName != LowerOp && ShiftName != UpperOp) {
4354  Error(Parser.getTok().getLoc(), Op + " operand expected.");
4355  return MatchOperand_ParseFail;
4356  }
4357  Parser.Lex(); // Eat shift type token.
4358 
4359  // There must be a '#' and a shift amount.
4360  if (Parser.getTok().isNot(AsmToken::Hash) &&
4361  Parser.getTok().isNot(AsmToken::Dollar)) {
4362  Error(Parser.getTok().getLoc(), "'#' expected");
4363  return MatchOperand_ParseFail;
4364  }
4365  Parser.Lex(); // Eat hash token.
4366 
4367  const MCExpr *ShiftAmount;
4368  SMLoc Loc = Parser.getTok().getLoc();
4369  SMLoc EndLoc;
4370  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4371  Error(Loc, "illegal expression");
4372  return MatchOperand_ParseFail;
4373  }
4374  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4375  if (!CE) {
4376  Error(Loc, "constant expression expected");
4377  return MatchOperand_ParseFail;
4378  }
4379  int Val = CE->getValue();
4380  if (Val < Low || Val > High) {
4381  Error(Loc, "immediate value out of range");
4382  return MatchOperand_ParseFail;
4383  }
4384 
4385  Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4386 
4387  return MatchOperand_Success;
4388 }
4389 
4391 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4392  MCAsmParser &Parser = getParser();
4393  const AsmToken &Tok = Parser.getTok();
4394  SMLoc S = Tok.getLoc();
4395  if (Tok.isNot(AsmToken::Identifier)) {
4396  Error(S, "'be' or 'le' operand expected");
4397  return MatchOperand_ParseFail;
4398  }
4399  int Val = StringSwitch<int>(Tok.getString().lower())
4400  .Case("be", 1)
4401  .Case("le", 0)
4402  .Default(-1);
4403  Parser.Lex(); // Eat the token.
4404 
4405  if (Val == -1) {
4406  Error(S, "'be' or 'le' operand expected");
4407  return MatchOperand_ParseFail;
4408  }
4409  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
4410  getContext()),
4411  S, Tok.getEndLoc()));
4412  return MatchOperand_Success;
4413 }
4414 
4415 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4416 /// instructions. Legal values are:
4417 /// lsl #n 'n' in [0,31]
4418 /// asr #n 'n' in [1,32]
4419 /// n == 32 encoded as n == 0.
4421 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4422  MCAsmParser &Parser = getParser();
4423  const AsmToken &Tok = Parser.getTok();
4424  SMLoc S = Tok.getLoc();
4425  if (Tok.isNot(AsmToken::Identifier)) {
4426  Error(S, "shift operator 'asr' or 'lsl' expected");
4427  return MatchOperand_ParseFail;
4428  }
4429  StringRef ShiftName = Tok.getString();
4430  bool isASR;
4431  if (ShiftName == "lsl" || ShiftName == "LSL")
4432  isASR = false;
4433  else if (ShiftName == "asr" || ShiftName == "ASR")
4434  isASR = true;
4435  else {
4436  Error(S, "shift operator 'asr' or 'lsl' expected");
4437  return MatchOperand_ParseFail;
4438  }
4439  Parser.Lex(); // Eat the operator.
4440 
4441  // A '#' and a shift amount.
4442  if (Parser.getTok().isNot(AsmToken::Hash) &&
4443  Parser.getTok().isNot(AsmToken::Dollar)) {
4444  Error(Parser.getTok().getLoc(), "'#' expected");
4445  return MatchOperand_ParseFail;
4446  }
4447  Parser.Lex(); // Eat hash token.
4448  SMLoc ExLoc = Parser.getTok().getLoc();
4449 
4450  const MCExpr *ShiftAmount;
4451  SMLoc EndLoc;
4452  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4453  Error(ExLoc, "malformed shift expression");
4454  return MatchOperand_ParseFail;
4455  }
4456  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4457  if (!CE) {
4458  Error(ExLoc, "shift amount must be an immediate");
4459  return MatchOperand_ParseFail;
4460  }
4461 
4462  int64_t Val = CE->getValue();
4463  if (isASR) {
4464  // Shift amount must be in [1,32]
4465  if (Val < 1 || Val > 32) {
4466  Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4467  return MatchOperand_ParseFail;
4468  }
4469  // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4470  if (isThumb() && Val == 32) {
4471  Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4472  return MatchOperand_ParseFail;
4473  }
4474  if (Val == 32) Val = 0;
4475  } else {
4476  // Shift amount must be in [1,32]
4477  if (Val < 0 || Val > 31) {
4478  Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4479  return MatchOperand_ParseFail;
4480  }
4481  }
4482 
4483  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4484 
4485  return MatchOperand_Success;
4486 }
4487 
4488 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4489 /// of instructions. Legal values are:
4490 /// ror #n 'n' in {0, 8, 16, 24}
4492 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4493  MCAsmParser &Parser = getParser();
4494  const AsmToken &Tok = Parser.getTok();
4495  SMLoc S = Tok.getLoc();
4496  if (Tok.isNot(AsmToken::Identifier))
4497  return MatchOperand_NoMatch;
4498  StringRef ShiftName = Tok.getString();
4499  if (ShiftName != "ror" && ShiftName != "ROR")
4500  return MatchOperand_NoMatch;
4501  Parser.Lex(); // Eat the operator.
4502 
4503  // A '#' and a rotate amount.
4504  if (Parser.getTok().isNot(AsmToken::Hash) &&
4505  Parser.getTok().isNot(AsmToken::Dollar)) {
4506  Error(Parser.getTok().getLoc(), "'#' expected");
4507  return MatchOperand_ParseFail;
4508  }
4509  Parser.Lex(); // Eat hash token.
4510  SMLoc ExLoc = Parser.getTok().getLoc();
4511 
4512  const MCExpr *ShiftAmount;
4513  SMLoc EndLoc;
4514  if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4515  Error(ExLoc, "malformed rotate expression");
4516  return MatchOperand_ParseFail;
4517  }
4518  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4519  if (!CE) {
4520  Error(ExLoc, "rotate amount must be an immediate");
4521  return MatchOperand_ParseFail;
4522  }
4523 
4524  int64_t Val = CE->getValue();
4525  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4526  // normally, zero is represented in asm by omitting the rotate operand
4527  // entirely.
4528  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4529  Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4530  return MatchOperand_ParseFail;
4531  }
4532 
4533  Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4534 
4535  return MatchOperand_Success;
4536 }
4537 
4539 ARMAsmParser::parseModImm(OperandVector &Operands) {
4540  MCAsmParser &Parser = getParser();
4541  MCAsmLexer &Lexer = getLexer();
4542  int64_t Imm1, Imm2;
4543 
4544  SMLoc S = Parser.getTok().getLoc();
4545 
4546  // 1) A mod_imm operand can appear in the place of a register name:
4547  // add r0, #mod_imm
4548  // add r0, r0, #mod_imm
4549  // to correctly handle the latter, we bail out as soon as we see an
4550  // identifier.
4551  //
4552  // 2) Similarly, we do not want to parse into complex operands:
4553  // mov r0, #mod_imm
4554  // mov r0, :lower16:(_foo)
4555  if (Parser.getTok().is(AsmToken::Identifier) ||
4556  Parser.getTok().is(AsmToken::Colon))
4557  return MatchOperand_NoMatch;
4558 
4559  // Hash (dollar) is optional as per the ARMARM
4560  if (Parser.getTok().is(AsmToken::Hash) ||
4561  Parser.getTok().is(AsmToken::Dollar)) {
4562  // Avoid parsing into complex operands (#:)
4563  if (Lexer.peekTok().is(AsmToken::Colon))
4564  return MatchOperand_NoMatch;
4565 
4566  // Eat the hash (dollar)
4567  Parser.Lex();
4568  }
4569 
4570  SMLoc Sx1, Ex1;
4571  Sx1 = Parser.getTok().getLoc();
4572  const MCExpr *Imm1Exp;
4573  if (getParser().parseExpression(Imm1Exp, Ex1)) {
4574  Error(Sx1, "malformed expression");
4575  return MatchOperand_ParseFail;
4576  }
4577 
4578  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4579 
4580  if (CE) {
4581  // Immediate must fit within 32-bits
4582  Imm1 = CE->getValue();
4583  int Enc = ARM_AM::getSOImmVal(Imm1);
4584  if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4585  // We have a match!
4586  Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4587  (Enc & 0xF00) >> 7,
4588  Sx1, Ex1));
4589  return MatchOperand_Success;
4590  }
4591 
4592  // We have parsed an immediate which is not for us, fallback to a plain
4593  // immediate. This can happen for instruction aliases. For an example,
4594  // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4595  // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4596  // instruction with a mod_imm operand. The alias is defined such that the
4597  // parser method is shared, that's why we have to do this here.
4598  if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4599  Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4600  return MatchOperand_Success;
4601  }
4602  } else {
4603  // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4604  // MCFixup). Fallback to a plain immediate.
4605  Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4606  return MatchOperand_Success;
4607  }
4608 
4609  // From this point onward, we expect the input to be a (#bits, #rot) pair
4610  if (Parser.getTok().isNot(AsmToken::Comma)) {
4611  Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4612  return MatchOperand_ParseFail;
4613  }
4614 
4615  if (Imm1 & ~0xFF) {
4616  Error(Sx1, "immediate operand must a number in the range [0, 255]");
4617  return MatchOperand_ParseFail;
4618  }
4619 
4620  // Eat the comma
4621  Parser.Lex();
4622 
4623  // Repeat for #rot
4624  SMLoc Sx2, Ex2;
4625  Sx2 = Parser.getTok().getLoc();
4626 
4627  // Eat the optional hash (dollar)
4628  if (Parser.getTok().is(AsmToken::Hash) ||
4629  Parser.getTok().is(AsmToken::Dollar))
4630  Parser.Lex();
4631 
4632  const MCExpr *Imm2Exp;
4633  if (getParser().parseExpression(Imm2Exp, Ex2)) {
4634  Error(Sx2, "malformed expression");
4635  return MatchOperand_ParseFail;
4636  }
4637 
4638  CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4639 
4640  if (CE) {
4641  Imm2 = CE->getValue();
4642  if (!(Imm2 & ~0x1E)) {
4643  // We have a match!
4644  Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4645  return MatchOperand_Success;
4646  }
4647  Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4648  return MatchOperand_ParseFail;
4649  } else {
4650  Error(Sx2, "constant expression expected");
4651  return MatchOperand_ParseFail;
4652  }
4653 }
4654 
4656 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4657  MCAsmParser &Parser = getParser();
4658  SMLoc S = Parser.getTok().getLoc();
4659  // The bitfield descriptor is really two operands, the LSB and the width.
4660  if (Parser.getTok().isNot(AsmToken::Hash) &&
4661  Parser.getTok().isNot(AsmToken::Dollar)) {
4662  Error(Parser.getTok().getLoc(), "'#' expected");
4663  return MatchOperand_ParseFail;
4664  }
4665  Parser.Lex(); // Eat hash token.
4666 
4667  const MCExpr *LSBExpr;
4668  SMLoc E = Parser.getTok().getLoc();
4669  if (getParser().parseExpression(LSBExpr)) {
4670  Error(E, "malformed immediate expression");
4671  return MatchOperand_ParseFail;
4672  }
4673  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4674  if (!CE) {
4675  Error(E, "'lsb' operand must be an immediate");
4676  return MatchOperand_ParseFail;
4677  }
4678 
4679  int64_t LSB = CE->getValue();
4680  // The LSB must be in the range [0,31]
4681  if (LSB < 0 || LSB > 31) {
4682  Error(E, "'lsb' operand must be in the range [0,31]");
4683  return MatchOperand_ParseFail;
4684  }
4685  E = Parser.getTok().getLoc();
4686 
4687  // Expect another immediate operand.
4688  if (Parser.getTok().isNot(AsmToken::Comma)) {
4689  Error(Parser.getTok().getLoc(), "too few operands");
4690  return MatchOperand_ParseFail;
4691  }
4692  Parser.Lex(); // Eat hash token.
4693  if (Parser.getTok().isNot(AsmToken::Hash) &&
4694  Parser.getTok().isNot(AsmToken::Dollar)) {
4695  Error(Parser.getTok().getLoc(), "'#' expected");
4696  return MatchOperand_ParseFail;
4697  }
4698  Parser.Lex(); // Eat hash token.
4699 
4700  const MCExpr *WidthExpr;
4701  SMLoc EndLoc;
4702  if (getParser().parseExpression(WidthExpr, EndLoc)) {
4703  Error(E, "malformed immediate expression");
4704  return MatchOperand_ParseFail;
4705  }
4706  CE = dyn_cast<MCConstantExpr>(WidthExpr);
4707  if (!CE) {
4708  Error(E, "'width' operand must be an immediate");
4709  return MatchOperand_ParseFail;
4710  }
4711 
4712  int64_t Width = CE->getValue();
4713  // The LSB must be in the range [1,32-lsb]
4714  if (Width < 1 || Width > 32 - LSB) {
4715  Error(E, "'width' operand must be in the range [1,32-lsb]");
4716  return MatchOperand_ParseFail;
4717  }
4718 
4719  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4720 
4721  return MatchOperand_Success;
4722 }
4723 
4725 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4726  // Check for a post-index addressing register operand. Specifically:
4727  // postidx_reg := '+' register {, shift}
4728  // | '-' register {, shift}
4729  // | register {, shift}
4730 
4731  // This method must return MatchOperand_NoMatch without consuming any tokens
4732  // in the case where there is no match, as other alternatives take other
4733  // parse methods.
4734  MCAsmParser &Parser = getParser();
4735  AsmToken Tok = Parser.getTok();
4736  SMLoc S = Tok.getLoc();
4737  bool haveEaten = false;
4738  bool isAdd = true;
4739  if (Tok.is(AsmToken::Plus)) {
4740  Parser.Lex(); // Eat the '+' token.
4741  haveEaten = true;
4742  } else if (Tok.is(AsmToken::Minus)) {
4743  Parser.Lex(); // Eat the '-' token.
4744  isAdd = false;
4745  haveEaten = true;
4746  }
4747 
4748  SMLoc E = Parser.getTok().getEndLoc();
4749  int Reg = tryParseRegister();
4750  if (Reg == -1) {
4751  if (!haveEaten)
4752  return MatchOperand_NoMatch;
4753  Error(Parser.getTok().getLoc(), "register expected");
4754  return MatchOperand_ParseFail;
4755  }
4756 
4758  unsigned ShiftImm = 0;
4759  if (Parser.getTok().is(AsmToken::Comma)) {
4760  Parser.Lex(); // Eat the ','.
4761  if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4762  return MatchOperand_ParseFail;
4763 
4764  // FIXME: Only approximates end...may include intervening whitespace.
4765  E = Parser.getTok().getLoc();
4766  }
4767 
4768  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4769  ShiftImm, S, E));
4770 
4771  return MatchOperand_Success;
4772 }
4773 
4775 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4776  // Check for a post-index addressing register operand. Specifically:
4777  // am3offset := '+' register
4778  // | '-' register
4779  // | register
4780  // | # imm
4781  // | # + imm
4782  // | # - imm
4783 
4784  // This method must return MatchOperand_NoMatch without consuming any tokens
4785  // in the case where there is no match, as other alternatives take other
4786  // parse methods.
4787  MCAsmParser &Parser = getParser();
4788  AsmToken Tok = Parser.getTok();
4789  SMLoc S = Tok.getLoc();
4790 
4791  // Do immediates first, as we always parse those if we have a '#'.
4792  if (Parser.getTok().is(AsmToken::Hash) ||
4793  Parser.getTok().is(AsmToken::Dollar)) {
4794  Parser.Lex(); // Eat '#' or '$'.
4795  // Explicitly look for a '-', as we need to encode negative zero
4796  // differently.
4797  bool isNegative = Parser.getTok().is(AsmToken::Minus);
4798  const MCExpr *Offset;
4799  SMLoc E;
4800  if (getParser().parseExpression(Offset, E))
4801  return MatchOperand_ParseFail;
4803  if (!CE) {
4804  Error(S, "constant expression expected");
4805  return MatchOperand_ParseFail;
4806  }
4807  // Negative zero is encoded as the flag value
4808  // std::numeric_limits<int32_t>::min().
4809  int32_t Val = CE->getValue();
4810  if (isNegative && Val == 0)
4811  Val = std::numeric_limits<int32_t>::min();
4812 
4813  Operands.push_back(
4814  ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
4815 
4816  return MatchOperand_Success;
4817  }
4818 
4819  bool haveEaten = false;
4820  bool isAdd = true;
4821  if (Tok.is(AsmToken::Plus)) {
4822  Parser.Lex(); // Eat the '+' token.
4823  haveEaten = true;
4824  } else if (Tok.is(AsmToken::Minus)) {
4825  Parser.Lex(); // Eat the '-' token.
4826  isAdd = false;
4827  haveEaten = true;
4828  }
4829 
4830  Tok = Parser.getTok();
4831  int Reg = tryParseRegister();
4832  if (Reg == -1) {
4833  if (!haveEaten)
4834  return MatchOperand_NoMatch;
4835  Error(Tok.getLoc(), "register expected");
4836  return MatchOperand_ParseFail;
4837  }
4838 
4839  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4840  0, S, Tok.getEndLoc()));
4841 
4842  return MatchOperand_Success;
4843 }
4844 
4845 /// Convert parsed operands to MCInst. Needed here because this instruction
4846 /// only has two register operands, but multiplication is commutative so
4847 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4848 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4849  const OperandVector &Operands) {
4850  ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4851  ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4852  // If we have a three-operand form, make sure to set Rn to be the operand
4853  // that isn't the same as Rd.
4854  unsigned RegOp = 4;
4855  if (Operands.size() == 6 &&
4856  ((ARMOperand &)*Operands[4]).getReg() ==
4857  ((ARMOperand &)*Operands[3]).getReg())
4858  RegOp = 5;
4859  ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4860  Inst.addOperand(Inst.getOperand(0));
4861  ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4862 }
4863 
4864 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4865  const OperandVector &Operands) {
4866  int CondOp = -1, ImmOp = -1;
4867  switch(Inst.getOpcode()) {
4868  case ARM::tB:
4869  case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4870 
4871  case ARM::t2B:
4872  case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4873 
4874  default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4875  }
4876  // first decide whether or not the branch should be conditional
4877  // by looking at it's location relative to an IT block
4878  if(inITBlock()) {
4879  // inside an IT block we cannot have any conditional branches. any
4880  // such instructions needs to be converted to unconditional form
4881  switch(Inst.getOpcode()) {
4882  case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4883  case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4884  }
4885  } else {
4886  // outside IT blocks we can only have unconditional branches with AL
4887  // condition code or conditional branches with non-AL condition code
4888  unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4889  switch(Inst.getOpcode()) {
4890  case ARM::tB:
4891  case ARM::tBcc:
4892  Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4893  break;
4894  case ARM::t2B:
4895  case ARM::t2Bcc:
4896  Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4897  break;
4898  }
4899  }
4900 
4901  // now decide on encoding size based on branch target range
4902  switch(Inst.getOpcode()) {
4903  // classify tB as either t2B or t1B based on range of immediate operand
4904  case ARM::tB: {
4905  ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4906  if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
4907  Inst.setOpcode(ARM::t2B);
4908  break;
4909  }
4910  // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4911  case ARM::tBcc: {
4912  ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4913  if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
4914  Inst.setOpcode(ARM::t2Bcc);
4915  break;
4916  }
4917  }
4918  ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4919  ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4920 }
4921 
4922 /// Parse an ARM memory expression, return false if successful else return true
4923 /// or an error. The first token must be a '[' when called.
4924 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4925  MCAsmParser &Parser = getParser();
4926  SMLoc S, E;
4927  if (Parser.getTok().isNot(AsmToken::LBrac))
4928  return TokError("Token is not a Left Bracket");
4929  S = Parser.getTok().getLoc();
4930  Parser.Lex(); // Eat left bracket token.
4931 
4932  const AsmToken &BaseRegTok = Parser.getTok();
4933  int BaseRegNum = tryParseRegister();
4934  if (BaseRegNum == -1)
4935  return Error(BaseRegTok.getLoc(), "register expected");
4936 
4937  // The next token must either be a comma, a colon or a closing bracket.
4938  const AsmToken &Tok = Parser.getTok();
4939  if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4940  !Tok.is(AsmToken::RBrac))
4941  return Error(Tok.getLoc(), "malformed memory operand");
4942 
4943  if (Tok.is(AsmToken::RBrac)) {
4944  E = Tok.getEndLoc();
4945  Parser.Lex(); // Eat right bracket token.
4946 
4947  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4948  ARM_AM::no_shift, 0, 0, false,
4949  S, E));
4950 
4951  // If there's a pre-indexing writeback marker, '!', just add it as a token
4952  // operand. It's rather odd, but syntactically valid.
4953  if (Parser.getTok().is(AsmToken::Exclaim)) {
4954  Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4955  Parser.Lex(); // Eat the '!'.
4956  }
4957 
4958  return false;
4959  }
4960 
4961  assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4962  "Lost colon or comma in memory operand?!");
4963  if (Tok.is(AsmToken::Comma)) {
4964  Parser.Lex(); // Eat the comma.
4965  }
4966 
4967  // If we have a ':', it's an alignment specifier.
4968  if (Parser.getTok().is(AsmToken::Colon)) {
4969  Parser.Lex(); // Eat the ':'.
4970  E = Parser.getTok().getLoc();
4971  SMLoc AlignmentLoc = Tok.getLoc();
4972 
4973  const MCExpr *Expr;
4974  if (getParser().parseExpression(Expr))
4975  return true;
4976 
4977  // The expression has to be a constant. Memory references with relocations
4978  // don't come through here, as they use the <label> forms of the relevant
4979  // instructions.
4980  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4981  if (!CE)
4982  return Error (E, "constant expression expected");
4983 
4984  unsigned Align = 0;
4985  switch (CE->getValue()) {
4986  default:
4987  return Error(E,
4988  "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4989  case 16: Align = 2; break;
4990  case 32: Align = 4; break;
4991  case 64: Align = 8; break;
4992  case 128: Align = 16; break;
4993  case 256: Align = 32; break;
4994  }
4995 
4996  // Now we should have the closing ']'
4997  if (Parser.getTok().isNot(AsmToken::RBrac))
4998  return Error(Parser.getTok().getLoc(), "']' expected");
4999  E = Parser.getTok().getEndLoc();
5000  Parser.Lex(); // Eat right bracket token.
5001 
5002  // Don't worry about range checking the value here. That's handled by
5003  // the is*() predicates.
5004  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5005  ARM_AM::no_shift, 0, Align,
5006  false, S, E, AlignmentLoc));
5007 
5008  // If there's a pre-indexing writeback marker, '!', just add it as a token
5009  // operand.
5010  if (Parser.getTok().is(AsmToken::Exclaim)) {
5011  Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5012  Parser.Lex(); // Eat the '!'.
5013  }
5014 
5015  return false;
5016  }
5017 
5018  // If we have a '#', it's an immediate offset, else assume it's a register
5019  // offset. Be friendly and also accept a plain integer (without a leading
5020  // hash) for gas compatibility.
5021  if (Parser.getTok().is(AsmToken::Hash) ||
5022  Parser.getTok().is(AsmToken::Dollar) ||
5023  Parser.getTok().is(AsmToken::Integer)) {
5024  if (Parser.getTok().isNot(AsmToken::Integer))
5025  Parser.Lex(); // Eat '#' or '$'.
5026  E = Parser.getTok().getLoc();
5027 
5028  bool isNegative = getParser().getTok().is(AsmToken::Minus);
5029  const MCExpr *Offset;
5030  if (getParser().parseExpression(Offset))
5031  return true;
5032 
5033  // The expression has to be a constant. Memory references with relocations
5034  // don't come through here, as they use the <label> forms of the relevant
5035  // instructions.
5037  if (!CE)
5038  return Error (E, "constant expression expected");
5039 
5040  // If the constant was #-0, represent it as
5041  // std::numeric_limits<int32_t>::min().
5042  int32_t Val = CE->getValue();
5043  if (isNegative && Val == 0)
5044  CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
5045  getContext());
5046 
5047  // Now we should have the closing ']'
5048  if (Parser.getTok().isNot(AsmToken::RBrac))
5049  return Error(Parser.getTok().getLoc(), "']' expected");
5050  E = Parser.getTok().getEndLoc();
5051  Parser.Lex(); // Eat right bracket token.
5052 
5053  // Don't worry about range checking the value here. That's handled by
5054  // the is*() predicates.
5055  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
5056  ARM_AM::no_shift, 0, 0,
5057  false, S, E));
5058 
5059  // If there's a pre-indexing writeback marker, '!', just add it as a token
5060  // operand.
5061  if (Parser.getTok().is(AsmToken::Exclaim)) {
5062  Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5063  Parser.Lex(); // Eat the '!'.
5064  }
5065 
5066  return false;
5067  }
5068 
5069  // The register offset is optionally preceded by a '+' or '-'
5070  bool isNegative = false;
5071  if (Parser.getTok().is(AsmToken::Minus)) {
5072  isNegative = true;
5073  Parser.Lex(); // Eat the '-'.
5074  } else if (Parser.getTok().is(AsmToken::Plus)) {
5075  // Nothing to do.
5076  Parser.Lex(); // Eat the '+'.
5077  }
5078 
5079  E = Parser.getTok().getLoc();
5080  int OffsetRegNum = tryParseRegister();
5081  if (OffsetRegNum == -1)
5082  return Error(E, "register expected");
5083 
5084  // If there's a shift operator, handle it.
5085  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
5086  unsigned ShiftImm = 0;
5087  if (Parser.getTok().is(AsmToken::Comma)) {
5088  Parser.Lex(); // Eat the ','.
5089  if (parseMemRegOffsetShift(ShiftType, ShiftImm))
5090  return true;
5091  }
5092 
5093  // Now we should have the closing ']'
5094  if (Parser.getTok().isNot(AsmToken::RBrac))
5095  return Error(Parser.getTok().getLoc(), "']' expected");
5096  E = Parser.getTok().getEndLoc();
5097  Parser.Lex(); // Eat right bracket token.
5098 
5099  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
5100  ShiftType, ShiftImm, 0, isNegative,
5101  S, E));
5102 
5103  // If there's a pre-indexing writeback marker, '!', just add it as a token
5104  // operand.
5105  if (Parser.getTok().is(AsmToken::Exclaim)) {
5106  Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5107  Parser.Lex(); // Eat the '!'.
5108  }
5109 
5110  return false;
5111 }
5112 
5113 /// parseMemRegOffsetShift - one of these two:
5114 /// ( lsl | lsr | asr | ror ) , # shift_amount
5115 /// rrx
5116 /// return true if it parses a shift otherwise it returns false.
5117 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
5118  unsigned &Amount) {
5119  MCAsmParser &Parser = getParser();
5120  SMLoc Loc = Parser.getTok().getLoc();
5121  const AsmToken &Tok = Parser.getTok();
5122  if (Tok.isNot(AsmToken::Identifier))
5123  return Error(Loc, "illegal shift operator");
5124  StringRef ShiftName = Tok.getString();
5125  if (ShiftName == "lsl" || ShiftName == "LSL" ||
5126  ShiftName == "asl" || ShiftName == "ASL")
5127  St = ARM_AM::lsl;
5128  else if (ShiftName == "lsr" || ShiftName == "LSR")
5129  St = ARM_AM::lsr;
5130  else if (ShiftName == "asr" || ShiftName == "ASR")
5131  St = ARM_AM::asr;
5132  else if (ShiftName == "ror" || ShiftName == "ROR")
5133  St = ARM_AM::ror;
5134  else if (ShiftName == "rrx" || ShiftName == "RRX")
5135  St = ARM_AM::rrx;
5136  else
5137  return Error(Loc, "illegal shift operator");
5138  Parser.Lex(); // Eat shift type token.
5139 
5140  // rrx stands alone.
5141  Amount = 0;
5142  if (St != ARM_AM::rrx) {
5143  Loc = Parser.getTok().getLoc();
5144  // A '#' and a shift amount.
5145  const AsmToken &HashTok = Parser.getTok();
5146  if (HashTok.isNot(AsmToken::Hash) &&
5147  HashTok.isNot(AsmToken::Dollar))
5148  return Error(HashTok.getLoc(), "'#' expected");
5149  Parser.Lex(); // Eat hash token.
5150 
5151  const MCExpr *Expr;
5152  if (getParser().parseExpression(Expr))
5153  return true;
5154  // Range check the immediate.
5155  // lsl, ror: 0 <= imm <= 31
5156  // lsr, asr: 0 <= imm <= 32
5157  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5158  if (!CE)
5159  return Error(Loc, "shift amount must be an immediate");
5160  int64_t Imm = CE->getValue();
5161  if (Imm < 0 ||
5162  ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5163  ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5164  return Error(Loc, "immediate shift value out of range");
5165  // If <ShiftTy> #0, turn it into a no_shift.
5166  if (Imm == 0)
5167  St = ARM_AM::lsl;
5168  // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5169  if (Imm == 32)
5170  Imm = 0;
5171  Amount = Imm;
5172  }
5173 
5174  return false;
5175 }
5176 
5177 /// parseFPImm - A floating point immediate expression operand.
5179 ARMAsmParser::parseFPImm(OperandVector &Operands) {
5180  MCAsmParser &Parser = getParser();
5181  // Anything that can accept a floating point constant as an operand
5182  // needs to go through here, as the regular parseExpression is
5183  // integer only.
5184  //
5185  // This routine still creates a generic Immediate operand, containing
5186  // a bitcast of the 64-bit floating point value. The various operands
5187  // that accept floats can check whether the value is valid for them
5188  // via the standard is*() predicates.
5189 
5190  SMLoc S = Parser.getTok().getLoc();
5191 
5192  if (Parser.getTok().isNot(AsmToken::Hash) &&
5193  Parser.getTok().isNot(AsmToken::Dollar))
5194  return MatchOperand_NoMatch;
5195 
5196  // Disambiguate the VMOV forms that can accept an FP immediate.
5197  // vmov.f32 <sreg>, #imm
5198  // vmov.f64 <dreg>, #imm
5199  // vmov.f32 <dreg>, #imm @ vector f32x2
5200  // vmov.f32 <qreg>, #imm @ vector f32x4
5201  //
5202  // There are also the NEON VMOV instructions which expect an
5203  // integer constant. Make sure we don't try to parse an FPImm
5204  // for these:
5205  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5206  ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5207  bool isVmovf = TyOp.isToken() &&
5208  (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
5209  TyOp.getToken() == ".f16");
5210  ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5211  bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5212  Mnemonic.getToken() == "fconsts");
5213  if (!(isVmovf || isFconst))
5214  return MatchOperand_NoMatch;
5215 
5216  Parser.Lex(); // Eat '#' or '$'.
5217 
5218  // Handle negation, as that still comes through as a separate token.
5219  bool isNegative = false;
5220  if (Parser.getTok().is(AsmToken::Minus)) {
5221  isNegative = true;
5222  Parser.Lex();
5223  }
5224  const AsmToken &Tok = Parser.getTok();
5225  SMLoc Loc = Tok.getLoc();
5226  if (Tok.is(AsmToken::Real) && isVmovf) {
5227  APFloat RealVal(APFloat::IEEEsingle(), Tok.getString());
5228  uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5229  // If we had a '-' in front, toggle the sign bit.
5230  IntVal ^= (uint64_t)isNegative << 31;
5231  Parser.Lex(); // Eat the token.
5232  Operands.push_back(ARMOperand::CreateImm(
5233  MCConstantExpr::create(IntVal, getContext()),
5234  S, Parser.getTok().getLoc()));
5235  return MatchOperand_Success;
5236  }
5237  // Also handle plain integers. Instructions which allow floating point
5238  // immediates also allow a raw encoded 8-bit value.
5239  if (Tok.is(AsmToken::Integer) && isFconst) {
5240  int64_t Val = Tok.getIntVal();
5241  Parser.Lex(); // Eat the token.
5242  if (Val > 255 || Val < 0) {
5243  Error(Loc, "encoded floating point value out of range");
5244  return MatchOperand_ParseFail;
5245  }
5246  float RealVal = ARM_AM::getFPImmFloat(Val);
5247  Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5248 
5249  Operands.push_back(ARMOperand::CreateImm(
5250  MCConstantExpr::create(Val, getContext()), S,
5251  Parser.getTok().getLoc()));
5252  return MatchOperand_Success;
5253  }
5254 
5255  Error(Loc, "invalid floating point immediate");
5256  return MatchOperand_ParseFail;
5257 }
5258 
5259 /// Parse a arm instruction operand. For now this parses the operand regardless
5260 /// of the mnemonic.
5261 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5262  MCAsmParser &Parser = getParser();
5263  SMLoc S, E;
5264 
5265  // Check if the current operand has a custom associated parser, if so, try to
5266  // custom parse the operand, or fallback to the general approach.
5267  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5268  if (ResTy == MatchOperand_Success)
5269  return false;
5270  // If there wasn't a custom match, try the generic matcher below. Otherwise,
5271  // there was a match, but an error occurred, in which case, just return that
5272  // the operand parsing failed.
5273  if (ResTy == MatchOperand_ParseFail)
5274  return true;
5275 
5276  switch (getLexer().getKind()) {
5277  default:
5278  Error(Parser.getTok().getLoc(), "unexpected token in operand");
5279  return true;
5280  case AsmToken::Identifier: {
5281  // If we've seen a branch mnemonic, the next operand must be a label. This
5282  // is true even if the label is a register name. So "br r1" means branch to
5283  // label "r1".
5284  bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
5285  if (!ExpectLabel) {
5286  if (!tryParseRegisterWithWriteBack(Operands))
5287  return false;
5288  int Res = tryParseShiftRegister(Operands);
5289  if (Res == 0) // success
5290  return false;
5291  else if (Res == -1) // irrecoverable error
5292  return true;
5293  // If this is VMRS, check for the apsr_nzcv operand.
5294  if (Mnemonic == "vmrs" &&
5295  Parser.getTok().getString().equals_lower("apsr_nzcv")) {