26#define DEBUG_TYPE "hexagon_cfg"
54 MachineFunctionProperties::Property::NoVRegs);
60char HexagonCFGOptimizer::ID = 0;
64 case Hexagon::J2_jumpt:
65 case Hexagon::J2_jumptpt:
66 case Hexagon::J2_jumpf:
67 case Hexagon::J2_jumpfpt:
68 case Hexagon::J2_jumptnew:
69 case Hexagon::J2_jumpfnew:
70 case Hexagon::J2_jumptnewpt:
71 case Hexagon::J2_jumpfnewpt:
78 return (Opc == Hexagon::J2_jump);
81void HexagonCFGOptimizer::InvertAndChangeJumpTarget(
84 MI.getParent()->getParent()->getSubtarget().getInstrInfo();
86 switch (
MI.getOpcode()) {
87 case Hexagon::J2_jumpt:
88 NewOpcode = Hexagon::J2_jumpf;
90 case Hexagon::J2_jumpf:
91 NewOpcode = Hexagon::J2_jumpt;
93 case Hexagon::J2_jumptnewpt:
94 NewOpcode = Hexagon::J2_jumpfnewpt;
96 case Hexagon::J2_jumpfnewpt:
97 NewOpcode = Hexagon::J2_jumptnewpt;
103 MI.setDesc(
TII->get(NewOpcode));
104 MI.getOperand(1).setMBB(NewTarget);
111 if (
PB->isLayoutSuccessor(
MBB) &&
PB->canFallThrough())
126 int Opc =
MI.getOpcode();
163 LayoutSucc = FirstSucc;
164 JumpAroundTarget = SecondSucc;
166 LayoutSucc = SecondSucc;
167 JumpAroundTarget = FirstSucc;
175 if (
MI.getOpcode() == Hexagon::J2_jumpt ||
176 MI.getOpcode() == Hexagon::J2_jumpf) {
177 CondBranchTarget =
MI.getOperand(1).getMBB();
180 if (!LayoutSucc || (CondBranchTarget != JumpAroundTarget)) {
184 if ((NumSuccs == 2) && LayoutSucc && (LayoutSucc->
pred_size() == 1)) {
186 if ((LayoutSucc->
size() == 1) &&
188 assert(JumpAroundTarget &&
"jump target is needed to process second basic block");
193 bool case2 = JumpAroundTarget->
isSuccessor(UncondTarget) &&
194 !JumpAroundTarget->
empty() &&
199 if (case1 || case2) {
200 InvertAndChangeJumpTarget(
MI, UncondTarget);
209 if (case2 && !case1) {
213 if (!isOnFallThroughPath(UncondTarget))
214 UncondTarget->
moveAfter(JumpAroundTarget);
220 std::vector<MachineBasicBlock::RegisterMaskPair> OrigLiveIn(
222 std::vector<MachineBasicBlock::RegisterMaskPair> NewLiveIn(
225 for (
const auto &OrigLI : OrigLiveIn)
227 for (
const auto &NewLI : NewLiveIn)
246 return new HexagonCFGOptimizer();
static bool IsConditionalBranch(int Opc)
static bool IsUnconditionalJump(int Opc)
const HexagonInstrInfo * TII
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass class - This class is used to implement most global optimizations.
unsigned pred_size() const
livein_iterator livein_end() const
void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New)
Replace successor OLD with NEW and update probability info.
bool canFallThrough()
Return true if the block can implicitly transfer control to the block after it by falling off the end...
succ_iterator succ_begin()
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
livein_iterator livein_begin() const
unsigned succ_size() const
SmallVectorImpl< MachineBasicBlock * >::iterator succ_iterator
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
void moveAfter(MachineBasicBlock *NewBefore)
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineBasicBlock * getMBB() const
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createHexagonCFGOptimizer()
void initializeHexagonCFGOptimizerPass(PassRegistry &)