25#define DEBUG_TYPE "hexagon_cfg"
53 MachineFunctionProperties::Property::NoVRegs);
59char HexagonCFGOptimizer::ID = 0;
63 case Hexagon::J2_jumpt:
64 case Hexagon::J2_jumptpt:
65 case Hexagon::J2_jumpf:
66 case Hexagon::J2_jumpfpt:
67 case Hexagon::J2_jumptnew:
68 case Hexagon::J2_jumpfnew:
69 case Hexagon::J2_jumptnewpt:
70 case Hexagon::J2_jumpfnewpt:
77 return (Opc == Hexagon::J2_jump);
80void HexagonCFGOptimizer::InvertAndChangeJumpTarget(
83 MI.getParent()->getParent()->getSubtarget().getInstrInfo();
85 switch (
MI.getOpcode()) {
86 case Hexagon::J2_jumpt:
87 NewOpcode = Hexagon::J2_jumpf;
89 case Hexagon::J2_jumpf:
90 NewOpcode = Hexagon::J2_jumpt;
92 case Hexagon::J2_jumptnewpt:
93 NewOpcode = Hexagon::J2_jumpfnewpt;
95 case Hexagon::J2_jumpfnewpt:
96 NewOpcode = Hexagon::J2_jumptnewpt;
102 MI.setDesc(
TII->get(NewOpcode));
103 MI.getOperand(1).setMBB(NewTarget);
110 if (
PB->isLayoutSuccessor(
MBB) &&
PB->canFallThrough())
125 int Opc =
MI.getOpcode();
162 LayoutSucc = FirstSucc;
163 JumpAroundTarget = SecondSucc;
165 LayoutSucc = SecondSucc;
166 JumpAroundTarget = FirstSucc;
174 if (
MI.getOpcode() == Hexagon::J2_jumpt ||
175 MI.getOpcode() == Hexagon::J2_jumpf) {
176 CondBranchTarget =
MI.getOperand(1).getMBB();
179 if (!LayoutSucc || (CondBranchTarget != JumpAroundTarget)) {
183 if ((NumSuccs == 2) && LayoutSucc && (LayoutSucc->
pred_size() == 1)) {
185 if ((LayoutSucc->
size() == 1) &&
187 assert(JumpAroundTarget &&
"jump target is needed to process second basic block");
192 bool case2 = JumpAroundTarget->
isSuccessor(UncondTarget) &&
193 !JumpAroundTarget->
empty() &&
198 if (case1 || case2) {
199 InvertAndChangeJumpTarget(
MI, UncondTarget);
208 if (case2 && !case1) {
212 if (!isOnFallThroughPath(UncondTarget))
213 UncondTarget->
moveAfter(JumpAroundTarget);
219 std::vector<MachineBasicBlock::RegisterMaskPair> OrigLiveIn(
221 std::vector<MachineBasicBlock::RegisterMaskPair> NewLiveIn(
224 for (
const auto &OrigLI : OrigLiveIn)
226 for (
const auto &NewLI : NewLiveIn)
245 return new HexagonCFGOptimizer();
static bool IsConditionalBranch(int Opc)
static bool IsUnconditionalJump(int Opc)
const HexagonInstrInfo * TII
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass class - This class is used to implement most global optimizations.
unsigned pred_size() const
livein_iterator livein_end() const
void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New)
Replace successor OLD with NEW and update probability info.
bool canFallThrough()
Return true if the block can implicitly transfer control to the block after it by falling off the end...
succ_iterator succ_begin()
void removeLiveIn(MCRegister Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
livein_iterator livein_begin() const
unsigned succ_size() const
SmallVectorImpl< MachineBasicBlock * >::iterator succ_iterator
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
void moveAfter(MachineBasicBlock *NewBefore)
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
MachineBasicBlock * getMBB() const
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createHexagonCFGOptimizer()
void initializeHexagonCFGOptimizerPass(PassRegistry &)